@@ -231,12 +231,6 @@ NV_STATUS nvos_forward_error_to_cray(struct pci_dev *, NvU32,
231231 const char * , va_list );
232232#endif
233233
234- #if defined(NVCPU_PPC64LE ) && defined(CONFIG_EEH )
235- #include <asm/eeh.h>
236- #define NV_PCI_ERROR_RECOVERY_ENABLED () eeh_enabled()
237- #define NV_PCI_ERROR_RECOVERY
238- #endif
239-
240234#if defined(NV_ASM_SET_MEMORY_H_PRESENT )
241235#include <asm/set_memory.h>
242236#endif
@@ -609,7 +603,7 @@ static NvBool nv_numa_node_has_memory(int node_id)
609603
610604#define NV_ALLOC_PAGES_NODE (ptr , nid , order , gfp_mask ) \
611605 { \
612- (ptr) = (unsigned long)page_address( alloc_pages_node(nid, gfp_mask, order) ); \
606+ (ptr) = (unsigned long) alloc_pages_node(nid, gfp_mask, order); \
613607 }
614608
615609#define NV_GET_FREE_PAGES (ptr , order , gfp_mask ) \
@@ -881,16 +875,6 @@ typedef void irqreturn_t;
881875#define PCI_CAP_ID_EXP 0x10
882876#endif
883877
884- /*
885- * On Linux on PPC64LE enable basic support for Linux PCI error recovery (see
886- * Documentation/PCI/pci-error-recovery.txt). Currently RM only supports error
887- * notification and data collection, not actual recovery of the device.
888- */
889- #if defined(NVCPU_PPC64LE ) && defined(CONFIG_EEH )
890- #include <asm/eeh.h>
891- #define NV_PCI_ERROR_RECOVERY
892- #endif
893-
894878/*
895879 * If the host OS has page sizes larger than 4KB, we may have a security
896880 * problem. Registers are typically grouped in 4KB pages, but if there are
@@ -1419,8 +1403,6 @@ typedef struct nv_dma_map_s {
14191403 0 ? NV_OK : NV_ERR_OPERATING_SYSTEM)
14201404#endif
14211405
1422- typedef struct nv_ibmnpu_info nv_ibmnpu_info_t ;
1423-
14241406typedef struct nv_work_s {
14251407 struct work_struct task ;
14261408 void * data ;
@@ -1468,7 +1450,6 @@ struct nv_dma_device {
14681450 } addressable_range ;
14691451
14701452 struct device * dev ;
1471- NvBool nvlink ;
14721453};
14731454
14741455/* Properties of the coherent link */
@@ -1517,9 +1498,6 @@ typedef struct nv_linux_state_s {
15171498 struct device * dev ;
15181499 struct pci_dev * pci_dev ;
15191500
1520- /* IBM-NPU info associated with this GPU */
1521- nv_ibmnpu_info_t * npu ;
1522-
15231501 /* coherent link information */
15241502 coherent_link_info_t coherent_link_info ;
15251503
@@ -1835,7 +1813,7 @@ static inline int nv_is_control_device(struct inode *inode)
18351813 return (minor ((inode )-> i_rdev ) == NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE );
18361814}
18371815
1838- #if defined(NV_DOM0_KERNEL_PRESENT ) || defined(NV_VGPU_KVM_BUILD )
1816+ #if defined(NV_DOM0_KERNEL_PRESENT ) || defined(NV_VGPU_KVM_BUILD ) || defined( NV_DEVICE_VM_BUILD )
18391817#define NV_VGX_HYPER
18401818#if defined(NV_XEN_IOEMU_INJECT_MSI )
18411819#include <xen/ioemu.h>
@@ -1872,59 +1850,6 @@ static inline NvBool nv_alloc_release(nv_linux_file_private_t *nvlfp, nv_alloc_t
18721850#define RB_EMPTY_ROOT (root ) ((root)->rb_node == NULL)
18731851#endif
18741852
1875- /*
1876- * Starting on Power9 systems, DMA addresses for NVLink are no longer
1877- * the same as used over PCIe.
1878- *
1879- * Power9 supports a 56-bit Real Address. This address range is compressed
1880- * when accessed over NVLink to allow the GPU to access all of memory using
1881- * its 47-bit Physical address.
1882- *
1883- * If there is an NPU device present on the system, it implies that NVLink
1884- * sysmem links are present and we need to apply the required address
1885- * conversion for NVLink within the driver.
1886- *
1887- * See Bug 1920398 for further background and details.
1888- *
1889- * Note, a deviation from the documented compression scheme is that the
1890- * upper address bits (i.e. bit 56-63) instead of being set to zero are
1891- * preserved during NVLink address compression so the orignal PCIe DMA
1892- * address can be reconstructed on expansion. These bits can be safely
1893- * ignored on NVLink since they are truncated by the GPU.
1894- *
1895- * Bug 1968345: As a performance enhancement it is the responsibility of
1896- * the caller on PowerPC platforms to check for presence of an NPU device
1897- * before the address transformation is applied.
1898- */
1899- static inline NvU64 nv_compress_nvlink_addr (NvU64 addr )
1900- {
1901- NvU64 addr47 = addr ;
1902-
1903- #if defined(NVCPU_PPC64LE )
1904- addr47 = addr & ((1ULL << 43 ) - 1 );
1905- addr47 |= (addr & (0x3ULL << 45 )) >> 2 ;
1906- WARN_ON (addr47 & (1ULL << 44 ));
1907- addr47 |= (addr & (0x3ULL << 49 )) >> 4 ;
1908- addr47 |= addr & ~((1ULL << 56 ) - 1 );
1909- #endif
1910-
1911- return addr47 ;
1912- }
1913-
1914- static inline NvU64 nv_expand_nvlink_addr (NvU64 addr47 )
1915- {
1916- NvU64 addr = addr47 ;
1917-
1918- #if defined(NVCPU_PPC64LE )
1919- addr = addr47 & ((1ULL << 43 ) - 1 );
1920- addr |= (addr47 & (3ULL << 43 )) << 2 ;
1921- addr |= (addr47 & (3ULL << 45 )) << 4 ;
1922- addr |= addr47 & ~((1ULL << 56 ) - 1 );
1923- #endif
1924-
1925- return addr ;
1926- }
1927-
19281853// Default flags for ISRs
19291854static inline NvU32 nv_default_irq_flags (nv_state_t * nv )
19301855{
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