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Merge branch 'master' into tomu to test split USB bootloader
2 parents e15f487 + 6e31253 commit ee3043b

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‎LICENSE‎

Lines changed: 202 additions & 674 deletions
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‎TinyFPGA-Bootloader.core‎

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@@ -36,6 +36,7 @@ filesets:
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- tests/top_tb_header.vh : {is_include_file : true}
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- tests/top_tb_footer.vh : {is_include_file : true}
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file_type : verilogSource
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depend : [">=::vlog_tb_utils:1.1"]
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address_device_test:
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files : [tests/address_device_test/test.v : {file_type : verilogSource}]
@@ -137,6 +138,7 @@ targets:
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address_device_test: &tc
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default_tool : icarus
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filesets : [common, test_common, address_device_test]
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parameters : [continue_on_fail]
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tools:
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modelsim:
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vlog_options : [-sv]
@@ -233,3 +235,9 @@ targets:
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win10_enumeration_test:
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<<: *tc
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filesets : [common, test_common, win10_enumeration_test]
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parameters:
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continue_on_fail:
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datatype : bool
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description : Continue instead of exit on failed assertions
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paramtype : vlogdefine

‎boards/TinyFPGA_B2/Makefile‎

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@@ -14,49 +14,67 @@
1414
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
1515
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1616

17-
PROJ = TinyFPGA_BX
17+
PROJ = bootloader
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OUTDIR = build
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1920
PIN_DEF = pins.pcf
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DEVICE = lp8k
21-
22-
all: $(PROJ).rpt $(PROJ).bin
23-
24-
%.blif: %.v *.v
25-
yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $^
26-
27-
%.asc: $(PIN_DEF) %.blif
28-
arachne-pnr -d 8k -P cm81 -o $@ -p $^
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PKG = cm81
23+
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all: $(OUTDIR)/fw.bin
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$(OUTDIR)/fw.bin: $(OUTDIR)/$(PROJ).img
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cp $< $@
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$(OUTDIR)/$(PROJ).blif $(OUTDIR)/$(PROJ).yosys.json $(OUTDIR)/$(PROJ).synthesis.rpt: $(PROJ).v ../../common/*.v
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$(OUTDIR)/$(PROJ).asc: $(PIN_DEF)
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$(OUTDIR)/$(PROJ).nextpnr.asc: $(PIN_DEF)
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$(OUTDIR)/bootmeta.json:
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@mkdir -p $(@D)
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echo '{' > $@
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echo ' "bootloader": "TinyFPGA USB Bootloader",' >> $@
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echo ' "bver": "$(shell git describe --tags || echo "Unknown")",' >> $@
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echo ' "addrmap": {' >> $@
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echo ' "bootloader": "0x00000-0x27FFF",' >> $@
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echo ' "userimage": "0x28000-0x4FFFF",' >> $@
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echo ' "userdata": "0x50000-0x7EFFF",' >> $@
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echo ' "bootmeta": "0x7F000-0x7FFFF"' >> $@
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echo ' }' >> $@
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echo '}' >> $@
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%.img: %.bin %.rpt $(OUTDIR)/bootmeta.json
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@mkdir -p $(@D)
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cp $< $(patsubst %.bin,%_0.bin,$<)
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cp $< $(patsubst %.bin,%_1.bin,$<)
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icemulti -v -o $@ -a15 -p0 $(patsubst %.bin,%_0.bin,$<) $(patsubst %.bin,%_1.bin,$<)
51+
truncate -s 512K $@
52+
dd if=$(OUTDIR)/bootmeta.json of=$@ bs=1 seek=508K conv=notrunc
53+
54+
%.blif %.yosys.json %.synthesis.rpt:
55+
@mkdir -p $(@D)
56+
yosys -q -l $*.synthesis.rpt -p 'synth_ice40 -top $(PROJ) -blif $*.blif -json $*.yosys.json' $^
57+
58+
%.asc: %.blif
59+
@mkdir -p $(@D)
60+
arachne-pnr -d 8k -P $(PKG) -o $@ -p $(filter %.pcf,$^) $(filter %.blif,$^)
61+
62+
%.nextpnr.asc: %.yosys.json
63+
@mkdir -p $(@D)
64+
nextpnr-ice40 --lp8k --package $(PKG) --json $(filter %.yosys.json,$^) --pcf $(filter %.pcf,$^) --asc $@
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3066
%.bin: %.asc
67+
@mkdir -p $(@D)
3168
icepack $< $@
3269

3370
%.rpt: %.asc
3471
icetime -d $(DEVICE) -mtr $@ $<
3572

36-
%_tb: %_tb.v %.v
37-
iverilog -o $@ $^
38-
39-
%_tb.vcd: %_tb
40-
vvp -N $< +vcd=$@
41-
4273
%_syn.v: %.blif
4374
yosys -p 'read_blif -wideports $^; write_verilog $@'
4475

45-
%_syntb: %_tb.v %_syn.v
46-
iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
47-
48-
%_syntb.vcd: %_syntb
49-
vvp -N $< +vcd=$@
50-
51-
prog: $(PROJ).bin
52-
iceprog $<
53-
54-
sudo-prog: $(PROJ).bin
55-
@echo 'Executing prog as root!!!'
56-
sudo iceprog $<
57-
5876
clean:
59-
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin
77+
[ -z "$(OUTDIR)" ] || rm -rf $(OUTDIR)/
6078

6179
.SECONDARY:
62-
.PHONY: all prog clean
80+
.PHONY: all clean

‎boards/TinyFPGA_B2/TinyFPGA_B2.v‎

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This file was deleted.

‎boards/TinyFPGA_B2/bootloader.v‎

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1+
module bootloader (
2+
input pin_clk,
3+
4+
inout pin_usbp,
5+
inout pin_usbn,
6+
7+
input pin_miso,
8+
output pin_cs,
9+
output pin_mosi,
10+
output pin_sck
11+
);
12+
// generate 48 mhz clock
13+
wire clk_48mhz;
14+
15+
SB_PLL40_CORE #(
16+
.DIVR(4'b0000),
17+
.DIVF(7'b0101111),
18+
.DIVQ(3'b100),
19+
.FILTER_RANGE(3'b001),
20+
.FEEDBACK_PATH("SIMPLE"),
21+
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
22+
.FDA_FEEDBACK(4'b0000),
23+
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
24+
.FDA_RELATIVE(4'b0000),
25+
.SHIFTREG_DIV_MODE(2'b00),
26+
.PLLOUT_SELECT("GENCLK"),
27+
.ENABLE_ICEGATE(1'b0)
28+
) usb_pll_inst (
29+
.REFERENCECLK(pin_clk),
30+
.PLLOUTCORE(clk_48mhz),
31+
.PLLOUTGLOBAL(),
32+
.EXTFEEDBACK(),
33+
.DYNAMICDELAY(),
34+
.RESETB(1'b1),
35+
.BYPASS(1'b0),
36+
.LATCHINPUTVALUE(),
37+
.LOCK(),
38+
.SDI(),
39+
.SDO(),
40+
.SCLK()
41+
);
42+
43+
// interface with iCE40 warmboot/multiboot capability
44+
wire boot;
45+
46+
SB_WARMBOOT warmboot_inst (
47+
.S1(1'b0),
48+
.S0(1'b1),
49+
.BOOT(boot)
50+
);
51+
52+
// instantiate tinyfpga bootloader
53+
wire reset;
54+
wire usb_p_tx;
55+
wire usb_n_tx;
56+
wire usb_p_rx;
57+
wire usb_n_rx;
58+
wire usb_tx_en;
59+
60+
tinyfpga_bootloader tinyfpga_bootloader_inst (
61+
.clk_48mhz(clk_48mhz),
62+
.reset(reset),
63+
.usb_p_tx(usb_p_tx),
64+
.usb_n_tx(usb_n_tx),
65+
.usb_p_rx(usb_p_rx),
66+
.usb_n_rx(usb_n_rx),
67+
.usb_tx_en(usb_tx_en),
68+
.spi_miso(pin_miso),
69+
.spi_cs(pin_cs),
70+
.spi_mosi(pin_mosi),
71+
.spi_sck(pin_sck),
72+
.boot(boot)
73+
);
74+
75+
wire usb_p_rx_in;
76+
wire usb_n_rx_in;
77+
SB_IO #(
78+
.PIN_TYPE(6'b1010_01), // simple input, tristate output
79+
.PULLUP(1'b0)
80+
) usb_io_buf [1:0] (
81+
.PACKAGE_PIN({pin_usbp, pin_usbn}),
82+
.OUTPUT_ENABLE({usb_tx_en, usb_tx_en}),
83+
.D_OUT_0({usb_p_tx, usb_n_tx}),
84+
.D_IN_0({usb_p_rx_in, usb_n_rx_in})
85+
);
86+
assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_rx_in;
87+
assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_rx_in;
88+
89+
assign reset = 1'b0;
90+
endmodule

‎boards/TinyFPGA_B2/pins.pcf‎

Lines changed: 13 additions & 48 deletions
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@@ -1,48 +1,13 @@
1-
###############################################################################
2-
# Family & Device: iCE40LP8K
3-
# Package: CM81
4-
###############################################################################
5-
6-
#set_io pin_1 A2
7-
#set_io pin_2 A1
8-
#set_io pin_3 B1
9-
#set_io pin_4 C2
10-
#set_io pin_5 C1
11-
#set_io pin_6 D2
12-
#set_io pin_7 D1
13-
#set_io pin_8 E2
14-
#set_io pin_9 E1
15-
#set_io pin_10 G2
16-
#set_io pin_11 H1
17-
#set_io pin_12 J1
18-
#set_io pin_13 H2
19-
#set_io pin_14 H9
20-
#set_io pin_15 D9
21-
#set_io pin_16 D8
22-
#set_io pin_17 C9
23-
#set_io pin_18 A9
24-
#set_io pin_19 B8
25-
#set_io pin_20 A8
26-
#set_io pin_21 B7
27-
#set_io pin_22 A7
28-
#set_io pin_23 B6
29-
#set_io pin_24 A6
30-
#set_io pin_25 G1
31-
#set_io pin_26 J3
32-
#set_io pin_27 J4
33-
#set_io pin_28 H4
34-
set_io pin_29_miso H7
35-
set_io pin_30_cs F7
36-
set_io pin_31_mosi G6
37-
set_io pin_32_sck G7
38-
#set_io pin_33 J8
39-
#set_io pin_34 G9
40-
#set_io pin_35 J9
41-
#set_io pin_36 E8
42-
#set_io pin_37 J2
43-
set_io pin_led B3
44-
set_io pin_usbp B4
45-
set_io pin_usbn A4
46-
set_io pin_pu A3
47-
set_io pin_clk B2
48-
1+
###############################################################################
2+
# Family & Device: iCE40LP8K
3+
# Package: CM81
4+
###############################################################################
5+
6+
set_io pin_cs F7
7+
set_io pin_sck G7
8+
set_io pin_mosi G6
9+
set_io pin_miso H7
10+
set_io pin_usbp A3
11+
set_io pin_usbn A4
12+
set_io pin_clk C4
13+

‎boards/TinyFPGA_BX/bootloader.v‎

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@@ -85,6 +85,8 @@ module bootloader (
8585
wire usb_n_tx;
8686
wire usb_p_rx;
8787
wire usb_n_rx;
88+
wire usb_p_rx_io;
89+
wire usb_n_rx_io;
8890
wire usb_tx_en;
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9092
tinyfpga_bootloader tinyfpga_bootloader_inst (

‎programmer/MANIFEST.in‎

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@@ -4,6 +4,7 @@ include *.md
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# Include the license file
55
include LICENSE
66

7+
include *.py
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include *.sh
89
include *.toml
910
include .coveragerc

‎programmer/check_doctests.py‎

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1+
#!/usr/bin/env python
2+
import doctest
3+
import tinyprog
4+
doctest.testmod(tinyprog)

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