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mithromithro
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Merge branch 'master' into clock-crossing
2 parents 6166d33 + 704c8fc commit 42c8da7

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16 files changed

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16 files changed

+1255
-915
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‎README.md‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,10 +50,10 @@ Optionally, an additional `desc.tgz` file may be included in the SPI flash itsel
5050
"bver": "2.0.0",
5151
"update": "https://tinyfpga.com/update/tinyfpga-bx",
5252
"addrmap": {
53-
"bootloader": "0x00000+131542",
54-
"userimage": "0x30000+131542",
55-
"userdata": "0x50000+710000",
56-
"desc.tgz": "0xFC000+16000"
53+
"bootloader": "0x00000-0x2FFFF",
54+
"userimage": "0x30000-0x4FFFF",
55+
"userdata": "0x50000-0xFBFFF",
56+
"desc.tgz": "0xFC000-0xFFFFF"
5757
}
5858
}
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```

‎boards/TinyFPGA_BX/bootloader.v‎

Lines changed: 145 additions & 144 deletions
Original file line numberDiff line numberDiff line change
@@ -1,144 +1,145 @@
1-
module bootloader (
2-
input pin_clk,
3-
4-
inout pin_usbp,
5-
inout pin_usbn,
6-
output pin_pu,
7-
8-
output pin_led,
9-
10-
input pin_29_miso,
11-
output pin_30_cs,
12-
output pin_31_mosi,
13-
output pin_32_sck
14-
);
15-
////////////////////////////////////////////////////////////////////////////////
16-
////////////////////////////////////////////////////////////////////////////////
17-
////////
18-
//////// generate 48 mhz clock
19-
////////
20-
////////////////////////////////////////////////////////////////////////////////
21-
////////////////////////////////////////////////////////////////////////////////
22-
wire clk_48mhz;
23-
wire lock;
24-
wire reset = !lock;
25-
26-
SB_PLL40_CORE #(
27-
.DIVR(4'b0000),
28-
.DIVF(7'b0101111),
29-
.DIVQ(3'b100),
30-
.FILTER_RANGE(3'b001),
31-
.FEEDBACK_PATH("SIMPLE"),
32-
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
33-
.FDA_FEEDBACK(4'b0000),
34-
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
35-
.FDA_RELATIVE(4'b0000),
36-
.SHIFTREG_DIV_MODE(2'b00),
37-
.PLLOUT_SELECT("GENCLK"),
38-
.ENABLE_ICEGATE(1'b0)
39-
) usb_pll_inst (
40-
.REFERENCECLK(pin_clk),
41-
.PLLOUTCORE(clk_48mhz),
42-
.PLLOUTGLOBAL(),
43-
.EXTFEEDBACK(),
44-
.DYNAMICDELAY(),
45-
.RESETB(1'b1),
46-
.BYPASS(1'b0),
47-
.LATCHINPUTVALUE(),
48-
.LOCK(lock),
49-
.SDI(),
50-
.SDO(),
51-
.SCLK()
52-
);
53-
54-
reg clk_24mhz;
55-
reg clk_12mhz;
56-
always @(posedge clk_48mhz) clk_24mhz = !clk_24mhz;
57-
always @(posedge clk_24mhz) clk_12mhz = !clk_12mhz;
58-
59-
wire clk = clk_12mhz; // quarter speed clock
60-
61-
////////////////////////////////////////////////////////////////////////////////
62-
////////////////////////////////////////////////////////////////////////////////
63-
////////
64-
//////// interface with iCE40 warmboot/multiboot capability
65-
////////
66-
////////////////////////////////////////////////////////////////////////////////
67-
////////////////////////////////////////////////////////////////////////////////
68-
wire boot;
69-
70-
SB_WARMBOOT warmboot_inst (
71-
.S1(1'b0),
72-
.S0(1'b1),
73-
.BOOT(boot)
74-
);
75-
76-
77-
////////////////////////////////////////////////////////////////////////////////
78-
////////////////////////////////////////////////////////////////////////////////
79-
////////
80-
//////// instantiate tinyfpga bootloader
81-
////////
82-
////////////////////////////////////////////////////////////////////////////////
83-
////////////////////////////////////////////////////////////////////////////////
84-
wire usb_p_tx;
85-
wire usb_n_tx;
86-
wire usb_p_rx;
87-
wire usb_n_rx;
88-
wire usb_p_rx_io;
89-
wire usb_n_rx_io;
90-
wire usb_tx_en;
91-
92-
tinyfpga_bootloader tinyfpga_bootloader_inst (
93-
.clk_48mhz(clk_48mhz),
94-
.clk(clk),
95-
.reset(reset),
96-
.usb_p_tx(usb_p_tx),
97-
.usb_n_tx(usb_n_tx),
98-
.usb_p_rx(usb_p_rx),
99-
.usb_n_rx(usb_n_rx),
100-
.usb_tx_en(usb_tx_en),
101-
.led(pin_led),
102-
.spi_miso(pin_29_miso),
103-
.spi_cs(pin_30_cs),
104-
.spi_mosi(pin_31_mosi),
105-
.spi_sck(pin_32_sck),
106-
.boot(boot)
107-
);
108-
109-
assign pin_pu = 1'b1;
110-
wire usb_p_rx_io;
111-
wire usb_n_rx_io;
112-
assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_rx_io;
113-
assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_rx_io;
114-
115-
tristate usbn_buffer(
116-
.pin(pin_usbn),
117-
.enable(usb_tx_en),
118-
.data_in(usb_n_rx_io),
119-
.data_out(usb_n_tx)
120-
);
121-
122-
tristate usbp_buffer(
123-
.pin(pin_usbp),
124-
.enable(usb_tx_en),
125-
.data_in(usb_p_rx_io),
126-
.data_out(usb_p_tx)
127-
);
128-
endmodule
129-
130-
module tristate(
131-
inout pin,
132-
input enable,
133-
input data_out,
134-
output data_in
135-
);
136-
SB_IO #(
137-
.PIN_TYPE(6'b1010_01) // tristatable output
138-
) buffer(
139-
.PACKAGE_PIN(pin),
140-
.OUTPUT_ENABLE(enable),
141-
.D_IN_0(data_in),
142-
.D_OUT_0(data_out)
143-
);
144-
endmodule
1+
module bootloader (
2+
input pin_clk,
3+
4+
inout pin_usbp,
5+
inout pin_usbn,
6+
output pin_pu,
7+
8+
output pin_led,
9+
10+
input pin_29_miso,
11+
output pin_30_cs,
12+
output pin_31_mosi,
13+
output pin_32_sck
14+
);
15+
////////////////////////////////////////////////////////////////////////////////
16+
////////////////////////////////////////////////////////////////////////////////
17+
////////
18+
//////// generate 48 mhz clock
19+
////////
20+
////////////////////////////////////////////////////////////////////////////////
21+
////////////////////////////////////////////////////////////////////////////////
22+
wire clk_48mhz;
23+
wire lock;
24+
wire reset = !lock;
25+
26+
SB_PLL40_CORE #(
27+
.DIVR(4'b0000),
28+
.DIVF(7'b0101111),
29+
.DIVQ(3'b100),
30+
.FILTER_RANGE(3'b001),
31+
.FEEDBACK_PATH("SIMPLE"),
32+
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
33+
.FDA_FEEDBACK(4'b0000),
34+
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
35+
.FDA_RELATIVE(4'b0000),
36+
.SHIFTREG_DIV_MODE(2'b00),
37+
.PLLOUT_SELECT("GENCLK"),
38+
.ENABLE_ICEGATE(1'b0)
39+
) usb_pll_inst (
40+
.REFERENCECLK(pin_clk),
41+
.PLLOUTCORE(clk_48mhz),
42+
.PLLOUTGLOBAL(),
43+
.EXTFEEDBACK(),
44+
.DYNAMICDELAY(),
45+
.RESETB(1'b1),
46+
.BYPASS(1'b0),
47+
.LATCHINPUTVALUE(),
48+
.LOCK(lock),
49+
.SDI(),
50+
.SDO(),
51+
.SCLK()
52+
);
53+
54+
reg clk_24mhz;
55+
reg clk_12mhz;
56+
always @(posedge clk_48mhz) clk_24mhz = !clk_24mhz;
57+
always @(posedge clk_24mhz) clk_12mhz = !clk_12mhz;
58+
59+
wire clk = clk_12mhz; // quarter speed clock
60+
61+
////////////////////////////////////////////////////////////////////////////////
62+
////////////////////////////////////////////////////////////////////////////////
63+
////////
64+
//////// interface with iCE40 warmboot/multiboot capability
65+
////////
66+
////////////////////////////////////////////////////////////////////////////////
67+
////////////////////////////////////////////////////////////////////////////////
68+
wire boot;
69+
70+
SB_WARMBOOT warmboot_inst (
71+
.S1(1'b0),
72+
.S0(1'b1),
73+
.BOOT(boot)
74+
);
75+
76+
77+
////////////////////////////////////////////////////////////////////////////////
78+
////////////////////////////////////////////////////////////////////////////////
79+
////////
80+
//////// instantiate tinyfpga bootloader
81+
////////
82+
////////////////////////////////////////////////////////////////////////////////
83+
////////////////////////////////////////////////////////////////////////////////
84+
wire usb_p_tx;
85+
wire usb_n_tx;
86+
wire usb_p_rx;
87+
wire usb_n_rx;
88+
wire usb_p_rx_io;
89+
wire usb_n_rx_io;
90+
wire usb_tx_en;
91+
92+
tinyfpga_bootloader tinyfpga_bootloader_inst (
93+
.clk_48mhz(clk_48mhz),
94+
.clk(clk),
95+
.reset(reset),
96+
.usb_p_tx(usb_p_tx),
97+
.usb_n_tx(usb_n_tx),
98+
.usb_p_rx(usb_p_rx),
99+
.usb_n_rx(usb_n_rx),
100+
.usb_tx_en(usb_tx_en),
101+
.led(pin_led),
102+
.spi_miso(pin_29_miso),
103+
.spi_cs(pin_30_cs),
104+
.spi_mosi(pin_31_mosi),
105+
.spi_sck(pin_32_sck),
106+
.boot(boot)
107+
);
108+
109+
assign pin_pu = 1'b1;
110+
111+
wire usb_p_rx_io;
112+
wire usb_n_rx_io;
113+
assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_rx_io;
114+
assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_rx_io;
115+
116+
tristate usbn_buffer(
117+
.pin(pin_usbn),
118+
.enable(usb_tx_en),
119+
.data_in(usb_n_rx_io),
120+
.data_out(usb_n_tx)
121+
);
122+
123+
tristate usbp_buffer(
124+
.pin(pin_usbp),
125+
.enable(usb_tx_en),
126+
.data_in(usb_p_rx_io),
127+
.data_out(usb_p_tx)
128+
);
129+
endmodule
130+
131+
module tristate(
132+
inout pin,
133+
input enable,
134+
input data_out,
135+
output data_in
136+
);
137+
SB_IO #(
138+
.PIN_TYPE(6'b1010_01) // tristatable output
139+
) buffer(
140+
.PACKAGE_PIN(pin),
141+
.OUTPUT_ENABLE(enable),
142+
.D_IN_0(data_in),
143+
.D_OUT_0(data_out)
144+
);
145+
endmodule

‎boards/Tomu_Fomu/Makefile‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
# Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile
2+
#
3+
# The following license is from the icestorm project and specifically applies to this file only:
4+
#
5+
# Permission to use, copy, modify, and/or distribute this software for any
6+
# purpose with or without fee is hereby granted, provided that the above
7+
# copyright notice and this permission notice appear in all copies.
8+
#
9+
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10+
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11+
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12+
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13+
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14+
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15+
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16+
17+
PROJ = bootloader
18+
19+
PIN_DEF = pins.pcf
20+
DEVICE = up5k
21+
PKG = uwg30
22+
SEED ?= 12345678
23+
24+
#all: $(PROJ).rpt multiboot.bin
25+
all: multiboot.bin
26+
27+
%.json: %.v ../../common/*.v
28+
yosys -q -p 'synth_ice40 -top $(PROJ) -json $@' $^
29+
%.blif: %.v ../../common/*.v
30+
yosys -q -p 'synth_ice40 -top $(PROJ) -blif $@' $^
31+
32+
%.asc: $(PIN_DEF) %.json
33+
nextpnr-ice40 \
34+
--seed $(SEED) \
35+
--up5k \
36+
--package $(PKG) \
37+
--json $(basename $@).json \
38+
--pcf $(PIN_DEF) \
39+
--asc $@ \
40+
41+
no-%.asc: $(PIN_DEF) %.blif
42+
arachne-pnr -d 5k -P $(PKG) -o $@ -p $^
43+
44+
%.bin: %.asc
45+
icepack $< $@
46+
47+
multiboot.bin: bootloader.bin
48+
cp bootloader.bin bootloader_0.bin
49+
cp bootloader.bin bootloader_1.bin
50+
icemulti -v -o multiboot.bin -a16 -p0 bootloader_0.bin bootloader_1.bin
51+
52+
%.rpt: %.asc
53+
icetime -d $(DEVICE) -mtr $@ $<
54+
55+
%_syn.v: %.blif
56+
yosys -p 'read_blif -wideports $^; write_verilog $@'
57+
58+
prog: multiboot.bin
59+
iceprog $<
60+
61+
sudo-prog: multiboot.bin
62+
@echo 'Executing prog as root!!!'
63+
sudo iceprog $<
64+
65+
clean:
66+
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin multiboot.bin
67+
68+
.SECONDARY:
69+
.PHONY: all prog clean

‎boards/Tomu_Fomu/boardmeta.json‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
{"boardmeta":{
2+
"name": "Tomu Fomu Hacker",
3+
"fpga": "ice40up5k-uwg30",
4+
"hver": "0.0",
5+
"serial": 1234
6+
}}

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