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Soft CPU
LiteX can create SoCs with or without CPU. Some simple SoCs don’t use any CPU (bridging SoCs for example), some SoCs use a CPU but external to the FPGA (PCIe SoCs for example where the CPU is directly the CPU of the Host machine) but in most of the cases the SoC embedded a "Soft CPU" to control the system and/or ease splitting tasks between software/hardware.
Currently the supported Soft CPUs are:
-
lm32-- a LatticeMico32 soft core. -
mor1kx-- an OpenRISC 1000 soft core (see also Open RISC on Wikipedia). -
picorv32-- a Small RISC V core by Clifford Wolf, implementing therv32imcinstruction set (or configured subsets) -
vexriscv-- an FPGA Friendly RISC V core by SpinalHDL, implementing therv32iminstruction set (hardware multiply optional) -
(TODO)
taiga-- an high performance FPGA Friendly RISC V core, implementing therv32iminstruction set. -
minerva-- a CPU core that currently implements the RISC-V RV32I instruction set with its microarchitecture described in plain Python code using the nMigen toolbox.
Most of these CPUs have multiple configuration variants which customize the configuration to target a specific type of firmware, performance and resource usage. All these CPUs can be used with your own bare metal firmware.
Aliases: min
Minimal is the smallest possible working configuration for a given CPU type. These features frequently disables a large number of useful such as illegal instruction exceptions and similar. It should only be used if the absolute smallest configuration is needed.
- lm32
- picorv32
- vexriscv
Aliases: zephyr, nuttx, light
Lite is the configuration which should work okay for bare metal firmware and RTOS like NuttX or Zephyr on small big FPGAs like the Lattice iCE40 parts. It can also be used for designs which are more resource constrained.
- Lattice iCE40 Series - iCE40HX, iCE40LP, iCE40UP5K
- Any resource constrained design.
- lm32
- vexriscv
Aliases: std
Standard is the default configuration which should work well for bare metal firmware and RTOS like NuttX or Zephyr on modern big FPGAs.
- lm32
- minerva
- picorv32
- mor1kx
- taiga
- vexriscv
- Xilinx 7-Series - Artix7, Kintex7, Spartan7
- Xilinx Spartan6
- Lattice ECP5
This target enables all features of each CPU.
- (TODO) - lm32
- (TODO) - minerva
- (TODO) - picorv32
- (TODO) - mor1kx
- vexriscv
- (TODO) - taiga
This target enables CPU features such as MMU that are required to get Linux booting.
- mor1kx
- vexriscv
- (TODO) taiga
Extensions are added to the CPU variant with a +. For example a minimal variant with the debug extension would be minimal+debug.
The debug extension enables extra features useful for debugging. This normally includes things like JTAG port.
- vexriscv
The mmu extension enables a memory protection unit.
- lm32 (untested)
- vexriscv
- mor1kx
- (TODO) taiga
The hmul extension enables hardware multiplication acceleration.
The fpu extension enables a floating point acceleration unit.
- mor1kx
- (TODO) taiga
- lm32 support was added to upstream GCC around ~2009, no clang support.
- mor1kx support was added to upstream GCC in version 9.0.0, clang support was added upstream in version XXX
- riscv support (VexRISCV, PicoRV32, Taiga and Minerva) was added to upstream GCC in version 7.1.0, clang support was added upstream in version 3.1
You can compile your own compiler, download a precompiled toolchain or use an environment like TimVideos LiteX BuildEnv which provides precompiled toolchain for all three architectures.
Note: RISC-V toolchains support or require various extensions. Generally rv32i is used on smaller FPGAs, and rv32im on larger FPGAs -- the rv32im adds hardware multiplication and division (see RISC V ISA base and extensions on Wikipedia for more detail).
lm32 - LatticeMico32
LatticeMico32 soft core, small and designed for an FPGA.
- minimal
- lite
- standard
-
debug -
mmu - (TODO)
hmul -
fpu
- Upstream GCC
- Upstream Binutils
- No upstream Linux, very old Linux port
- Upstream NuttX
- No Zephyr support
- No current new activity
An OpenRISC 1000 soft core (see also Open RISC on Wikipedia).
- standard
- linux
-
debug -
mmu - (TODO)
hmul - (TODO)
fpu
- Upstream GCC
- Upstream Binutils
- Upstream clang
- No Zephyr support
- No NuttX support
- Upstream Linux
- Reasonable amount of activity.
RISC-V - VexRiscv
A FPGA Friendly RISC V core by SpinalHDL, implementing the rv32im instruction set (hardware multiply optional).
- minimal
- minimal_debug
- lite
- lite_debug
- standard
- standard_debug
- linux
-
debug -
mmu - (TODO)
hmul -
fpu
- Upstream GCC
- Upstream Binutils
- Upstream clang
- Upstream Zephyr
- Unknown NuttX support
- Upstream Linux (in progress)
- Lots of current activity
- Currently supported under both LiteX & MiSoC
RISC-V - picorv32
A small RISC V core by Clifford Wolf, implementing the rv32imc instruction set (or configured subsets).
minimalstandard
-
debug -
mmu - (TODO)
hmul -
fpu
- Upstream GCC
- Upstream Binutils
- Upstream clang
- Out of tree Zephyr
- Unknown NuttX support
- Too small for Linux
- Some activity
RISC-V - minerva
The Minerva is a CPU core that currently implements the RISC-V RV32I instruction set with its microarchitecture described in plain Python code using the nMigen toolbox.
standard
-
debug -
mmu -
hmul -
fpu
- Upstream GCC
- Upstream Binutils
- Upstream clang
- Unknown Zephyr support
- Unknown NuttX support
- Unknown Linux support
- Some activity
(TODO) - RISC-V - Taiga
From Taiga README file;
Taiga is a 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide and Atomic extensions (RV32IMA). The processor is written in SystemVerilog and has been designed to be both highly extensible and highly configurable. The pipeline has been designed to support parallel, variable-latency execution units and to readily support the inclusion of new execution units.
- minimal
- standard
- linux
-
debug -
mmu - (TODO)
hmul - (TODO)
fpu
- Upstream GCC
- Upstream Binutils
- Upstream clang
- Upstream Zephyr
- Unknown NuttX support
- Upstream Linux (in progress)
- Lots of current activity
- Currently supported under LiteX