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SimConfig.ini
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SimConfig.ini
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######## Hardware Configuration #####
[Device level]
Device_Tech = 130
# tech unit: nm
Device_Type = NVM
# device type: now support two kinds: NVM and SRAM
Device_Area = 1.44
# 3.38 RRAM ref: A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing
# 0.205 RRAM ref: A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN- Based AI Edge Processors
# 1.44 RRAM ref: Suppress variations of analog resistive memory for neuromorphic computing by localizing Vo formation
# 0.25 SRAM ref: A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic- Based ADC-less SRAM Compute-In-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
# area unit: um^2
Read_Level = 2
#
Read_Voltage = 0,0.15
# read voltage unit: V
Write_Level = 2
#
Write_Voltage = 0,3
# write voltage unit: V
Read_Latency = 3.16
# read latency unit: ns, 3.16 NTHU ISSCC19
Write_Latency = 10
# write latency unit: ns
Device_Level = 2
# For SRAM, this parameter should be set to 2
Device_Resistance = 1e6, 1e4
# when using SRAM type, the equvilant resistance is: 1.7e6, 1.7e6
# 1.2e6,4e4,1e7,10000,5000,3333 from BUAA
# resistence unit: ohm, the item number in this tuple is bit_level
# from HRS to LRS
Device_Variation = 1
# only used for NVM
# x% of ideal resistance
Device_SAF = 1,1
# only used for NVM
# X% of Stuck-At-HRS and Stuck-At-LRS
Read_Energy = 1.12e-15
# only used for SRAM, energy per bit
Write_Energy = 1.6e-15
# only used for SRAM, energy per bit
[Crossbar level]
Xbar_Size = 256,256
# (Row, Column)
# RRAM_ref: 256, 256
Subarray_Size = 256
# (Row)
# assume the subarray has the same column number as the crossbar
Cell_Type = 1T1R
# cell type option: 1T1R, 0T1R, only suitable for NVM
Transistor_Tech = 130
# transistor technology unit: nm
Wire_Resistance = -1
# wire resistance option: value (unit: ohm) or Default (-1)
Wire_Capacity = -1
# wire capacity option: value (unit: fF) or Default (-1)
Load_Resistance = -1
# load resistance (unit:ohm) or Default (-1)
Area_Calculation = 0
# different area calculation methods: 0: use device area for computing; 1: use device tech for computing
[Interface level]
DAC_Choice = 1
# DAC choice option: -1: User defined, 1~7: SEVEN default configurations
DAC_Area = 0
# DAC area option: 0: default configurations, x: unit um^2
DAC_Precision = 0
# DAC precision option: 0: default configurations, x: unit bit
DAC_Power = 0
# DAC power option: 0: default configurations, x: unit W
DAC_Sample_Rate = 0
# DAC sample rate option: 0: default configurations, x: GSamples/s
ADC_Choice = 2
# ADC choice option: -1: User defined, 1~8: eight default configurations
# especially, ADC_Choice 8 means SA
ADC_Area = 0
# ADC area option: 0: default configurations, x: unit um^2
ADC_Precision = 0
# ADC precision option: 0: default configurations, x: unit bit
ADC_Power = 0
# ADC power option: 0: default configurations, x: unit W
ADC_Sample_Rate = 0
# ADC sample rate option: 0: default configurations, x: Samples/s
ADC_Interval_Thres = -1
# ADC sample interval threshold option: -1 default configurations, x: a list with the length of 2^Precision. unit: V
Logic_Op = -1
# only used for digital PIM
# -1: not support, 0: AND, 1: OR, 2: XOR
[Process element level]
PIM_Type = 0
# 0: analog PIM, 1: digital PIM
# digital PIM will use 1bit interface
Xbar_Polarity = 2
# polarity 1: one xbar for both pos and neg; polarity 2: one pos xbar and one neg xbar
# in digital PIM, the polarity should set to 1
Sub_Position = 0
# only effective when the crossbar polarity equals to 2
# 0: the subtraction of pos and neg xbar is performed in the analog domain; 1: in the digital domain (sub after ADC quantization)
Group_Num = 1
# number of crossbar groups
DAC_Num = 256
# number of DAC per *subarray* in each group: 0: default configuration, x: user defined
ADC_Num = 128
# number of ADC per *subarray* in each group: 0: default configuration, x: user defined
PE_inBuf_Size = 0
# the input buffer size in each PE: 0: default configuration, x: user defined
PE_inBuf_Area = 0
# PE input buffer area option: 0: default configurations, x: um^2
Tile_outBuf_Size = 0
Tile_outBuf_Area = 0
DFU_Buf_Size = 0
DFU_Buf_Area = 0
[Digital module]
Digital_Frequency = 500
# digital part frequency unit: MHz
Adder_Tech = 45
# adder technology unit: nm
Adder_Area = 0
# adder area option: 0:default configurations x: unit um^2
Adder_Power = 0
# adder power option: 0:default configurations x: unit W
ShiftReg_Tech = 65
# shiftreg technology unit: nm
ShiftReg_Area = 0
# shiftreg area option: 0:default configurations x: unit um^2
ShiftReg_Power = 0
# shiftreg power option: 0:default configurations x: unit W
Reg_Tech = 45
# shiftreg technology unit: nm
Reg_Area = 0
# shiftreg area option: 0:default configurations x: unit um^2
Reg_Power = 0
# shiftreg power option: 0:default configurations x: unit W
JointModule_Tech = 45
# JointModule technology unit: nm
JointModule_Area = 0
# jointmodule area option: 0:default configurations x: unit um^2
JointModule_Power = 0
# jointmodule power option: 0:default configurations x: unit W
[Tile level]
PE_Num = 2,2
# number of PEs in each tile (x,y): 0,0: default configuration (4x4), x,y: user defined
Pooling_shape = 3,3
# Pooling Kernel size of the hardware actually suppoert (x,y): 0,0:default configuration (3x3), x,y: user defined
Pooling_unit_num = 64
# the Pooling unit in a tile. 0: default configuration, x: user defined
Pooling_Tech = 65
# technology for pooling unit used, unit is nm. 0: default configuration, x: user defined
Pooling_area = 0
# area for total Pooling part in the tile: 0: default configuration, x: user defined
Tile_Adder_Num = 0
# number of adders in each tile: 0: default configuration, x: user defined
Tile_Adder_Level = 0
# max adder level in each tile: 0: default configuration, x: user defined
Tile_ShiftReg_Num = 0
# number of shiftregs in each tile: 0: default configuration, x: user defined
Tile_ShiftReg_Level = 0
# max shiftreg level in each tile: 0: default configuration, x: user defined
Inter_Tile_Bandwidth = 20
# inter tile bandwidth, unit: Gbps
Intra_Tile_Bandwidth = 1024
# intra tile bandwidth (inter PE), unit: Gbps
Tile_outBuf_Size = 0
# the output buffer size in each Tile: 0: default configuration, x: user defined
Tile_outBuf_Area = 0
# Tile output buffer area option: 0: default configurations, x: um^2
DFU_Buf_Size = 0
# the buffer size in Data Forwarding Unit of each Tile: 0: default configuration, x: user defined
DFU_Buf_Area = 0
# DFU buffer area option: 0: default configurations, x: um^2
[Architecture level]
Buffer_Choice = 1
# buffer choice option: 0: User defined, 1: SRAM, 2:DRAM, 3:RRAM
Buffer_Technology = 90
# buffer technology option: 0: default configurations, x:nm
Buffer_ReadPower = 0
# buffer read power option: 0: default configurations, x:mW
Buffer_WritePower = 0
# buffer read power option: 0: default configurations, x:mW
Buffer_Bitwidth = 64
# buffer bitwidth option: 0: default configurations, x:bit
LUT_Capacity = 1
# LUT capacity unit: Mb
LUT_Area = 0
# LUT are option: 0: default configurations, x: mm^2
LUT_Power = 0
# LUT power option: 0: default configurations, x:mW
LUT_Bandwidth = 0
# LUT bandwidth option: 0: default configurations, x:Mb/s
Tile_Connection = 2
# Option: 0, 1, 2, 3
Tile_Num = 64,64
# number of Tiles in accelerator (x,y): 0,0: default configuration (8x8), x,y: user defined
########### Algorithm Configuration ################
[Algorithm Configuration]
Weight_Polarity = 1
# 1 or 2
Simulation_Level = 0
# 0: Behavior, do not consider specific weight values; 1: Estimation, consider the specific weight values
NoC_enable = 0
# 0: not call booksim to simulate the NoC part; 1: Call booksim to simulate NoC part
#shiftreg, adder, outputmux, oreg =0