ASOC: SOF: set clock and power gating ops for SKL+ platforms

Set ops for audio dsp clock and power gating for SKL+ platforms.

Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>

Author: ranj063

sound/soc/sof/intel/apl.c

@@ -103,5 +103,6 @@ struct snd_sof_dsp_ops sof_apl_ops = {
 	.resume			= hda_dsp_resume,
 	.runtime_suspend	= hda_dsp_runtime_suspend,
 	.runtime_resume		= hda_dsp_runtime_resume,
+	.clock_power_gating	= hda_dsp_ctrl_clock_power_gating,
 };
 EXPORT_SYMBOL(sof_apl_ops);

sound/soc/sof/intel/hda-ctrl.c

@@ -29,6 +29,7 @@
 #include <sound/sof.h>
 #include <sound/pcm_params.h>
 #include <linux/pm_runtime.h>
+#include <sound/hda_register.h>
 
 #include "../sof-priv.h"
 #include "../ops.h"
@@ -148,6 +149,24 @@ void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
 	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
 }
 
+void hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
+{
+	struct hdac_bus *bus = sof_to_bus(sdev);
+	u32 val;
+
+	/* Update PDCGE bit of CGCTL register */
+	val = enable ? PCI_CGCTL_ADSPDCGE : 0;
+	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
+
+	/* Update L1SEN bit of EM2 register */
+	val = enable ? SOF_HDA_VS_EM2_L1SEN : 0;
+	snd_hdac_chip_updatel(bus, VS_EM2, SOF_HDA_VS_EM2_L1SEN, val);
+
+	/* Update ADSPPGD bit of PGCTL register */
+	val = enable ? 0 : PCI_TCSEL_ADSPPGD;
+	snd_sof_pci_update_bits(sdev, PCI_TCSEL, PCI_TCSEL_ADSPPGD, val);
+}
+
 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 /*
  * While performing reset, controller may not come back properly and causing

sound/soc/sof/intel/hda.h

@@ -17,9 +17,13 @@
 #define PCI_TCSEL			0x44
 #define PCI_CGCTL			0x48
 
+/* PCI_TVSEL bits */
+#define PCI_TCSEL_ADSPPGD               BIT(2)
+
 /* PCI_CGCTL bits */
 #define PCI_CGCTL_MISCBDCGE_MASK	BIT(6)
 #define PCI_CGCTL_LSRMD_MASK		BIT(4)
+#define PCI_CGCTL_ADSPDCGE              BIT(1)
 
 /* Legacy HDA registers and bits used - widths are variable */
 #define SOF_HDA_GCAP			0x0
@@ -32,6 +36,7 @@
 #define SOF_HDA_WAKESTS			0x0E
 #define SOF_HDA_WAKESTS_INT_MASK	((1 << 8) - 1)
 #define SOF_HDA_RIRBSTS			0x5d
+#define SOF_HDA_VS_EM2_L1SEN            BIT(13)
 
 /* SOF_HDA_GCTL register bist */
 #define SOF_HDA_GCTL_RESET		BIT(0)
@@ -490,6 +495,7 @@ int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev);
 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
+void hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
 
 /*