improvements for armv7a-none-eabi docs

Author: robamu

src/doc/rustc/src/SUMMARY.md

@@ -48,7 +48,6 @@
     - [\*-apple-visionos](platform-support/apple-visionos.md)
     - [aarch64-nintendo-switch-freestanding](platform-support/aarch64-nintendo-switch-freestanding.md)
     - [aarch64-unknown-linux-musl](platform-support/aarch64-unknown-linux-musl.md)
-    - [aarch64-unknown-none{,-softfloat}](aarch64-unknown-none.md)
     - [aarch64_be-unknown-none-softfloat](platform-support/aarch64_be-unknown-none-softfloat.md)
     - [aarch64_be-unknown-linux-musl](platform-support/aarch64_be-unknown-linux-musl.md)
     - [amdgcn-amd-amdhsa](platform-support/amdgcn-amd-amdhsa.md)

src/doc/rustc/src/platform-support/armv7a-none-eabi.md

@@ -24,28 +24,45 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
 
 ## Requirements
 
-All Armv7-A processors include an FPU (a VFPv3 or a VFPv4). The difference
+All known Armv7-A processors include an FPU (a VFPv3 or a VFPv4). The difference
 between the `-eabi` and `-eabihf` targets is whether the FPU is used for
-passing function arguments. You may prefer the `-eabi` soft-float target when 
+passing function arguments. You may prefer the `-eabi` soft-float target when
+the processor does not have a floating point unit or the compiled code should not use the floating
+point unit.
 
 When using the hardfloat targets, the minimum floating-point features assumed
-are those of the `vfpv3-d16`, which includes single- and double-precision,
+are those of the VFPv3-D16, which includes single- and double-precision,
 with 16 double-precision registers. This floating-point unit appears in
-Cortex-A8 and Cortex-A8 processors. See [VFP in the Cortex-A processors][vfp]
+Cortex-A8 and Cortex-A9 processors. See [VFP in the Cortex-A processors][vfp]
 for more details on the possible FPU variants.
 
 If your processor supports a different set of floating-point features than the
-default expectations of `vfpv3-d16`, then these should also be enabled or
+default expectations of VFPv3-D16, then these should also be enabled or
 disabled as needed with `-C target-feature=(+/-)`.
 
+In general, the following four combinations are possible:
+
+- VFPv3-D16, target feature `+vfp3` and `-d32`
+- VFPv3-D32, target feature `+vfp3` and `+d32`
+- VFPv4-D16, target feature `+vfp4` and `-d32`
+- VFPv4-D32, target feature `+vfp4` and `+d32`
+
+An Armv7-A processor may optionally include a NEON hardware unit which provides Single Instruction
+Multiple Data (SIMD) operations. The implementation of this unit implies VFPv3-D32.
+The target feature `+neon` may be added to inform the compiler about the availability of NEON.
+
+You can refer to the [arm-none-eabi](arm-none-eabi.md) documentation for a generic guide on target
+feature and target CPU specification and how to enable and disable them via `.cargo/config.toml`
+file.
+
 [vfp]: https://developer.arm.com/documentation/den0013/0400/Floating-Point/Floating-point-basics-and-the-IEEE-754-standard/ARM-VFP
 
 ## Start-up and Low-Level Code
 
 The [Rust Embedded Devices Working Group Arm Team] maintain the [`cortex-ar`]
 and [`cortex-a-rt`] crates, which may be useful for writing bare-metal code
-using this target. Those crates include several examples which run in QEMU and
-build using these targets.
+using this target. The [`cortex-ar` repository](https://github.com/rust-embedded/cortex-ar)
+includes several examples which run in QEMU and build using these targets.
 
 [`cortex-ar`]: https://docs.rs/cortex-ar
 [`cortex-a-rt`]: https://docs.rs/cortex-a-rt