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teknoman117teknoman117
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add a 25 MHz output to PLL
1 parent 500b9ad commit 79a75bf

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5 files changed

+263
-257
lines changed

5 files changed

+263
-257
lines changed

‎hdl/mojo/ise/shared/coregen/clk_wiz_v3_6.v‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,8 @@
5656
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
5757
//----------------------------------------------------------------------------
5858
// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
59-
// CLK_OUT2____12.500______0.000______50.0_____1800.000____150.000
59+
// CLK_OUT2____25.000______0.000______50.0______300.000____150.000
60+
// CLK_OUT3____12.500______0.000______50.0_____1800.000____150.000
6061
//
6162
//----------------------------------------------------------------------------
6263
// "Input Clock Freq (MHz) Input Jitter (UI)"
@@ -65,12 +66,13 @@
6566

6667
`timescale 1ps/1ps
6768

68-
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
69+
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
6970
module clk_wiz_v3_6
7071
(// Clock in ports
7172
input clk_50_in,
7273
// Clock out ports
7374
output clk_50_out,
75+
output clk_25_out,
7476
output clk_12_5_out,
7577
// Status and control signals
7678
input rst_in,
@@ -96,9 +98,10 @@ module clk_wiz_v3_6
9698
wire clkfb;
9799
wire clk0;
98100
wire clkfx;
101+
wire clkdv;
99102

100103
DCM_SP
101-
#(.CLKDV_DIVIDE (4.000),
104+
#(.CLKDV_DIVIDE (2.000),
102105
.CLKFX_DIVIDE (8),
103106
.CLKFX_MULTIPLY (2),
104107
.CLKIN_DIVIDE_BY_2 ("FALSE"),
@@ -121,7 +124,7 @@ module clk_wiz_v3_6
121124
.CLK2X180 (),
122125
.CLKFX (clkfx),
123126
.CLKFX180 (),
124-
.CLKDV (),
127+
.CLKDV (clkdv),
125128
// Ports for dynamic phase shift
126129
.PSCLK (1'b0),
127130
.PSEN (1'b0),
@@ -147,6 +150,10 @@ module clk_wiz_v3_6
147150

148151

149152
BUFG clkout2_buf
153+
(.O (clk_25_out),
154+
.I (clkdv));
155+
156+
BUFG clkout3_buf
150157
(.O (clk_12_5_out),
151158
.I (clkfx));
152159

‎hdl/mojo/ise/shared/coregen/clk_wiz_v3_6.veo‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,8 @@
5555
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
5656
//----------------------------------------------------------------------------
5757
// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
58-
// CLK_OUT2____12.500______0.000______50.0_____1800.000____150.000
58+
// CLK_OUT2____25.000______0.000______50.0______300.000____150.000
59+
// CLK_OUT3____12.500______0.000______50.0_____1800.000____150.000
5960
//
6061
//----------------------------------------------------------------------------
6162
// "Input Clock Freq (MHz) Input Jitter (UI)"
@@ -73,6 +74,7 @@
7374
.clk_50_in(clk_50_in), // IN
7475
// Clock out ports
7576
.clk_50_out(clk_50_out), // OUT
77+
.clk_25_out(clk_25_out), // OUT
7678
.clk_12_5_out(clk_12_5_out), // OUT
7779
// Status and control signals
7880
.rst_in(rst_in),// IN

‎hdl/mojo/ise/shared/coregen/clk_wiz_v3_6.xco‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
##############################################################
22
#
33
# Xilinx Core Generator version 14.7
4-
# Date: Wed Sep 15 03:00:30 2021
4+
# Date: Thu Sep 16 04:18:53 2021
55
#
66
##############################################################
77
#
@@ -43,9 +43,9 @@ CSET calc_done=DONE
4343
CSET clk_in_sel_port=CLK_IN_SEL
4444
CSET clk_out1_port=clk_50_out
4545
CSET clk_out1_use_fine_ps_gui=false
46-
CSET clk_out2_port=clk_12_5_out
46+
CSET clk_out2_port=clk_25_out
4747
CSET clk_out2_use_fine_ps_gui=false
48-
CSET clk_out3_port=CLK_OUT3
48+
CSET clk_out3_port=clk_12_5_out
4949
CSET clk_out3_use_fine_ps_gui=false
5050
CSET clk_out4_port=CLK_OUT4
5151
CSET clk_out4_use_fine_ps_gui=false
@@ -74,14 +74,14 @@ CSET clkout1_requested_out_freq=50.0
7474
CSET clkout1_requested_phase=0.000
7575
CSET clkout2_drives=BUFG
7676
CSET clkout2_requested_duty_cycle=50.000
77-
CSET clkout2_requested_out_freq=12.5
78-
CSET clkout2_requested_phase=0.000
77+
CSET clkout2_requested_out_freq=25
78+
CSET clkout2_requested_phase=0
7979
CSET clkout2_used=true
8080
CSET clkout3_drives=BUFG
8181
CSET clkout3_requested_duty_cycle=50.000
82-
CSET clkout3_requested_out_freq=100.000
82+
CSET clkout3_requested_out_freq=12.5
8383
CSET clkout3_requested_phase=0.000
84-
CSET clkout3_used=false
84+
CSET clkout3_used=true
8585
CSET clkout4_drives=BUFG
8686
CSET clkout4_requested_duty_cycle=50.000
8787
CSET clkout4_requested_out_freq=100.000
@@ -108,12 +108,12 @@ CSET daddr_port=DADDR
108108
CSET dclk_port=DCLK
109109
CSET dcm_clk_feedback=1X
110110
CSET dcm_clk_out1_port=CLK0
111-
CSET dcm_clk_out2_port=CLKFX
112-
CSET dcm_clk_out3_port=CLK0
113-
CSET dcm_clk_out4_port=CLK0
111+
CSET dcm_clk_out2_port=CLKDV
112+
CSET dcm_clk_out3_port=CLKFX
113+
CSET dcm_clk_out4_port=CLK2X
114114
CSET dcm_clk_out5_port=CLK0
115115
CSET dcm_clk_out6_port=CLK0
116-
CSET dcm_clkdv_divide=4.0
116+
CSET dcm_clkdv_divide=2.0
117117
CSET dcm_clkfx_divide=8
118118
CSET dcm_clkfx_multiply=2
119119
CSET dcm_clkgen_clk_out1_port=CLKFX
@@ -189,7 +189,7 @@ CSET mmcm_notes=None
189189
CSET mmcm_ref_jitter1=0.010
190190
CSET mmcm_ref_jitter2=0.010
191191
CSET mmcm_startup_wait=false
192-
CSET num_out_clks=2
192+
CSET num_out_clks=3
193193
CSET override_dcm=false
194194
CSET override_dcm_clkgen=false
195195
CSET override_mmcm=false
@@ -266,4 +266,4 @@ CSET use_status=false
266266
MISC pkg_timestamp=2012-05-10T12:44:55Z
267267
# END Extra information
268268
GENERATE
269-
# CRC: 3ddebbca
269+
# CRC: 5bbe592

‎hdl/mojo/ise/shared/coregen/clk_wiz_v3_6.xise‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -379,8 +379,8 @@
379379
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
380380
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
381381
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
382-
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-09-14T20:00:45" xil_pn:valueState="non-default"/>
383-
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F14FC94E2F21EE40A287576848C02289" xil_pn:valueState="non-default"/>
382+
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-09-15T21:19:07" xil_pn:valueState="non-default"/>
383+
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8147A6BCD7F8A64B61CF18E07671CAAE" xil_pn:valueState="non-default"/>
384384
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
385385
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
386386
</properties>

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