Skip to content

Commit 2c39695

Browse files
teknoman117teknoman117
committed
read and write to bus complete
1 parent 6467945 commit 2c39695

File tree

3 files changed

+132
-68
lines changed

3 files changed

+132
-68
lines changed

‎hdl/mojo/ise/bus-to-uart/m68k_tester.v‎

Lines changed: 86 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ ODDR2 m68k_CLK_buffer(
7070

7171
// M68K data bus control
7272
wire [15:0] m68k_D_out;
73-
wire [15:0] m68k_D_in;
73+
wire [15:0] m68k_D_in = m68k_D;
7474
assign m68k_D[7:0] = (m68k_RW & ~m68k_LDS_n) ? m68k_D_out[7:0] : 8'dZ;
7575
assign m68k_D[15:8] = (m68k_RW & ~m68k_UDS_n) ? m68k_D_out[15:8] : 8'dZ;
7676

@@ -136,20 +136,20 @@ end
136136
assign m68k_RESET_in = ~m68k_RESET_in_n_q;
137137

138138
// synchronize the m68k bus signals with the FPGA
139-
reg [23:0] a_sample;
140-
reg [15:0] d_sample;
141-
reg [2:0] fc_sample;
142-
reg as_sample;
143-
reg lds_sample;
144-
reg uds_sample;
145-
reg rw_sample;
146-
reg bg_sample;
139+
reg [23:0] a_sample = 24'h0;
140+
reg [15:0] d_sample = 16'h0;
141+
reg [2:0] fc_sample = 3'h0;
142+
reg as_sample = 1'h0;
143+
reg lds_sample = 1'h0;
144+
reg uds_sample = 1'h0;
145+
reg rw_sample = 1'h0;
146+
reg bg_sample = 1'h0;
147147

148148
always @(posedge clk_m68k_sample) begin
149149
if (~m68k_RESET_out_n) begin
150-
a_sample <= 24'hFFFFFF;
151-
d_sample <= 16'hFFFF;
152-
fc_sample <= 3'h7;
150+
a_sample <= 24'h0;
151+
d_sample <= 16'h0;
152+
fc_sample <= 3'h0;
153153
as_sample <= 1'd0;
154154
lds_sample <= 1'd0;
155155
uds_sample <= 1'd0;
@@ -169,29 +169,88 @@ end
169169

170170
// system logic reading synchronized m68k bus signals
171171

172-
// Address Strobe edges
173-
reg as_edge;
172+
// Address and Data Strobe edges
173+
reg as_edge = 1'd0;
174+
reg lds_edge = 1'd0;
175+
reg uds_edge = 1'd0;
174176
always @(posedge clk_sys) begin
175-
if (rst) begin
177+
if (~m68k_RESET_out_n) begin
176178
as_edge <= 1'd0;
179+
lds_edge <= 1'd0;
180+
uds_edge <= 1'd0;
177181
end else begin
178182
as_edge <= as_sample;
183+
lds_edge <= lds_sample;
184+
uds_edge <= uds_sample;
179185
end
180186
end
181187

182-
wire as_asserted;
183-
wire as_deasserted;
184-
assign as_asserted = ~as_edge & as_sample;
185-
assign as_deasserted = as_edge & ~as_sample;
188+
wire as_asserted = ~as_edge & as_sample;
189+
wire lds_asserted = ~lds_edge & lds_sample;
190+
wire uds_asserted = ~uds_edge & uds_sample;
191+
wire as_deasserted = as_edge & ~as_sample;
192+
193+
// transmit data state machine
194+
localparam TX_STATE_IDLE = 7'd1;
195+
localparam TX_STATE_ADDRESS_3 = 7'd2;
196+
localparam TX_STATE_ADDRESS_2 = 7'd4;
197+
localparam TX_STATE_ADDRESS_1 = 7'd8;
198+
localparam TX_STATE_SIGNALS = 7'd16;
199+
localparam TX_STATE_DATA_H = 7'd32;
200+
localparam TX_STATE_DATA_L = 7'd64;
201+
202+
reg [6:0] TX_state = TX_STATE_IDLE;
203+
always @(posedge clk_sys) begin
204+
if (~m68k_RESET_out_n) begin
205+
TX_state <= TX_STATE_IDLE;
206+
end else if (TX_state[0] & (lds_asserted | uds_asserted)) begin
207+
// data phase started, begin transmission
208+
TX_state <= TX_STATE_ADDRESS_3;
209+
end else if (~avr_data_out_busy) begin
210+
// byte was possibly transmitted, advance state
211+
if (TX_state[1]) begin
212+
TX_state <= TX_STATE_ADDRESS_2;
213+
end else if (TX_state[2]) begin
214+
TX_state <= TX_STATE_ADDRESS_1;
215+
end else if (TX_state[3]) begin
216+
TX_state <= TX_STATE_SIGNALS;
217+
end else if (TX_state[4]) begin
218+
TX_state <= TX_STATE_DATA_H;
219+
end else if (TX_state[5]) begin
220+
TX_state <= TX_STATE_DATA_L;
221+
end else if (TX_state[6]) begin
222+
TX_state <= TX_STATE_IDLE;
223+
end
224+
end
225+
end
226+
227+
// output data select
228+
reg [7:0] TX_data;
229+
wire [7:0] bus_signals = {2'd0, fc_sample, rw_sample, uds_sample, lds_sample};
230+
always @(*) begin
231+
case (TX_state)
232+
TX_STATE_IDLE: TX_data = 8'd0;
233+
TX_STATE_ADDRESS_3: TX_data = a_sample[23:16];
234+
TX_STATE_ADDRESS_2: TX_data = a_sample[15:8];
235+
TX_STATE_ADDRESS_1: TX_data = a_sample[7:0];
236+
TX_STATE_SIGNALS: TX_data = bus_signals;
237+
TX_STATE_DATA_H: TX_data = d_sample[15:8];
238+
TX_STATE_DATA_L: TX_data = d_sample[7:0];
239+
default: TX_data = 8'd0;
240+
endcase
241+
end
242+
243+
assign avr_data_out = TX_data;
244+
assign avr_data_out_ready = |TX_state[6:1] & ~avr_data_out_busy;
186245

187246
// DTACK and BERR driver
188-
reg dtack;
189-
reg berr;
247+
reg dtack = 1'd0;
248+
reg berr = 1'd0;
190249
wire cycle_end_success;
191250
wire cycle_end_failure;
192251

193252
always @(posedge clk_sys) begin
194-
if (rst) begin
253+
if (~m68k_RESET_out_n) begin
195254
dtack <= 1'd0;
196255
berr <= 1'd0;
197256
end else if (as_deasserted) begin
@@ -210,21 +269,17 @@ end
210269
assign m68k_DTACK_n = ~dtack;
211270
assign m68k_BERR_n = ~berr;
212271

213-
// send uart char on assert
214-
assign avr_data_out = 8'h41;
215-
assign avr_data_out_ready = as_asserted;
216-
217272
// received data state machine
218273
localparam RCVR_STATE_IDLE = 4'd1;
219274
localparam RCVR_STATE_LOAD_BYTE_1 = 4'd2;
220275
localparam RCVR_STATE_LOAD_BYTE_2 = 4'd4;
221276
localparam RCVR_STATE_LOAD_BYTE_L = 4'd8;
222277

223-
reg [15:0] m68k_D_out_buffer;
224-
reg [3:0] RCVR_state;
278+
reg [15:0] m68k_D_out_buffer = 16'd0;
279+
reg [3:0] RCVR_state = RCVR_STATE_IDLE;
225280

226281
always @(posedge clk_sys) begin
227-
if (rst) begin
282+
if (~m68k_RESET_out_n) begin
228283
RCVR_state <= RCVR_STATE_IDLE;
229284
m68k_D_out_buffer <= 16'd0;
230285
end else if (avr_data_in_ready) begin
@@ -259,10 +314,10 @@ assign cycle_end_success = RCVR_state[0] & avr_data_in_ready & (avr_data_in == 8
259314
assign cycle_end_failure = RCVR_state[0] & avr_data_in_ready & (avr_data_in == 8'h45);
260315

261316
// assign leds on the start of the bus cycle
262-
reg [7:0] leds_q;
317+
reg [7:0] leds_q = 8'd0;
263318
assign led = leds_q;
264319
always @(posedge clk_sys) begin
265-
if (rst) begin
320+
if (~m68k_RESET_out_n) begin
266321
leds_q <= 8'd0;
267322
end else if (as_asserted) begin
268323
leds_q <= m68k_A[8:1];

‎src/monitor/monitor.py‎

100644100755
Lines changed: 45 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,45 +1,54 @@
1+
#!/usr/bin/env python
2+
13
import serial
24

35
interface = serial.Serial('/dev/ttyACM0', 500000, timeout=60)
46

57
while (True):
6-
# get a cmd value
7-
op = interface.read(1)[0]
8-
9-
# op[7:4] is the op type, op[3:0] depends on the command
10-
if (op & 0xf0) == 0x10:
11-
# A operation
12-
data = interface.read(3)
13-
address = int.from_bytes(data, byteorder='big', signed=False)
14-
print("Address: 0x{:06x}".format(address))
8+
# read address for bus cycle
9+
address_in = interface.read(3)
10+
address = int.from_bytes(address_in, byteorder='big', signed=False)
1511

16-
elif (op & 0xf0) == 0x20:
17-
# D operation
18-
uds = (op & 0x02) != 0;
19-
lds = (op & 0x01) != 0;
20-
if (op & 0x04) != 0:
21-
# read operation
22-
data = input("Read Data (high = {}, low = {}) = ".format(uds, lds))
23-
value = int(data, 16)
24-
if (uds and lds):
25-
data = value.to_bytes(2, byteorder='big', signed=False)
26-
interface.write(data)
27-
else:
28-
data = value.to_bytes(1, byteorder='big', signed=False)
29-
interface.write(data)
12+
# bus cycle
13+
op = int(interface.read(1)[0])
14+
data_in = interface.read(2)
3015

31-
else:
32-
# write operation
33-
print("Write Data (high = {}, low = {}) = ".format(uds, lds))
34-
if (uds and lds):
35-
data = interface.read(2)
36-
value = int.from_bytes(data, byteorder='big', signed=False)
37-
print("0x{:04x}".format(value))
38-
else:
39-
data = interface.read(1)
40-
value = int.from_bytes(data, byteorder='big', signed=False)
41-
print("0x{:02x}".format(0))
16+
fc = (op >> 0x3) & 0x7
4217

43-
# write ack
44-
interface.write(bytearray([0xaa]))
18+
if (op & 0x04) == 0:
19+
# write cycle
20+
# low byte cycle
21+
if (op & 0x3) == 0x1:
22+
print("Address 0x{:06x}: Wrote Byte: 0x{:02x}".format(address, data_in[1]))
23+
# high byte cycle
24+
elif (op & 0x3) == 0x2:
25+
print("Address 0x{:06x}: Wrote Byte: 0x{:02x}".format(address+1, data_in[0]))
26+
# word cycle
27+
elif (op & 0x3) == 0x3:
28+
word = int.from_bytes(data_in, byteorder='big', signed=False)
29+
print("Address 0x{:06x}: Wrote Word: 0x{:04x}".format(address, word))
30+
# response
31+
response = bytes('D', 'ascii')
32+
else:
33+
# read cycle
34+
# low byte cycle
35+
if (op & 0x3) == 0x1:
36+
data = input("Address 0x{:06x}: Read Byte: ".format(address))
37+
value = int(data, 16)
38+
response = bytearray('L', 'ascii')
39+
response.extend(value.to_bytes(1, byteorder='little', signed=False))
40+
elif (op & 0x3) == 0x2:
41+
data = input("Address 0x{:06x}: Read Byte: ".format(address+1))
42+
value = int(data, 16)
43+
response = bytearray('H', 'ascii')
44+
response.extend(value.to_bytes(1, byteorder='little', signed=False))
45+
elif (op & 0x3) == 0x3:
46+
data = input("Address 0x{:06x}: Read Word: ".format(address))
47+
value = int(data, 16)
48+
response = bytearray('B', 'ascii')
49+
response.extend(value.to_bytes(2, byteorder='little', signed=False))
50+
# response
51+
response.extend(bytes('D', 'ascii'))
4552

53+
# write response
54+
interface.write(response)

‎src/test3/test.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ _start:
88
move.w #0xaaaa, %d0
99
move.w _display, %a0
1010
_loop:
11-
move.w %d0, (%a0)
11+
move.w %d0, (%a0)+
1212
not.w %d0
1313
bra.s _loop
1414

0 commit comments

Comments
 (0)