Implement VirtIO PCI transport layer

[shengwen-tw]

Background

During the development of VirtIO GPU in #34, a critical issue was identified: applications leveraging Mesa3D (e.g., glxgears, kmscube) consistently fall back to software rendering (softpipe), despite a correct configuration of X11, Mesa3D, and a host virglrenderer.

Analysis suggests this behavior is likely due to the current implementation of VirtIO GPU being based on VirtIO MMIO (registered as a platform device via the device tree), rather than utilizing the VirtIO PCI transport layer. Key observations include:

• GLX/X11 path: Mesa3D does not load virtio_gpu_dri.so because Xorg fails to initialize DRI2.
• Xorg logs: The GPU is not recognized as a PCI device (no primary bus or device found), which prevents DRI2 from initializing and causes a fallback to the software renderer (swrast).

[    29.010] (II) Platform probe for /sys/devices/platform/soc@F0000000/f4800000.virtio/drm/card0                                                 
[    29.018] (II) no primary bus or device found                                                                                                  
[    29.018]    falling back to /sys/devices/platform/soc@F0000000/f4800000.virtio/drm/card0
...
[    29.354] (II) modeset(0): using drv /dev/dri/card0                                                                      
...
[    29.666] (II) AIGLX: Screen 0 is not DRI2 capable
[    31.222] (II) IGLX: Loaded and initialized swrast

Proposal

To resolve this limitation and enable proper VirGL hardware acceleration, I propose implementing a VirtIO PCI transport layer for VirtIO GPU.

[shengwen-tw]

PCIe Spec.

PCI Express Base Specification, Revision 2.1 (Apr 15, 2003)

• 7.5.2 Type 0 Configuration Space Header

---

Enhanced Configuration Access Mechanism (ECAM)

PCIe uses ECAM (Enhanced Configuration Access Mechanism) where each PCI function has a fixed 4KiB configuration space. The memory address of a function can be calculated with:

ECAM_ADDRESS = ECAM_BASE
             + (bus_number     << 20)
             + (device_number  << 15)
             + (function_number << 12)

https://en.wikipedia.org/wiki/PCI_configuration_space
PCI-X 2.0 and PCI Express introduced an extended configuration space, up to 4096 bytes.

Assuming 16MiB space of memory preserved for PCIe ECAM:

Field	Shift	Block Size	Max Capacity
Bus	<< 20	1MiB per bus	Up to 16 buses (16MiB)
Device	<< 15	32KiB per dev	32 devices per bus
Function	<< 12	4KiB per func	8 functions per device