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Add doc comments for some concrete SIMD overloads. (#81890)
Also removed concrete SIMDMask(lowHalf:highHalf:) init, as there is no corresponding generic operation; it was added in error.
1 parent 82e6d7b commit 4007e44

6 files changed

+57
-63
lines changed

stdlib/public/core/SIMDFloatConcreteOperations.swift.gyb

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,15 @@ extension SIMD${n} where Scalar == ${Scalar} {
3434
_storage = ${Scalar}.SIMD${storageN}Storage(_builtin)
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}
3636

37+
/// A vector with the specified scalar in all lanes.
38+
///
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/// Equivalent to:
40+
/// ```
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/// var result = SIMD${n}<${Scalar}>()
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/// for i in result.indices {
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/// result[i] = scalar
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/// }
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/// ```
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@_alwaysEmitIntoClient @_transparent
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public init(repeating scalar: ${Scalar}) {
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let asVector = Builtin.insertelement_${Builtin}_FPIEEE${bits}_Int32(
@@ -52,6 +61,16 @@ extension SIMD${n} where Scalar == ${Scalar} {
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}
5362

5463
% if n >= 4:
64+
/// A vector formed by concatenating lowHalf and highHalf.
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///
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/// Equivalent to:
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/// ```
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/// var result = SIMD${n}<${Scalar}>()
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/// for i in 0..<${n//2} {
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/// result[i] = lowHalf[i]
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/// result[${n//2}+i] = highHalf[i]
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/// }
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/// ```
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@_alwaysEmitIntoClient @_transparent
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public init(
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lowHalf: SIMD${n//2}<${Scalar}>,

stdlib/public/core/SIMDIntegerConcreteOperations.swift.gyb

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,15 @@ extension SIMD${n} where Scalar == ${Scalar} {
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_storage = ${Scalar}.SIMD${storageN}Storage(_builtin)
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}
3333

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/// A vector with the specified scalar in all lanes.
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///
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/// Equivalent to:
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/// ```
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/// var result = SIMD${n}<${Scalar}>()
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/// for i in result.indices {
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/// result[i] = scalar
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/// }
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/// ```
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@_alwaysEmitIntoClient @_transparent
3544
public init(repeating scalar: ${Scalar}) {
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let asVector = Builtin.insertelement_${Builtin}_Int${int.bits}_Int32(
@@ -49,6 +58,16 @@ extension SIMD${n} where Scalar == ${Scalar} {
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}
5059

5160
% if n >= 4:
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/// A vector formed by concatenating lowHalf and highHalf.
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///
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/// Equivalent to:
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/// ```
65+
/// var result = SIMD${n}<${Scalar}>()
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/// for i in 0..<${n//2} {
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/// result[i] = lowHalf[i]
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/// result[${n//2}+i] = highHalf[i]
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/// }
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/// ```
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@_alwaysEmitIntoClient @_transparent
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public init(
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lowHalf: SIMD${n//2}<${Scalar}>,

stdlib/public/core/SIMDMaskConcreteOperations.swift.gyb

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -36,19 +36,6 @@ extension SIMDMask where Storage == ${Vector} {
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_storage = ${Vector}(repeating: scalar ? -1 : 0)
3737
}
3838

39-
% if n >= 4:
40-
@_alwaysEmitIntoClient @_transparent
41-
public init(
42-
lowHalf: SIMDMask<SIMD${n//2}<${Scalar}>>,
43-
highHalf: SIMDMask<SIMD${n//2}<${Scalar}>>
44-
) {
45-
_storage = ${Vector}(
46-
lowHalf: lowHalf._storage,
47-
highHalf: highHalf._storage
48-
)
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}
50-
51-
% end
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@_alwaysEmitIntoClient
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internal static var allTrue: Self {
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let zero = ${Vector}()

stdlib/public/core/SIMDVector.swift

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,15 @@ extension SIMD {
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return 0 ..< scalarCount
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}
113113

114-
/// A vector with the specified value in all lanes.
114+
/// A vector with the specified scalar in all lanes.
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///
116+
/// Equivalent to:
117+
/// ```
118+
/// var result = Self()
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/// for i in result.indices {
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/// result[i] = scalar
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/// }
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/// ```
115123
@_transparent
116124
public init(repeating value: Scalar) {
117125
self.init()

stdlib/public/core/SIMDVectorTypes.swift.gyb

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,16 @@ public struct SIMD${n}<Scalar>: SIMD where Scalar: SIMDScalar {
8888
% end
8989
% end
9090
% if n >= 4:
91-
/// Creates a new vector from two half-length vectors.
91+
/// A vector formed by concatenating lowHalf and highHalf.
92+
///
93+
/// Equivalent to:
94+
/// ```
95+
/// var result = SIMD${n}<Scalar>()
96+
/// for i in 0..<${n//2} {
97+
/// result[i] = lowHalf[i]
98+
/// result[${n//2}+i] = highHalf[i]
99+
/// }
100+
/// ```
92101
@_transparent
93102
public init(lowHalf: SIMD${n//2}<Scalar>, highHalf: SIMD${n//2}<Scalar>) {
94103
self.init()

test/stdlib/SIMDMaskInitializers.swift.gyb

Lines changed: 0 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -34,51 +34,3 @@ func repeating${n}_mask${bits}(_ scalar: Bool) -> SIMDMask<SIMD${n}<Int${bits}>>
3434
% end
3535
% end
3636
%end
37-
38-
func concat8x8(_ a: SIMDMask<SIMD8<Int8>>, _ b: SIMDMask<SIMD8<Int8>>) -> SIMDMask<SIMD16<Int8>> {
39-
SIMDMask(lowHalf: a, highHalf: b)
40-
}
41-
// CHECK: s20SIMDMaskInitializers9concat8x8ys0A0Vys6SIMD16Vys4Int8VGGADys5SIMD8VyAHGG_ANtF:
42-
// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
43-
// CHECKO-arm64-NEXT: ret
44-
// CHECKO-x86_64: punpcklqdq
45-
46-
func concat16x8(_ a: SIMDMask<SIMD16<Int8>>, _ b: SIMDMask<SIMD16<Int8>>) -> SIMDMask<SIMD32<Int8>> {
47-
SIMDMask(lowHalf: a, highHalf: b)
48-
}
49-
// CHECK: s20SIMDMaskInitializers10concat16x8ys0A0Vys6SIMD32Vys4Int8VGGADys6SIMD16VyAHGG_ANtF:
50-
// CHECKO-arm64-NEXT: ret
51-
52-
func concat4x16(_ a: SIMDMask<SIMD4<Int16>>, _ b: SIMDMask<SIMD4<Int16>>) -> SIMDMask<SIMD8<Int16>> {
53-
SIMDMask(lowHalf: a, highHalf: b)
54-
}
55-
// CHECK: s20SIMDMaskInitializers10concat4x16ys0A0Vys5SIMD8Vys5Int16VGGADys5SIMD4VyAHGG_ANtF:
56-
// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
57-
// CHECKO-arm64-NEXT: ret
58-
// CHECKO-x86_64: punpcklqdq
59-
60-
func concat8x16(_ a: SIMDMask<SIMD8<Int16>>, _ b: SIMDMask<SIMD8<Int16>>) -> SIMDMask<SIMD16<Int16>> {
61-
SIMDMask(lowHalf: a, highHalf: b)
62-
}
63-
// CHECK: s20SIMDMaskInitializers10concat8x16ys0A0Vys6SIMD16Vys5Int16VGGADys5SIMD8VyAHGG_ANtF:
64-
// CHECKO-arm64-NEXT: ret
65-
66-
func concat2x32(_ a: SIMDMask<SIMD2<Int32>>, _ b: SIMDMask<SIMD2<Int32>>) -> SIMDMask<SIMD4<Int32>> {
67-
SIMDMask(lowHalf: a, highHalf: b)
68-
}
69-
// CHECK: s20SIMDMaskInitializers10concat2x32ys0A0Vys5SIMD4Vys5Int32VGGADys5SIMD2VyAHGG_ANtF:
70-
// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
71-
// CHECKO-arm64-NEXT: ret
72-
// CHECKO-x86_64: punpcklqdq
73-
74-
func concat4x32(_ a: SIMDMask<SIMD4<Int32>>, _ b: SIMDMask<SIMD4<Int32>>) -> SIMDMask<SIMD8<Int32>> {
75-
SIMDMask(lowHalf: a, highHalf: b)
76-
}
77-
// CHECK: s20SIMDMaskInitializers10concat4x32ys0A0Vys5SIMD8Vys5Int32VGGADys5SIMD4VyAHGG_ANtF:
78-
// CHECKO-arm64-NEXT: ret
79-
80-
func concat2x64(_ a: SIMDMask<SIMD2<Int64>>, _ b: SIMDMask<SIMD2<Int64>>) -> SIMDMask<SIMD4<Int64>> {
81-
SIMDMask(lowHalf: a, highHalf: b)
82-
}
83-
// CHECK: s20SIMDMaskInitializers10concat2x64ys0A0Vys5SIMD4Vys5Int64VGGADys5SIMD2VyAHGG_ANtF:
84-
// CHECKO-arm64-NEXT: ret

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