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[GlobalISel] Add G_ABS computeKnownBits (llvm#154413)
The code is taken from `SelectionDAG::computeKnownBits`. This ticks off ABS from llvm#150515
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+98
-20
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4 files changed

+98
-20
lines changed

‎llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -675,6 +675,14 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
675675
}
676676
break;
677677
}
678+
case TargetOpcode::G_ABS: {
679+
Register SrcReg = MI.getOperand(1).getReg();
680+
computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
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Known = Known.abs();
682+
Known.Zero.setHighBits(computeNumSignBits(SrcReg, DemandedElts, Depth + 1) -
683+
1);
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break;
685+
}
678686
}
679687

680688
LLVM_DEBUG(dumpResult(MI, Known, Depth));

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir‎

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,83 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=aarch64 -passes='print<gisel-value-tracking>' -filetype=null %s 2>&1 | FileCheck %s
3+
4+
---
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name: Cst
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body: |
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bb.0:
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; CHECK-LABEL: name: @Cst
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; CHECK-NEXT: %0:_ KnownBits:00010011 SignBits:3
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; CHECK-NEXT: %1:_ KnownBits:00010011 SignBits:3
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%0:_(s8) = G_CONSTANT i8 19
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%1:_(s8) = G_ABS %0
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...
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---
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name: CstNeg
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body: |
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bb.0:
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; CHECK-LABEL: name: @CstNeg
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; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
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; CHECK-NEXT: %1:_ KnownBits:00010010 SignBits:3
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%0:_(s8) = G_CONSTANT i8 238
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%1:_(s8) = G_ABS %0
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...
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---
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name: SplatVecCst
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body: |
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bb.0:
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; CHECK-LABEL: name: @SplatVecCst
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; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
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; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
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; CHECK-NEXT: %2:_ KnownBits:00000110 SignBits:5
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%0:_(s8) = G_CONSTANT i8 250
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%1:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %0(s8)
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%2:_(<vscale x 16 x s8>) = G_ABS %1
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...
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---
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name: VecCst
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body: |
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bb.0:
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; CHECK-LABEL: name: @VecCst
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; CHECK-NEXT: %0:_ KnownBits:00011001 SignBits:3
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; CHECK-NEXT: %1:_ KnownBits:11100001 SignBits:3
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; CHECK-NEXT: %2:_ KnownBits:?????001 SignBits:3
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; CHECK-NEXT: %3:_ KnownBits:00?????1 SignBits:2
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%0:_(s8) = G_CONSTANT i8 25
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%1:_(s8) = G_CONSTANT i8 225
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%2:_(<2 x s8>) = G_BUILD_VECTOR %0:_(s8), %1:_(s8)
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%3:_(<2 x s8>) = G_ABS %2
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...
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---
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name: ImplicitDef
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body: |
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bb.0:
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; CHECK-LABEL: name: @ImplicitDef
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; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
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; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
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%0:_(s8) = G_IMPLICIT_DEF
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%1:_(s8) = G_ABS %0
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...
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---
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name: CstSext
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body: |
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bb.0:
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; CHECK-LABEL: name: @CstSext
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; CHECK-NEXT: %0:_ KnownBits:11000111 SignBits:2
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; CHECK-NEXT: %1:_ KnownBits:1111111111000111 SignBits:10
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; CHECK-NEXT: %2:_ KnownBits:0000000000111001 SignBits:10
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%0:_(s8) = G_CONSTANT i8 199
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%1:_(s16) = G_SEXT %0
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%2:_(s16) = G_ABS %1
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...
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---
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name: ImplicitDefSext
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body: |
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bb.0:
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; CHECK-LABEL: name: @ImplicitDefSext
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; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
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; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
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; CHECK-NEXT: %2:_ KnownBits:00000000???????? SignBits:8
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%0:_(s8) = G_IMPLICIT_DEF
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%1:_(s16) = G_SEXT %0
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%2:_(s16) = G_ABS %1
83+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir‎

Lines changed: 6 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -302,11 +302,8 @@ body: |
302302
; SI-NEXT: [[ABS:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG]]
303303
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
304304
; SI-NEXT: [[ABS1:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG1]]
305-
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
306-
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ABS]], [[C1]]
307-
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ABS1]], [[C1]]
308-
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
309-
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
305+
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ABS1]], [[C]](s32)
306+
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ABS]], [[SHL]]
310307
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
311308
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
312309
;
@@ -429,16 +426,11 @@ body: |
429426
; SI-NEXT: [[ABS2:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG2]]
430427
; SI-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
431428
; SI-NEXT: [[ABS3:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG3]]
432-
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
433-
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ABS]], [[C1]]
434-
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ABS1]], [[C1]]
435-
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
436-
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
429+
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ABS1]], [[C]](s32)
430+
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ABS]], [[SHL]]
437431
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
438-
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ABS2]], [[C1]]
439-
; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ABS3]], [[C1]]
440-
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
441-
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
432+
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ABS3]], [[C]](s32)
433+
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ABS2]], [[SHL1]]
442434
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
443435
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
444436
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll‎

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -459,8 +459,6 @@ define amdgpu_cs <2 x i16> @abs_sgpr_v2i16(<2 x i16> inreg %arg) {
459459
; GFX8-NEXT: s_sext_i32_i16 s0, s0
460460
; GFX8-NEXT: s_abs_i32 s1, s1
461461
; GFX8-NEXT: s_abs_i32 s0, s0
462-
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
463-
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
464462
; GFX8-NEXT: s_lshl_b32 s1, s1, 16
465463
; GFX8-NEXT: s_or_b32 s0, s0, s1
466464
; GFX8-NEXT: ; return to shader part epilog
@@ -548,12 +546,9 @@ define amdgpu_cs <3 x i16> @abs_sgpr_v3i16(<3 x i16> inreg %arg) {
548546
; GFX8-NEXT: s_abs_i32 s2, s2
549547
; GFX8-NEXT: s_abs_i32 s0, s0
550548
; GFX8-NEXT: s_sext_i32_i16 s1, s1
551-
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
552-
; GFX8-NEXT: s_abs_i32 s1, s1
553-
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
554549
; GFX8-NEXT: s_lshl_b32 s2, s2, 16
550+
; GFX8-NEXT: s_abs_i32 s1, s1
555551
; GFX8-NEXT: s_or_b32 s0, s0, s2
556-
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
557552
; GFX8-NEXT: ; return to shader part epilog
558553
;
559554
; GFX10-LABEL: abs_sgpr_v3i16:

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