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Petar AvramovicPetar Avramovic
Petar Avramovic
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Petar Avramovic
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[MIParser] Set RegClassOrRegBank during instruction parsing
MachineRegisterInfo::createGenericVirtualRegister sets RegClassOrRegBank to static_cast<RegisterBank *>(nullptr). MIParser on the other hand doesn't. When we attempt to constrain Register Class on such VReg, additional COPY is generated. This way we avoid COPY instructions showing in test that have MIR input while they are not present with llvm-ir input that was used to create given MIR for a -run-pass test. Differential Revision: https://reviews.llvm.org/D68946 llvm-svn: 375502
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-41
lines changed

4 files changed

+29
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lines changed

‎llvm/lib/CodeGen/MIRParser/MIParser.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1437,6 +1437,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
14371437
if (MRI.getType(Reg).isValid() && MRI.getType(Reg) != Ty)
14381438
return error("inconsistent type for generic virtual register");
14391439

1440+
MRI.setRegClassOrRegBank(Reg, static_cast<RegisterBank *>(nullptr));
14401441
MRI.setType(Reg, Ty);
14411442
}
14421443
}
@@ -1455,6 +1456,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
14551456
if (MRI.getType(Reg).isValid() && MRI.getType(Reg) != Ty)
14561457
return error("inconsistent type for generic virtual register");
14571458

1459+
MRI.setRegClassOrRegBank(Reg, static_cast<RegisterBank *>(nullptr));
14581460
MRI.setType(Reg, Ty);
14591461
} else if (Register::isVirtualRegister(Reg)) {
14601462
// Generic virtual registers must have a type.

‎llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
33

4-
# Check there are COPY instructions surrounding ADDVI_W instruction.
5-
# MIParser does not set RegClassOrRegBank for parsed virtual registers.
4+
# Check there are no COPY instructions surrounding ADDVI_W instruction.
5+
# MIParser sets RegClassOrRegBank for parsed virtual registers.
66
# Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
7-
# gets selected into ADDVI_W creates additional copies.
8-
# FixMe: Make sure this test has same output as setRegClassOrRegBank.ll.
7+
# gets selected into ADDVI_W works as expected.
8+
# Check that setRegClassOrRegBank.ll has same output.
99

1010
--- |
1111

@@ -25,11 +25,9 @@ body: |
2525
; P5600: liveins: $a0, $a1
2626
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
2727
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
28-
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
29-
; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
30-
; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
31-
; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
32-
; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
28+
; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
29+
; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
30+
; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
3331
; P5600: RetRA
3432
%0:_(p0) = COPY $a0
3533
%1:_(p0) = COPY $a1

‎llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -151,11 +151,9 @@ body: |
151151
; P5600: liveins: $a0, $a1
152152
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
153153
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
154-
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
155-
; P5600: [[COPY2:%[0-9]+]]:msa128b = COPY [[LOAD]](<16 x s8>)
156-
; P5600: [[ADDVI_B:%[0-9]+]]:msa128b = ADDVI_B [[COPY2]], 3
157-
; P5600: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ADDVI_B]]
158-
; P5600: G_STORE [[COPY3]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c)
154+
; P5600: [[LOAD:%[0-9]+]]:msa128b(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
155+
; P5600: [[ADDVI_B:%[0-9]+]]:msa128b(<16 x s8>) = ADDVI_B [[LOAD]](<16 x s8>), 3
156+
; P5600: G_STORE [[ADDVI_B]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c)
159157
; P5600: RetRA
160158
%0:_(p0) = COPY $a0
161159
%1:_(p0) = COPY $a1
@@ -177,11 +175,9 @@ body: |
177175
; P5600: liveins: $a0, $a1
178176
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
179177
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
180-
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
181-
; P5600: [[COPY2:%[0-9]+]]:msa128h = COPY [[LOAD]](<8 x s16>)
182-
; P5600: [[ADDVI_H:%[0-9]+]]:msa128h = ADDVI_H [[COPY2]], 18
183-
; P5600: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ADDVI_H]]
184-
; P5600: G_STORE [[COPY3]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
178+
; P5600: [[LOAD:%[0-9]+]]:msa128h(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
179+
; P5600: [[ADDVI_H:%[0-9]+]]:msa128h(<8 x s16>) = ADDVI_H [[LOAD]](<8 x s16>), 18
180+
; P5600: G_STORE [[ADDVI_H]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
185181
; P5600: RetRA
186182
%0:_(p0) = COPY $a0
187183
%1:_(p0) = COPY $a1
@@ -203,11 +199,9 @@ body: |
203199
; P5600: liveins: $a0, $a1
204200
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
205201
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
206-
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
207-
; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
208-
; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
209-
; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
210-
; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
202+
; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
203+
; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
204+
; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
211205
; P5600: RetRA
212206
%0:_(p0) = COPY $a0
213207
%1:_(p0) = COPY $a1
@@ -229,11 +223,9 @@ body: |
229223
; P5600: liveins: $a0, $a1
230224
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
231225
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
232-
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
233-
; P5600: [[COPY2:%[0-9]+]]:msa128d = COPY [[LOAD]](<2 x s64>)
234-
; P5600: [[ADDVI_D:%[0-9]+]]:msa128d = ADDVI_D [[COPY2]], 31
235-
; P5600: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ADDVI_D]]
236-
; P5600: G_STORE [[COPY3]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
226+
; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
227+
; P5600: [[ADDVI_D:%[0-9]+]]:msa128d(<2 x s64>) = ADDVI_D [[LOAD]](<2 x s64>), 31
228+
; P5600: G_STORE [[ADDVI_D]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
237229
; P5600: RetRA
238230
%0:_(p0) = COPY $a0
239231
%1:_(p0) = COPY $a1

‎llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -343,21 +343,19 @@ body: |
343343
344344
; FP32-LABEL: name: u32tof32
345345
; FP32: liveins: $a0
346-
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
346+
; FP32: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0
347347
; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
348-
; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
349-
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32)
348+
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY]](s32), [[C]](s32)
350349
; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
351350
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]]
352351
; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
353352
; FP32: $f0 = COPY [[FPTRUNC]](s32)
354353
; FP32: RetRA implicit $f0
355354
; FP64-LABEL: name: u32tof32
356355
; FP64: liveins: $a0
357-
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
356+
; FP64: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0
358357
; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
359-
; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
360-
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32)
358+
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY]](s32), [[C]](s32)
361359
; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
362360
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]]
363361
; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
@@ -501,20 +499,18 @@ body: |
501499
502500
; FP32-LABEL: name: u32tof64
503501
; FP32: liveins: $a0
504-
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
502+
; FP32: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0
505503
; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
506-
; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
507-
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32)
504+
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY]](s32), [[C]](s32)
508505
; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
509506
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]]
510507
; FP32: $d0 = COPY [[FSUB]](s64)
511508
; FP32: RetRA implicit $d0
512509
; FP64-LABEL: name: u32tof64
513510
; FP64: liveins: $a0
514-
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
511+
; FP64: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0
515512
; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
516-
; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
517-
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32)
513+
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY]](s32), [[C]](s32)
518514
; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
519515
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]]
520516
; FP64: $d0 = COPY [[FSUB]](s64)

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