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[Aarch64][SVE] Add intrinsics for gather loads (vector + imm)
This patch adds intrinsics for SVE gather loads from memory addresses generated by a vector base plus immediate index: * @llvm.aarch64.sve.ld1.gather.imm This intrinsics maps 1-1 to the corresponding SVE instruction (example for half-words): * ld1h { z0.d }, p0/z, [z0.d, #16] Committed on behalf of Andrzej Warzynski (andwar) Reviewers: sdesmalen, huntergr, kmclaughlin, eli.friedman, rengolin, rovka, dancgr, mgudim, efriedma Reviewed By: sdesmalen Tags: #llvm Differential Revision: https://reviews.llvm.org/D70806
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6 files changed

+198
-29
lines changed

‎llvm/include/llvm/IR/IntrinsicsAArch64.td‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -990,6 +990,15 @@ class AdvSIMD_GatherLoad_32bitOffset_Intrinsic
990990

991991
let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
992992

993+
class AdvSIMD_GatherLoad_VecTorBase_Intrinsic
994+
: Intrinsic<[llvm_anyvector_ty],
995+
[
996+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
997+
llvm_anyvector_ty,
998+
llvm_i64_ty
999+
],
1000+
[IntrReadMem, IntrArgMemOnly]>;
1001+
9931002
//
9941003
// Integer arithmetic
9951004
//
@@ -1229,6 +1238,9 @@ def int_aarch64_sve_ld1_gather_uxtw : AdvSIMD_GatherLoad_32bitOffset_Intrinsic;
12291238
def int_aarch64_sve_ld1_gather_sxtw_index : AdvSIMD_GatherLoad_32bitOffset_Intrinsic;
12301239
def int_aarch64_sve_ld1_gather_uxtw_index : AdvSIMD_GatherLoad_32bitOffset_Intrinsic;
12311240

1241+
// vector base + immediate index
1242+
def int_aarch64_sve_ld1_gather_imm : AdvSIMD_GatherLoad_VecTorBase_Intrinsic;
1243+
12321244
//
12331245
// SVE2 - Non-widening pairwise arithmetic
12341246
//

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1342,6 +1342,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
13421342
case AArch64ISD::GLD1_UXTW: return "AArch64ISD::GLD1_UXTW";
13431343
case AArch64ISD::GLD1_SXTW_SCALED: return "AArch64ISD::GLD1_SXTW_SCALED";
13441344
case AArch64ISD::GLD1_UXTW_SCALED: return "AArch64ISD::GLD1_UXTW_SCALED";
1345+
case AArch64ISD::GLD1_IMM: return "AArch64ISD::GLD1_IMM";
13451346
}
13461347
return nullptr;
13471348
}
@@ -11943,6 +11944,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
1194311944
return performLD1GatherCombine(N, DAG, AArch64ISD::GLD1_SXTW_SCALED);
1194411945
case Intrinsic::aarch64_sve_ld1_gather_uxtw_index:
1194511946
return performLD1GatherCombine(N, DAG, AArch64ISD::GLD1_UXTW_SCALED);
11947+
case Intrinsic::aarch64_sve_ld1_gather_imm:
11948+
return performLD1GatherCombine(N, DAG, AArch64ISD::GLD1_IMM);
1194611949
default:
1194711950
break;
1194811951
}

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,7 @@ enum NodeType : unsigned {
205205
GLD1_SXTW,
206206
GLD1_UXTW_SCALED,
207207
GLD1_SXTW_SCALED,
208+
GLD1_IMM,
208209

209210
// NEON Load/Store with post-increment base updates
210211
LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 33 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -15,12 +15,18 @@ def SDT_AArch64_GLD1 : SDTypeProfile<1, 4, [
1515
SDTCVecEltisVT<1,i1>, SDTCisSameNumEltsAs<0,1>
1616
]>;
1717

18+
def SDT_AArch64_GLD1_IMM : SDTypeProfile<1, 4, [
19+
SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>, SDTCisVT<4, OtherVT>,
20+
SDTCVecEltisVT<1,i1>, SDTCisSameNumEltsAs<0,1>
21+
]>;
22+
1823
def AArch64ld1_gather : SDNode<"AArch64ISD::GLD1", SDT_AArch64_GLD1, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue]>;
1924
def AArch64ld1_gather_scaled : SDNode<"AArch64ISD::GLD1_SCALED", SDT_AArch64_GLD1, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue]>;
2025
def AArch64ld1_gather_uxtw : SDNode<"AArch64ISD::GLD1_UXTW", SDT_AArch64_GLD1, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue]>;
2126
def AArch64ld1_gather_sxtw : SDNode<"AArch64ISD::GLD1_SXTW", SDT_AArch64_GLD1, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue]>;
2227
def AArch64ld1_gather_uxtw_scaled : SDNode<"AArch64ISD::GLD1_UXTW_SCALED", SDT_AArch64_GLD1, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue]>;
2328
def AArch64ld1_gather_sxtw_scaled : SDNode<"AArch64ISD::GLD1_SXTW_SCALED", SDT_AArch64_GLD1, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue]>;
29+
def AArch64ld1_gather_imm : SDNode<"AArch64ISD::GLD1_IMM", SDT_AArch64_GLD1_IMM, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue]>;
2430

2531
let Predicates = [HasSVE] in {
2632

@@ -434,35 +440,35 @@ let Predicates = [HasSVE] in {
434440
defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", AArch64ld1_gather_sxtw_scaled, AArch64ld1_gather_uxtw_scaled, ZPR32ExtSXTW32, ZPR32ExtUXTW32, nxv4i32>;
435441
defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", null_frag, null_frag, ZPR32ExtSXTW32, ZPR32ExtUXTW32, nxv4i32>;
436442

437-
// Gathers using scaled 32-bit pointers with offset, e.g.
443+
// Gathers using 32-bit pointers with scaled offset, e.g.
438444
// ld1h z0.s, p0/z, [z0.s, #16]
439-
defm GLD1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb", imm0_31>;
440-
defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31>;
441-
defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31>;
442-
defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31>;
443-
defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2>;
444-
defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2>;
445-
defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2>;
446-
defm GLDFF1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h", uimm5s2>;
447-
defm GLD1W : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w", uimm5s4>;
448-
defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4>;
449-
450-
// Gathers using scaled 64-bit pointers with offset, e.g.
445+
defm GLD1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb", imm0_31, null_frag, nxv4i8>;
446+
defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31, null_frag, nxv4i8>;
447+
defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31, AArch64ld1_gather_imm, nxv4i8>;
448+
defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31, null_frag, nxv4i8>;
449+
defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2, null_frag, nxv4i16>;
450+
defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2, null_frag, nxv4i16>;
451+
defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2, AArch64ld1_gather_imm, nxv4i16>;
452+
defm GLDFF1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h", uimm5s2, null_frag, nxv4i16>;
453+
defm GLD1W : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w", uimm5s4, AArch64ld1_gather_imm, nxv4i32>;
454+
defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4, null_frag, nxv4i32>;
455+
456+
// Gathers using 64-bit pointers with scaled offset, e.g.
451457
// ld1h z0.d, p0/z, [z0.d, #16]
452-
defm GLD1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb", imm0_31>;
453-
defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31>;
454-
defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31>;
455-
defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31>;
456-
defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2>;
457-
defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2>;
458-
defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2>;
459-
defm GLDFF1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h", uimm5s2>;
460-
defm GLD1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw", uimm5s4>;
461-
defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4>;
462-
defm GLD1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w", uimm5s4>;
463-
defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4>;
464-
defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8>;
465-
defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8>;
458+
defm GLD1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb", imm0_31, null_frag, nxv2i8>;
459+
defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31, null_frag, nxv2i8>;
460+
defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31, AArch64ld1_gather_imm, nxv2i8>;
461+
defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31, null_frag, nxv2i8>;
462+
defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2, null_frag, nxv2i16>;
463+
defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2, null_frag, nxv2i16>;
464+
defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2, AArch64ld1_gather_imm, nxv2i16>;
465+
defm GLDFF1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h", uimm5s2, null_frag, nxv2i16>;
466+
defm GLD1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw", uimm5s4, null_frag, nxv2i32>;
467+
defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4, null_frag, nxv2i32>;
468+
defm GLD1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w", uimm5s4, AArch64ld1_gather_imm, nxv2i32>;
469+
defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4, null_frag, nxv2i32>;
470+
defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8, AArch64ld1_gather_imm, nxv2i64>;
471+
defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8, null_frag, nxv2i64>;
466472

467473
// Gathers using unscaled 64-bit offsets, e.g.
468474
// ld1h z0.d, p0/z, [x0, z0.d]

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5357,7 +5357,8 @@ class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
53575357
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
53585358
}
53595359

5360-
multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty> {
5360+
multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty,
5361+
SDPatternOperator op, ValueType vt> {
53615362
def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>;
53625363

53635364
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
@@ -5366,6 +5367,9 @@ multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty> {
53665367
(!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
53675368
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
53685369
(!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
5370+
5371+
def : Pat<(nxv4i32 (op (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt)),
5372+
(!cast<Instruction>(NAME # _IMM_REAL) PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
53695373
}
53705374

53715375
class sve_mem_prfm_si<bits<2> msz, string asm>
@@ -5687,7 +5691,8 @@ class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
56875691
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
56885692
}
56895693

5690-
multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
5694+
multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty,
5695+
SDPatternOperator op, ValueType vt> {
56915696
def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
56925697

56935698
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
@@ -5696,6 +5701,9 @@ multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
56965701
(!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
56975702
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
56985703
(!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
5704+
5705+
def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt)),
5706+
(!cast<Instruction>(NAME # _IMM_REAL) PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
56995707
}
57005708

57015709
// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)

‎llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll‎

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,139 @@
1+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
2+
3+
;
4+
; LD1B, LD1W, LD1H, LD1D: vector + immediate (index)
5+
; e.g. ld1h { z0.s }, p0/z, [z0.s, #16]
6+
;
7+
8+
; LD1B
9+
define <vscale x 4 x i32> @gld1b_s_imm(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base) {
10+
; CHECK-LABEL: gld1b_s_imm:
11+
; CHECK: ld1b { z0.s }, p0/z, [z0.s, #16]
12+
; CHECK-NEXT: mov w8, #255
13+
; CHECK-NEXT: mov z1.s, w8
14+
; CHECK-NEXT: and z0.d, z0.d, z1.d
15+
; CHECK-NEXT: ret
16+
%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.imm.nxv4i8.nxv4i32(<vscale x 4 x i1> %pg,
17+
<vscale x 4 x i32> %base,
18+
i64 16)
19+
%res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
20+
ret <vscale x 4 x i32> %res
21+
}
22+
23+
define <vscale x 2 x i64> @gld1b_d_imm(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
24+
; CHECK-LABEL: gld1b_d_imm:
25+
; CHECK: ld1b { z0.d }, p0/z, [z0.d, #16]
26+
; CHECK-NEXT: mov w8, #255
27+
; CHECK-NEXT: mov z1.d, x8
28+
; CHECK-NEXT: and z0.d, z0.d, z1.d
29+
; CHECK-NEXT: ret
30+
%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.imm.nxv2i8.nxv2i64(<vscale x 2 x i1> %pg,
31+
<vscale x 2 x i64> %base,
32+
i64 16)
33+
%res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
34+
ret <vscale x 2 x i64> %res
35+
}
36+
37+
; LD1H
38+
define <vscale x 4 x i32> @gld1h_s_imm(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base) {
39+
; CHECK-LABEL: gld1h_s_imm:
40+
; CHECK: ld1h { z0.s }, p0/z, [z0.s, #16]
41+
; CHECK-NEXT: mov w8, #65535
42+
; CHECK-NEXT: mov z1.s, w8
43+
; CHECK-NEXT: and z0.d, z0.d, z1.d
44+
; CHECK-NEXT: ret
45+
%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.imm.nxv4i16.nxv4i32(<vscale x 4 x i1> %pg,
46+
<vscale x 4 x i32> %base,
47+
i64 16)
48+
%res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
49+
ret <vscale x 4 x i32> %res
50+
}
51+
52+
define <vscale x 2 x i64> @gld1h_d_imm(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
53+
; CHECK-LABEL: gld1h_d_imm:
54+
; CHECK: ld1h { z0.d }, p0/z, [z0.d, #16]
55+
; CHECK-NEXT: mov w8, #65535
56+
; CHECK-NEXT: mov z1.d, x8
57+
; CHECK-NEXT: and z0.d, z0.d, z1.d
58+
; CHECK-NEXT: ret
59+
%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.imm.nxv2i16.nxv2i64(<vscale x 2 x i1> %pg,
60+
<vscale x 2 x i64> %base,
61+
i64 16)
62+
%res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
63+
ret <vscale x 2 x i64> %res
64+
}
65+
66+
; LD1W
67+
define <vscale x 4 x i32> @gld1w_s_imm(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base) {
68+
; CHECK-LABEL: gld1w_s_imm:
69+
; CHECK: ld1w { z0.s }, p0/z, [z0.s, #16]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.imm.nxv4i32.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 16)
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ret <vscale x 4 x i32> %load
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}
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define <vscale x 2 x i64> @gld1w_d_imm(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
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; CHECK-LABEL: gld1w_d_imm:
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; CHECK: ld1w { z0.d }, p0/z, [z0.d, #16]
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; CHECK-NEXT: mov w8, #-1
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; CHECK-NEXT: mov z1.d, x8
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.imm.nxv2i32.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 16)
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%res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 4 x float> @gld1w_s_imm_float(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base) {
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; CHECK-LABEL: gld1w_s_imm_float:
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; CHECK: ld1w { z0.s }, p0/z, [z0.s, #16]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.imm.nxv4f32.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 16)
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ret <vscale x 4 x float> %load
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}
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; LD1D
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define <vscale x 2 x i64> @gld1d_d_imm(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
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; CHECK-LABEL: gld1d_d_imm:
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; CHECK: ld1d { z0.d }, p0/z, [z0.d, #16]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.imm.nxv2i64.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 16)
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ret <vscale x 2 x i64> %load
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}
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define <vscale x 2 x double> @gld1d_d_imm_double(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
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; CHECK-LABEL: gld1d_d_imm_double:
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; CHECK: ld1d { z0.d }, p0/z, [z0.d, #16]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.imm.nxv2f64.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 16)
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ret <vscale x 2 x double> %load
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}
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; LD1B
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declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.imm.nxv4i8.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.imm.nxv2i8.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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; LD1H
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declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.imm.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.imm.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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; LD1W
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declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.imm.nxv4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.imm.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.imm.nxv4f32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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; LD1D
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declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.imm.nxv2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.imm.nxv2f64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)

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