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‎llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll

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@@ -1,10 +1,57 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=128 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_128
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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define <4 x i32> @sdiv_v4i32_negative_pow2_divisor_packed(<4 x i32> %op1) vscale_range(1,0) #0 {
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; CHECK-LABEL: sdiv_v4i32_negative_pow2_divisor_packed:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.4s, v0.4s, #0
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; CHECK-NEXT: usra v0.4s, v1.4s, #29
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; CHECK-NEXT: sshr v0.4s, v0.4s, #3
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: ret
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%res = sdiv <4 x i32> %op1, splat (i32 -8)
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ret <4 x i32> %res
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}
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define <2 x i32> @sdiv_v2i32_negative_pow2_divisor_unpacked(<2 x i32> %op1) vscale_range(1,0) #0 {
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; CHECK-LABEL: sdiv_v2i32_negative_pow2_divisor_unpacked:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.2s, v0.2s, #0
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; CHECK-NEXT: usra v0.2s, v1.2s, #29
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; CHECK-NEXT: sshr v0.2s, v0.2s, #3
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; CHECK-NEXT: neg v0.2s, v0.2s
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; CHECK-NEXT: ret
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%res = sdiv <2 x i32> %op1, splat (i32 -8)
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ret <2 x i32> %res
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}
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define <4 x i32> @sdiv_v4i32_positive_pow2_divisor_packed(<4 x i32> %op1) vscale_range(1,0) #0 {
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; CHECK-LABEL: sdiv_v4i32_positive_pow2_divisor_packed:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.4s, v0.4s, #0
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; CHECK-NEXT: usra v0.4s, v1.4s, #29
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; CHECK-NEXT: sshr v0.4s, v0.4s, #3
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; CHECK-NEXT: ret
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%res = sdiv <4 x i32> %op1, splat (i32 8)
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ret <4 x i32> %res
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}
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define <2 x i32> @sdiv_v2i32_positive_pow2_divisor_unpacked(<2 x i32> %op1) vscale_range(1,0) #0 {
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; CHECK-LABEL: sdiv_v2i32_positive_pow2_divisor_unpacked:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.2s, v0.2s, #0
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; CHECK-NEXT: usra v0.2s, v1.2s, #29
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; CHECK-NEXT: sshr v0.2s, v0.2s, #3
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; CHECK-NEXT: ret
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%res = sdiv <2 x i32> %op1, splat (i32 8)
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ret <2 x i32> %res
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}
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define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) vscale_range(2,0) #0 {
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; CHECK-LABEL: sdiv_v8i8:
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; CHECK: // %bb.0:
@@ -45,6 +92,26 @@ define void @sdiv_v32i8(ptr %a) vscale_range(2,0) #0 {
4592
}
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define void @sdiv_v64i8(ptr %a) #0 {
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; VBITS_GE_128-LABEL: sdiv_v64i8:
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; VBITS_GE_128: // %bb.0:
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; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32]
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; VBITS_GE_128-NEXT: ldp q3, q4, [x0]
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; VBITS_GE_128-NEXT: cmlt v2.16b, v0.16b, #0
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; VBITS_GE_128-NEXT: cmlt v5.16b, v1.16b, #0
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; VBITS_GE_128-NEXT: cmlt v6.16b, v3.16b, #0
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; VBITS_GE_128-NEXT: usra v0.16b, v2.16b, #3
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; VBITS_GE_128-NEXT: cmlt v2.16b, v4.16b, #0
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; VBITS_GE_128-NEXT: usra v1.16b, v5.16b, #3
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; VBITS_GE_128-NEXT: usra v3.16b, v6.16b, #3
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; VBITS_GE_128-NEXT: usra v4.16b, v2.16b, #3
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; VBITS_GE_128-NEXT: sshr v0.16b, v0.16b, #5
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; VBITS_GE_128-NEXT: sshr v1.16b, v1.16b, #5
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; VBITS_GE_128-NEXT: sshr v2.16b, v3.16b, #5
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; VBITS_GE_128-NEXT: sshr v3.16b, v4.16b, #5
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; VBITS_GE_128-NEXT: stp q0, q1, [x0, #32]
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; VBITS_GE_128-NEXT: stp q2, q3, [x0]
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; VBITS_GE_128-NEXT: ret
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;
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; VBITS_GE_256-LABEL: sdiv_v64i8:
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; VBITS_GE_256: // %bb.0:
50117
; VBITS_GE_256-NEXT: ptrue p0.b, vl32
@@ -139,6 +206,26 @@ define void @sdiv_v16i16(ptr %a) vscale_range(2,0) #0 {
139206
}
140207

141208
define void @sdiv_v32i16(ptr %a) #0 {
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; VBITS_GE_128-LABEL: sdiv_v32i16:
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; VBITS_GE_128: // %bb.0:
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; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32]
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; VBITS_GE_128-NEXT: ldp q3, q4, [x0]
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; VBITS_GE_128-NEXT: cmlt v2.8h, v0.8h, #0
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; VBITS_GE_128-NEXT: cmlt v5.8h, v1.8h, #0
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; VBITS_GE_128-NEXT: cmlt v6.8h, v3.8h, #0
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; VBITS_GE_128-NEXT: usra v0.8h, v2.8h, #11
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; VBITS_GE_128-NEXT: cmlt v2.8h, v4.8h, #0
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; VBITS_GE_128-NEXT: usra v1.8h, v5.8h, #11
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; VBITS_GE_128-NEXT: usra v3.8h, v6.8h, #11
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; VBITS_GE_128-NEXT: usra v4.8h, v2.8h, #11
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; VBITS_GE_128-NEXT: sshr v0.8h, v0.8h, #5
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; VBITS_GE_128-NEXT: sshr v1.8h, v1.8h, #5
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; VBITS_GE_128-NEXT: sshr v2.8h, v3.8h, #5
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; VBITS_GE_128-NEXT: sshr v3.8h, v4.8h, #5
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; VBITS_GE_128-NEXT: stp q0, q1, [x0, #32]
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; VBITS_GE_128-NEXT: stp q2, q3, [x0]
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; VBITS_GE_128-NEXT: ret
228+
;
142229
; VBITS_GE_256-LABEL: sdiv_v32i16:
143230
; VBITS_GE_256: // %bb.0:
144231
; VBITS_GE_256-NEXT: ptrue p0.h, vl16
@@ -234,6 +321,26 @@ define void @sdiv_v8i32(ptr %a) vscale_range(2,0) #0 {
234321
}
235322

236323
define void @sdiv_v16i32(ptr %a) #0 {
324+
; VBITS_GE_128-LABEL: sdiv_v16i32:
325+
; VBITS_GE_128: // %bb.0:
326+
; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32]
327+
; VBITS_GE_128-NEXT: ldp q3, q4, [x0]
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; VBITS_GE_128-NEXT: cmlt v2.4s, v0.4s, #0
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; VBITS_GE_128-NEXT: cmlt v5.4s, v1.4s, #0
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; VBITS_GE_128-NEXT: cmlt v6.4s, v3.4s, #0
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; VBITS_GE_128-NEXT: usra v0.4s, v2.4s, #27
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; VBITS_GE_128-NEXT: cmlt v2.4s, v4.4s, #0
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; VBITS_GE_128-NEXT: usra v1.4s, v5.4s, #27
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; VBITS_GE_128-NEXT: usra v3.4s, v6.4s, #27
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; VBITS_GE_128-NEXT: usra v4.4s, v2.4s, #27
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; VBITS_GE_128-NEXT: sshr v0.4s, v0.4s, #5
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; VBITS_GE_128-NEXT: sshr v1.4s, v1.4s, #5
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; VBITS_GE_128-NEXT: sshr v2.4s, v3.4s, #5
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; VBITS_GE_128-NEXT: sshr v3.4s, v4.4s, #5
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; VBITS_GE_128-NEXT: stp q0, q1, [x0, #32]
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; VBITS_GE_128-NEXT: stp q2, q3, [x0]
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; VBITS_GE_128-NEXT: ret
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;
237344
; VBITS_GE_256-LABEL: sdiv_v16i32:
238345
; VBITS_GE_256: // %bb.0:
239346
; VBITS_GE_256-NEXT: ptrue p0.s, vl8
@@ -329,6 +436,26 @@ define void @sdiv_v4i64(ptr %a) vscale_range(2,0) #0 {
329436
}
330437

331438
define void @sdiv_v8i64(ptr %a) #0 {
439+
; VBITS_GE_128-LABEL: sdiv_v8i64:
440+
; VBITS_GE_128: // %bb.0:
441+
; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32]
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; VBITS_GE_128-NEXT: ldp q3, q4, [x0]
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; VBITS_GE_128-NEXT: cmlt v2.2d, v0.2d, #0
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; VBITS_GE_128-NEXT: cmlt v5.2d, v1.2d, #0
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; VBITS_GE_128-NEXT: cmlt v6.2d, v3.2d, #0
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; VBITS_GE_128-NEXT: usra v0.2d, v2.2d, #59
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; VBITS_GE_128-NEXT: cmlt v2.2d, v4.2d, #0
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; VBITS_GE_128-NEXT: usra v1.2d, v5.2d, #59
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; VBITS_GE_128-NEXT: usra v3.2d, v6.2d, #59
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; VBITS_GE_128-NEXT: usra v4.2d, v2.2d, #59
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; VBITS_GE_128-NEXT: sshr v0.2d, v0.2d, #5
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; VBITS_GE_128-NEXT: sshr v1.2d, v1.2d, #5
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; VBITS_GE_128-NEXT: sshr v2.2d, v3.2d, #5
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; VBITS_GE_128-NEXT: sshr v3.2d, v4.2d, #5
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; VBITS_GE_128-NEXT: stp q0, q1, [x0, #32]
456+
; VBITS_GE_128-NEXT: stp q2, q3, [x0]
457+
; VBITS_GE_128-NEXT: ret
458+
;
332459
; VBITS_GE_256-LABEL: sdiv_v8i64:
333460
; VBITS_GE_256: // %bb.0:
334461
; VBITS_GE_256-NEXT: ptrue p0.d, vl4

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