Skip to content

Commit 59b59b0

Browse files
author
kubi48
committed
GetFrequency for 20MHz operation
git-svn-id: svn://mikrocontroller.net/transistortester@783 6ebdd44f-5a7e-449c-b779-36259138d2c7
1 parent e32d0d5 commit 59b59b0

File tree

1 file changed

+13
-5
lines changed

1 file changed

+13
-5
lines changed

Software/trunk/GetFrequency.c

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -119,30 +119,38 @@ void GetFrequency(uint8_t range) {
119119
TCCR1A = 0; // normal operation
120120
#define CNT1_END_VAL ((F_CPU / 256UL) + 1)
121121
#define CNT1_DIVIDER (1<<CS12)
122-
#if CNT1_END_VAL > 0xffff
122+
#if (CNT1_END_VAL > 0xffff) && (F_CPU == ((F_CPU / 1024UL) * 1024UL))
123123
#undef CNT1_END_VAL
124124
#undef CNT1_DIVIDER
125125
#define CNT1_END_VAL ((F_CPU / 1024UL) + 1)
126126
#define CNT1_DIVIDER ((1<<CS12) | (1<<CS10))
127-
#if F_CPU != ((F_CPU / 1024UL) * 1024UL)
128-
#warning F_CPU can not be divided by 1024, measured frequency is wrong!
129-
#endif
130127
#else
131128
#if F_CPU != ((F_CPU / 256UL) * 256UL)
132129
#warning F_CPU can not be divided by 256, measured frequency is wrong!
133130
#endif
134131
#endif
135-
OCR1B = CNT1_END_VAL; // set to 1 second (counter 0 is started with 1)
132+
OCR1B = (CNT1_END_VAL & 0xffff); // set to 1 second (counter 0 is started with 1)
136133
OCR1A = 1; // start counter 0 with first count
137134
TCNT1 = 0; // set counter to zero
138135
GTCCR |= (1<<PSRSYNC); // reset clock precounter
139136
TIFR1 = (1<<OCF1B) | (1<<OCF1A); // clear Output compare match
137+
#if CNT1_END_VAL > 0xffff
138+
TIMSK1 = (1<<OCIE1A); // enable the Compare A match interrupt
139+
#else
140140
TIMSK1 = (1<<OCIE1B) | (1<<OCIE1A); // enable the Compare A match and Compare B match interrupt
141+
#endif
141142
sei(); // set interrupt enable
142143
TCCR1B = CNT1_DIVIDER; // divide CPU clock by 256, start counter
143144
// both counter are running now, wait for counter 1 reach OCR1A
144145
for (ii=0;ii<50;ii++) {
145146
wait20ms(); // first count of counter 1 (<32us) has started the counter 0
147+
#if CNT1_END_VAL > 0xffff
148+
TIMSK1 &= ~(1<<OCIE1A); // disable the Compare A match interrupt
149+
if ((TIFR1 & (1<<TOV1)) != 0) {
150+
TIFR1 = (1<<OCF1B)|(1<<TOV1); // reset TOV1 Overflow and Output compare B match Flag
151+
TIMSK1 = (1<<OCIE1B); // enable the Compare B match interrupt
152+
}
153+
#endif
146154
wdt_reset();
147155
if (!(RST_PIN_REG & (1<<RST_PIN))) taste = 1; // user request stop of operation
148156
#if PROCESSOR_TYP == 1280

0 commit comments

Comments
 (0)