A minimal GPU design in Verilog to learn how GPUs work from the ground up

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

VeeR EH1 core

Common SystemVerilog components

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

VeeR EL2 Core

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog