diff --git a/docs/datasheet/cpu.adoc b/docs/datasheet/cpu.adoc index 563dfdc96..921d89580 100644 --- a/docs/datasheet/cpu.adoc +++ b/docs/datasheet/cpu.adoc @@ -1,9 +1,9 @@ :sectnums: == NEORV32 Central Processing Unit (CPU) -The NEORV32 CPU is an area-optimized RISC-V core implementing the `rv32iZicsr` base ISA and supporting -several additional/optional ISA extensions. The CPU's micro architecture is based on a von-Neumann machine build -upon a mixture of multi-cycle and pipelined execution schemes. +The NEORV32 CPU is an area-optimized RISC-V core implementing the `rv32i_zicsr_zifencei` base (privileged) ISA and +supporting several additional/optional ISA extensions. The CPU's micro architecture is based on a von-Neumann +machine build upon a mixture of multi-cycle and pipelined execution schemes. [NOTE] This chapter assumes that the reader is familiar with the official @@ -385,7 +385,7 @@ via the according <<_processor_top_entity_generics>>. This chapter gives a brief | <<_m_isa_extension,`M`>> | Integer multiplication and division instructions | | <<_u_isa_extension,`U`>> | Less-privileged _user_ mode extension | | <<_x_isa_extension,`X`>> | Platform-specific / NEORV32-specific extension | **Always enabled** -| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction | +| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction | **Always enabled** | <<_zfinx_isa_extension,`Zfinx`>> | Floating-point instructions using integer registers | `F` alternative | <<_zicntr_isa_extension,`Zicntr`>> | Base counters extension | | <<_zicsr_isa_extension,`Zicsr`>> | Control and status register access instructions | **Always enabled** @@ -590,7 +590,8 @@ RISC-V specs. Also, custom trap codes for <<_mcause>> are implemented. ==== `Zifencei` ISA Extension -The `Zifencei` CPU extension allows manual synchronization of the instruction stream. +The `Zifencei` CPU extension allows manual synchronization of the instruction stream. This extension is always enabled. + The `fence.i` instruction resets the CPU's front-end (instruction fetch) and flushes the prefetch buffer. This allows a clean re-fetch of modified instructions from memory. Also, the top's `i_bus_fencei_o` signal is set high for one cycle to inform the memory system (like the <<_processor_internal_instruction_cache_icache>> to perform a flush/reload. diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index 07f6f3198..ca3e81868 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -208,18 +208,17 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt | `ON_CHIP_DEBUGGER_EN` | boolean | false | Implement the on-chip debugger and the CPU debug mode. | `DM_LEGACY_MODE` | boolean | false | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode). 4+^| **CPU <<_instruction_sets_and_extensions>>** -| `CPU_EXTENSION_RISCV_A` | boolean | false | Enable <<_a_isa_extension>> (atomic memory accesses). -| `CPU_EXTENSION_RISCV_B` | boolean | false | Enable <<_b_isa_extension>> (bit-manipulation). -| `CPU_EXTENSION_RISCV_C` | boolean | false | Enable <<_c_isa_extension>> (compressed instructions). -| `CPU_EXTENSION_RISCV_E` | boolean | false | Enable <<_e_isa_extension>> (reduced register file size). -| `CPU_EXTENSION_RISCV_M` | boolean | false | Enable <<_m_isa_extension>> (hardware-based integer multiplication and division). -| `CPU_EXTENSION_RISCV_U` | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode). -| `CPU_EXTENSION_RISCV_Zfinx` | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit). -| `CPU_EXTENSION_RISCV_Zicntr` | boolean | true | Enable <<_zicntr_isa_extension>> (CPU base counters). -| `CPU_EXTENSION_RISCV_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors). -| `CPU_EXTENSION_RISCV_Zifencei` | boolean | false | Enable <<_zifencei_isa_extension>> (instruction stream synchronization). -| `CPU_EXTENSION_RISCV_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication). -| `CPU_EXTENSION_RISCV_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions). +| `CPU_EXTENSION_RISCV_A` | boolean | false | Enable <<_a_isa_extension>> (atomic memory accesses). +| `CPU_EXTENSION_RISCV_B` | boolean | false | Enable <<_b_isa_extension>> (bit-manipulation). +| `CPU_EXTENSION_RISCV_C` | boolean | false | Enable <<_c_isa_extension>> (compressed instructions). +| `CPU_EXTENSION_RISCV_E` | boolean | false | Enable <<_e_isa_extension>> (reduced register file size). +| `CPU_EXTENSION_RISCV_M` | boolean | false | Enable <<_m_isa_extension>> (hardware-based integer multiplication and division). +| `CPU_EXTENSION_RISCV_U` | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode). +| `CPU_EXTENSION_RISCV_Zfinx` | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit). +| `CPU_EXTENSION_RISCV_Zicntr` | boolean | true | Enable <<_zicntr_isa_extension>> (CPU base counters). +| `CPU_EXTENSION_RISCV_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors). +| `CPU_EXTENSION_RISCV_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication). +| `CPU_EXTENSION_RISCV_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions). 4+^| **CPU Tuning Options** | `FAST_MUL_EN` | boolean | false | Implement fast (but large) full-parallel multipliers (trying to infer DSP blocks). | `FAST_SHIFT_EN` | boolean | false | Implement fast (but large) full-parallel barrel shifters. diff --git a/docs/userguide/customizing_the_bootloader.adoc b/docs/userguide/customizing_the_bootloader.adoc index 3d846cd68..264f4ab61 100644 --- a/docs/userguide/customizing_the_bootloader.adoc +++ b/docs/userguide/customizing_the_bootloader.adoc @@ -12,7 +12,7 @@ bootloader ROM) and the processor has to be re-synthesized. [NOTE] Keep in mind that the maximum size for the bootloader is limited to 8kB and it should be compiled using the -minimal base & privileged ISA `rv32i_zicsr` only to ensure it can work independently of the actual CPU configuration. +minimal base & privileged ISA `rv32i_zicsr_zifencei` only to ensure it can work independently of the actual CPU configuration. .Bootloader configuration parameters [cols="<2,^1,^2,<6"] diff --git a/docs/userguide/debugging_with_ocd.adoc b/docs/userguide/debugging_with_ocd.adoc index 6619c1119..7db07c3bf 100644 --- a/docs/userguide/debugging_with_ocd.adoc +++ b/docs/userguide/debugging_with_ocd.adoc @@ -21,8 +21,7 @@ for more information regarding the actual hardware. .OCD CPU Requirements [NOTE] The on-chip debugger is only implemented if the _ON_CHIP_DEBUGGER_EN_ generic is set _true_. Furthermore, it requires -the `Zicsr` and `Zifencei` CPU extension to be implemented (top generics _CPU_EXTENSION_RISCV_Zicsr_ = _true_ -and _CPU_EXTENSION_RISCV_Zifencei_ = _true_). +the `Zicsr` and `Zifencei` CPU extension, which are always enabled by the CPU. :sectnums: