From 7114677d971ab76d7c3ea19d3ebbb0840f0c715f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 22 Nov 2024 14:41:40 +0100 Subject: [PATCH 001/141] chore: update core version to 2.10.0-dev (0x021000F0) Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/inc/stm32_def.h | 4 ++-- platform.txt | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index 9d073f3b06..a101654ce6 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -6,7 +6,7 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x09U) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_MINOR (0x10U) /*!< [23:16] minor version */ #define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ /* * Extra label for development: @@ -14,7 +14,7 @@ * [1-9]: release candidate * F[0-9]: development */ -#define STM32_CORE_VERSION_EXTRA (0x00U) /*!< [7:0] extra version */ +#define STM32_CORE_VERSION_EXTRA (0xF0U) /*!< [7:0] extra version */ #define STM32_CORE_VERSION ((STM32_CORE_VERSION_MAJOR << 24U)\ |(STM32_CORE_VERSION_MINOR << 16U)\ |(STM32_CORE_VERSION_PATCH << 8U )\ diff --git a/platform.txt b/platform.txt index edfce65bf1..8858440c3a 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.9.0 +version=2.10.0-dev # Define variables used multiple times in platform file From f2dc38281b235c4805427deedcd77d3ebcd334c6 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 25 Nov 2024 16:10:46 +0100 Subject: [PATCH 002/141] fix: arduino legacy ide warning Fixes #2577. Signed-off-by: Frederic Pillon --- boards.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/boards.txt b/boards.txt index ece804f324..729b1a000a 100644 --- a/boards.txt +++ b/boards.txt @@ -13671,6 +13671,7 @@ ELV_Modular_System.menu.upload_method.serialMethod.upload.tool=stm32CubeProg # STeaMi board STeaMi.name=STeaMi Board STeaMi.build.core=arduino +STeaMi.build.board=STeaMi STeaMi.build.variant_h=variant_{build.board}.h STeaMi.build.st_extra_flags=-D{build.product_line} {build.xSerial} STeaMi.build.flash_offset=0x0 From 6f28a4884a77ffddc8bdc1e44a781b9f6cbccf08 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 27 Nov 2024 14:36:55 +0100 Subject: [PATCH 003/141] chore(c0): enable usb Enable the HSI48 for USB (not done thanks CubeMX code generation). Add GenC0 USB menu. Moved G0 one in alphabetical order. Fixes #2582. Signed-off-by: Frederic Pillon --- boards.txt | 24 ++++++++++++------- .../STM32C0xx/C071R(8-B)T/generic_clock.c | 3 +++ .../C071R(8-B)T/variant_NUCLEO_C071RB.cpp | 3 +++ 3 files changed, 22 insertions(+), 8 deletions(-) diff --git a/boards.txt b/boards.txt index 729b1a000a..07fc51e3ad 100644 --- a/boards.txt +++ b/boards.txt @@ -14013,6 +14013,14 @@ Eval.menu.xusb.HS.build.usb_speed=-DUSE_USB_HS Eval.menu.xusb.HSFS=High Speed in Full Speed mode Eval.menu.xusb.HSFS.build.usb_speed=-DUSE_USB_HS -DUSE_USB_HS_IN_FS +GenC0.menu.usb.none=None +GenC0.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) +GenC0.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC +GenC0.menu.usb.CDC=CDC (no generic 'Serial') +GenC0.menu.usb.CDC.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB +GenC0.menu.usb.HID=HID (keyboard and mouse) +GenC0.menu.usb.HID.build.enable_usb={build.usb_flags} -DUSBD_USE_HID_COMPOSITE + GenF0.menu.usb.none=None GenF0.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) GenF0.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC @@ -14086,6 +14094,14 @@ GenF7.menu.xusb.HS.build.usb_speed=-DUSE_USB_HS GenF7.menu.xusb.HSFS=High Speed in Full Speed mode GenF7.menu.xusb.HSFS.build.usb_speed=-DUSE_USB_HS -DUSE_USB_HS_IN_FS +GenG0.menu.usb.none=None +GenG0.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) +GenG0.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC +GenG0.menu.usb.CDC=CDC (no generic 'Serial') +GenG0.menu.usb.CDC.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB +GenG0.menu.usb.HID=HID (keyboard and mouse) +GenG0.menu.usb.HID.build.enable_usb={build.usb_flags} -DUSBD_USE_HID_COMPOSITE + GenG4.menu.usb.none=None GenG4.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) GenG4.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC @@ -14099,14 +14115,6 @@ GenG4.menu.xusb.HS.build.usb_speed=-DUSE_USB_HS GenG4.menu.xusb.HSFS=High Speed in Full Speed mode GenG4.menu.xusb.HSFS.build.usb_speed=-DUSE_USB_HS -DUSE_USB_HS_IN_FS -GenG0.menu.usb.none=None -GenG0.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) -GenG0.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC -GenG0.menu.usb.CDC=CDC (no generic 'Serial') -GenG0.menu.usb.CDC.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB -GenG0.menu.usb.HID=HID (keyboard and mouse) -GenG0.menu.usb.HID.build.enable_usb={build.usb_flags} -DUSBD_USE_HID_COMPOSITE - GenH5.menu.usb.none=None GenH5.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) GenH5.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC diff --git a/variants/STM32C0xx/C071R(8-B)T/generic_clock.c b/variants/STM32C0xx/C071R(8-B)T/generic_clock.c index cfb7612e69..b38455c2b8 100644 --- a/variants/STM32C0xx/C071R(8-B)T/generic_clock.c +++ b/variants/STM32C0xx/C071R(8-B)T/generic_clock.c @@ -27,6 +27,9 @@ WEAK void SystemClock_Config(void) LL_RCC_HSI_Enable(); while (LL_RCC_HSI_IsReady() != 1) { } + LL_RCC_HSI48_Enable(); + while (LL_RCC_HSI48_IsReady() != 1) { + } LL_RCC_HSI_SetCalibTrimming(64); LL_RCC_SetHSIDiv(LL_RCC_HSI_DIV_1); diff --git a/variants/STM32C0xx/C071R(8-B)T/variant_NUCLEO_C071RB.cpp b/variants/STM32C0xx/C071R(8-B)T/variant_NUCLEO_C071RB.cpp index cb7abaf86d..8fd887581a 100644 --- a/variants/STM32C0xx/C071R(8-B)T/variant_NUCLEO_C071RB.cpp +++ b/variants/STM32C0xx/C071R(8-B)T/variant_NUCLEO_C071RB.cpp @@ -116,6 +116,9 @@ WEAK void SystemClock_Config(void) LL_RCC_HSI_Enable(); while (LL_RCC_HSI_IsReady() != 1) { } + LL_RCC_HSI48_Enable(); + while (LL_RCC_HSI48_IsReady() != 1) { + } LL_RCC_HSI_SetCalibTrimming(64); LL_RCC_SetHSIDiv(LL_RCC_HSI_DIV_1); From 8ef8b6ad325061abd67e31881595532593fdbf42 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Dec 2024 14:19:19 +0100 Subject: [PATCH 004/141] system(H5) update STM32H5xx HAL Drivers to v1.4.0 Included in STM32CubeH5 FW v1.4.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 77 +- .../STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h | 4 +- .../Inc/stm32h5xx_hal_cortex.h | 56 +- .../Inc/stm32h5xx_hal_dac.h | 11 +- .../Inc/stm32h5xx_hal_def.h | 4 +- .../Inc/stm32h5xx_hal_eth.h | 36 +- .../Inc/stm32h5xx_hal_flash.h | 18 +- .../Inc/stm32h5xx_hal_flash_ex.h | 1 + .../Inc/stm32h5xx_hal_gpio_ex.h | 110 +- .../Inc/stm32h5xx_hal_hcd.h | 59 +- .../Inc/stm32h5xx_hal_i2s.h | 5 + .../Inc/stm32h5xx_hal_lptim.h | 3 - .../Inc/stm32h5xx_hal_pcd.h | 86 +- .../Inc/stm32h5xx_hal_pcd_ex.h | 12 +- .../Inc/stm32h5xx_hal_pka.h | 3 + .../Inc/stm32h5xx_hal_rcc.h | 269 +- .../Inc/stm32h5xx_hal_rcc_ex.h | 12 + .../Inc/stm32h5xx_hal_rng.h | 1 + .../Inc/stm32h5xx_hal_rtc_ex.h | 11 + .../Inc/stm32h5xx_hal_spi.h | 7 + .../Inc/stm32h5xx_hal_spi_ex.h | 4 + .../Inc/stm32h5xx_hal_wwdg.h | 2 +- .../Inc/stm32h5xx_hal_xspi.h | 128 +- .../Inc/stm32h5xx_ll_bus.h | 2 - .../Inc/stm32h5xx_ll_cortex.h | 51 +- .../Inc/stm32h5xx_ll_crs.h | 6 +- .../Inc/stm32h5xx_ll_exti.h | 26 +- .../Inc/stm32h5xx_ll_gpio.h | 5 +- .../Inc/stm32h5xx_ll_pwr.h | 4 +- .../Inc/stm32h5xx_ll_rcc.h | 11 +- .../Inc/stm32h5xx_ll_rtc.h | 46 +- .../Inc/stm32h5xx_ll_spi.h | 2 +- .../Inc/stm32h5xx_ll_ucpd.h | 49 +- .../Inc/stm32h5xx_ll_usb.h | 340 ++- .../Inc/stm32h5xx_ll_utils.h | 38 +- .../Inc/stm32h5xx_util_i3c.h | 4 +- .../STM32H5xx_HAL_Driver/Release_Notes.html | 137 +- .../STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c | 4 +- .../Src/stm32h5xx_hal_adc.c | 3 +- .../Src/stm32h5xx_hal_adc_ex.c | 6 +- .../Src/stm32h5xx_hal_cortex.c | 23 +- .../Src/stm32h5xx_hal_cryp.c | 122 +- .../Src/stm32h5xx_hal_cryp_ex.c | 70 +- .../Src/stm32h5xx_hal_dac.c | 8 + .../Src/stm32h5xx_hal_dac_ex.c | 15 +- .../Src/stm32h5xx_hal_dma_ex.c | 17 +- .../Src/stm32h5xx_hal_eth.c | 27 +- .../Src/stm32h5xx_hal_fdcan.c | 4 +- .../Src/stm32h5xx_hal_flash.c | 55 +- .../Src/stm32h5xx_hal_flash_ex.c | 38 +- .../Src/stm32h5xx_hal_fmac.c | 17 +- .../Src/stm32h5xx_hal_gtzc.c | 8 +- .../Src/stm32h5xx_hal_hcd.c | 1953 +++++++++++++- .../Src/stm32h5xx_hal_i2c.c | 67 +- .../Src/stm32h5xx_hal_i2s.c | 101 + .../Src/stm32h5xx_hal_i3c.c | 20 +- .../Src/stm32h5xx_hal_pcd.c | 844 +++++- .../Src/stm32h5xx_hal_pcd_ex.c | 305 ++- .../Src/stm32h5xx_hal_pka.c | 128 +- .../Src/stm32h5xx_hal_pwr.c | 7 + .../Src/stm32h5xx_hal_rcc.c | 7 + .../Src/stm32h5xx_hal_rcc_ex.c | 90 +- .../Src/stm32h5xx_hal_rng.c | 15 +- .../Src/stm32h5xx_hal_rng_ex.c | 5 + .../Src/stm32h5xx_hal_rtc_ex.c | 32 + .../Src/stm32h5xx_hal_smartcard.c | 56 + .../Src/stm32h5xx_hal_spi.c | 388 ++- .../Src/stm32h5xx_hal_spi_ex.c | 95 +- .../Src/stm32h5xx_hal_uart.c | 8 +- .../Src/stm32h5xx_hal_xspi.c | 44 +- .../Src/stm32h5xx_ll_dac.c | 24 +- .../Src/stm32h5xx_ll_dma.c | 9 +- .../Src/stm32h5xx_ll_exti.c | 14 +- .../Src/stm32h5xx_ll_gpio.c | 19 +- .../Src/stm32h5xx_ll_i3c.c | 2 +- .../Src/stm32h5xx_ll_rcc.c | 14 +- .../Src/stm32h5xx_ll_spi.c | 2 +- .../Src/stm32h5xx_ll_usb.c | 2264 ++++++++++++++++- .../Src/stm32h5xx_util_i3c.c | 4 + .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 80 files changed, 7521 insertions(+), 1055 deletions(-) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 5c2adb67f4..cf3942e283 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +817,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1999,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -3665,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3916,8 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || \ - defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4211,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h index bfbbe410f5..23439ec7e9 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h @@ -320,10 +320,10 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ -#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ +#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h index d6fe1ea256..dc6bd57898 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h @@ -123,14 +123,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers, - privileged software access to the default memory map is disabled */ -#define MPU_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers, - privileged software access to the default memory map is disabled */ -#define MPU_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers, - privileged software access to the default memory map is enabled */ -#define MPU_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers, - privileged software access to the default memory map is enabled */ +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -138,8 +134,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE 1U /*!< MPU region enabled */ -#define MPU_REGION_DISABLE 0U /*!< MPU region disabled */ +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ /** * @} */ @@ -147,8 +143,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< MPU region execution permitted (if read permitted) */ -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< MPU region execution not permitted */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ /** * @} */ @@ -156,9 +152,9 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< MPU region not shareable */ -#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< MPU region outer shareable */ -#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< MPU region inner shareable */ +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ /** * @} */ @@ -166,10 +162,10 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_PRIV_RW 0U /*!< MPU region Read/write by privileged code only */ -#define MPU_REGION_ALL_RW 1U /*!< MPU region Read/write by any privilege level */ -#define MPU_REGION_PRIV_RO 2U /*!< MPU region Read-only by privileged code only */ -#define MPU_REGION_ALL_RO 3U /*!< MPU region Read-only by any privilege level */ +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -213,18 +209,26 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */ +/* Device memory attributes */ +#define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ -#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ #define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ -#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* - transient mode attribute */ #define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ #define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ - +/* - allocation attribute */ #define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ #define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ #define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h index d147af57fb..01c13b4e74 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h @@ -297,10 +297,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h index fe75b0d496..b01fcfa517 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h @@ -175,7 +175,7 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) /* ARM Compiler @@ -208,7 +208,7 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ ) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ ) /* ARM & GNUCompiler */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h index c32b34c6ac..153c2c369c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h @@ -105,7 +105,7 @@ typedef struct uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*> 10) #endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \ - defined(STM32H523xx) || defined(STM32H503xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || \ - defined(STM32H5E5xx) || defined(STM32H5E4xx)*/ + defined(STM32H523xx) || defined(STM32H503xx) */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hcd.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hcd.h index c73f5e17b8..3c515a2921 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hcd.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hcd.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_ll_usb.h" -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32H5xx_HAL_Driver * @{ */ @@ -53,12 +53,20 @@ typedef enum HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; +#if defined (USB_DRD_FS) typedef USB_DRD_TypeDef HCD_TypeDef; typedef USB_DRD_CfgTypeDef HCD_InitTypeDef; typedef USB_DRD_HCTypeDef HCD_HCTypeDef; typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef; typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef; - +#else +typedef USB_OTG_GlobalTypeDef HCD_TypeDef; +typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +#endif /* defined (USB_DRD_FS) */ +#if defined (USB_DRD_FS) typedef enum { HCD_HCD_STATE_DISCONNECTED = 0x00U, @@ -73,7 +81,7 @@ typedef enum * 8Bytes each Block 32Bit in each word */ #define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U)) - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -90,13 +98,13 @@ typedef struct HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ - +#if defined (USB_DRD_FS) uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */ uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */ uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/ uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */ HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */ - +#endif /* defined (USB_DRD_FS) */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ __IO uint32_t ErrorCode; /*!< HCD Error code */ @@ -130,6 +138,7 @@ typedef struct /** @defgroup HCD_Speed HCD Speed * @{ */ +#define HCD_SPEED_HIGH USBH_HS_SPEED #define HCD_SPEED_FULL USBH_FSLS_SPEED #define HCD_SPEED_LOW USBH_FSLS_SPEED /** @@ -181,11 +190,29 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ & (__INTERRUPT__)) == (__INTERRUPT__)) +#if defined (USB_DRD_FS) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#else +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#endif /* defined (USB_DRD_FS) */ #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) +#if defined (USB_DRD_FS) #define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN) #define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR) +#else +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -205,9 +232,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); - +#if defined (USB_DRD_FS) HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); - +#endif /* defined (USB_DRD_FS) */ void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); @@ -282,10 +309,10 @@ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); - +#if defined (USB_DRD_FS) void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd); void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd); - +#endif /* defined (USB_DRD_FS) */ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state); /** @@ -299,11 +326,11 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); - +#if defined (USB_DRD_FS) HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd); - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -319,7 +346,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, u uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); - +#if defined (USB_DRD_FS) /* PMA Allocation functions **********************************************/ /** @addtogroup PMA Allocation * @{ @@ -333,7 +360,7 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); /** * @} */ - +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -343,7 +370,7 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_Private_Macros HCD Private Macros * @{ */ - +#if defined (USB_DRD_FS) #define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) #define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) @@ -577,7 +604,7 @@ __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint1 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum)); } - +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -593,7 +620,7 @@ __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint1 /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2s.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2s.h index bbd0a528de..a9030e38d7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2s.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2s.h @@ -505,6 +505,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); +/* IO Swap feature */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s); + /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h index 228003eb58..303706eefb 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h @@ -1086,9 +1086,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ - ((__AUTORELOAD__) <= 0x0000FFFFUL)) - #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) #define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h index ca798235ae..86a762c08f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_ll_usb.h" -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32H5xx_HAL_Driver * @{ @@ -80,9 +80,16 @@ typedef enum } PCD_BCD_MsgTypeDef; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) typedef USB_DRD_TypeDef PCD_TypeDef; typedef USB_DRD_CfgTypeDef PCD_InitTypeDef; typedef USB_DRD_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_DRD_FS) */ /** * @brief PCD Handle Structure definition @@ -96,14 +103,21 @@ typedef struct PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ __IO uint8_t USB_Address; /*!< USB Address */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_DRD_FS) */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ __IO uint32_t ErrorCode; /*!< PCD Error code */ uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . @@ -149,6 +163,8 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED #define PCD_SPEED_FULL USBD_FS_SPEED /** * @} @@ -191,13 +207,25 @@ typedef struct #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ - &= (uint16_t)(~(__INTERRUPT__))) +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) -#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE -#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE) +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ + &= (uint16_t)(~(__INTERRUPT__))) +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -334,6 +362,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); /** * @} @@ -359,15 +391,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 15) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 28) /*!< USB HS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - +#if defined (USB_DRD_FS) #define USB_WAKEUP_EXTI_LINE (0x1U << 15) /*!< USB FS EXTI Line WakeUp Interrupt */ - +#endif /* defined (USB_DRD_FS) */ /** * @} */ - +#if defined (USB_DRD_FS) /** @defgroup PCD_EP0_MPS PCD EP0 MPS * @{ */ @@ -402,16 +438,42 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */ - +#endif /* defined (USB_DRD_FS) */ /** * @} */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif /* defined USB_OTG_DOEPINT_NAK */ + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NAKM */ + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NYETM */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ */ - +#if defined (USB_DRD_FS) /* PMA RX counter */ #ifndef PCD_RX_PMA_CNT #define PCD_RX_PMA_CNT 10U @@ -607,7 +669,7 @@ __STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint1 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum)); } - +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -620,7 +682,7 @@ __STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint1 /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h index eb75ab685d..cb91e40ff3 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32H5xx_HAL_Driver * @{ */ @@ -45,11 +45,15 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - +#if defined (USB_DRD_FS) HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); - +#endif /* defined (USB_DRD_FS) */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); @@ -77,7 +81,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h index a96befc261..cadb56f2ea 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h @@ -107,6 +107,9 @@ typedef struct PKA_TypeDef *Instance; /*!< Register base address */ __IO HAL_PKA_StateTypeDef State; /*!< PKA state */ __IO uint32_t ErrorCode; /*!< PKA Error code */ + __IO uint32_t primeordersize; /*!< Elliptic curve prime order length */ + __IO uint32_t opsize; /*!< Modular exponentiation operand length */ + __IO uint32_t modulussize; /*!< Elliptic curve modulus length */ #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */ void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h index 3a73efd8e5..2f3ed7912d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h @@ -873,6 +873,7 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) #define __HAL_RCC_ETHRX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) + #endif /*ETH*/ #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) @@ -1122,6 +1123,7 @@ typedef struct #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) #endif /* SAES */ + #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) #if defined(SRAM3_BASE) @@ -1149,16 +1151,6 @@ typedef struct } while(0) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1199,34 +1191,10 @@ typedef struct } while(0) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPIM */ - #if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) #endif /* SDMMC1 */ @@ -1243,13 +1211,6 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) -#endif /* OCTOSPIM */ /** * @} */ @@ -1802,25 +1763,6 @@ typedef struct } while(0) #endif /*USB_DRD_FS*/ -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /*LTDC*/ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /*GFXTIM*/ #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -1863,14 +1805,6 @@ typedef struct #if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) #endif /* USB_DRD_FS */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) -#endif /* GFXTIM */ /** * @} */ @@ -2004,24 +1938,6 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined (PLAY1) -#define __HAL_RCC_PLAY1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_PLAY1APB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* PLAY1 */ - #define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) #if defined(SPI5) @@ -2066,10 +1982,6 @@ typedef struct #define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) -#if defined (PLAY1) -#define __HAL_RCC_PLAY1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) -#define __HAL_RCC_PLAY1APB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) -#endif /* PLAY1 */ /** * @} */ @@ -2372,10 +2284,6 @@ typedef struct #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) != 0U) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) != 0U) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) != 0U) #endif /* SDMMC1 */ @@ -2392,22 +2300,10 @@ typedef struct #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) != 0U) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) != 0U) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) != 0U) -#endif /* OCTOSPIM */ - #if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) == 0U) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) == 0U) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == 0U) #endif /* SDMMC1 */ @@ -2424,14 +2320,6 @@ typedef struct #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) == 0U) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) == 0U) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) == 0U) -#endif /* OCTOSPIM */ - /** * @} */ @@ -2710,14 +2598,6 @@ typedef struct #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) #endif /* USB_DRD_FS */ -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) -#endif /* GFXTIM */ - #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) @@ -2759,14 +2639,6 @@ typedef struct #if defined(USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) #endif /* USB_DRD_FS */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) -#endif /* GFXTIM */ /** * @} */ @@ -2823,11 +2695,6 @@ typedef struct #define __HAL_RCC_RTC_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) != 0U) -#define __HAL_RCC_PLAY1APB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) != 0U) -#endif /* PLAY1 */ - #define __HAL_RCC_SBS_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) == 0U) #if defined(SPI5) @@ -2872,11 +2739,6 @@ typedef struct #define __HAL_RCC_RTC_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) == 0U) -#define __HAL_RCC_PLAY1APB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) == 0U) -#endif /* PLAY1 */ - /** * @} */ @@ -3026,10 +2888,6 @@ typedef struct #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) #endif /* SAES*/ -#if defined(RCC_AHB2RSTR_OTGHSPHYRST) -#define __HAL_RCC_OTGPHY_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSPHYRST) -#endif /* RCC_AHB2RSTR_OTGHSPHYRST */ - #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) @@ -3085,10 +2943,6 @@ typedef struct #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) #endif /* SAES*/ -#if defined(RCC_AHB2RSTR_OTGHSPHYRST) -#define __HAL_RCC_OTGPHY_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSPHYRST) -#endif /* RCC_AHB2RSTR_OTGHSPHYRST */ - /** * @} */ @@ -3122,18 +2976,6 @@ typedef struct #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI2RST) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC2RST) -#endif /* OTFDEC2 */ - #if defined(FMC_BASE) #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) #endif /* FMC_BASE */ @@ -3158,18 +3000,6 @@ typedef struct #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI2RST) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC2RST) -#endif /* OTFDEC2 */ - /** * @} */ @@ -3446,14 +3276,6 @@ typedef struct #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) #endif /* SAI2 */ -#if defined(LTDC) -#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) -#endif /* GFXTIM */ - #if defined(USB_DRD_FS) #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) #endif /* USB_DRD_FS */ @@ -3498,14 +3320,6 @@ typedef struct #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) #endif /* SAI2 */ -#if defined(LTDC) -#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) -#endif /* GFXTIM */ - #if defined(USB_DRD_FS) #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) #endif /* USB_DRD_FS */ @@ -3561,11 +3375,6 @@ typedef struct #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) #endif /* VREFBUF */ -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1RST) -#define __HAL_RCC_PLAY1POR_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1POR) -#endif /* PLAY1 */ - #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) #if defined(SPI5) @@ -3608,10 +3417,6 @@ typedef struct #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) #endif /* VREFBUF */ -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1RST) -#define __HAL_RCC_PLAY1POR_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1POR) -#endif /* PLAY1 */ /** * @} */ @@ -3647,10 +3452,6 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) #define __HAL_RCC_ETHRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) - -#if defined(RCC_AHB1LPENR_ETHCKLPEN) -#define __HAL_RCC_ETHINTERN_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHCKLPEN) -#endif /* RCC_AHB1LPENR_ETHCKLPEN */ #endif /* ETH */ #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) @@ -3690,10 +3491,6 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) #define __HAL_RCC_ETHRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) - -#if defined(RCC_AHB1LPENR_ETHCKLPEN) -#define __HAL_RCC_ETHINTERN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHCKLPEN) -#endif /* RCC_AHB1LPENR_ETHCKLPEN */ #endif /* ETH */ #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) @@ -3754,10 +3551,6 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility */ #endif /* DCMI */ -#if defined(RCC_AHB2LPENR_OTGPHYLPEN) -#define __HAL_RCC_OTGPHY_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGPHYLPEN); -#endif /* RCC_AHB2LPENR_OTGPHYLPEN */ - #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); #endif /* AES */ @@ -3817,10 +3610,6 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility */ #endif /* DCMI */ -#if defined(RCC_AHB2LPENR_OTGPHYLPEN) -#define __HAL_RCC_OTGPHY_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGPHYLPEN) -#endif /* RCC_AHB2LPENR_OTGPHYLPEN */ - #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); #endif /* AES */ @@ -3857,10 +3646,6 @@ typedef struct #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC2LPEN) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) #endif /* SDMMC1*/ @@ -3877,22 +3662,10 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI2LPEN) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPIMLPEN) -#endif /* OCTOSPIM */ - #if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC2LPEN) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) #endif /* SDMMC1*/ @@ -3909,14 +3682,6 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI2LPEN) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPIMLPEN) -#endif /* OCTOSPIM */ - /** * @} */ @@ -4186,14 +3951,6 @@ typedef struct #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) #endif /* SAI2 */ -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_LTDCLPEN) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_GFXTIMLPEN) -#endif /* GFXTIM */ - #if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) #endif /* USB_DRD_FS */ @@ -4236,15 +3993,6 @@ typedef struct #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) #endif /* SAI2 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_LTDCLPEN) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_GFXTMLPEN) -#endif /* GFXTIM */ - #if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) #endif /* USB_DRD_FS */ @@ -4303,10 +4051,6 @@ typedef struct #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_PLAY1LPEN) -#endif /* PLAY1 */ - #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) #if defined(SPI5) @@ -4351,9 +4095,6 @@ typedef struct #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_PLAY1LPEN) -#endif /* PLAY1 */ /** * @} */ @@ -5316,16 +5057,10 @@ typedef struct ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ ((DIV) == RCC_MCODIV_15)) -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) -#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) -#else #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) -#endif /* STM32H5E5xx || STM32H5E4xx || !STM32H5F5xx || STM32H5F4xx */ #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h index e9d7b77b39..b72a8063b4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h @@ -429,6 +429,16 @@ typedef struct * @} */ +#if defined(PWR_USBSCR_OTGHSEN) +/** @defgroup OTGHS_CLK48_VALUE OTG_HS output clock + * @{ + */ +#define OTGHS_CLK48_VALUE 48000000U /*!< Value of the OTGHS_CLK48 in Hz*/ +/** + * @} + */ +#endif /* PWR_USBSCR_OTGHSEN */ + /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection * @{ */ @@ -531,6 +541,7 @@ typedef struct #if defined(I3C2) #define RCC_PERIPHCLK_I3C2 ((uint64_t)0x100000000000U) #endif /* I3C2 */ + /** * @} */ @@ -1372,6 +1383,7 @@ typedef struct #define __HAL_RCC_TIMIC_ENABLE() SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< HSI/1024, CSI/128 and HSI/8 generation for Timers 12,15 and LPTimer2 Input capture */ #define __HAL_RCC_TIMIC_DISABLE() CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< No clock available for Timers Input capture */ + /** @brief Macro to configure the PLL2 clock source. * @note This function must be used only when all PLL2 is disabled. * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng.h index 7989951776..8837fb6fdc 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h index e4ff1c700d..1a52499574 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h @@ -1736,6 +1736,17 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_ */ #endif /* TAMP_PRIVCFGR_TAMPPRIV */ +#if defined (RTC_OR_OUT2_RMP) +/** @defgroup RTCEx_Exported_Functions_Group9 Extended RTC Backup register functions + * @{ + */ +void HAL_RTCEx_EnableRemapRtcOut2(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_DisableRemapRtcOut2(RTC_HandleTypeDef *hrtc); +/** + * @} + */ +#endif /* defined (RTC_OR_OUT2_RMP) */ + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi.h index 15bf52d9fc..e1332b18cb 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi.h @@ -1091,6 +1091,9 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + +#define IS_SPI_LIMITED_TRANSFER_SIZE(SIZE) (((SIZE) < 0x3FFU) && ((SIZE) != 0U)) + /** * @brief CRC Length for limited instance */ @@ -1100,6 +1103,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) +#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) + #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ @@ -1113,6 +1118,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) + +#define IS_SPI_TRANSFER_SIZE(SIZE) (((SIZE) < 0xFFFFU) && ((SIZE) != 0U)) /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi_ex.h index b840f05ee2..72a3a69039 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi_ex.h @@ -76,6 +76,10 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour); +#if defined(SPI_CFG1_DRDS) +HAL_StatusTypeDef HAL_SPIEx_EnableDelayReadDataSampling(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_DisableDelayReadDataSampling(SPI_HandleTypeDef *hspi); +#endif /* SPI_CFG1_DRDS */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_wwdg.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_wwdg.h index 3ed2304e32..6504dee469 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_wwdg.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h index 3bb5f15564..9231b0784c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h @@ -341,38 +341,38 @@ typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); /** @defgroup XSPI_MemorySize XSPI Memory Size * @{ */ -#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ -#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ -#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ -#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ -#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ -#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ -#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ -#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ -#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ -#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ -#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ -#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ -#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ -#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ -#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ -#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ -#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ -#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ -#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ -#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ -#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ -#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ -#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ -#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ -#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ -#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ -#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ -#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ -#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ -#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ -#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ -#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ +#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Bytes = 2^( 0+1)) */ +#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Bytes = 2^( 1+1)) */ +#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Bytes = 2^( 2+1)) */ +#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Bytes = 2^( 3+1)) */ +#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Bytes = 2^( 4+1)) */ +#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Bytes = 2^( 5+1)) */ +#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Bytes = 2^( 6+1)) */ +#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Bytes = 2^( 7+1)) */ +#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Bytes = 2^( 8+1)) */ +#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KBytes = 2^( 9+1)) */ +#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KBytes = 2^(10+1)) */ +#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KBytes = 2^(11+1)) */ +#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KBytes = 2^(12+1)) */ +#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */ +#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */ +#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */ +#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KBytes = 2^(16+1)) */ +#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KBytes = 2^(17+1)) */ +#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KBytes = 2^(18+1)) */ +#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MBytes = 2^(19+1)) */ +#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MBytes = 2^(20+1)) */ +#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MBytes = 2^(21+1)) */ +#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MBytes = 2^(22+1)) */ +#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */ +#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */ +#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */ +#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MBytes = 2^(26+1)) */ +#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MBytes = 2^(27+1)) */ +#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (512 MBytes = 2^(28+1)) */ +#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits ( 1 GBytes = 2^(29+1)) */ +#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits ( 2 GBytes = 2^(30+1)) */ +#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits ( 4 GBytes = 2^(31+1)) */ /** * @} */ @@ -428,38 +428,38 @@ typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary * @{ */ -#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ -#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ -#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ -#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ -#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ -#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ -#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ -#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ -#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ -#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ -#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ -#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ -#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ -#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ -#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ -#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ -#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ -#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ -#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ -#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ -#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ -#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ -#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ -#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ -#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ -#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ -#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ -#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ -#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ -#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ -#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ -#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ +#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ +#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Bytes = 2^(1)) */ +#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Bytes = 2^(2)) */ +#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Bytes = 2^(3)) */ +#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Bytes = 2^(4)) */ +#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Bytes = 2^(5)) */ +#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Bytes = 2^(6)) */ +#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Bytes = 2^(7)) */ +#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Bytes = 2^(8)) */ +#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Bytes = 2^(9)) */ +#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KBytes = 2^(10)) */ +#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KBytes = 2^(11)) */ +#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KBytes = 2^(12)) */ +#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KBytes = 2^(13)) */ +#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KBytes = 2^(14)) */ +#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KBytes = 2^(15)) */ +#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KBytes = 2^(16)) */ +#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KBytes = 2^(17)) */ +#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KBytes = 2^(18)) */ +#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KBytes = 2^(19)) */ +#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MBytes = 2^(20)) */ +#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MBytes = 2^(21)) */ +#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MBytes = 2^(22)) */ +#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MBytes = 2^(23)) */ +#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MBytes = 2^(24)) */ +#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MBytes = 2^(25)) */ +#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MBytes = 2^(26)) */ +#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MBytes = 2^(27)) */ +#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MBytes = 2^(28)) */ +#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MBytes = 2^(29)) */ +#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GBytes = 2^(30)) */ +#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GBytes = 2^(31)) */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h index 3973a6c567..f84959f497 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h @@ -2236,7 +2236,6 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -2325,7 +2324,6 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB - * * (*) : Not available for all stm32h5xxxx family lines. * @retval None diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h index 83282d7440..ae3e9e84d3 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h @@ -103,14 +103,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers, - privileged software access to the default memory map is disabled */ -#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers, - privileged software access to the default memory map is disabled */ -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers, - privileged software access to the default memory map is enabled */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers, - privileged software access to the default memory map is enabled */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -118,18 +114,24 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes * @{ */ -#define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ -#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ #define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ -#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* - transient mode attribute */ #define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ #define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ - +/* - allocation attribute */ #define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ #define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ #define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ @@ -150,9 +152,8 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< MPU region execution permitted - if read permitted */ -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< MPU region execution not permitted */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ /** * @} */ @@ -160,9 +161,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable * @{ */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< MPU region not shareable */ -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< MPU region outer shareable */ -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< MPU region inner shareable */ +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ /** * @} */ @@ -170,10 +171,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes * @{ */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< MPU region Read/write by privileged code only */ -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< MPU region Read/write by any privilege level */ -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< MPU region Read-only by privileged code only */ -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< MPU region Read-only by any privilege level */ +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h index 8479714cb7..4daf0368e8 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h @@ -107,9 +107,9 @@ extern "C" { /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source * @{ */ -#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ -#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h index 5adeee312f..e19224a371 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h @@ -193,21 +193,6 @@ typedef struct #if defined(EXTI_IMR2_IM58) #define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ #endif /* EXTI_IMR2_IM58 */ -#if defined(EXTI_IMR2_IM59) -#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */ -#endif /* EXTI_IMR2_IM59 */ -#if defined(EXTI_IMR2_IM60) -#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */ -#endif /* EXTI_IMR2_IM60 */ -#if defined(EXTI_IMR2_IM61) -#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */ -#endif /* EXTI_IMR2_IM61 */ -#if defined(EXTI_IMR2_IM62) -#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */ -#endif /* EXTI_IMR2_IM62 */ -#if defined(EXTI_IMR2_IM63) -#define LL_EXTI_LINE_63 EXTI_IMR2_IM63 /*!< Extended line 63 */ -#endif /* EXTI_IMR2_IM63 */ #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< ALL Extended lines */ #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ @@ -928,7 +913,6 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * @note Please check each device line mapping for EXTI Line availability @@ -988,7 +972,6 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * @@ -1036,7 +1019,6 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * @@ -1211,6 +1193,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1429,6 +1412,7 @@ __STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1478,6 +1462,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1619,8 +1604,6 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_EXTI_PORTG (*) * @arg @ref LL_EXTI_EXTI_PORTH * @arg @ref LL_EXTI_EXTI_PORTI (*) - * @arg @ref LL_EXTI_EXTI_PORTJ (*) - * @arg @ref LL_EXTI_EXTI_PORTK (*) * * (*) value not defined in all devices * @param Line This parameter can be one of the following values: @@ -1693,8 +1676,6 @@ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) * @arg @ref LL_EXTI_EXTI_PORTG (*) * @arg @ref LL_EXTI_EXTI_PORTH * @arg @ref LL_EXTI_EXTI_PORTI (*) - * @arg @ref LL_EXTI_EXTI_PORTJ (*) - * @arg @ref LL_EXTI_EXTI_PORTK (*) * * (*) value not defined in all devices */ @@ -2053,6 +2034,7 @@ __STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_56 * @arg @ref LL_EXTI_LINE_57 * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_63 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval None diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h index a5c0c6020b..72db31d699 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h @@ -32,7 +32,7 @@ extern "C" { */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) /** @defgroup GPIO_LL GPIO * @{ @@ -1169,8 +1169,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || \ - defined (GPIOK) */ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h index 4c992b2879..f2e046e83e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h @@ -1567,13 +1567,13 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) } /** - * @brief Indicate whether the VDD voltage is below the threshold or not. + * @brief Indicate whether the VDDA voltage is below the threshold or not. * @rmtoll VMSR AVDO LL_PWR_IsActiveFlag_AVDO * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) { - return ((READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == (PWR_VMSR_AVDO)) ? 1UL : 0UL); + return ((READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == (PWR_VMSR_AVDO)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h index ee4a74ccc1..75c5eebf1e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h @@ -920,6 +920,8 @@ typedef struct #define LL_RCC_USB_CLKSOURCE_PLL1Q RCC_CCIPR4_USBSEL_0 /*!< PLL1 Q clock used as USB clock source */ #if defined(RCC_CR_PLL3ON) #define LL_RCC_USB_CLKSOURCE_PLL3Q RCC_CCIPR4_USBSEL_1 /*!< PLL3 Q clock used as USB clock source */ +#else +#define LL_RCC_USB_CLKSOURCE_PLL2Q RCC_CCIPR4_USBSEL_1 /*!< PLL2 Q clock used as USB clock source */ #endif /* PLL3 */ #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CCIPR4_USBSEL /*!< HSI48 clock used as USB clock source */ /** @@ -2821,8 +2823,9 @@ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) * @retval None * - * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (*) : For stm32h56xxx, stm32h57xxx, stm32h5exxx and stm32h5fxxx family lines. * (**) : For stm32h503xx family line. + * (***) : For stm32h5exxx and stm32h5fxxx family lines. */ __STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t I3CxSource) { @@ -3013,10 +3016,11 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) * @param USBxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_NONE * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2Q (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*) * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 * - * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (*) : Available in some STM32H5 lines only. * @retval None */ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) @@ -3776,10 +3780,11 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_NONE * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2Q (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*) * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 * - * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (*) : Available in some STM32H5 lines only. */ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h index 5984bb4e99..c12adfe691 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h @@ -3507,7 +3507,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32 /** * @brief Enable backup register erase after internal tamper event detection * @rmtoll TAMP_CR3 ITAMP1NOER LL_RTC_TAMPER_ITAMP_EnableEraseBKP - * @rmtoll TAMP_CR3 ITAMP2NOER LL_RTC_TAMPER_ITAMP_EnableEraseBKP + * TAMP_CR3 ITAMP2NOER... LL_RTC_TAMPER_ITAMP_EnableEraseBKP * @param RTCx RTC Instance * @param InternalTamper This parameter can be a combination of the following values: * @arg @ref RTC_LL_EC_ITAMPER_NOERASE @@ -3523,7 +3523,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_EnableEraseBKP(const RTC_TypeDef *RTCx, /** * @brief Disable backup register erase after internal tamper event detection * @rmtoll TAMP_CR3 ITAMP1NOER LL_RTC_TAMPER_ITAMP_DisableEraseBKP - * @rmtoll TAMP_CR3 ITAMP2NOER LL_RTC_TAMPER_ITAMP_DisableEraseBKP + * TAMP_CR3 ITAMP2NOER... LL_RTC_TAMPER_ITAMP_DisableEraseBKP * @param RTCx RTC Instance * @param InternalTamper This parameter can be a combination of the following values: * @arg @ref RTC_LL_EC_ITAMPER_NOERASE @@ -6413,9 +6413,49 @@ __STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(const RTC_TypeDef *RTCx) return READ_REG(TAMP->COUNT1R); } +#if defined (RTC_OR_OUT2_RMP) /** - * @} + * @brief Enable RTC OUT2 remap feature. + * @rmtoll RTC_OR OUT2_RMP LL_RTC_EnableRemapRtcOut2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableRemapRtcOut2(const RTC_TypeDef *RTCx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(RTCx); + /* Enable RTC OUT2 remap */ + SET_BIT(RTC->OR, RTC_OR_OUT2_RMP); +} + +/** + * @brief Disable RTC OUT2 remap feature. + * @rmtoll RTC_OR OUT2_RMP LL_RTC_DisableRemapRtcOut2 + * @param RTCx RTC Instance + * @retval None */ +__STATIC_INLINE void LL_RTC_DisableRemapRtcOut2(const RTC_TypeDef *RTCx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(RTCx); + /* Disable RTC OUT2 remap */ + CLEAR_BIT(RTC->OR, RTC_OR_OUT2_RMP); +} + +/** + * @brief Check if RTC_OUT2 is mapped on PB2. + * @rmtoll RTC_OR OUT2_RMP IsEnabledRemapRtcOut2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledRemapRtcOut2(const RTC_TypeDef *RTCx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(RTCx); + /* Disable RTC OUT2 remap */ + return ((READ_BIT(RTC->OR, RTC_OR_OUT2_RMP) == (RTC_OR_OUT2_RMP)) ? 1U : 0U); +} +#endif /* defined (RTC_OR_OUT2_RMP) */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h index 88b6e715e0..ba71bac454 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h @@ -3632,7 +3632,7 @@ __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) */ ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h index 70f3038036..72aae2579d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h @@ -1468,10 +1468,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) */ /** - * @brief Check if FRS interrupt + * @brief Check if FRS Event Flag is active * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { @@ -1482,7 +1482,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD * @brief Check if type c event on CC2 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { @@ -1493,7 +1493,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @brief Check if type c event on CC1 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { @@ -1501,10 +1501,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * } /** - * @brief Check if Rx message end interrupt + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { @@ -1512,10 +1523,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const } /** - * @brief Check if Rx overrun interrupt + * @brief Check if Rx overrun flag is active * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { @@ -1523,10 +1534,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard reset interrupt + * @brief Check if Rx hard reset flag is active * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { @@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U } /** - * @brief Check if Rx orderset interrupt + * @brief Check if Rx orderset flag is active * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con } /** - * @brief Check if Rx non empty interrupt + * @brief Check if Rx non empty flag is active * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP } /** - * @brief Check if TX underrun interrupt + * @brief Check if TX underrun flag is active * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC } /** - * @brief Check if hard reset sent interrupt + * @brief Check if hard reset sent flag is active * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con } /** - * @brief Check if hard reset discard interrupt + * @brief Check if hard reset discard flag is active * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con } /** - * @brief Check if Tx message abort interrupt + * @brief Check if Tx message abort flag is active * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const } /** - * @brief Check if Tx message sent interrupt + * @brief Check if Tx message sent flag is active * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1611,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons } /** - * @brief Check if Tx message discarded interrupt + * @brief Check if Tx message discarded flag is active * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1622,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons } /** - * @brief Check if Tx data receive interrupt + * @brief Check if Tx data interrupt flag is active * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h index b310e7ee41..2b84d460af 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32H5xx_HAL_Driver * @{ */ @@ -41,6 +41,10 @@ extern "C" { #define HAL_USB_TIMEOUT 0xF000000U #endif /* define HAL_USB_TIMEOUT */ +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ + /** * @brief USB Mode definition */ @@ -48,7 +52,8 @@ extern "C" { typedef enum { USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1 + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 } USB_ModeTypeDef; /** @@ -117,9 +122,16 @@ typedef struct uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) uint8_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ +#endif /* defined (USB_DRD_FS) */ } USB_CfgTypeDef; typedef struct @@ -133,13 +145,18 @@ typedef struct uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_LL_EP_Type */ uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - +#if defined (USB_DRD_FS) uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ @@ -151,7 +168,7 @@ typedef struct uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ - +#endif /* defined (USB_DRD_FS) */ uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ @@ -162,29 +179,57 @@ typedef struct uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_size; /*!< requested transfer size */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ +#endif /* defined (USB_DRD_FS) */ } USB_EPTypeDef; typedef struct { uint8_t dev_addr; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - +#if defined (USB_DRD_FS) uint8_t phy_ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t ch_dir; /*!< channel direction This parameter store the physical channel direction IN/OUT/BIDIR */ +#else + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_DRD_FS) */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint8_t speed; /*!< USB Host Channel speed. This parameter can be any value of @ref HCD_Device_Speed: (HCD_DEVICE_SPEED_xxx) */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint8_t hub_port_nbr; /*!< USB HUB port number */ uint8_t hub_addr; /*!< USB HUB address */ @@ -199,10 +244,14 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - uint32_t xfer_len; /*!< Current transfer length. */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint32_t XferSize; /*!< OTG Channel transfer size. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint32_t xfer_len; /*!< Current transfer length. */ +#if defined (USB_DRD_FS) uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ - +#endif /* defined (USB_DRD_FS) */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ @@ -211,9 +260,14 @@ typedef struct uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t ErrCnt; /*!< Host channel error count. */ +#if defined (USB_DRD_FS) uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ @@ -225,6 +279,7 @@ typedef struct uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ +#endif /* defined (USB_DRD_FS) */ USB_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_URBStateTypeDef */ @@ -233,18 +288,113 @@ typedef struct This parameter can be any value of @ref USB_HCStateTypeDef */ } USB_HCTypeDef; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; typedef USB_EPTypeDef USB_DRD_EPTypeDef; typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; typedef USB_HCTypeDef USB_DRD_HCTypeDef; +#endif /* defined (USB_DRD_FS) */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_EMBEDDED_PHY 2U +#define USB_OTG_HS_EMBEDDED_PHY 3U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -292,12 +442,105 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; /** @defgroup USB_LL Device Speed * @{ */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U #define USBD_FS_SPEED 2U #define USBH_FSLS_SPEED 1U /** * @} */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + + +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) #define EP_ADDR_MSK 0x7U #ifndef USE_USB_DOUBLE_BUFFER @@ -692,7 +935,7 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ @@ -824,12 +1067,22 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; */ #define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) #define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) - +#endif /* defined (USB_DRD_FS) */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -838,8 +1091,65 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; /** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - +#if defined (USB_DRD_FS) HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); @@ -885,7 +1195,7 @@ void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -901,7 +1211,7 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h index 86bcdd01aa..0391069307 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h @@ -186,25 +186,25 @@ typedef struct /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE * @{ */ -#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ -#define LL_UTILS_PACKAGETYPE_VFQFPN68 0x00000001U /*!< VFQFPN68 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA176 0x00000003U /*!< UFBGA176+25 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000006U /*!< UFBGA169 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP176 0x00000007U /*!< LQFP176 package type */ -#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000009U /*!< UFQFPN32 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000BU /*!< UFBGA176+25 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x0000000DU /*!< LQFP176 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000EU /*!< UFBGA169 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP25 0x0000000FU /*!< WLCSP25 package type */ -#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQFPN48 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP39 0x00000011U /*!< WLCSP39 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000014U /*!< UFBGA100 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000015U /*!< UFBGA144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_VFQFPN68 0x00000001U /*!< VFQFPN68 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176 0x00000003U /*!< UFBGA176+25 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000006U /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176 0x00000007U /*!< LQFP176 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000009U /*!< UFQFPN32 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000BU /*!< UFBGA176+25 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x0000000DU /*!< LQFP176 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000EU /*!< UFBGA169 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP25 0x0000000FU /*!< WLCSP25 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP39 0x00000011U /*!< WLCSP39 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000014U /*!< UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000015U /*!< UFBGA144 package type */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h index 2cd97d7ff2..146828c24e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h @@ -33,7 +33,8 @@ extern "C" { #include "stm32h5xx_ll_i3c.h" #endif /* USE_FULL_LL_DRIVER */ -/** @addtogroup STM32H5xx_UTIL_Driver +#if (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) +/** @addtogroup STM32H7RSxx_UTIL_Driver * @{ */ @@ -128,6 +129,7 @@ ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming, * @} */ +#endif /* (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) */ #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html index 0a95394326..98bfe52f2d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html @@ -40,10 +40,123 @@

Purpose

Update History

- +

Main Changes

    +
  • Maintenance Release V1.4.0 of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx / STM32H523xx/ STM32H533xx devices
    • +
  • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and Coverity compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
    • +

  • General updates to fix known defects and implementation enhancements

    +
      +
    • HAL drivers : +
        +
      • HAL CRYP driver +
          +
        • Code quality enhancement MISRAC 2012 Rule-10.4
          • +
        • +
      • HAL DAC driver +
          +
        • HAL DAC calibration procedure (function HAL_DACEx_SelfCalibrate() ) fix to manage case of calibration factor equal to range maximum value (previously, in this case calibration factor was reset, leading to voltage accuracy not optimal)
          • +
        • +
      • HAL DMA_EX driver +
          +
        • Update CLLR register value
          • +
        • Remove duplicated assert checking
          • +
        • +
      • HAL FLASH driver +
          +
        • Update Flash driver to support 32 bits write operation in the EDATA area
          • +
        • +
      • HAL FLASH_EX driver +
          +
        • Add of HAL_FLASHEx_OBK_Swap_IT() function
          • +
        • +
      • HAL FMAC driver +
          +
        • Add action to abort, if configured, the DMAIn and/or the DMAOut in HAL_FMAC_FilterStop. This allows to reset the DMA State to READY
          • +
        • +
      • HAL GTZC driver +
          +
        • Updated HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() and HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes() for MPCWM3 and MPCWM4 to be aligned with the hardware specification
          • +
        • +
      • HAL LPTIM driver +
          +
        • Remove redundant IS_LPTIM_AUTORELOAD macro
          • +
        • +
      • HAL PKA driver +
          +
        • add check for MontgomeryParam not equal to null
          • +
        • +
      • HAL PWR driver +
          +
        • Add guidance for HAL_PWR_ConfigAttributes() API calls
          • +
        • +
      • HAL RCC driver +
          +
        • Fix incorrect HAL_RCCEx_GetPLLxClockFreq() when fractional part is enabled
          • +
        • Add g for HAL_RCC_ConfigAttributes() API calls
          • +
        • +
      • HAL RNG driver +
          +
        • Add HAL_RNG_ERROR_RECOVERSEED define
          • +
        • +
      • HAL RTC_EX driver +
          +
        • Add HAL_RTCEx_EnableRemapRtcOut2 and HAL_RTCEx_DisableRemapRtcOut2 defines
          +
          • +
        • +
      • HAL SPI driver +
          +
        • Fix issue with HAL_SPI_Abort_IT in DMA mode to ensure DMA RX aborts after DMA TX
          • +
        • HAL code quality enhancement for MISRA-C2012 Rule-8.13
          • +
        • +
      • HAL UART driver +
          +
        • Fix DMA Rx abort procedure impact on ongoing Tx transfer in polling
          • +
        • +
      • HAL XSPI driver +
          +
        • Check BUSY flag instead of TC flag in indirect mode to be sure that command is well completed (FIFO flush)
          • +
        • +
      • +
    • LL drivers : +
        +
      • LL DMA driver +
          +
        • Fix in linked list node initialization
          • +
        • Add missing assert checking in some LL linked-list case
          • +
        • +
      • LL RCC driver +
          +
        • Add missing definition and processing of LL_RCC_USB_CLKSOURCE_PLL2Q
          • +
        • +
      • LL RTC driver +
          +
        • Add LL_RTC_EnableRemapRtcOut2 define
          • +
        • +
      • LL USB driver +
          +
        • Fix added to support bulk transfer in double buffer mode
          • +
        • +
      • +
    • +
+

Note: HAL/LL Backward compatibility ensured by legacy defines.

+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • No compatibility break
    • +
+
+
+
+ +
+

Main Changes

+
  • Maintenance release V1.3.0 of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx / STM32H523xx/ STM32H533xx devices
  • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and Coverity compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors

  • General updates to fix known defects and implementation enhancements

    @@ -74,11 +187,11 @@

    Main Changes

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -87,7 +200,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First offiicial release of HAL and LL drivers to support STM32H533xx and STM32H523xx devices

      @@ -257,11 +370,11 @@

      Main Changes

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -270,7 +383,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Maintenance Release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices

      @@ -342,11 +455,11 @@

      Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -355,15 +468,15 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First official release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices
-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Not Applicable
diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c index 42780e8e8a..f7e50f7883 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c @@ -48,10 +48,10 @@ /* Private typedef ---------------------------------------------------------------------------------------------------*/ /* Private define ----------------------------------------------------------------------------------------------------*/ /** - * @brief STM32H5xx HAL Driver version number 1.3.0 + * @brief STM32H5xx HAL Driver version number 1.4.0 */ #define __STM32H5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5XX_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32H5XX_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32H5XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32H5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c index 1441e27558..c2e280c941 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c @@ -2843,7 +2843,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_Chann /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { - if (pConfig->Channel == ADC_CHANNEL_0) + if ((pConfig->Channel == ADC_CHANNEL_0) + || ((pConfig->Channel == ADC_CHANNEL_1) && (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED))) { LL_ADC_EnableChannel0_GPIO(hadc->Instance); } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c index 9fb60dca32..16cd801f4b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c @@ -1907,11 +1907,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, /* mode is disabled. */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { - if (pConfigInjected->InjectedChannel == ADC_CHANNEL_0) + if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_0) + || ((pConfigInjected->InjectedChannel == ADC_CHANNEL_1) + && (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)) + ) { LL_ADC_EnableChannel0_GPIO(hadc->Instance); } - /* If auto-injected mode is disabled: no constraint */ if (pConfigInjected->AutoInjectedConv == DISABLE) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c index 624abb2b62..8d1b01e063 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c @@ -74,19 +74,22 @@ (++) Reload Value should not exceed 0xFFFFFF [..] - *** How to configure MPU (secure and non secure) using CORTEX HAL driver *** - =========================================================== + *** How to configure MPU regions using CORTEX HAL driver *** + ============================================================ [..] - This section provides functions allowing to Enable and configure the MPU secure and non-secure. + This section provides functions allowing to configure the Memory Protection Unit (MPU). + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. (#) Enable the MPU using HAL_MPU_Enable() function. - (#) Disable the MPU using HAL_MPU_Disable() function. - (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU. - (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU. - (#) Configure the MPU region using HAL_MPU_ConfigRegion() - and HAL_MPU_ConfigRegion_NS() to address the non secure MPU. - (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes() - and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context @endverbatim ****************************************************************************** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c index 179643cf84..6997679741 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c @@ -363,6 +363,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp); static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); @@ -635,6 +636,13 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); @@ -649,10 +657,23 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD { /* Disable AES to change key mode */ __HAL_CRYP_DISABLE(hcryp); + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set key mode selection (Normal, Wrapped or Shared key )*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ @@ -1206,7 +1227,11 @@ HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_Contex hcryp->Init.KeyMode = pcont->KeyMode; hcryp->Phase = pcont->Phase; hcryp->KeyIVConfig = pcont->KeyIVConfig; - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } /* Restore CRYP CR register content */ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); @@ -1379,11 +1404,25 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); } else { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode and normal key selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); } @@ -1474,10 +1513,22 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, { hcryp->Size = Size; } - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + if (IS_AES_ALL_INSTANCE(hcryp->Instance)) + { + /* Set Decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_DECRYPT | CRYP_KEYMODE_NORMAL); + } /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; @@ -1584,7 +1635,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1687,7 +1744,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1772,7 +1835,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1934,7 +2003,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -3573,7 +3648,31 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Writes Key in Key registers. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3647,7 +3746,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -5998,7 +6096,7 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *In static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - uint32_t count = 0U; + uint32_t count; /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c index 3637c02260..d6a95d9965 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c @@ -39,7 +39,7 @@ /** @addtogroup CRYPEx_Private_Defines * @{ */ - +#define CRYPEx_GENERAL_TIMEOUT 82U #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ @@ -66,6 +66,7 @@ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyGeneration(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions @@ -126,6 +127,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c /* Check if initialization phase has already been performed */ if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -144,19 +152,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -504,7 +509,13 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Encryption operating mode(Mode 0)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -568,7 +579,13 @@ HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Decryption operating mode(Mode 3)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -809,6 +826,31 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T __HAL_UNLOCK(hcryp); return HAL_OK; } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ + +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Key Generation * @param hcryp pointer to a CRYP_HandleTypeDef structure diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c index 79388cd6b2..f1f2940894 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c @@ -1250,6 +1250,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c index 8ba7fbfc74..9d541efef6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c @@ -749,8 +749,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16UL; - delta = 8UL; + trimmingvalue = 0x10UL; + delta = 0x08UL; while (delta != 0UL) { /* Set candidate trimming */ @@ -796,8 +796,12 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* Trimming is actually one value more */ - trimmingvalue++; + /* Check trimming value below maximum */ + if (trimmingvalue < 0x1FU) + { + /* Trimming is actually one value more */ + trimmingvalue++; + } /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } @@ -870,8 +874,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval Trimming value : range: 0->31 - * + * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c index 21d339b5b0..27d2c19b62 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c @@ -1091,10 +1091,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); } /* Check DMA channel security and privilege attributes parameters */ @@ -3903,8 +3899,19 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); } /********************************************************************************* CBR2 register value is updated */ - } + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + else + { + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } /* Update node information value ************************************************************************************/ /* Set node information */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c index d04ecc6f43..be5ef6cf96 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c @@ -1081,7 +1081,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) heth->RxDescList.RxDataLength = 0; } - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + /* Get the Frame Length of the received packet */ bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; /* Check if last descriptor */ @@ -1209,7 +1209,7 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { /* Set the tail pointer index */ - tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT; /* DMB instruction to avoid race condition */ __DMB(); @@ -1429,7 +1429,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) #ifdef HAL_ETH_USE_PTP /* Disable Ptp transmission */ - CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); + CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE); if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD) && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS)) @@ -1506,6 +1506,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT return HAL_ERROR; } + /* Mask the Timestamp Trigger interrupt */ + CLEAR_BIT(heth->Instance->MACIER, ETH_MACIER_TSIE); + tmpTSCR = ptpconfig->Timestamp | ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) | ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) | @@ -1539,8 +1542,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT } } - /* Ptp Init */ - SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) + { + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT); + } /* Set PTP Configuration done */ heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED; @@ -1552,6 +1558,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT HAL_ETH_PTP_SetTime(heth, &time); + /* Ptp Init */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Return function status */ return HAL_OK; } @@ -1969,7 +1978,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) if ((mac_flag & ETH_MAC_LPI_IT) != 0U) { /* Get MAC LPI interrupt source and clear the status register pending bit */ - heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); + heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered EEE callback*/ @@ -2453,7 +2462,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_ ((uint32_t)pFilterConfig->HashMulticast << 2) | ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | ((uint32_t)pFilterConfig->PassAllMulticast << 4) | - ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) | ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | @@ -2486,7 +2495,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_ pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; - pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE; pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; @@ -3018,7 +3027,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param pTxConfig: Tx packet configuration - * @param ItMode: Enable or disable Tx EOT interrept + * @param ItMode: Enable or disable Tx EOT interrupt * @retval Status */ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fdcan.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fdcan.c index 68c573d403..99c1543a8d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fdcan.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fdcan.c @@ -1309,7 +1309,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA if (sFilterConfig->IdType == FDCAN_STANDARD_ID) { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); @@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c index ae7425ca07..363a539ae1 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c @@ -124,6 +124,9 @@ static void FLASH_Program_QuadWord(uint32_t FlashAddress, uint32_t Data static void FLASH_Program_QuadWord_OBK(uint32_t FlashAddress, uint32_t DataAddress); #endif /* FLASH_SR_OBKERR */ static void FLASH_Program_HalfWord(uint32_t FlashAddress, uint32_t DataAddress); +#if defined(FLASH_EDATAR_EDATA_EN) +static void FLASH_Program_Word(uint32_t FlashAddress, uint32_t DataAddress); +#endif /* FLASH_EDATAR_EDATA_EN */ /** * @} @@ -170,9 +173,6 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - /* Process Locked */ - __HAL_LOCK(&pFlash); - /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; @@ -218,6 +218,14 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, /* Program a Flash high-cycle data half-word at a specified address */ FLASH_Program_HalfWord(FlashAddress, DataAddress); } + else if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_WORD_EDATA) + { + /* Check the parameters */ + assert_param(IS_FLASH_EDATA_ADDRESS(FlashAddress)); + + /* Program a Flash high-cycle data half-word at a specified address */ + FLASH_Program_Word(FlashAddress, DataAddress); + } #endif /* FLASH_EDATAR_EDATA_EN */ else { @@ -246,9 +254,6 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK | FLASH_OTP))); #endif /* FLASH_SR_OBKERR */ } - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - /* return status */ return status; } @@ -271,9 +276,6 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - /* Process Locked */ - __HAL_LOCK(&pFlash); - /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; @@ -336,6 +338,14 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre /* Program a Flash high-cycle data half-word at a specified address */ FLASH_Program_HalfWord(FlashAddress, DataAddress); } + else if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_WORD_EDATA) + { + /* Check the parameters */ + assert_param(IS_FLASH_EDATA_ADDRESS(FlashAddress)); + + /* Program a Flash high-cycle data word at a specified address */ + FLASH_Program_Word(FlashAddress, DataAddress); + } #endif /* FLASH_EDATAR_EDATA_EN */ else { @@ -483,8 +493,6 @@ void HAL_FLASH_IRQHandler(void) (*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \ FLASH_IT_STRBERR | FLASH_IT_INCERR | FLASH_IT_OPTCHANGEERR); #endif /* FLASH_SR_OBKERR */ - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); } } @@ -916,6 +924,31 @@ static void FLASH_Program_HalfWord(uint32_t FlashAddress, uint32_t DataAddress) *(__IO uint16_t *)FlashAddress = *(__IO uint16_t *)DataAddress; } +#if defined(FLASH_EDATAR_EDATA_EN) +/** + * @brief Program a word (32-bit) at a specified address. + * @param FlashAddress specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t FlashAddress, uint32_t DataAddress) +{ + __IO uint32_t *reg_cr; + + /* Access to SECCR or NSCR registers depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Set PG bit */ + SET_BIT((*reg_cr), FLASH_CR_PG); + + *(__IO uint32_t *)FlashAddress = *(__IO uint32_t *)DataAddress; +} +#endif /* FLASH_EDATAR_EDATA_EN */ + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c index 2d83c5411c..db13a53225 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c @@ -261,9 +261,6 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - /* Process Locked */ - __HAL_LOCK(&pFlash); - /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; @@ -272,8 +269,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) if (status != HAL_OK) { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); + return status; } else { @@ -597,6 +593,38 @@ HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset) return status; } +/** + * @brief Swap the FLASH Option Bytes Keys (OBK) with interrupt enabled + * @param SwapOffset Specifies the number of keys to be swapped. + * This parameter can be a value between 0 (no OBK data swapped) and 511 (all OBK data swapped). + * Typical value are available in @ref FLASH_OBK_SWAP_Offset + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap_IT(uint32_t SwapOffset) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_obkcfgr; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Access to SECOBKCFGR or NSOBKCFGR registers depends on operation type */ + reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR); + + /* Enable End of Operation and Error interrupts */ + (*reg_obkcfgr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR); + + /* Set OBK swap offset */ + MODIFY_REG((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_OFFSET, (SwapOffset << FLASH_OBKCFGR_SWAP_OFFSET_Pos)); + + /* Set OBK swap request */ + SET_BIT((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_SECT_REQ); + } + + return status; +} #endif /* FLASH_SR_OBKERR */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fmac.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fmac.c index 8709c66720..a336d765a8 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fmac.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fmac.c @@ -1199,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1218,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1235,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gtzc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gtzc.c index 26ccc25b54..13482f839d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gtzc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gtzc.c @@ -599,7 +599,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddres * (Parameter already checked) */ size = GTZC_TZSC_MPCWM3_MEM_SIZE; - register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR); + register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3BR); break; #endif /* (FMC_SDRAM_BANK_1) */ #if defined(BKPSRAM_BASE) @@ -617,7 +617,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddres * (Parameter already checked) */ size = GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE ; - register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR); + register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4BR); break; #endif /* (FMC_SDRAM_BANK_2) */ default: @@ -697,7 +697,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd #endif /* defined(FMC_BANK3) */ #if defined(FMC_SDRAM_BANK_1) case FMC_SDRAM_BANK_1: - register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR); + register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3BR); break; #endif /* (FMC_SDRAM_BANK_1) */ #if defined(BKPSRAM_BASE) @@ -707,7 +707,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd #endif /* (BKPSRAM_BASE) */ #if defined(FMC_SDRAM_BANK_2) case FMC_SDRAM_BANK_2: - register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR); + register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4BR); break; #endif /* (FMC_SDRAM_BANK_2) */ default: diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c index ab74378f59..9d5019227d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c @@ -35,29 +35,1953 @@ (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_CLK_ENABLE(); (##) Initialize the related GPIO clocks (##) Configure HCD pin-out (##) Configure HCD NVIC interrupt - (#)Associate the Upper USB Host stack to the HAL HCD Driver: - (##) hhcd.pData = phost; + (#)Associate the Upper USB Host stack to the HAL HCD Driver: + (##) hhcd.pData = phost; + + (#)Enable HCD transmission and reception: + (##) HAL_HCD_Start(); + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +#ifdef HAL_HCD_MODULE_ENABLED +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @defgroup HCD HCD + * @brief HCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + +#if defined (USB_OTG_FS) + USBx = hhcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if (USBx == USB_OTG_FS) + { + hhcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + + /* Disable the Interrupts */ + __HAL_HCD_DISABLE(hhcd); + + /* Init the Core (common init.) */ + if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Host Mode */ + if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Init Host */ + if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_DEVICE_SPEED_HIGH: High speed mode, + * HCD_DEVICE_SPEED_FULL: Full speed mode, + * HCD_DEVICE_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochronous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef status; + uint32_t HostCoreSpeed; + uint32_t HCcharMps = mps; + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].dev_addr = dev_address; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].ep_type = ep_type; + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num); + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + + HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + if (ep_type == EP_TYPE_ISOC) + { + /* FS device plugged to HS HUB */ + if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + if (HCcharMps > ISO_SPLT_MPS) + { + /* ISO Max Packet Size for Split mode */ + HCcharMps = ISO_SPLT_MPS; + } + } + } + + hhcd->hc[ch_num].speed = speed; + hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps; + + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, + dev_address, speed, ep_type, (uint16_t)HCcharMps); + + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Halt(hhcd->Instance, ch_num); + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_HCD_MspDeInit(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_DISABLE(hhcd); + + hhcd->State = HAL_HCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USB Host Data + Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochronous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + hhcd->hc[ch_num].ep_is_in = direction; + hhcd->hc[ch_num].ep_type = ep_type; + + if (token == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if (token == 1U) /* send data */ + { + if (direction == 0U) + { + if (length == 0U) + { + /* For Status OUT stage, Length == 0U, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].do_ssplit == 1U) + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + + break; + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num].xfer_buff = pbuff; + hhcd->hc[ch_num].xfer_len = length; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].state = HC_IDLE; + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); +} + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + uint32_t interrupt; + + /* Ensure that we are in device mode */ + if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) + { + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + { + return; + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle Host Disconnect Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Flush USB Fifo */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Host Port Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + { + HCD_Port_IRQHandler(hhcd); + } + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + { + interrupt = USB_HC_ReadInterrupt(hhcd->Instance); + for (i = 0U; i < hhcd->Init.Host_channels; i++) + { + if ((interrupt & (1UL << (i & 0xFU))) != 0U) + { + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) + { + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); + } + else + { + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); + } + } + } + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); + } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + } +} + + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callback is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the HCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + /* Enable port power */ + (void)USB_DriveVbus(hhcd->Instance, 1U); + + /* Enable global interrupt */ + __HAL_HCD_ENABLE(hhcd); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + (void)USB_StopHost(hhcd->Instance); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + return (USB_ResetPort(hhcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetCurrentFrame(hhcd->Instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetHostSpeed(hhcd->Instance)); +} + +/** + * @brief Set host channel Hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + /* LS/FS device plugged to HS HUB */ + if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + hhcd->hc[ch_num].do_ssplit = 1U; + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U)) + { + hhcd->hc[ch_num].toggle_in = 1U; + } + } + + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].do_ssplit = 0U; + hhcd->hc[ch_num].do_csplit = 0U; + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup HCD_Private_Functions + * @{ + */ +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else + { + /* ... */ + } + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) + { + /* Clear any pending ACK IT */ + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + if (hhcd->Init.dma_enable != 0U) + { + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + } + + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) + { + USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + /* ... */ + } + + if (hhcd->Init.dma_enable == 1U) + { + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 1U; + hhcd->hc[chnum].state = HC_ACK; + + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].NyetErrCnt++; + if (hhcd->hc[chnum].NyetErrCnt > 2U) + { + hhcd->hc[chnum].NyetErrCnt = 0U; + hhcd->hc[chnum].do_csplit = 0U; + + if (hhcd->hc[chnum].ErrCnt < 3U) + { + hhcd->hc[chnum].ep_ss_schedule = 1U; + } + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Set Complete split and re-activate the channel */ + USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else if (hhcd->hc[chnum].state == HC_BBLERR) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; - (#)Enable HCD transmission and reception: - (##) HAL_HCD_Start(); + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].ErrCnt = 0U; + } - @endverbatim - ****************************************************************************** + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) + { + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + } + else + { + /* ... */ + } + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + __HAL_HCD_UNMASK_ACK_HC_INT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t num_packets; -/* Includes ------------------------------------------------------------------*/ -#include "stm32h5xx_hal.h" + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); -/** @addtogroup STM32H5xx_HAL_Driver - * @{ + if (hhcd->hc[chnum].do_ping == 1U) + { + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + + if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) + { + if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) + { + hhcd->hc[chnum].do_csplit = 1U; + } + + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + + /* reset error_count */ + hhcd->hc[chnum].ErrCnt = 0U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + /* transaction completed with NYET state, update do ping state */ + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + + if (hhcd->hc[chnum].do_csplit != 0U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].do_ping = 1U; + } + + hhcd->hc[chnum].ErrCnt = 0U; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + + if (hhcd->hc[chnum].do_ping == 0U) + { + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) + { + hhcd->hc[chnum].do_ping = 1U; + } + } + + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else + { + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) + { + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) + { + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else + { + return; + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + return; + } +} + +/** + * @brief Handle Rx Queue Level interrupt requests. + * @param hhcd HCD handle + * @retval none */ +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t pktsts; + uint32_t pktcnt; + uint32_t GrxstspReg; + uint32_t xferSizePktCnt; + uint32_t tmpreg; + uint32_t chnum; + + GrxstspReg = hhcd->Instance->GRXSTSP; + chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; + + switch (pktsts) + { + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) + { + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) + { + (void)USB_ReadPacket(hhcd->Instance, + hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); -#ifdef HAL_HCD_MODULE_ENABLED + /* manage multiple Xfer */ + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; + + /* get transfer size packet count */ + xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_ERROR; + } + } + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } +} + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0; + __IO uint32_t hprt0_dup; + + /* Handle Host Port Interrupts */ + hprt0 = USBx_HPRT0; + hprt0_dup = USBx_HPRT0; + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); + } + else + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + } + else + { + if (hhcd->Init.speed == HCD_SPEED_FULL) + { + USBx_HOST->HFIR = HFIR_60_MHZ; + } + } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } + else + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + } + + /* Clear Port Interrupts */ + USBx_HPRT0 = hprt0_dup; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #if defined (USB_DRD_FS) /** @defgroup HCD HCD @@ -222,7 +2146,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, return HAL_ERROR; } - if (((epnum & 0xFU)== 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + if (((epnum & 0xFU) == 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) { hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; @@ -1510,6 +3434,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) * @param hhcd HCD handle * @retval speed : Device speed after Host enumeration * This parameter can be one of these values: + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode * @arg HCD_DEVICE_SPEED_FULL: Full speed mode * @arg HCD_DEVICE_SPEED_LOW: Low speed mode */ @@ -1522,7 +3447,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) * @brief Set host channel Hub Information. * @param hhcd HCD handle * @param ch_num Channel number. - * This parameter can be a value from 1 to 8 + * This parameter can be a value from 1 to 15 * @param addr Hub address * @param PortNbr Hub port number * @retval HAL status @@ -1541,7 +3466,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, * @brief Clear host channel hub information. * @param hhcd HCD handle * @param ch_num Channel number. - * This parameter can be a value from 1 to 8 + * This parameter can be a value from 1 to 15 * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c index f2314a6268..5214c911ec 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c @@ -3424,6 +3424,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3481,37 +3483,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -7590,15 +7619,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2s.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2s.c index c5c92b8a53..cda2d90a22 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2s.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2s.c @@ -2004,6 +2004,107 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) return errorcode; } +/** + * @brief Enable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDO and original SDO pin becomes SDI (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature enabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Enable IO Swap feature */ + SET_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Disable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDI and original SDO pin becomes SDO (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature disabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Disable the IO Swap feature */ + CLEAR_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Retrieve the SDO/SDI alternate functions inversion feature status for the dedicated I2Sx. + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval 1 when I2S IO swap feature is enabled, 0 otherwise, or when hi2s pointer is null. + */ +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return 0; + } + + return ((READ_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + /** * @brief This function handles I2S interrupt request. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c index 13dffa2fdf..fe73e7c155 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c @@ -127,7 +127,7 @@ The I3C_XferTypeDef structure contains different parameters about Control, Status buffer, and Transmit and Receive buffer. Use HAL_I3C_AddDescToFrame() function each time application add a descriptor in the frame before call - an IO operation interface + a Controller IO operation interface One element of the frame descriptor correspond to one frame to manage through IO operation. (#) To check if I3C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() @@ -1661,8 +1661,8 @@ void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c) /* Derogation MISRAC2012-Rul All different characteristics must be fill through structure I3C_DeviceConfTypeDef. This function is called only when mode is Controller. - (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a transfer descriptor - which contained different buffer pointers and their associated size through I3C_XferTypeDef. + (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a Controller transfer + descriptor which contained different buffer pointers and their associated size through I3C_XferTypeDef. This function must be called before initiate any communication transfer. (+) Call the function HAL_I3C_Ctrl_SetConfigResetPattern() to configure the insertion of the reset pattern at the end of a Frame. @@ -2141,10 +2141,10 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef *hi3 } /** - * @brief Add Private or CCC descriptor in the user data transfer descriptor. - * @note This function must be called before initiate any communication transfer. This function help the preparation - * of the full transfer usecase in a transfer descriptor which contained different buffer pointers - * and their associated size through I3C_XferTypeDef. + * @brief Add Private or CCC descriptor in the user data transfer controller descriptor. + * @note This function must be called before initiate initiate any controller communication transfer. This function + * help the preparation of the full transfer usecase in a transfer descriptor which contained different buffer + * pointers and their associated size through I3C_XferTypeDef. * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains * multiple transmission frames. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information @@ -5495,7 +5495,6 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data * to transmit in bytes (TxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @param timeout : [IN] Timeout duration in millisecond. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ @@ -5639,7 +5638,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data * to transmit in bytes (TxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) @@ -5738,7 +5736,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeD * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data * to transmit in bytes (TxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) @@ -5899,7 +5896,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferType * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data * to be received in bytes (RxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @param timeout : [IN] Timeout duration in millisecond. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ @@ -6042,7 +6038,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef * * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data * to be received in bytes (RxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) @@ -6137,7 +6132,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDe * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data * to be received in bytes (RxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c index 67bcd95c1f..b1f98c349e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c @@ -38,6 +38,8 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -67,7 +69,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -86,13 +88,19 @@ /** @defgroup PCD_Private_Functions PCD Private Functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); #if (USE_USB_DOUBLE_BUFFER == 1U) static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -123,6 +131,9 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ @@ -134,6 +145,10 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); +#if defined (USB_OTG_FS) + USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + if (hpcd->State == HAL_PCD_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -169,15 +184,40 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if (USBx == USB_OTG_FS) + { + hpcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; hpcd->IN_ep[i].num = i; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + hpcd->IN_ep[i].tx_fifo_num = i; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; hpcd->IN_ep[i].maxpacket = 0U; @@ -197,7 +237,11 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) } /* Init Device */ - (void)USB_DevInit(hpcd->Instance, hpcd->Init); + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; @@ -208,6 +252,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) (void)HAL_PCDEx_ActivateLPM(hpcd); } + (void)USB_DevDisconnect(hpcd->Instance); + return HAL_OK; } @@ -975,7 +1021,18 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } +#endif /* defined (USB_OTG_FS) */ __HAL_PCD_ENABLE(hpcd); (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); @@ -990,15 +1047,493 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); (void)USB_DevDisconnect(hpcd->Instance); + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } +#endif /* defined (USB_OTG_FS) */ + __HAL_UNLOCK(hpcd); return HAL_OK; } +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + { + return; + } + + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + { + /* incorrect mode, acknowledge the interrupt */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + RegVal = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; + + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + /* Class B setup phase done for previous decoded setup */ + (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + } + + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + { + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + + if (hpcd->Init.dma_enable == 1U) + { + hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; + + /* this is ZLP, so prepare EP0 for next setup */ + if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) + { + /* prepare to rx more setup packets */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + } + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + } + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + } + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + { + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + + if (hpcd->LPM_State == LPM_L1) + { + hpcd->LPM_State = LPM_L0; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + } + + /* Handle Suspend Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + { + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + } + + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); + + if (hpcd->LPM_State == LPM_L0) + { + hpcd->LPM_State = LPM_L1; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Reset Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) + { + USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM; + + USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + else + { + USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM | + USB_OTG_DOEPMSK_OTEPSPRM | + USB_OTG_DOEPMSK_NAKM; + + USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + + /* setup EP0 to receive SETUP packets */ + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, + (uint8_t *)hpcd->Setup); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + } + + /* Handle SOF Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + + /* Handle Incomplete ISO IN Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; + + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + } + + /* Handle Incomplete ISO OUT Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; + + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + /* Handle Connection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else + HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + } + /* Handle Disconnection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + { + RegVal = hpcd->Instance->GOTGINT; + + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else + HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + hpcd->Instance->GOTGINT |= RegVal; + } + } +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) /** * @brief This function handles PCD interrupt request. * @param hpcd PCD handle @@ -1142,7 +1677,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) return; } } - +#endif /* defined (USB_DRD_FS) */ /** * @brief Data OUT stage callback. @@ -1342,7 +1877,20 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); + +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } +#endif /* defined (USB_OTG_FS) */ + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); @@ -1356,8 +1904,21 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); + +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } +#endif /* defined (USB_OTG_FS) */ + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1407,6 +1968,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) { @@ -1470,7 +2039,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0U; ep->num = ep_addr & EP_ADDR_MSK; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +#else (void)USB_EPStartXfer(hpcd->Instance, ep); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ return HAL_OK; } @@ -1502,13 +2080,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; +#if defined (USB_DRD_FS) ep->xfer_fill_db = 1U; ep->xfer_len_db = len; +#endif /* defined (USB_DRD_FS) */ ep->xfer_count = 0U; ep->is_in = 1U; ep->num = ep_addr & EP_ADDR_MSK; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +#else (void)USB_EPStartXfer(hpcd->Instance, ep); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ return HAL_OK; } @@ -1546,6 +2135,13 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) (void)USB_EPSetStall(hpcd->Instance, ep); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1686,6 +2282,35 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) return hpcd->State; } +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -1698,8 +2323,215 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) /** @addtogroup PCD_Private_Functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, + (uint8_t)hpcd->Init.dma_enable); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_EPTypeDef *ep; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if (hpcd->Init.dma_enable == 1U) + { + if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + } + else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + ep = &hpcd->OUT_ep[epnum]; + + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + + if (epnum == 0U) + { + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + /* ... */ + } + } + else + { + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) + { + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) /** * @brief This function handles PCD Endpoint interrupt request. * @param hpcd PCD handle @@ -2225,12 +3057,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, return HAL_OK; } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - +#endif /* defined (USB_DRD_FS) */ /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c index 8edff61212..48c89e7211 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c @@ -34,7 +34,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -59,7 +59,306 @@ @endverbatim * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set Tx FIFO + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if (fifo == 0U) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + + return HAL_OK; +} + +/** + * @brief Set Rx FIFO + * @param hpcd PCD handle + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} + +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Handle BatteryCharging Process. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t gccfg_msk; + uint32_t tickstart = HAL_GetTick(); + + /* Enable DCD : Data Contact Detect */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG |= USB_OTG_GCCFG_DCDETEN; + } +#endif /* defined (USB_OTG_HS) */ + + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + /* Check Detect flag */ + if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDETEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDETEN; + } +#endif /* defined (USB_OTG_HS) */ + HAL_Delay(50U); + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + gccfg_msk = USB_OTG_GCCFG_PDET; + } +#if defined (USB_OTG_HS) + else + { + gccfg_msk = USB_OTG_GCCFG_CHGDET; + } +#endif /* defined (USB_OTG_HS) */ + + if ((USBx->GCCFG & gccfg_msk) == 0U) + { + /* Case of Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + HAL_Delay(50U); + + gccfg_msk = USB_OTG_GCCFG_SDET; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDETEN; + HAL_Delay(50U); + + gccfg_msk = USB_OTG_GCCFG_FSVPLUS; + } +#endif /* defined (USB_OTG_HS) */ + + if ((USBx->GCCFG & gccfg_msk) == gccfg_msk) + { + /* case Dedicated Charging Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* case Charging Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Battery Charging capability discovery finished */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Activate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Power Down USB transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Enable Battery charging */ + USBx->GCCFG |= USB_OTG_GCCFG_BCDEN; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN); + } +#endif /* defined (USB_OTG_HS) */ + + hpcd->battery_charging_active = 1U; + + return HAL_OK; +} + +/** + * @brief Deactivate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Disable Battery charging */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN); + } +#endif /* defined (USB_OTG_HS) */ + + hpcd->battery_charging_active = 0U; + + return HAL_OK; +} + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) /** * @brief Configure PMA for EP * @param hpcd Device instance @@ -276,7 +575,7 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } - +#endif /* defined (USB_DRD_FS) */ /** * @brief Send LPM message to user layer callback. @@ -319,7 +618,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c index d130001620..19c742326e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c @@ -276,6 +276,7 @@ * @{ */ #define PKA_RAM_SIZE 1334U +#define PKA_RAM_ERASE_TIMEOUT 1000U /* Private macro -------------------------------------------------------------*/ #define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \ @@ -287,9 +288,6 @@ */ /* Private variables ---------------------------------------------------------*/ -static uint32_t primeordersize; -static uint32_t opsize; -static uint32_t modulussize; /* Private function prototypes -----------------------------------------------*/ /** @defgroup PKA_Private_Functions PKA Private Functions * @{ @@ -399,8 +397,22 @@ HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka) /* Set the state to busy */ hpka->State = HAL_PKA_STATE_BUSY; - /* Reset the control register and enable the PKA */ - hpka->Instance->CR = PKA_CR_EN; + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Reset the control register and enable the PKA (wait the end of PKA RAM erase) */ + while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) + { + hpka->Instance->CR = PKA_CR_EN; + + /* Check the Timeout */ + if ((HAL_GetTick() - tickstart) > PKA_RAM_ERASE_TIMEOUT) + { + /* Set timeout status */ + err = HAL_TIMEOUT; + break; + } + } /* Get current tick */ tickstart = HAL_GetTick(); @@ -502,12 +514,50 @@ __weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka) */ __weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpka); - - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, the HAL_PKA_MspDeInit can be implemented in the user file + user should take into consideration PKA RAM erase when resetting PKA */ + uint32_t tickstart = HAL_GetTick(); + + /* Enable PKA reset state */ + __HAL_RCC_PKA_FORCE_RESET(); + + /* Release PKA from reset state */ + __HAL_RCC_PKA_RELEASE_RESET(); + + /* Wait the INITOK flag Setting */ + while (hpka->Instance->CR != PKA_CR_EN) + { + hpka->Instance->CR = PKA_CR_EN; + + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PKA_RAM_ERASE_TIMEOUT) + { + /* update the state */ + hpka->State = HAL_PKA_STATE_ERROR; + } + } + + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Wait the INITOK flag Setting */ + if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, PKA_RAM_ERASE_TIMEOUT) != HAL_OK) + { + /* update the state */ + hpka->State = HAL_PKA_STATE_ERROR; + } + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* PKA Periph clock disable */ + hpka->Instance->CR = 0; + __HAL_RCC_PKA_CLK_DISABLE(); + + /* PKA Periph IRQ disable */ + HAL_NVIC_DisableIRQ(PKA_IRQn); } #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) @@ -811,7 +861,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); } @@ -826,7 +876,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); } @@ -842,7 +892,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); } @@ -857,7 +907,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); } @@ -875,7 +925,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); } @@ -890,7 +940,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } @@ -906,7 +956,7 @@ void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) uint32_t size; /* Get output result size */ - size = opsize; + size = hpka->opsize; /* Move the result to appropriate location (indicated in out parameter) */ PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); @@ -923,7 +973,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - primeordersize = in->primeOrderSize; + hpka->primeordersize = in->primeOrderSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); } @@ -938,7 +988,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - primeordersize = in->primeOrderSize; + hpka->primeordersize = in->primeOrderSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); } @@ -955,7 +1005,7 @@ void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDe uint32_t size; /* Get output result size */ - size = primeordersize; + size = hpka->primeordersize; if (out != NULL) @@ -1071,11 +1121,18 @@ void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) */ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + } + else + { + return HAL_ERROR; + } } /** @@ -1086,11 +1143,18 @@ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTy */ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + } + else + { + return HAL_ERROR; + } } /** @@ -1116,7 +1180,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - modulussize = in->modulusSize; + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1131,7 +1195,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - modulussize = in->modulusSize; + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1146,7 +1210,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDe { /* Set input parameter in PKA RAM */ PKA_ECCMulEx_Set(hpka, in); - modulussize = in->modulusSize; + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1161,7 +1225,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTyp { /* Set input parameter in PKA RAM */ PKA_ECCMulEx_Set(hpka, in); - modulussize = in->modulusSize; + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1176,7 +1240,7 @@ void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out uint32_t size; /* Get output result size */ - size = modulussize; + size = hpka->modulussize; /* If a destination buffer is provided */ if (out != NULL) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c index d714293178..aca2facf61 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c @@ -518,6 +518,13 @@ __weak void HAL_PWR_PVDCallback(void) * privileged access. * @note Privilege attribute for nsecure items can be managed by a secure * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). * @param Item : Specifies the item(s) to set attributes on. * This parameter can be a combination of @ref PWR_Items. * @param Attributes : Specifies the available attribute(s). diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c index b142aa486f..466d625fb0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c @@ -1742,6 +1742,13 @@ __weak void HAL_RCC_CSSCallback(void) * Default state is non-secure and unprivileged access allowed. * @note Secure and non-secure attributes can only be set from the secure * state when the system implements the security (TZEN=1). + * @note As the privileged attributes concern either all secure or all non-secure + * RCC resources accesses and not each RCC individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on RCC individual items + * so not to overwrite a previous more restricted access rule (consider either + * all secure and/or all non-secure RCC resources accesses by privileged-only + * transactions or privileged and unprivileged transactions). * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref RCC_items (**). * @param Attributes specifies the RCC secure/privilege attributes. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c index 6eb5ad771b..84eb931fe2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c @@ -2448,7 +2448,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe * clocks (ADC12, DAC, SDMMC1, SDMMC2, OCTOSPI1, TIM, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6, * SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, * UART9, USART10, USART11, UART12, LPUART1, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, CEC, FDCAN, SAI1, - * SAI2, USB, PLAY1), PLL2 and PLL3. + * SAI2, USB), PLL2 and PLL3. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) @@ -2758,61 +2758,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) { pPeriphClkInit->TimPresSelection = RCC_TIMPRES_ACTIVATED; } - -#if defined(PLAY1) - /* Get the PLAY1 clock source ------------------------------------------------*/ - pPeriphClkInit->PLAY1ClockSelection = __HAL_RCC_GET_PLAY1_SOURCE(); -#endif /* PLAY1 */ - -#if defined(USB_OTG_FS) - /* Get the USB_OTG_FS clock source ------------------------------------------------*/ - pPeriphClkInit->OtgfsClockSelection = __HAL_RCC_GET_OTGFS_SOURCE(); -#endif /* USB_OTG_FS */ - -#if defined(USB_OTG_HS) - /* Get the USB_OTG_HS clock source ------------------------------------------------*/ - pPeriphClkInit->OtghsClockSelection = __HAL_RCC_GET_OTGHS_SOURCE(); -#endif /* USB_OTG_HS */ - -#if defined(OCTOSPI2) - /* Get the OSPI2 clock source -----------------------------------------------*/ - pPeriphClkInit->Ospi2ClockSelection = __HAL_RCC_GET_OSPI2_SOURCE(); -#endif /* OCTOSPI2 */ - -#if defined(LTDC) - /* Get the LTDC clock source ------------------------------------------------*/ - pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); -#endif /* LTDC */ - -#if defined(ADF1) - /* Get the ADF1 clock source ------------------------------------------------*/ - pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); -#endif /* ADF1 */ - -#if defined(MDF1) - /* Get the MDF1 clock source ------------------------------------------------*/ - pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE(); -#endif /* MDF1 */ - -#if defined(RCC_CCIPR4_ETHCLKSEL) - /* Get the ETH clock source ------------------------------------------------*/ - pPeriphClkInit->EthClockSelection = __HAL_RCC_GET_ETH_SOURCE(); -#endif /* RCC_CCIPR4_ETHCLKSEL */ - -#if defined(RCC_CCIPR5_ETHPTPCLKSEL) - /* Get the ETHPTP clock source ------------------------------------------------*/ - pPeriphClkInit->EthptpClockSelection = __HAL_RCC_GET_ETHPTP_SOURCE(); -#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ - -#if defined(RCC_CCIPR5_ETHT1SCLKSEL) - /* Get the ETHT1S clock source ------------------------------------------------*/ - pPeriphClkInit->Etht1sClockSelection = __HAL_RCC_GET_ETHT1S_SOURCE(); -#endif /* RCC_CCIPR5_ETHT1SCLKSEL */ - -#if defined(RCC_CCIPR5_ETHREFCLKSEL) - /* Get the ETHREF clock source ------------------------------------------------*/ - pPeriphClkInit->EthrefClockSelection = __HAL_RCC_GET_ETHREF_SOURCE(); -#endif /* RCC_CCIPR5_ETHREFCLKSEL */ } /** @@ -2847,7 +2792,7 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks) pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N); pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); - pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN; + pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ RCC_PLL1FRACR_PLL1FRACN_Pos)); @@ -2983,7 +2928,7 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks) pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N); pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos); - pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN; + pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ RCC_PLL2FRACR_PLL2FRACN_Pos)); @@ -3117,7 +3062,7 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks) pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N); pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC); pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos); - pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN; + pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos); fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ RCC_PLL3FRACR_PLL3FRACN_Pos)); @@ -5308,33 +5253,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) frequency = 0U; break; #endif /* USB_DRD_FS */ - -#if defined(RCC_CCIPR4_ETHCLKSEL) - case RCC_PERIPHCLK_ETH: - - /* Get the current ETH kernel source */ - srcclk = __HAL_RCC_GET_ETH_SOURCE(); - switch (srcclk) - { - case RCC_ETHCLKSOURCE_PLL1Q: - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - } - case RCC_ETHCLKSOURCE_HSE: - { - frequency = HSE_VALUE; - break; - } - default: - { - frequency = 0U; - break; - } - } - break; -#endif /* RCC_CCIPR4_ETHCLKSEL */ } } return (frequency); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c index caecaa7c5c..cb6ca88a7d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c @@ -197,19 +197,20 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); - /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ - MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); #if defined(RNG_CR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ - WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE); -#endif /* defined(RNG_CR_NIST_VALUE) */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else + /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#endif /* RNG_CR_NIST_VALUE */ #if defined(RNG_HTCR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); -#endif /* defined(RNG_HTCR_NIST_VALUE) */ +#endif /* RNG_HTCR_NIST_VALUE */ #if defined(RNG_NSCR_NIST_VALUE) WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); -#endif /* defined(RNG_NSCR_NIST_VALUE) */ +#endif /* RNG_NSCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -652,6 +653,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c index 96bd9d982b..693747bdeb 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c @@ -306,6 +306,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c index 348ead9a4b..10dc59269f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c @@ -3099,6 +3099,38 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_ */ #endif /* TAMP_PRIVCFGR_TAMPPRIV */ +#if defined (RTC_OR_OUT2_RMP) +/** + * @brief Enable RTC OUT2 remap feature. + * @note When enable RTC_OUT2 is mapped on PB2. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_EnableRemapRtcOut2(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Enable RTC OUT2 remap */ + SET_BIT(RTC->OR, RTC_OR_OUT2_RMP); +} + +/** + * @brief Disable RTC OUT2 remap feature. + * @note When disable RTC_OUT2 is mapped on PI8. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_DisableRemapRtcOut2(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Disable RTC OUT2 remap */ + CLEAR_BIT(RTC->OR, RTC_OR_OUT2_RMP); +} +#endif /* defined (RTC_OR_OUT2_RMP) */ + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c index 13efd25711..62a740c020 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c @@ -828,6 +828,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, co /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -935,6 +943,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; @@ -1001,6 +1017,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->TxXferCount = Size; hsmartcard->TxISR = NULL; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -1094,6 +1118,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Configure Rx interrupt processing */ if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) { @@ -1395,8 +1427,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1420,8 +1454,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1492,8 +1528,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1558,8 +1596,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1657,9 +1697,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable DMA Tx at UART level */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1681,8 +1723,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1771,8 +1815,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1869,8 +1915,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -2052,8 +2100,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel */ if (hsmartcard->hdmarx != NULL) { @@ -2106,8 +2156,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel */ if (hsmartcard->hdmatx != NULL) { @@ -2759,10 +2811,12 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); hsmartcard->TxXferCount = 0U; +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } @@ -2782,10 +2836,12 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c index 02a4f07768..69990384a5 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c @@ -242,6 +242,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { uint32_t crc_length; uint32_t packet_length; +#if (USE_SPI_CRC != 0UL) + uint32_t crc_poly_msb_mask; +#endif /* USE_SPI_CRC */ /* Check the SPI handle allocation */ if (hspi == NULL) @@ -329,6 +332,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) crc_length = hspi->Init.CRCLength; } + /* Verify the correctness of polynom size */ + assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length)); + /* Verify that the CRC Length is higher than DataSize */ if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) { @@ -446,15 +452,21 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) { + /* Set SPI_CR1_CRC33_17 bit */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); } else { + /* Clear SPI_CR1_CRC33_17 bit */ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); - } - /* Write CRC polynomial in SPI Register */ - WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + /* Write CRC polynomial and set MSB bit at 1 in SPI Register */ + /* Set MSB is mandatory for a correct CRC computation */ + crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U)); + WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask); + } } #endif /* USE_SPI_CRC */ @@ -836,6 +848,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1052,6 +1074,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t temp_sr_reg; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ @@ -1059,6 +1084,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1117,8 +1152,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/EOT flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) { *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); hspi->pRxBuffPtr += sizeof(uint32_t); @@ -1149,6 +1194,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1156,6 +1204,34 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; @@ -1185,6 +1261,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1192,6 +1271,26 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr += sizeof(uint8_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } else { /* Timeout management */ @@ -1262,12 +1361,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t uint32_t tickstart; uint32_t fifo_length; + uint32_t temp_sr_reg; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1343,28 +1455,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check RXWNE/EOT flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL)) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount --; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1390,32 +1518,70 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } - - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1434,28 +1600,58 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1497,6 +1693,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if ((pData == NULL) || (Size == 0UL)) { return HAL_ERROR; @@ -1581,6 +1787,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1676,6 +1892,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1793,6 +2019,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1979,6 +2215,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } if (hspi->State != HAL_SPI_STATE_READY) { @@ -2169,6 +2414,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -2203,9 +2458,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) || \ + (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD)) && \ (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE) || \ + (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)))) { /* Restriction the DMA data received is not allowed in this mode */ /* Unlock the process */ @@ -2618,6 +2877,15 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized before any call to DMA Abort functions */ + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + } + if (hspi->hdmatx != NULL) { if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi_ex.c index 6df6b9b5e9..b5ae786b94 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi_ex.c @@ -57,7 +57,6 @@ data transfers. (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_ConfigureUnderrun() @@ -208,6 +207,100 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t __HAL_UNLOCK(hspi); return errorcode; } +#if defined(SPI_CFG1_DRDS) + +/** + * @brief Enable the Delay Read Data Sampling on Master Input IO + * DRDS setting has no impact on the other SCK management. + * When CRC is enabled, CRC computation and evaluation is delayed too. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_EnableDelayReadDataSampling(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check if the SPI is disabled to edit DRDS bit */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Disable the Delay Read Data Sampling on Master Input IO + * DRDS setting has no impact on the other SCK management. + * When CRC is enabled, CRC computation and evaluation is delayed too. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_DisableDelayReadDataSampling(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check if the SPI is disabled to edit DRDS bit */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} +#endif /* SPI_CFG1_DRDS */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c index 241bd8f83b..c0f6fb8dc2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c @@ -1452,6 +1452,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ if (huart->hdmatx != NULL) { /* Set the UART DMA transfer complete callback */ @@ -1514,9 +1519,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } } +#if !defined(USART_DMAREQUESTS_SW_WA) /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3968,7 +3975,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c index c2015166ee..466490ba4b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c @@ -865,9 +865,10 @@ HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTyp if (pCmd->DataMode == HAL_XSPI_DATA_NONE) { /* When there is no data phase, the transfer start as soon as the configuration is done - so wait until TC flag is set to go back in idle state */ - status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + so wait until BUSY flag is reset to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + /* Clear TC flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); } else @@ -2394,12 +2395,10 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSP HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; uint32_t tickstart = HAL_GetTick(); - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Check if the DMA is enabled */ if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) @@ -2472,11 +2471,9 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Disable all interrupts */ HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); @@ -3050,6 +3047,14 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the CCR register with DQS and SIOO modes */ *ccr_reg = (pCmd->DQSMode | pCmd->SIOOMode); + /* Workaround for Erratasheet: Memory-mapped write error response when DQS output is disabled */ + if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + /* When doing memory-mapped writes, set the DQSE bit of the OCTOSPI_WCCR register, + even for memories that have no DQS pin. */ + SET_BIT((*ccr_reg), XSPI_CCR_DQSE); + } + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) { /* Configure the ABR register with alternate bytes value */ @@ -3072,6 +3077,25 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC } } + /* Configure SSHIFT register to handle SDR/DTR data transfer */ + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) + { + /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */ + CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) + { + /* Configure sample shifting */ + SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else + { + /* Do nothing */ + } + } + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) { if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dac.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dac.c index 4583232d48..df2c52616d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dac.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dac.c @@ -54,22 +54,22 @@ /* Devices STM32H563/H573xx */ #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_CH1) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ ) #else /* Devices STM32H503xx */ #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ + ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c index 054beb89d7..d2d784ac70 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c @@ -847,8 +847,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); } - /* Check node type */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE) + /* Check non 2D addressing settings */ { assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength)); assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength)); @@ -1087,7 +1086,11 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2)); } } - + else + { + /* Reset of the CLLR of the node being created */ + pNode->LinkRegisters[reg_counter] = 0U; + } return (uint32_t)SUCCESS; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c index 58c008e9f5..5029fdbcf2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c @@ -81,20 +81,17 @@ ErrorStatus LL_EXTI_DeInit(void) { /* Interrupt mask register set to default reset values */ LL_EXTI_WriteReg(IMR1, 0xFFFE0000U); -#if defined(STM32H533xx) || defined(STM32H523xx) +#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) + LL_EXTI_WriteReg(IMR2, 0x03DBBFFFU); +#elif defined(STM32H533xx) LL_EXTI_WriteReg(IMR2, 0x07DBFFFFU); -#elif defined(STM32H503xx) - LL_EXTI_WriteReg(IMR2, 0x001BFFFFU); #else - LL_EXTI_WriteReg(IMR2, 0x03DBBFFFU); -#endif /* defined(STM32H533xx) || defined(STM32H523xx) */ + LL_EXTI_WriteReg(IMR2, 0x001BFFFFU); +#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ /* Event mask register set to default reset values */ LL_EXTI_WriteReg(EMR1, 0x00000000U); LL_EXTI_WriteReg(EMR2, 0x00000000U); -#if defined(EXTI_EMR3_EM) - LL_EXTI_WriteReg(EMR3, 0x00000000U); -#endif /* EXTI_EMR3_EM */ /* Rising Trigger selection register set to default reset values */ LL_EXTI_WriteReg(RTSR1, 0x00000000U); @@ -262,7 +259,6 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) /* De-configure EXTI Lines in range from 32 to 63 */ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); - } return status; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c index efa633a2b3..340ed846b4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c @@ -31,7 +31,7 @@ */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) /** @addtogroup GPIO_LL * @{ @@ -166,20 +166,6 @@ ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI); } #endif /* GPIOI */ -#if defined(GPIOJ) - else if (GPIOx == GPIOJ) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOJ); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOJ); - } -#endif /* GPIOJ */ -#if defined(GPIOK) - else if (GPIOx == GPIOK) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOK); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOK); - } -#endif /* GPIOK */ else { status = ERROR; @@ -293,8 +279,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || \ - defined (GPIOK) ||*/ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_i3c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_i3c.c index cabc24279f..634a567576 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_i3c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_i3c.c @@ -18,8 +18,8 @@ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ -#include "stm32h5xx_ll_i3c.h" #include "stm32h5xx_ll_bus.h" +#include "stm32h5xx_ll_i3c.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c index 59aadb8861..3930068f2a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c @@ -2098,6 +2098,7 @@ uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource) } break; + case LL_RCC_I3C2_CLKSOURCE_NONE: /* No Clock used for I3C2 */ break; @@ -2884,7 +2885,18 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) } } break; -#endif /* LL_RCC_USB_CLKSOURCE_PLL3 */ +#else + case LL_RCC_USB_CLKSOURCE_PLL2Q: /* PLL2 Q clock used as USB clock source */ + if (LL_RCC_PLL2_IsReady() != 0U) + { + if (LL_RCC_PLL2Q_IsEnabled() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + usb_frequency = PLL_Clocks.PLL_Q_Frequency; + } + } + break; +#endif /* LL_RCC_USB_CLKSOURCE_PLL3Q */ case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ if (LL_RCC_HSI48_IsReady() == 1U) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_spi.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_spi.c index d0b0e04d14..12233eb705 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_spi.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_spi.c @@ -566,7 +566,7 @@ ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) * - SUCCESS: SPI registers are Initialized * - ERROR: SPI registers are not Initialized */ -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct) { uint32_t i2sdiv = 0UL; uint32_t i2sodd = 0UL; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c index bcff169016..7904b05e68 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c @@ -46,14 +46,2272 @@ */ #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; +#if defined (STM32H5F5xx) || defined (STM32H5E5xx) + if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + /* Init The UTMI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS); + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.dma_enable == 1U) + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + +#else + + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.battery_charging_enable == 0U) + { + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + else + { + /* Deactivate the USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } +#endif /* defined (STM32H5F5xx) || defined (STM32H5E5xx) */ + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else if (speed == USBD_HS_SPEED) + { + UsbTrd = USBD_HS_TRDT_VALUE; + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + uint32_t ms = 0U; + + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else if (mode == USB_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else + { + return HAL_ERROR; + } + + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + /* Disable USB PHY pulldown resistors */ + USBx->GCCFG &= ~USB_OTG_GCCFG_PULLDOWNEN; + } + + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + /* Deactivate VBUS Sensing B */ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; + USBx->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; + } +#endif /* defined (USB_OTG_HS) */ + } + else + { + /* B-peripheral session valid override disable */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALEXTOEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL; + } +#endif /* defined (USB_OTG_HS) */ + + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + +#if defined (STM32H5F5xx) || defined (STM32H5E5xx) + if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else +#endif /* defined (STM32H5F5xx) || defined (STM32H5E5xx) */ + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + } + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + + if (cfg.Sof_enable != 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + } + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_FlushTxFifo Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX Fifo */ + count = 0U; + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg USBD_HS_SPEED: High speed mode + * @arg USBD_FS_SPEED: Full speed mode + */ +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (pktcnt << 29)); + } + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + pSrc++; + pSrc++; + pSrc++; + } + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pDest = dest; + uint32_t pData; + uint32_t i; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval USB Device OUT EP interrupt status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval USB Device IN EP interrupt status + */ +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; + + msk = USBx_DEVICE->DIEPMSK; + emp = USBx_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS &= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRSTDONE) == 0U); + + /* Clear Core Soft Reset */ + USBx->GRSTCTL &= ~USB_OTG_GRSTCTL_CSRST; + + return HAL_OK; +} + +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + /* Enable USB PHY pulldown resistors */ + USBx->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN; + } + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { +#if defined (USB_OTG_HS) + /* Disable VBUS override */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBVALOVAL | USB_OTG_GCCFG_VBVALEXTOEN); +#endif /* defined (USB_OTG_HS) */ + } + + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + } +#if defined (USB_OTG_HS) + else + { + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + } +#endif /* defined (USB_OTG_HS) */ + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + + /* Make sure the FIFOs are flushed. */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + } + else +#endif /* defined (USB_OTG_HS) */ + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return ret; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = HFIR_48_MHZ; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = HFIR_6_MHZ; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate VBUS + * 1 : Activate VBUS + * @retval HAL status + */ +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_HIGH: High speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; + uint32_t HostCoreSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + else + { +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM; + } +#endif /* defined (USB_OTG_HS) */ + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; + + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + __IO uint32_t tmpreg; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; + +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if (dma == 1U) + { + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) + { + + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + } + else + { + if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } + } + } +#endif /* defined (USB_OTG_HS) */ + + if (hc->do_ssplit == 1U) + { + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; + + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; + + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } + } + else + { + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; + + /* unmask ack & nyet for IN/OUT transactions */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NYET); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch (hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if (dma != 0U) /* dma mode */ + { + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + __IO uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; + + /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. + At the end of the next uframe/frame (in the worst case), the core generates a channel halted + and disables the channel automatically. */ + + if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) + { + return HAL_OK; + } + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) + { + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; + + (void)USB_EnableGlobalInt(USBx); + + return ret; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx); #if (USE_USB_DOUBLE_BUFFER == 1U) static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, @@ -1469,7 +3727,7 @@ HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx) return HAL_OK; } - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -1477,7 +3735,7 @@ HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx) /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_util_i3c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_util_i3c.c index 19d16d2dfc..fcd6c007f9 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_util_i3c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_util_i3c.c @@ -27,6 +27,8 @@ * @{ */ +#if (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) + /* Private typedef ---------------------------------------------------------------------------------------------------*/ /* Private define ----------------------------------------------------------------------------------------------------*/ /** @defgroup I3C_UTIL_Private_Define I3C Utility Private Define @@ -412,6 +414,8 @@ ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming, */ /* Private functions ---------------------------------------------------------*/ + +#endif /* (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) */ /** * @} */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 3b963a2342..21e70f326f 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.3.1 * STM32G0: 1.4.6 * STM32G4: 1.2.5 - * STM32H5: 1.3.0 + * STM32H5: 1.4.0 * STM32H7: 1.11.3 * STM32L0: 1.10.6 * STM32L1: 1.4.5 From 68462f538ff5a84a0a7b36c807b6438071ad4b3b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Dec 2024 14:19:20 +0100 Subject: [PATCH 005/141] system(H5): update STM32H5xx CMSIS Drivers to v1.3.1 Included in STM32CubeH5 FW v1.4.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32H5xx/Include/stm32h503xx.h | 4 ++-- .../Device/ST/STM32H5xx/Include/stm32h523xx.h | 2 +- .../Device/ST/STM32H5xx/Include/stm32h533xx.h | 2 +- .../Device/ST/STM32H5xx/Include/stm32h562xx.h | 2 +- .../Device/ST/STM32H5xx/Include/stm32h563xx.h | 2 +- .../Device/ST/STM32H5xx/Include/stm32h573xx.h | 2 +- .../Device/ST/STM32H5xx/Include/stm32h5xx.h | 12 ++++++------ .../Device/ST/STM32H5xx/Release_Notes.html | 19 +++++++++++++++---- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 9 files changed, 29 insertions(+), 18 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h index bc59cb054b..3399c9f16e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h @@ -186,7 +186,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ @@ -13300,7 +13300,7 @@ typedef struct /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS)) -#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == NULL) +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == ((SPI_TypeDef *) 0xDEADDEADUL)) #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h index 0d5f8cdda1..1ec059f200 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h @@ -215,7 +215,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h index 4bcb43a9d6..bad6174bb6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h @@ -218,7 +218,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h index ecd0ae8fb5..333ff277e5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h @@ -234,7 +234,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h index b4631f9fbe..45beaa1976 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h @@ -239,7 +239,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h index fcb7e97fe3..a2d20dd2ff 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h @@ -242,7 +242,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h index 947ccec927..e60a558bbb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h @@ -57,7 +57,7 @@ application */ -#if !defined (STM32H573xx) && !defined (STM32H563xx) \ +#if !defined (STM32H573xx) && !defined (STM32H563xx) \ && !defined (STM32H562xx) && !defined (STM32H503xx) \ && !defined (STM32H533xx) && !defined (STM32H523xx) /* #define STM32H573xx */ /*!< STM32H573xx Devices */ @@ -81,12 +81,12 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.3.0 + * @brief CMSIS Device version number 1.3.1 */ -#define __STM32H5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32H5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32H5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32H5_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32H5_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\ |(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html index 8bfe3012e8..7e68b547b7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html @@ -30,11 +30,22 @@

Release Notes for  STM32H5xx C

Update History

- +

Main Changes

CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0481 (STM32H5 reference manual)

    +
  • Update to use #include "core_cm33.h" instead of #include <core_cm33.h> to force the first searches for the core_cm33.h file in the same directory as the file that contains the #include directive (Drivers\CMSIS\Core\Include)
    • +
  • Update IS_SPI_LIMITED macro to return an essential boolean
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0481 (STM32H5 reference manual)

+
  • Add RNG_CR_NIST_VALUE, RNG_NSCR_NIST_VALUE and RNG_HTCR_NIST_VALUE defines
  • Add Bits definition for RNG_NSCR register : Add RNG_NSCR_EN_OSC1, RNG_NSCR_EN_OSC2, RNG_NSCR_EN_OSC3, RNG_NSCR_EN_OSC4, RNG_NSCR_EN_OSC5 and RNG_NSCR_EN_OSC6 defines
  • Add USART_DMAREQUESTS_SW_WA define
    • @@ -50,7 +61,7 @@

    Main Changes

    -

    Main Changes

    +

    Main Changes

    • First official release of STM32H5xx CMSIS drivers to support STM32H533xx and STM32H523xx devices
    • Add bit definition for I3C_BCR register
      • @@ -69,7 +80,7 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Add DUA addresses constants definitions for STM32H573xx devices only
      • Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE & IS_TIM_TISEL_INSTANCE macros
        • @@ -80,7 +91,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)
        diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 4cc65c8401..8759dce9cd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.2.9 * STM32G0: 1.4.4 * STM32G4: 1.2.5 - * STM32H5: 1.3.0 + * STM32H5: 1.3.1 * STM32H7: 1.10.4 * STM32L0: 1.9.3 * STM32L1: 2.3.3 From 25a475773804940d58b1ada3120df168ebe1122e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 10:58:39 +0100 Subject: [PATCH 006/141] system(C0) update STM32C0xx HAL Drivers to v1.3.0 Included in STM32CubeC0 FW v1.3.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 61 +- .../STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h | 123 +- .../Inc/stm32c0xx_hal_adc.h | 14 +- .../Inc/stm32c0xx_hal_adc_ex.h | 2 +- .../Inc/stm32c0xx_hal_conf_template.h | 28 +- .../Inc/stm32c0xx_hal_cortex.h | 26 +- .../Inc/stm32c0xx_hal_dma.h | 93 +- .../Inc/stm32c0xx_hal_dma_ex.h | 8 +- .../Inc/stm32c0xx_hal_fdcan.h | 1442 +++++++ .../Inc/stm32c0xx_hal_flash.h | 4 +- .../Inc/stm32c0xx_hal_gpio_ex.h | 63 +- .../Inc/stm32c0xx_hal_pcd.h | 8 + .../Inc/stm32c0xx_hal_rcc.h | 154 +- .../Inc/stm32c0xx_hal_rcc_ex.h | 59 +- .../Inc/stm32c0xx_hal_rtc_ex.h | 6 +- .../Inc/stm32c0xx_hal_spi.h | 6 + .../Inc/stm32c0xx_hal_tim_ex.h | 10 + .../Inc/stm32c0xx_hal_uart_ex.h | 43 + .../Inc/stm32c0xx_ll_adc.h | 126 +- .../Inc/stm32c0xx_ll_bus.h | 90 +- .../Inc/stm32c0xx_ll_crs.h | 48 +- .../Inc/stm32c0xx_ll_dma.h | 516 ++- .../Inc/stm32c0xx_ll_dmamux.h | 67 +- .../Inc/stm32c0xx_ll_rcc.h | 55 + .../Inc/stm32c0xx_ll_spi.h | 8 +- .../Inc/stm32c0xx_ll_system.h | 176 + .../Inc/stm32c0xx_ll_tim.h | 67 +- .../Inc/stm32c0xx_ll_usart.h | 4 +- .../Inc/stm32c0xx_ll_utils.h | 14 + .../STM32C0xx_HAL_Driver/Release_Notes.html | 109 +- .../STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c | 2 +- .../Src/stm32c0xx_hal_adc.c | 10 +- .../Src/stm32c0xx_hal_adc_ex.c | 2 +- .../Src/stm32c0xx_hal_cortex.c | 2 +- .../Src/stm32c0xx_hal_dma.c | 4 +- .../Src/stm32c0xx_hal_fdcan.c | 3526 +++++++++++++++++ .../Src/stm32c0xx_hal_flash_ex.c | 4 +- .../Src/stm32c0xx_hal_i2c.c | 79 +- .../Src/stm32c0xx_hal_pcd.c | 35 +- .../Src/stm32c0xx_hal_rcc.c | 2 + .../Src/stm32c0xx_hal_rcc_ex.c | 47 + .../Src/stm32c0xx_hal_smbus.c | 4 +- .../Src/stm32c0xx_hal_spi.c | 53 + .../Src/stm32c0xx_hal_tim_ex.c | 13 +- .../Src/stm32c0xx_hal_uart.c | 1 - .../Src/stm32c0xx_ll_adc.c | 6 +- .../Src/stm32c0xx_ll_crs.c | 29 +- .../Src/stm32c0xx_ll_dma.c | 29 +- .../Src/stm32c0xx_ll_rcc.c | 47 + .../Src/stm32c0xx_ll_tim.c | 11 +- .../Src/stm32c0xx_ll_usart.c | 40 +- .../Src/stm32c0xx_ll_usb.c | 73 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 53 files changed, 7058 insertions(+), 393 deletions(-) create mode 100644 system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_fdcan.h create mode 100644 system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_fdcan.c diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 43e6777750..286664e7a0 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -875,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -1012,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1264,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1279,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -2014,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -3680,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3931,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4225,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h index 5959f02cfb..69361ca4f6 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h @@ -110,6 +110,40 @@ typedef enum #define HAL_BIND_WLCSP19_PINB3_PB8 LL_PINMUX_WLCSP19_PINB3_PB8 /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB8 */ #define HAL_BIND_TSSOP20_PIN1_PB7 LL_PINMUX_TSSOP20_PIN1_PB7 /*!< STM32C071 TSSOP20 package, Pin1 assigned to GPIO PB7 */ #define HAL_BIND_TSSOP20_PIN1_PB8 LL_PINMUX_TSSOP20_PIN1_PB8 /*!< STM32C071 TSSOP20 package, Pin1 assigned to GPIO PB8 */ +#elif (DEV_ID == 0x44CUL) +#define HAL_BIND_WLCSP15_PINH3_PF2 LL_PINMUX_WLCSP15_PINH3_PF2 /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PF2 */ +#define HAL_BIND_WLCSP15_PINH3_PA0 LL_PINMUX_WLCSP15_PINH3_PA0 /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PA0 */ +#define HAL_BIND_WLCSP15_PING2_PA1 LL_PINMUX_WLCSP15_PING2_PA1 /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA1 */ +#define HAL_BIND_WLCSP15_PING2_PA2 LL_PINMUX_WLCSP15_PING2_PA2 /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA2 */ +#define HAL_BIND_WLCSP15_PINK3_PA3 LL_PINMUX_WLCSP15_PINK3_PA3 /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA3 */ +#define HAL_BIND_WLCSP15_PINK3_PA4 LL_PINMUX_WLCSP15_PINK3_PA4 /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA4 */ +#define HAL_BIND_WLCSP15_PINJ2_PA5 LL_PINMUX_WLCSP15_PINJ2_PA5 /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA5 */ +#define HAL_BIND_WLCSP15_PINJ2_PA6 LL_PINMUX_WLCSP15_PINJ2_PA6 /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA6 */ +#define HAL_BIND_WLCSP15_PINH1_PA7 LL_PINMUX_WLCSP15_PINH1_PA7 /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA7 */ +#define HAL_BIND_WLCSP15_PINH1_PA12 LL_PINMUX_WLCSP15_PINH1_PA12 /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA12 */ +#define HAL_BIND_WLCSP15_PINE2_PA14 LL_PINMUX_WLCSP15_PINE2_PA14 /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA14 */ +#define HAL_BIND_WLCSP15_PINE2_PA15 LL_PINMUX_WLCSP15_PINE2_PA15 /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA15 */ +#define HAL_BIND_WLCSP15_PINB1_PA3 LL_PINMUX_WLCSP15_PINB1_PA3 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA3 */ +#define HAL_BIND_WLCSP15_PINB1_PA4 LL_PINMUX_WLCSP15_PINB1_PA4 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA4 */ +#define HAL_BIND_WLCSP15_PINB1_PA5 LL_PINMUX_WLCSP15_PINB1_PA5 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA5 */ +#define HAL_BIND_WLCSP15_PINB1_PA6 LL_PINMUX_WLCSP15_PINB1_PA6 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA6 */ +#define HAL_BIND_WLCSP15_PINA2_PB7 LL_PINMUX_WLCSP15_PINA2_PB7 /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB7 */ +#define HAL_BIND_WLCSP15_PINA2_PB8 LL_PINMUX_WLCSP15_PINA2_PB8 /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB8 */ +#elif (DEV_ID == 0x44DUL) +#define HAL_BIND_TSSOP20_PIN19_PA14 LL_PINMUX_TSSOP20_PIN19_PA14 /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA14 */ +#define HAL_BIND_TSSOP20_PIN19_PA15 LL_PINMUX_TSSOP20_PIN19_PA15 /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA15 */ +#define HAL_BIND_TSSOP20_PIN15_PA8 LL_PINMUX_TSSOP20_PIN15_PA8 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PA8 */ +#define HAL_BIND_TSSOP20_PIN15_PB0 LL_PINMUX_TSSOP20_PIN15_PB0 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB0 */ +#define HAL_BIND_TSSOP20_PIN15_PB1 LL_PINMUX_TSSOP20_PIN15_PB1 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB1 */ +#define HAL_BIND_TSSOP20_PIN15_PB2 LL_PINMUX_TSSOP20_PIN15_PB2 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB2 */ +#define HAL_BIND_TSSOP20_PIN20_PB6 LL_PINMUX_TSSOP20_PIN20_PB6 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB6 */ +#define HAL_BIND_TSSOP20_PIN20_PB3 LL_PINMUX_TSSOP20_PIN20_PB3 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB3 */ +#define HAL_BIND_TSSOP20_PIN20_PB4 LL_PINMUX_TSSOP20_PIN20_PB4 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB4 */ +#define HAL_BIND_TSSOP20_PIN20_PB5 LL_PINMUX_TSSOP20_PIN20_PB5 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB5 */ +#define HAL_BIND_WLCSP24_PINA3_PB5 LL_PINMUX_WLCSP24_PINA3_PB5 /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB5 */ +#define HAL_BIND_WLCSP24_PINA3_PB3 LL_PINMUX_WLCSP24_PINA3_PB3 /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB3 */ +#define HAL_BIND_WLCSP24_PINB4_PB7 LL_PINMUX_WLCSP24_PINB4_PB7 /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB7 */ +#define HAL_BIND_WLCSP24_PINB4_PB8 LL_PINMUX_WLCSP24_PINB4_PB8 /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB8 */ #endif /* DEV_ID == 0x443UL */ /** @@ -140,6 +174,21 @@ typedef enum #define HAL_BIND_TSSOP20_PIN20 LL_PINMUX_TSSOP20_PIN20 /*!< STM32C071 TSSOP20 package, GPIO Pin20 multiplexer */ #define HAL_BIND_WLCSP19_PINB3 LL_PINMUX_WLCSP19_PINB3 /*!< STM32C071 WLCSP19 package, GPIO PinB3 multiplexer */ #define HAL_BIND_TSSOP20_PIN1 LL_PINMUX_TSSOP20_PIN1 /*!< STM32C071 TSSOP20 package, GPIO Pin1 multiplexer */ +#elif (DEV_ID == 0x44CUL) +#define HAL_BIND_WLCSP15_PINH3 LL_PINMUX_WLCSP15_PINH3 /*!< STM32C051 WLCSP15 package, GPIO PinH3 multiplexer */ +#define HAL_BIND_WLCSP15_PING2 LL_PINMUX_WLCSP15_PING2 /*!< STM32C051 WLCSP15 package, GPIO PinG2 multiplexer */ +#define HAL_BIND_WLCSP15_PINK3 LL_PINMUX_WLCSP15_PINK3 /*!< STM32C051 WLCSP15 package, GPIO PinK3 multiplexer */ +#define HAL_BIND_WLCSP15_PINJ2 LL_PINMUX_WLCSP15_PINJ2 /*!< STM32C051 WLCSP15 package, GPIO PinJ2 multiplexer */ +#define HAL_BIND_WLCSP15_PINH1 LL_PINMUX_WLCSP15_PINH1 /*!< STM32C051 WLCSP15 package, GPIO PinH1 multiplexer */ +#define HAL_BIND_WLCSP15_PINE2 LL_PINMUX_WLCSP15_PINE2 /*!< STM32C051 WLCSP15 package, GPIO PinE2 multiplexer */ +#define HAL_BIND_WLCSP15_PINB1 LL_PINMUX_WLCSP15_PINB1 /*!< STM32C051 WLCSP15 package, GPIO PinB1 multiplexer */ +#define HAL_BIND_WLCSP15_PINA2 LL_PINMUX_WLCSP15_PINA2 /*!< STM32C051 WLCSP15 package, GPIO PinA2 multiplexer */ +#elif (DEV_ID == 0x44DUL) +#define HAL_BIND_TSSOP20_PIN19 LL_PINMUX_TSSOP20_PIN19 /*!< STM32C051 WLCSP15 package, GPIO PinH3 multiplexer */ +#define HAL_BIND_TSSOP20_PIN15 LL_PINMUX_TSSOP20_PIN15 /*!< STM32C051 WLCSP15 package, GPIO PinG2 multiplexer */ +#define HAL_BIND_TSSOP20_PIN20 LL_PINMUX_TSSOP20_PIN20 /*!< STM32C051 WLCSP15 package, GPIO PinK3 multiplexer */ +#define HAL_BIND_WLCSP24_PINA3 LL_PINMUX_WLCSP24_PINA3 /*!< STM32C051 WLCSP15 package, GPIO PinJ2 multiplexer */ +#define HAL_BIND_WLCSP24_PINB4 LL_PINMUX_WLCSP24_PINB4 /*!< STM32C051 WLCSP15 package, GPIO PinH1 multiplexer */ #endif /* DEV_ID == 0x443UL */ /** * @} @@ -243,7 +292,7 @@ typedef enum #define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */ #define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */ #define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */ -#if defined(USB) +#if defined(USB_DRD_FS) #define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */ #endif /* USB */ #define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */ @@ -257,6 +306,9 @@ typedef enum #endif /* TIM2 */ #define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */ #define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */ +#if defined(TIM15) +#define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */ +#endif /* TIM15 */ #define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */ #define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */ #define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */ @@ -269,6 +321,13 @@ typedef enum #endif /* SPI2 */ #define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */ #define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */ +#if defined(USART3) +#define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */ +#endif /* USART3 */ +#if defined(FDCAN1) +#define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */ +#endif /* FDCAN1 */ #define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_WWDG) /*!< WWDG Interrupt */ #define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC Interrupt */ @@ -293,7 +352,7 @@ typedef enum #define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */ #define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */ #define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */ -#if defined(USB) +#if defined(USB_DRD_FS) #define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */ #endif /* USB */ #define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */ @@ -306,6 +365,12 @@ typedef enum #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) #define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */ #endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +#define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */ +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +#define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */ +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ #define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */ #define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */ #define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */ @@ -317,6 +382,9 @@ typedef enum #endif /* TIM2 */ #define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */ #define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */ +#if defined(TIM15) +#define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB) /*!< TIM15 Interrupt */ +#endif /* TIM15 */ #define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */ #define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */ #define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt */ @@ -329,6 +397,16 @@ typedef enum #endif /* SPI2 */ #define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt */ #define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt */ +#if defined(USART3) +#define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 GLB Interrupt */ +#endif /* USART3 */ +#if defined(USART4) +#define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB) /*!< USART4 GLB Interrupt */ +#endif /* USART4 */ +#if defined(FDCAN1) +#define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_FDCAN1_IT0_GLB) /*!< FDCAN1_IT0 GLB Interrupt */ +#define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_FDCAN1_IT1_GLB) /*!< FDCAN1_IT1 GLB Interrupt */ +#endif /* FDCAN1 */ /** * @} @@ -390,6 +468,11 @@ typedef enum #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) #endif /* DBG_APB_FZ2_DBG_TIM14_STOP */ +#if defined(DBG_APB_FZ2_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */ + #if defined(DBG_APB_FZ2_DBG_TIM16_STOP) #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) @@ -563,7 +646,41 @@ typedef enum ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB5) || \ ((PIN) == LL_PINMUX_WLCSP19_PINB3_PB7) || \ ((PIN) == LL_PINMUX_WLCSP19_PINB3_PB8)) -#endif /* DEV_ID == 0x443UL | DEV_ID == 0x453UL | DEV_ID == 0x493UL */ +#elif (DEV_ID == 0x44CUL) +#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_WLCSP15_PINH3_PF2) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINH3_PA0) || \ + ((PIN) == LL_PINMUX_WLCSP15_PING2_PA1) || \ + ((PIN) == LL_PINMUX_WLCSP15_PING2_PA2) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINK3_PA3) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINK3_PA4) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINJ2_PA5) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINJ2_PA6) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINH1_PA7) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINH1_PA12) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINE2_PA14) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINE2_PA15) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA3) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA4) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA5) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA6) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINA2_PB7) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINA2_PB8)) +#elif (DEV_ID == 0x44DUL) +#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_TSSOP20_PIN19_PA14) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN19_PA15) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN15_PA8) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB0) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB1) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB2) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB6) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB3) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB4) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB5) || \ + ((PIN) == LL_PINMUX_WLCSP24_PINA3_PB5) || \ + ((PIN) == LL_PINMUX_WLCSP24_PINA3_PB3) || \ + ((PIN) == LL_PINMUX_WLCSP24_PINB4_PB7) || \ + ((PIN) == LL_PINMUX_WLCSP24_PINB4_PB8)) +#endif /* DEV_ID == 0x443UL | DEV_ID == 0x453UL | DEV_ID == 0x493UL | DEV_ID == 0x44CUL | DEV_ID == 0x44DUL */ /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h index ffe4f36794..07388f88e7 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h @@ -481,6 +481,10 @@ typedef struct void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ + void (* CalibrationCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of calibration callback */ + void (* ADCReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Ready callback */ + void (* ChannelConfigReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Channel Configuration Ready + callback */ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ @@ -1864,7 +1868,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); @@ -1883,8 +1887,8 @@ void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} @@ -1894,8 +1898,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h index e60ae852b6..57ccdebbdd 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h @@ -143,7 +143,7 @@ extern "C" { /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_conf_template.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_conf_template.h index 22ea0a0eed..020150b241 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_conf_template.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_conf_template.h @@ -39,12 +39,15 @@ extern "C" { #define HAL_CRC_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED +#define HAL_FDCAN_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_I2S_MODULE_ENABLED #define HAL_IRDA_MODULE_ENABLED #define HAL_IWDG_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED #define HAL_RTC_MODULE_ENABLED @@ -66,11 +69,14 @@ extern "C" { * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef * for each PPP peripheral). */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ @@ -181,6 +187,10 @@ in voltage and temperature.*/ #include "stm32c0xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32c0xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + #ifdef HAL_DMA_MODULE_ENABLED #include "stm32c0xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ @@ -202,6 +212,10 @@ in voltage and temperature.*/ #include "stm32c0xx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32c0xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32c0xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ @@ -222,6 +236,10 @@ in voltage and temperature.*/ #include "stm32c0xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32c0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED #include "stm32c0xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h index 026bdcd967..dc1532d580 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h @@ -274,7 +274,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_EnableRegion(uint32_t RegionNumber); void HAL_MPU_DisableRegion(uint32_t RegionNumber); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** * @} @@ -334,7 +334,19 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); ((NUMBER) == MPU_REGION_NUMBER6) || \ ((NUMBER) == MPU_REGION_NUMBER7)) -#if defined(STM32C071xx) +#if defined(STM32C091xx) || defined(STM32C092xx) +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB)) +#elif defined(STM32C071xx) #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ ((SIZE) == MPU_REGION_SIZE_512B) || \ ((SIZE) == MPU_REGION_SIZE_1KB) || \ @@ -345,6 +357,16 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); ((SIZE) == MPU_REGION_SIZE_32KB) || \ ((SIZE) == MPU_REGION_SIZE_64KB) || \ ((SIZE) == MPU_REGION_SIZE_128KB)) +#elif defined(STM32C051xx) +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB)) #else #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ ((SIZE) == MPU_REGION_SIZE_512B) || \ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h index a24e5b9574..648c72ac32 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h @@ -103,7 +103,6 @@ typedef enum HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ - } HAL_DMA_CallbackIDTypeDef; /** @@ -212,6 +211,12 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_TIM3_CH4 35U /*!< DMAMUX TIM3 CH4 request */ #define DMA_REQUEST_TIM3_TRIG 36U /*!< DMAMUX TIM3 TRIG request */ #define DMA_REQUEST_TIM3_UP 37U /*!< DMAMUX TIM3 UP request */ +#if defined(TIM15) +#define DMA_REQUEST_TIM15_CH1 40U /*!< DMAMUX TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_CH2 41U /*!< DMAMUX TIM15 CH2 request */ +#define DMA_REQUEST_TIM15_TRIG_COM 42U /*!< DMAMUX TIM15 TRIG COM request */ +#define DMA_REQUEST_TIM15_UP 43U /*!< DMAMUX TIM15 UP request */ +#endif /* TIM15 */ #define DMA_REQUEST_TIM16_CH1 44U /*!< DMAMUX TIM16 CH1 request */ #define DMA_REQUEST_TIM16_TRIG_COM 45U /*!< DMAMUX TIM16 TRIG COM request */ #define DMA_REQUEST_TIM16_UP 46U /*!< DMAMUX TIM16 UP request */ @@ -222,6 +227,14 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_USART1_TX 51U /*!< DMAMUX USART1 TX request */ #define DMA_REQUEST_USART2_RX 52U /*!< DMAMUX USART2 RX request */ #define DMA_REQUEST_USART2_TX 53U /*!< DMAMUX USART2 TX request */ +#if defined(USART3) +#define DMA_REQUEST_USART3_RX 54U /*!< DMAMUX USART3 RX request */ +#define DMA_REQUEST_USART3_TX 55U /*!< DMAMUX USART3 TX request */ +#endif /* USART3 */ +#if defined(USART4) +#define DMA_REQUEST_USART4_RX 56U /*!< DMAMUX USART4 RX request */ +#define DMA_REQUEST_USART4_TX 57U /*!< DMAMUX USART4 TX request */ +#endif /* USART4 */ /** * @} */ @@ -333,7 +346,18 @@ typedef struct __DMA_HandleTypeDef #define DMA_FLAG_HT5 DMA_ISR_HTIF5 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 #endif /* DMA1_Channel5 */ - +#if defined(DMA1_Channel6) +#define DMA_FLAG_GI6 DMA_ISR_GIF6 +#define DMA_FLAG_TC6 DMA_ISR_TCIF6 +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define DMA_FLAG_GI7 DMA_ISR_GIF7 +#define DMA_FLAG_TC7 DMA_ISR_TCIF7 +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 +#endif /* DMA1_Channel7 */ /** * @} */ @@ -374,7 +398,16 @@ typedef struct __DMA_HandleTypeDef * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ -#if defined(DMA1_Channel5) +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) +#elif defined(DMA1_Channel5) #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ @@ -386,14 +419,23 @@ typedef struct __DMA_HandleTypeDef (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ DMA_FLAG_TC3) -#endif /* DMA1_Channel5 */ +#endif /* DMA1_Channel7 */ /** * @brief Return the current DMA Channel half transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ -#if defined(DMA1_Channel5) +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) +#elif defined(DMA1_Channel5) #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ @@ -405,14 +447,23 @@ typedef struct __DMA_HandleTypeDef (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ DMA_FLAG_HT3) -#endif /* DMA1_Channel5 */ +#endif /* DMA1_Channel7 */ /** * @brief Return the current DMA Channel transfer error flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ -#if defined(DMA1_Channel5) +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) +#elif defined(DMA1_Channel5) #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ @@ -424,14 +475,23 @@ typedef struct __DMA_HandleTypeDef (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ DMA_FLAG_TE3) -#endif /* DMA1_Channel5 */ +#endif /* DMA1_Channel7 */ /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ -#if defined(DMA1_Channel5) +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ + DMA_FLAG_GI7) +#elif defined(DMA1_Channel5) #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ @@ -443,7 +503,7 @@ typedef struct __DMA_HandleTypeDef (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ DMA_FLAG_GI3) -#endif /* DMA1_Channel5 */ +#endif /* DMA1_Channel7 */ /** * @brief Get the DMA Channel pending flags. @@ -454,7 +514,7 @@ typedef struct __DMA_HandleTypeDef * @arg DMA_FLAG_HTIFx: Half transfer complete flag * @arg DMA_FLAG_TEIFx: Transfer error flag * @arg DMA_FLAG_GIFx: Global interrupt flag - * Where x can be 1_5 to select the DMA Channel flag. + * Where x can be 1_7 to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) @@ -468,7 +528,7 @@ typedef struct __DMA_HandleTypeDef * @arg DMA_FLAG_HTIFx: Half transfer complete flag * @arg DMA_FLAG_TEIFx: Transfer error flag * @arg DMA_FLAG_GIFx: Global interrupt flag - * Where x can be 1_5 to select the DMA Channel flag. + * Where x can be 1_7 to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) @@ -563,8 +623,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); /** * @} */ @@ -589,8 +649,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ ((STATE) == DMA_MINC_DISABLE)) - +#if defined(USART4) +#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART4_TX) +#else #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART2_TX) +#endif /* USART4 */ #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h index cf45d5704b..cc0cf16427 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h @@ -115,9 +115,9 @@ typedef struct #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ -#if defined(STM32C071xx) +#if defined(DMAMUX1_Channel3) #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ -#endif /* STM32C071xx */ +#endif /* DMAMUX1_Channel3 */ #define HAL_DMAMUX1_SYNC_TIM14_OC 22U /*!< Synchronization Signal is TIM14 OC */ /** @@ -157,9 +157,9 @@ typedef struct #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ -#if defined(STM32C071xx) +#if defined(DMAMUX1_Channel3) #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ -#endif /* STM32C071xx */ +#endif /* DMAMUX1_Channel3 */ #define HAL_DMAMUX1_REQ_GEN_TIM14_OC 22U /*!< Request generator Signal is TIM14 OC */ /** * @} diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_fdcan.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_fdcan.h new file mode 100644 index 0000000000..dc58b75fa7 --- /dev/null +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_fdcan.h @@ -0,0 +1,1442 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_fdcan.h + * @author MCD Application Team + * @brief Header file of FDCAN HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_FDCAN_H +#define STM32C0xx_HAL_FDCAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +#if defined(FDCAN1) + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FDCAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Types FDCAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ + HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ + HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ + HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ +} HAL_FDCAN_StateTypeDef; + +/** + * @brief FDCAN Init structure definition + */ +typedef struct +{ + uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider. + The clock is common to all FDCAN instances. + This parameter is applied only at initialisation of + first FDCAN instance. + This parameter can be a value of @ref FDCAN_clock_divider. */ + + uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. + This parameter can be a value of @ref FDCAN_frame_format */ + + uint32_t Mode; /*!< Specifies the FDCAN mode. + This parameter can be a value of @ref FDCAN_operating_mode */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the nominal bit time quanta. + This parameter must be a number between 1 and 512 */ + + uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a bit to perform + resynchronization. + This parameter must be a number between 1 and 128 */ + + uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter must be a number between 2 and 256 */ + + uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter must be a number between 2 and 128 */ + + uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the data bit time quanta. + This parameter must be a number between 1 and 32 */ + + uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a data bit to + perform resynchronization. + This parameter must be a number between 1 and 16 */ + + uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. + This parameter must be a number between 1 and 32 */ + + uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. + This parameter must be a number between 1 and 16 */ + + uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. + This parameter must be a number between 0 and 28 */ + + uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. + This parameter must be a number between 0 and 8 */ + + uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. + This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ + +} FDCAN_InitTypeDef; + +/** + * @brief FDCAN filter structure definition + */ +typedef struct +{ + uint32_t IdType; /*!< Specifies the identifier type. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. + This parameter must be a number between: + - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID + - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ + + uint32_t FilterType; /*!< Specifies the filter type. + This parameter can be a value of @ref FDCAN_filter_type. + The value FDCAN_FILTER_RANGE_NO_EIDM is permitted + only when IdType is FDCAN_EXTENDED_ID. */ + + uint32_t FilterConfig; /*!< Specifies the filter configuration. + This parameter can be a value of @ref FDCAN_filter_config */ + + uint32_t FilterID1; /*!< Specifies the filter identification 1. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t FilterID2; /*!< Specifies the filter identification 2. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + +} FDCAN_FilterTypeDef; + +/** + * @brief FDCAN Tx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the message that will be + transmitted. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without + bit rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or + FD format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. + This parameter can be a value of @ref FDCAN_EFC */ + + uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO + element for identification of Tx message status. + This parameter must be a number between 0 and 0xFF */ + +} FDCAN_TxHeaderTypeDef; + +/** + * @brief FDCAN Rx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type of the received message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t RxFrameType; /*!< Specifies the the received message frame type. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the received frame length. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame + reception. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. + This parameter must be a number between: + - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID + - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID + When the frame is a Non-Filter matching frame, this parameter + is unused. */ + + uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. + Acceptance of non-matching frames may be enabled via + HAL_FDCAN_ConfigGlobalFilter(). + This parameter takes 0 if the frame matched an Rx filter or + 1 if it did not match any Rx filter */ + +} FDCAN_RxHeaderTypeDef; + +/** + * @brief FDCAN Tx event FIFO structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the transmitted frame. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame + transmission. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element + for identification of Tx message status. + This parameter must be a number between 0 and 0xFF */ + + uint32_t EventType; /*!< Specifies the event type. + This parameter can be a value of @ref FDCAN_event_type */ + +} FDCAN_TxEventFifoTypeDef; + +/** + * @brief FDCAN High Priority Message Status structure definition + */ +typedef struct +{ + uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. + This parameter can be: + - 0 : Standard Filter List + - 1 : Extended Filter List */ + + uint32_t FilterIndex; /*!< Specifies the index of matching filter element. + This parameter can be a number between: + - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard) + - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */ + + uint32_t MessageStorage; /*!< Specifies the HP Message Storage. + This parameter can be a value of @ref FDCAN_hp_msg_storage */ + + uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the + message was stored. + This parameter is valid only when MessageStorage is: + FDCAN_HP_STORAGE_RXFIFO0 + or + FDCAN_HP_STORAGE_RXFIFO1 */ + +} FDCAN_HpMsgStatusTypeDef; + +/** + * @brief FDCAN Protocol Status structure definition + */ +typedef struct +{ + uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. + This parameter can be a value of @ref FDCAN_protocol_error_code */ + + uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase + of a CAN FD format frame with its BRS flag set. + This parameter can be a value of @ref FDCAN_protocol_error_code */ + + uint32_t Activity; /*!< Specifies the FDCAN module communication state. + This parameter can be a value of @ref FDCAN_communication_state */ + + uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. + This parameter can be: + - 0 : The FDCAN is in Error_Active state + - 1 : The FDCAN is in Error_Passive state */ + + uint32_t Warning; /*!< Specifies the FDCAN module warning status. + This parameter can be: + - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the + Error_Warning limit of 96 + - 1 : at least one of error counters has reached the Error_Warning + limit of 96 */ + + uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. + This parameter can be: + - 0 : The FDCAN is not in Bus_Off state + - 1 : The FDCAN is in Bus_Off state */ + + uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. + This parameter can be: + - 0 : Last received CAN FD message did not have its ESI flag set + - 1 : Last received CAN FD message had its ESI flag set */ + + uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. + This parameter can be: + - 0 : Last received CAN FD message did not have its BRS flag set + - 1 : Last received CAN FD message had its BRS flag set */ + + uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received + since last protocol status. + This parameter can be: + - 0 : No CAN FD message received + - 1 : CAN FD message received */ + + uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. + This parameter can be: + - 0 : No protocol exception event occurred since last read access + - 1 : Protocol exception event occurred */ + + uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. + This parameter can be a number between 0 and 127 */ + +} FDCAN_ProtocolStatusTypeDef; + +/** + * @brief FDCAN Error Counters structure definition + */ +typedef struct +{ + uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. + This parameter can be a number between 0 and 255 */ + + uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. + This parameter can be a number between 0 and 127 */ + + uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. + This parameter can be: + - 0 : The Receive Error Counter (RxErrorCnt) is below the error + passive level of 128 + - 1 : The Receive Error Counter (RxErrorCnt) has reached the error + passive level of 128 */ + + uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. + This parameter can be a number between 0 and 255. + This counter is incremented each time when a FDCAN protocol error causes + the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; + the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag + FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ + +} FDCAN_ErrorCountersTypeDef; + +/** + * @brief FDCAN Message RAM blocks + */ +typedef struct +{ + uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. + This parameter must be a 32-bit word address */ + + uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. + This parameter must be a 32-bit word address */ + +} FDCAN_MsgRamAddressTypeDef; + +/** + * @brief FDCAN handle structure definition + */ +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +typedef struct __FDCAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +{ + FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ + + FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ + + FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ + + uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index + of latest Tx FIFO/Queue request */ + + __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ + + HAL_LockTypeDef Lock; /*!< FDCAN locking object */ + + __IO uint32_t ErrorCode; /*!< FDCAN Error code */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ + void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ + void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ + void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ + void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ + void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ + void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ + void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ + void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ + void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ + void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ + + void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ + void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +} FDCAN_HandleTypeDef; + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL FDCAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ + HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, /*!< FDCAN High priority message callback ID */ + HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, /*!< FDCAN Timestamp wraparound callback ID */ + HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U, /*!< FDCAN Timeout occurred callback ID */ + HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */ + + HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */ + HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */ + +} HAL_FDCAN_CallbackIDTypeDef; + +/** + * @brief HAL FDCAN Callback pointer definition + */ +typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ +typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ +typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ +typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ +typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ +typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ +typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants + * @{ + */ + +/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code + * @{ + */ +#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ +#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ +#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ +#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ +#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ +#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ +#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ +#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ +#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ +#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ +#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ +#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_format FDCAN Frame Format + * @{ + */ +#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ +#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ +#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ +/** + * @} + */ + +/** @defgroup FDCAN_operating_mode FDCAN Operating Mode + * @{ + */ +#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ +#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ +#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ +#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ +/** + * @} + */ + +/** @defgroup FDCAN_clock_divider FDCAN Clock Divider + * @{ + */ +#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ +#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */ +#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */ +#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */ +#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */ +#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */ +#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */ +#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */ +#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */ +#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */ +#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */ +#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */ +#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */ +#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */ +#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */ +#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */ +/** + * @} + */ + +/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode + * @{ + */ +#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ +#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ +/** + * @} + */ + +/** @defgroup FDCAN_id_type FDCAN ID Type + * @{ + */ +#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ +#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_type FDCAN Frame Type + * @{ + */ +#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ +#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup FDCAN_data_length_code FDCAN Data Length Code + * @{ + */ +#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */ +/** + * @} + */ + +/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator + * @{ + */ +#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ +#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ +/** + * @} + */ + +/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching + * @{ + */ +#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ +#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ +/** + * @} + */ + +/** @defgroup FDCAN_format FDCAN format + * @{ + */ +#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ +#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ +/** + * @} + */ + +/** @defgroup FDCAN_EFC FDCAN Event FIFO control + * @{ + */ +#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ +#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ +/** + * @} + */ + +/** @defgroup FDCAN_filter_type FDCAN Filter Type + * @{ + */ +#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ +#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ +#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ +#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ +/** + * @} + */ + +/** @defgroup FDCAN_filter_config FDCAN Filter Configuration + * @{ + */ +#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ +#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ +#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ +#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ +/** + * @} + */ + +/** @defgroup FDCAN_Tx_location FDCAN Tx Location + * @{ + */ +#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ +#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ +#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_location FDCAN Rx Location + * @{ + */ +#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ +#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_event_type FDCAN Event Type + * @{ + */ +#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ +#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ +/** + * @} + */ + +/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage + * @{ + */ +#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ +#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ +#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ +#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code + * @{ + */ +#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ +#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ +#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ +#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ +#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ +#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ +#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ +#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ +/** + * @} + */ + +/** @defgroup FDCAN_communication_state FDCAN communication state + * @{ + */ +#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ +#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ +#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ +#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode + * @{ + */ +#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ +#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */ +/** + * @} + */ + +/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames + * @{ + */ +#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ +#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ +#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ +/** + * @} + */ + +/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames + * @{ + */ +#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ +#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line + * @{ + */ +#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ +#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Timestamp FDCAN timestamp + * @{ + */ +#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ +#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ +/** + * @} + */ + +/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler + * @{ + */ +#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ +#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ +#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ +#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ +#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ +#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ +#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ +#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ +#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ +#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ +#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ +#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ +#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ +#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ +#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ +#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ +/** + * @} + */ + +/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation + * @{ + */ +#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ +#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ +#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ +#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup Interrupt_Masks Interrupt masks + * @{ + */ +#define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */ +#define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */ +/** + * @} + */ + +/** @defgroup FDCAN_flags FDCAN Flags + * @{ + */ +#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ +#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ +#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ +#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ +#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ +#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ +#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ +#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ +#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ +#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ +#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ +#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ +#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ +#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ +#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ +#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ +#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ +#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ +#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ +#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ +#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ +#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ +#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts FDCAN Interrupts + * @{ + */ + +/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts + * @{ + */ +#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ +#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ +#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts + * @{ + */ +#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ +/** + * @} + */ + +/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts + * @{ + */ +#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ +#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ +/** + * @} + */ + +/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts + * @{ + */ +#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ +#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ +#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts + * @{ + */ +#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ +#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ +#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts + * @{ + */ +#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ +#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ +#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts + * @{ + */ +#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ +#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ +#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ +#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ +#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ +/** + * @} + */ + +/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts + * @{ + */ +#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ +#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ +#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List + * @{ + */ +#define FDCAN_IT_LIST_RX_FIFO0 (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \ + FDCAN_IT_RX_FIFO0_FULL | \ + FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */ +#define FDCAN_IT_LIST_RX_FIFO1 (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \ + FDCAN_IT_RX_FIFO1_FULL | \ + FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */ +#define FDCAN_IT_LIST_SMSG (FDCAN_IT_TX_ABORT_COMPLETE | \ + FDCAN_IT_TX_COMPLETE | \ + FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */ +#define FDCAN_IT_LIST_TX_FIFO_ERROR (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \ + FDCAN_IT_TX_EVT_FIFO_FULL | \ + FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \ + FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */ +#define FDCAN_IT_LIST_MISC (FDCAN_IT_TIMEOUT_OCCURRED | \ + FDCAN_IT_RAM_ACCESS_FAILURE | \ + FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */ +#define FDCAN_IT_LIST_BIT_LINE_ERROR (FDCAN_IT_ERROR_PASSIVE | \ + FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */ +#define FDCAN_IT_LIST_PROTOCOL_ERROR (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \ + FDCAN_IT_DATA_PROTOCOL_ERROR | \ + FDCAN_IT_ARB_PROTOCOL_ERROR | \ + FDCAN_IT_RAM_WATCHDOG | \ + FDCAN_IT_BUS_OFF | \ + FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group + * @{ + */ +#define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group: + RF0LL: Rx FIFO 0 Message Lost + RF0FL: Rx FIFO 0 is Full + RF0NL: Rx FIFO 0 Has New Message */ +#define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group: + RF1LL: Rx FIFO 1 Message Lost + RF1FL: Rx FIFO 1 is Full + RF1NL: Rx FIFO 1 Has New Message */ +#define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG /*!< Status Message Interrupts Group: + TCFL: Transmission Cancellation Finished + TCL: Transmission Completed + HPML: High Priority Message */ +#define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group: + TEFLL: Tx Event FIFO Element Lost + TEFFL: Tx Event FIFO Full + TEFNL: Tx Event FIFO New Entry + TFEL: Tx FIFO Empty Interrupt Line */ +#define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC /*!< Misc. Interrupts Group: + TOOL: Timeout Occurred + MRAFL: Message RAM Access Failure + TSWL: Timestamp Wraparound */ +#define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group: + EPL: Error Passive + ELOL: Error Logging Overflow */ +#define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR /*!< Protocol Error Group: + ARAL: Access to Reserved Address Line + PEDL: Protocol Error in Data Phase Line + PEAL: Protocol Error in Arbitration Phase Line + WDIL: Watchdog Interrupt Line + BOL: Bus_Off Status + EWL: Warning Status */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros + * @{ + */ + +/** @brief Reset FDCAN handle state. + * @param __HANDLE__ FDCAN handle. + * @retval None + */ +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (__HANDLE__)->Instance->IE |= (__INTERRUPT__) + +/** + * @brief Disable the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__) + +/** + * @brief Check whether the specified FDCAN interrupt is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be one of @arg FDCAN_Interrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) + +/** + * @brief Clear the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the interrupts to clear. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->IR) = (__INTERRUPT__) + +/** + * @brief Check whether the specified FDCAN flag is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ FDCAN flag. + * This parameter can be one of @arg FDCAN_flags + * @retval FlagStatus + */ +#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__)) + +/** + * @brief Clear the specified FDCAN flags. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ specifies the flags to clear. + * This parameter can be any combination of @arg FDCAN_flags + * @retval None + */ +#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->IR) = (__FLAG__) + +/** @brief Check if the specified FDCAN interrupt source is enabled or disabled. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. + * This parameter can be a value of @arg FDCAN_Interrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FDCAN_Exported_Functions + * @{ + */ + +/** @addtogroup FDCAN_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, + pFDCAN_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxEventFifoCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo0CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo1CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferAbortCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ErrorStatusCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group2 + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, + uint32_t NonMatchingExt, uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt); +HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); +HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); +HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); +HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); +HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, + uint32_t TimeoutPeriod); +HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, + uint32_t TdcFilter); +HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group3 + * @{ + */ +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData); +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, + FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); +HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_HpMsgStatusTypeDef *HpMsgStatus); +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus); +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters); +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group4 + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, + uint32_t BufferIndexes); +HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group5 + * @{ + */ +/* Callback functions *********************************************************/ +void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); +void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); +void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); +void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group6 + * @{ + */ +/* Peripheral State functions *************************************************/ +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan); +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Variables FDCAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Constants FDCAN Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Macros FDCAN Private Macros + * @{ + */ +#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ + ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ + ((FORMAT) == FDCAN_FRAME_FD_BRS )) +#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ + ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ + ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ + ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ + ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) +#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV10) || \ + ((CKDIV) == FDCAN_CLOCK_DIV12) || \ + ((CKDIV) == FDCAN_CLOCK_DIV14) || \ + ((CKDIV) == FDCAN_CLOCK_DIV16) || \ + ((CKDIV) == FDCAN_CLOCK_DIV18) || \ + ((CKDIV) == FDCAN_CLOCK_DIV20) || \ + ((CKDIV) == FDCAN_CLOCK_DIV22) || \ + ((CKDIV) == FDCAN_CLOCK_DIV24) || \ + ((CKDIV) == FDCAN_CLOCK_DIV26) || \ + ((CKDIV) == FDCAN_CLOCK_DIV28) || \ + ((CKDIV) == FDCAN_CLOCK_DIV30)) +#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) +#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) +#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) +#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) +#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) +#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) +#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) +#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) +#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_)) +#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_)) +#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ + ((MODE) == FDCAN_TX_QUEUE_OPERATION)) +#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ + ((ID_TYPE) == FDCAN_EXTENDED_ID)) +#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ + ((CONFIG) == FDCAN_FILTER_REJECT ) || \ + ((CONFIG) == FDCAN_FILTER_HP ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP)) +#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER2 )) +#define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \ + ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2))) +#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ + ((FIFO) == FDCAN_RX_FIFO1)) +#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ + ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) +#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ + ((TYPE) == FDCAN_FILTER_DUAL ) || \ + ((TYPE) == FDCAN_FILTER_MASK )) +#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ + ((TYPE) == FDCAN_FILTER_DUAL ) || \ + ((TYPE) == FDCAN_FILTER_MASK ) || \ + ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) +#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ + ((TYPE) == FDCAN_REMOTE_FRAME)) +#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ + ((DLC) == FDCAN_DLC_BYTES_1 ) || \ + ((DLC) == FDCAN_DLC_BYTES_2 ) || \ + ((DLC) == FDCAN_DLC_BYTES_3 ) || \ + ((DLC) == FDCAN_DLC_BYTES_4 ) || \ + ((DLC) == FDCAN_DLC_BYTES_5 ) || \ + ((DLC) == FDCAN_DLC_BYTES_6 ) || \ + ((DLC) == FDCAN_DLC_BYTES_7 ) || \ + ((DLC) == FDCAN_DLC_BYTES_8 ) || \ + ((DLC) == FDCAN_DLC_BYTES_12) || \ + ((DLC) == FDCAN_DLC_BYTES_16) || \ + ((DLC) == FDCAN_DLC_BYTES_20) || \ + ((DLC) == FDCAN_DLC_BYTES_24) || \ + ((DLC) == FDCAN_DLC_BYTES_32) || \ + ((DLC) == FDCAN_DLC_BYTES_48) || \ + ((DLC) == FDCAN_DLC_BYTES_64)) +#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ + ((ESI) == FDCAN_ESI_PASSIVE)) +#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ + ((BRS) == FDCAN_BRS_ON )) +#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ + ((FDF) == FDCAN_FD_CAN )) +#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ + ((EFC) == FDCAN_STORE_TX_EVENTS)) +#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U) +#define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U) +#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ + ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ + ((DESTINATION) == FDCAN_REJECT )) +#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ + ((DESTINATION) == FDCAN_REJECT_REMOTE)) +#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ + ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) +#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ + ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) +#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) +#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ + ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ + ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ + ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) + +#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* FDCAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_FDCAN_H */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h index 6e66e792ce..268ae2a2a6 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h @@ -480,8 +480,8 @@ typedef struct /** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit * @{ */ -#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */ -#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */ +#define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler enable */ +#define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset handler disable */ /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h index 0efd54d74c..c7215053cc 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h @@ -61,15 +61,18 @@ extern "C" { #define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ #define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ #endif /* !STM32C011xx */ -#if defined(STM32C031xx) || defined(STM32C071xx) +#if defined(STM32C031xx) || defined(STM32C071xx) || defined(STM32C091xx) || defined(STM32C092xx) #define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ -#endif /* STM32C031xx | STM32C071xx */ +#endif /* STM32C031xx | STM32C071xx | STM32C091xx | STM32C092xx*/ #if defined(SPI2) #define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ #endif /* SPI2 */ #if defined(CRS) #define GPIO_AF0_CRS ((uint8_t)0x00) /*!< CRS Alternate Function mapping */ #endif /* CRS */ +#if defined(USART3) +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ /** * @brief AF 1 selection @@ -80,6 +83,9 @@ extern "C" { #define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ #define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ #define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#if defined(USART4) +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ +#endif /* USART4 */ /** * @brief AF 2 selection @@ -88,6 +94,9 @@ extern "C" { #if !defined(STM32C011xx) #define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ #endif /* STM32C011xx */ +#if defined(TIM15) +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#endif /* TIM15 */ #define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ #define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ #if defined(USB_DRD_FS) @@ -105,11 +114,23 @@ extern "C" { #if defined(TIM2) #define GPIO_AF3_TIM2 ((uint8_t)0x03) /*!< TIM2 Alternate Function mapping */ #endif /* TIM2 */ +#if defined(STM32C051xx) +#define GPIO_AF3_USART1 ((uint8_t)0x03) /*!< USART1 Alternate Function mapping */ +#endif /* STM32C051xx */ +#if defined(FDCAN1) +#define GPIO_AF3_FDCAN1 ((uint8_t)0x03) /*!< FDCAN1 Alternate Function mapping */ +#endif /* TIM2 */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#if defined(TIM15) +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#endif /* TIM15 */ +#if defined(USART3) +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ #define GPIO_AF4_USART2 ((uint8_t)0x04) /*!< USART2 Alternate Function mapping */ #define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ #if defined(CRS) @@ -118,6 +139,9 @@ extern "C" { #if defined(SPI2) #define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ #endif /* SPI2 */ +#if defined(FDCAN1) +#define GPIO_AF4_FDCAN1 ((uint8_t)0x04) /*!< FDCAN1 Alternate Function mapping */ +#endif /* FDCAN1 */ /** * @brief AF 5 selection @@ -130,12 +154,21 @@ extern "C" { #if defined(TIM2) #define GPIO_AF5_TIM2 ((uint8_t)0x05) /*!< TIM2 Alternate Function mapping */ #endif /* TIM2 */ +#if defined(TIM15) +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#endif /* TIM15 */ #if defined(SPI2) #define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ #endif /* SPI2 */ #if defined(I2C2) #define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< I2C2 Alternate Function mapping */ #endif /* I2C2 */ +#if defined(USART3) +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ +#if defined(USART4) +#define GPIO_AF5_USART4 ((uint8_t)0x05) /*!< USART4 Alternate Function mapping */ +#endif /* USART4 */ /** * @brief AF 6 selection @@ -153,6 +186,9 @@ extern "C" { #if defined(USB_DRD_FS) #define GPIO_AF6_USB ((uint8_t)0x06) /*!< USB Alternate Function mapping */ #endif /* USB_DRD_FS */ +#if defined(USART4) +#define GPIO_AF6_USART4 ((uint8_t)0x06) /*!< USART4 Alternate Function mapping */ +#endif /* USART4 */ /** * @brief AF 7 selection @@ -168,12 +204,24 @@ extern "C" { #if defined(I2C2) #define GPIO_AF8_I2C2 ((uint8_t)0x08) /*!< I2C2 Alternate Function mapping */ #endif /* I2C2 */ +#if defined(TIM15) +#define GPIO_AF8_TIM15 ((uint8_t)0x08) /*!< TIM15 Alternate Function mapping */ +#endif /* TIM15 */ +#if defined(USART3) +#define GPIO_AF8_USART3 ((uint8_t)0x08) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ +#if defined(FDCAN1) +#define GPIO_AF8_FDCAN1 ((uint8_t)0x08) /*!< FDCAN1 Alternate Function mapping */ +#endif /* FDCAN1 */ /** * @brief AF 9 selection */ #define GPIO_AF9_TIM1 ((uint8_t)0x09) /*!< TIM1 Alternate Function mapping */ #define GPIO_AF9_USART2 ((uint8_t)0x09) /*!< USART2 Alternate Function mapping */ +#if defined(USART4) +#define GPIO_AF9_USART4 ((uint8_t)0x09) /*!< USART4 Alternate Function mapping */ +#endif /* USART4 */ #define GPIO_AF9_SPI1 ((uint8_t)0x09) /*!< SPI1 Alternate Function mapping */ #define GPIO_AF9_I2S1 ((uint8_t)0x09) /*!< I2S1 Alternate Function mapping */ @@ -198,9 +246,9 @@ extern "C" { */ #define GPIO_AF12_TIM3 ((uint8_t)0x0C) /*!< TIM3 Alternate Function mapping */ #define GPIO_AF12_USART1 ((uint8_t)0x0C) /*!< USART1 Alternate Function mapping */ -#if defined(STM32C071xx) +#if defined(SPI2) #define GPIO_AF12_SPI2 ((uint8_t)0x0C) /*!< SPI2 Alternate Function mapping */ -#endif /* STM32C071xx */ +#endif /* SPI2 */ /** * @brief AF 13 selection @@ -220,9 +268,12 @@ extern "C" { */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ #define GPIO_AF15_MCO2 ((uint8_t)0x0F) /*!< MCO2 Alternate Function mapping */ -#if defined(STM32C011xx) || defined(STM32C031xx) || defined(STM32C071xx) +#if defined(STM32C011xx) || defined(STM32C031xx) || defined(STM32C051xx) || defined(STM32C071xx) #define GPIO_AF15_TIM17 ((uint8_t)0x0F) /*!< TIM17 Alternate Function mapping */ -#endif /* STM32C011xx | STM32C031xx | STM32C071xx */ +#endif /* STM32C011xx | STM32C031xx | STM32C051xx || STM32C071xx */ +#if defined(FDCAN1) +#define GPIO_AF15_FDCAN1 ((uint8_t)0x0F) /*!< FDCAN1 Alternate Function mapping */ +#endif /* FDCAN1 */ #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) /** diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pcd.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pcd.h index ce10c814e3..2b04997806 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pcd.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pcd.h @@ -462,6 +462,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h index dd0ee5d2a2..588ba84bb5 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h @@ -659,7 +659,6 @@ typedef struct #define RCC_FLAG_IWDGRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ #define RCC_FLAG_WWDGRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ #define RCC_FLAG_LPWRRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_LPWRRSTF_Pos) /*!< Low-Power reset flag */ - /** * @} */ @@ -837,6 +836,16 @@ typedef struct } while(0U) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* FDCAN1 */ + #if defined(SPI2) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -864,6 +873,25 @@ typedef struct tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ UNUSED(tmpreg); \ } while(0U) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USART3 */ + +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USART4 */ #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -907,6 +935,9 @@ typedef struct #if defined (USB_DRD_FS) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN) +#endif /* FDCAN1 */ #if defined(SPI2) #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) #endif /* SPI2 */ @@ -914,6 +945,12 @@ typedef struct #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) #endif /* CRS */ #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) +#endif /* USART4 */ #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) #if defined(I2C2) #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) @@ -971,6 +1008,16 @@ typedef struct UNUSED(tmpreg); \ } while(0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* TIM15 */ + #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ @@ -1000,6 +1047,9 @@ typedef struct #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) @@ -1067,6 +1117,9 @@ typedef struct #if defined (USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN) != 0U) +#endif /* FDCAN1 */ #if defined(SPI2) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U) #endif /* SPI2 */ @@ -1074,6 +1127,12 @@ typedef struct #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U) #endif /* CRS */ #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U) +#endif /* USART4 */ #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U) #if defined(I2C2) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U) @@ -1090,6 +1149,9 @@ typedef struct #if defined (USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN) == 0U) +#endif /* FDCAN1 */ #if defined(SPI2) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U) #endif /* SPI2 */ @@ -1097,6 +1159,12 @@ typedef struct #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U) #endif /* CRS */ #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U) +#endif /* USART4 */ #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U) #if defined(I2C2) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U) @@ -1119,6 +1187,9 @@ typedef struct #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U) #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U) #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U) @@ -1128,6 +1199,9 @@ typedef struct #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U) #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U) #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U) #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U) @@ -1189,6 +1263,9 @@ typedef struct #if defined (USB_DRD_FS) #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCAN1RST) +#endif /* FDACN1 */ #if defined(SPI2) #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) #endif /* SPI2 */ @@ -1196,6 +1273,12 @@ typedef struct #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) #endif /* CRS */ #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) +#if defined(USART3) +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) +#endif /* USART4 */ #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) #if defined(I2C2) #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) @@ -1211,6 +1294,9 @@ typedef struct #if defined (USB_DRD_FS) #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCAN1RST) +#endif /* FDACN1 */ #if defined(SPI2) #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) #endif /* SPI2 */ @@ -1218,6 +1304,12 @@ typedef struct #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) #endif /* CRS */ #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) +#if defined(USART3) +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) +#endif /* USART4 */ #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) #if defined(I2C2) #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) @@ -1238,6 +1330,9 @@ typedef struct #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) +#if defined(TIM15) +#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) @@ -1248,6 +1343,9 @@ typedef struct #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) +#if defined(TIM15) +#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) @@ -1320,6 +1418,9 @@ typedef struct #if defined (USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCAN1SMEN) +#endif /* FDCAN1 */ #if defined(SPI2) #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) #endif /* SPI2 */ @@ -1327,6 +1428,12 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) #endif /* CRS */ #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) +#endif /* USART4 */ #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) #if defined(I2C2) #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) @@ -1340,6 +1447,9 @@ typedef struct #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCAN1SMEN) +#endif /* FDCAN1 */ #if defined (USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) #endif /* USB_DRD_FS */ @@ -1350,6 +1460,12 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) #endif /* CRS */ #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) +#endif /* USART4 */ #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) #if defined(I2C2) #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) @@ -1373,6 +1489,9 @@ typedef struct #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) @@ -1382,6 +1501,9 @@ typedef struct #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) @@ -1439,7 +1561,8 @@ typedef struct * @} */ -/** @defgroup RCC_APB1_GRP1_Clock_Sleep_Enabled_Disabled_Status APB1_GRP1 Peripheral Clock Sleep Enabled or Disabled Status +/** @defgroup RCC_APB1_GRP1_Clock_Sleep_Enabled_Disabled_Status APB1_GRP1 Peripheral Clock Sleep Enabled or + * Disabled Status * @brief Check whether the APB1_GRP1 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. @@ -1456,6 +1579,9 @@ typedef struct #if defined (USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCAN1SMEN) != RESET) +#endif /* FDCAN1 */ #if defined(SPI2) #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET) #endif /* SPI2 */ @@ -1463,6 +1589,12 @@ typedef struct #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET) #endif /* CRS */ #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET) +#endif /* USART4 */ #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET) #if defined(I2C2) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET) @@ -1479,6 +1611,9 @@ typedef struct #if defined (USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCAN1SMEN) == RESET) +#endif /* FDCAN1 */ #if defined(SPI2) #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET) #endif /* SPI2 */ @@ -1486,6 +1621,12 @@ typedef struct #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET) #endif /* CRS */ #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET) +#endif /* USART4 */ #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET) #if defined(I2C2) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET) @@ -1496,7 +1637,8 @@ typedef struct * @} */ -/** @defgroup RCC_APB1_GRP2_Clock_Sleep_Enabled_Disabled_Status APB1_GRP2 Peripheral Clock Sleep Enabled or Disabled Status +/** @defgroup RCC_APB1_GRP2_Clock_Sleep_Enabled_Disabled_Status APB1_GRP2 Peripheral Clock Sleep Enabled or + * Disabled Status * @brief Check whether the APB1_GRP2 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. @@ -1509,6 +1651,9 @@ typedef struct #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET) #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET) #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET) @@ -1518,6 +1663,9 @@ typedef struct #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET) #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET) +#endif /* TIM15 */ #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET) #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET) diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h index 8e4b55820a..ce1f9d154d 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h @@ -66,6 +66,11 @@ typedef struct This parameter can be a value of @ref RCCEx_USB_Clock_Source */ #endif /* USB_DRD_FS */ +#if defined(FDCAN1) + uint32_t Fdcan1ClockSelection; /*!< Specifies FDCAN1 clock source. + This parameter can be a value of @ref RCCEx_FDCAN1_Clock_Source */ +#endif /* FDCAN1 */ + uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ @@ -154,6 +159,9 @@ typedef struct #if defined(USB_DRD_FS) #define RCC_PERIPHCLK_USB 0x00000008U #endif /* USB_DRD_FS */ +#if defined(FDCAN1) +#define RCC_PERIPHCLK_FDCAN1 0x00000010U +#endif /* FDCAN1 */ #define RCC_PERIPHCLK_ADC 0x00000020U #define RCC_PERIPHCLK_RTC 0x00000040U #define RCC_PERIPHCLK_HSIKER 0x00000080U @@ -206,6 +214,18 @@ typedef struct */ #endif /* USB_DRD_FS */ +#if defined(FDCAN1) +/** @defgroup RCCEx_FDCAN1_Clock_Source FDCAN1 Clock Source + * @{ + */ +#define RCC_FDCAN1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FDCAN1CLKSOURCE_HSIKER RCC_CCIPR_FDCAN1SEL_0 +#define RCC_FDCAN1CLKSOURCE_HSE RCC_CCIPR_FDCAN1SEL_1 +/** + * @} + */ +#endif /* FDCAN1 */ + /** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source * @{ */ @@ -436,6 +456,27 @@ typedef struct #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL))) #endif /* USB_DRD_FS */ +#if defined(FDCAN1) +/** @brief Macro to configure the FDCAN1 clock (FDCAN1CLK). + * + * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_FDCAN1CLKSOURCE_PCLK1 APB Clock selected as FDCAN1 clock + * @arg @ref RCC_FDCAN1CLKSOURCE_HSIKER HSI Kernel Clock selected as FDCAN1 clock + * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE clock selected as FDCAN1 clock + */ +#define __HAL_RCC_FDCAN1_CONFIG(__FDCAN1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCAN1SEL, (uint32_t)(__FDCAN1_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_FDCAN1CLKSOURCE_PCLK1 APB Clock selected as FDCAN1 clock + * @arg @ref RCC_FDCAN1CLKSOURCE_HSIKER HSI Kernel Clock selected as FDCAN1 clock + * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE clock selected as FDCAN1 clock + */ +#define __HAL_RCC_GET_FDCAN1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCAN1SEL))) +#endif /* FDCAN1 */ + /** @brief Macro to configure the ADC interface clock * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. * This parameter can be one of the following values: @@ -724,6 +765,15 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ (((__SELECTION__) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)) +#elif defined (FDCAN1) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN1) == RCC_PERIPHCLK_FDCAN1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)) #else #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ @@ -750,6 +800,13 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSIKER) || \ ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) +#if defined (FDCAN1) +#define IS_RCC_FDCAN1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSIKER)|| \ + ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PCLK1)) +#endif /* FDCAN1 */ + #if defined (USB_DRD_FS) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \ @@ -766,7 +823,6 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__DIV__) == RCC_HSIKER_DIV7) || ((__DIV__) == RCC_HSIKER_DIV8)) #if defined(CRS) - #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) @@ -787,7 +843,6 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) - #endif /* CRS */ /** * @} diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rtc_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rtc_ex.h index 5aaabf23a0..3f744b3ffd 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rtc_ex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rtc_ex.h @@ -237,9 +237,9 @@ extern "C" { * @retval None */ #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - (((__FLAG__) == RTC_FLAG_TSF) ? \ - (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \ - (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF))) + (((__FLAG__) == RTC_FLAG_TSF) ? \ + (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \ + (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF))) /** * @brief Enable interrupt on the RTC Timestamp associated Exti line. diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_spi.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_spi.h index 4c21e820aa..ed2f5aba32 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_spi.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_spi.h @@ -754,6 +754,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) +/** @brief Checks if a data address is 16bit aligned. + * @param __DATA__ specifies a data address. + * @retval None + */ +#define IS_SPI_16BIT_ALIGNED_ADDRESS(__DATA__) (((uint32_t)(__DATA__) % 2U) == 0U) + /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h index 6a988b168f..c4c094a717 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h @@ -147,6 +147,16 @@ typedef struct #define TIM_TIM14_TI1_MCO 0x00000003U /*!< TIM14_TI1 is connected to MCO */ #define TIM_TIM14_TI1_MCO2 0x00000004U /*!< TIM14_TI1 is connected to MCO2 */ +#if defined(TIM15) +#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 0x00000001U /*!< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 0x00000002U /*!< TIM15_TI1 is connected to TIM3 CH1 */ + +#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 0x00000100U /*!< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 0x00000200U /*!< TIM15_TI2 is connected to TIM3 CH2 */ +#endif /* TIM15 */ + #define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16_TI1 is connected to GPIO */ #define TIM_TIM16_TI1_LSI 0x00000001U /*!< TIM16_TI1 is connected to LSI */ #define TIM_TIM16_TI1_LSE 0x00000002U /*!< TIM16_TI1 is connected to LSE */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h index b0e37370ec..a86faa62e2 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h @@ -196,6 +196,48 @@ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef * * @{ */ +#if defined(USART4) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSIKER: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -228,6 +270,7 @@ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef * (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#endif /* USART4 */ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h index 9fec4d9eb4..40edaef634 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h @@ -1955,7 +1955,7 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { /* Prevent unused argument(s) compilation warning */ (void)(Register); @@ -2033,7 +2033,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * is set to clock source asynchronous. * (refer to function @ref LL_ADC_SetClock() ). */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); } @@ -2164,7 +2164,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); } @@ -2224,7 +2224,7 @@ __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) * cycle). * Refer to reference manual. */ -__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetClock(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); } @@ -2260,7 +2260,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t Cal * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); } @@ -2298,7 +2298,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); } @@ -2332,7 +2332,7 @@ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAli * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); } @@ -2442,7 +2442,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_AUTOPOWEROFF * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF))); } @@ -2485,7 +2485,7 @@ __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH * @arg @ref LL_ADC_TRIGGER_FREQ_LOW */ -__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); } @@ -2567,7 +2567,7 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uin * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 */ -__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY) { return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); @@ -2642,7 +2642,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 * (1) ADC external trigger available on STM32C071xx device only. */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); @@ -2669,7 +2669,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); } @@ -2704,7 +2704,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); } @@ -2767,7 +2767,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_REG_SEQ_FIXED * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD)); } @@ -2898,7 +2898,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; @@ -2960,7 +2960,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uin * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); } @@ -2996,7 +2996,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); } @@ -3172,7 +3172,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). * (3) ADC channels available on STM32C031xx device only. */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -3567,7 +3567,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). * (3) ADC channels available on STM32C031xx device only. */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx) { uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); @@ -3632,7 +3632,7 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); } @@ -3702,7 +3702,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATr * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); } @@ -3740,7 +3740,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); } @@ -3915,7 +3915,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { __IO uint32_t smpr = READ_REG(ADCx->SMPR); @@ -4110,7 +4110,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CH_VDDA_REG * @arg @ref LL_ADC_AWD_CH_VSSA_REG * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. - */__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) + */__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) @@ -4357,7 +4357,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ /* position in register and register position depending on parameters */ @@ -4410,7 +4410,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); } @@ -4452,7 +4452,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); } @@ -4508,7 +4508,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); } @@ -4528,7 +4528,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } @@ -4593,7 +4593,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -4653,7 +4653,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -4664,7 +4664,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -4713,7 +4713,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -4780,7 +4780,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -4791,7 +4791,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -4805,7 +4805,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } @@ -4820,7 +4820,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } @@ -4835,7 +4835,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } @@ -4850,7 +4850,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } @@ -4865,7 +4865,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } @@ -4887,7 +4887,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -4914,7 +4914,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); } @@ -4925,7 +4925,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -4936,7 +4936,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -4947,7 +4947,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -4958,7 +4958,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -4969,7 +4969,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -4980,7 +4980,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -4991,7 +4991,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -5002,7 +5002,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL); } @@ -5354,7 +5354,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -5365,7 +5365,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); } @@ -5377,7 +5377,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -5389,7 +5389,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -5401,7 +5401,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -5413,7 +5413,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -5425,7 +5425,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -5437,7 +5437,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -5449,7 +5449,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -5461,7 +5461,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); } @@ -5477,17 +5477,17 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) /* Initialization of some features of ADC common parameters and multimode */ ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); /* De-initialization of ADC instance */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); /* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct); void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); /** diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_bus.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_bus.h index 32a9d8cb18..0f08069558 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_bus.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_bus.h @@ -94,6 +94,9 @@ extern "C" { #if defined (USB_DRD_FS) #define LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define LL_APB1_GRP1_PERIPH_FDCAN1 RCC_APBENR1_FDCAN1EN +#endif /* FDCAN1 */ #if defined(SPI2) #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN #endif /* SPI2 */ @@ -101,6 +104,12 @@ extern "C" { #define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN #endif /* CRS */ #define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN +#endif /* USART3 */ +#if defined(USART4) +#define LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN +#endif /* USART4 */ #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN #if defined(I2C2) #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN @@ -121,6 +130,9 @@ extern "C" { #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APBENR2_SPI1EN #define LL_APB1_GRP2_PERIPH_USART1 RCC_APBENR2_USART1EN #define LL_APB1_GRP2_PERIPH_TIM14 RCC_APBENR2_TIM14EN +#if defined(TIM15) +#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APBENR2_TIM15EN +#endif /* TIM15 */ #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APBENR2_TIM16EN #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APBENR2_TIM17EN #define LL_APB1_GRP2_PERIPH_ADC RCC_APBENR2_ADCEN @@ -315,6 +327,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * APBENR1 SPI2EN LL_APB1_GRP1_EnableClock\n (*) * APBENR1 I2C2EN LL_APB1_GRP1_EnableClock\n (*) * APBENR1 USBEN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 FDCAN1EN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 USART3EN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 USART4EN LL_APB1_GRP1_EnableClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 * @arg @ref LL_APB1_GRP1_PERIPH_RTC @@ -326,6 +341,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) * @note (*) peripheral not available on all devices * @retval None */ @@ -351,6 +369,9 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) * APBENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n (*) * APBENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n (*) * APBENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 FDCAN1EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 USART4EN LL_APB1_GRP1_IsEnabledClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 * @arg @ref LL_APB1_GRP1_PERIPH_RTC @@ -363,6 +384,9 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) * @note (*) peripheral not available on all devices * @retval State of Periphs (1 or 0). */ @@ -384,6 +408,9 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) * APBENR1 SPI2EN LL_APB1_GRP1_DisableClock\n (*) * APBENR1 I2C2EN LL_APB1_GRP1_DisableClock\n (*) * APBENR1 USBEN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 FDACN1EN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 USART3EN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 USART4EN LL_APB1_GRP1_DisableClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 * @arg @ref LL_APB1_GRP1_PERIPH_RTC @@ -396,6 +423,9 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) * @note (*) peripheral not available on all devices * @retval None */ @@ -416,6 +446,9 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) * APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n (*) * APBRSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n (*) * APBRSTR1 USBRST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 FDCAN1RST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 USART3RST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 USART4RST LL_APB1_GRP1_ForceReset (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 @@ -428,6 +461,9 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) * @note (*) peripheral not available on all devices * @retval None */ @@ -448,6 +484,9 @@ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) * APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n (*) * APBRSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n (*) * APBRSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 FDCAN1RST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 USART4RST LL_APB1_GRP1_ReleaseReset (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 @@ -460,6 +499,9 @@ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) * @note (*) peripheral not available on all devices * @retval None */ @@ -480,6 +522,9 @@ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) * APBSMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) * APBSMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) * APBSMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 FDCAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 USART4SMEN LL_APB1_GRP1_EnableClockStopSleep (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 * @arg @ref LL_APB1_GRP1_PERIPH_RTC @@ -491,6 +536,9 @@ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) * @note (*) peripheral not available on all devices * @retval None */ @@ -515,6 +563,9 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * APBSMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) * APBSMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) * APBSMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 FDCAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 USART4SMEN LL_APB1_GRP1_DisableClockStopSleep (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 * @arg @ref LL_APB1_GRP1_PERIPH_RTC @@ -526,6 +577,9 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) * @note (*) peripheral not available on all devices * @retval None */ @@ -551,7 +605,8 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * APBENR2 TIM14EN LL_APB1_GRP2_EnableClock\n * APBENR2 TIM16EN LL_APB1_GRP2_EnableClock\n * APBENR2 TIM17EN LL_APB1_GRP2_EnableClock\n - * APBENR2 ADCEN LL_APB1_GRP2_EnableClock + * APBENR2 ADCEN LL_APB1_GRP2_EnableClock\n + * APBENR2 TIM15EN LL_APB1_GRP2_EnableClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 @@ -561,6 +616,8 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) @@ -582,7 +639,8 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * APBENR2 TIM14EN LL_APB1_GRP2_IsEnabledClock\n * APBENR2 TIM16EN LL_APB1_GRP2_IsEnabledClock\n * APBENR2 TIM17EN LL_APB1_GRP2_IsEnabledClock\n - * APBENR2 ADCEN LL_APB1_GRP2_IsEnabledClock + * APBENR2 ADCEN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 TIM15EN LL_APB1_GRP2_IsEnabledClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 @@ -592,6 +650,8 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) @@ -609,7 +669,8 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * APBENR2 TIM14EN LL_APB1_GRP2_DisableClock\n * APBENR2 TIM16EN LL_APB1_GRP2_DisableClock\n * APBENR2 TIM17EN LL_APB1_GRP2_DisableClock\n - * APBENR2 ADCEN LL_APB1_GRP2_DisableClock + * APBENR2 ADCEN LL_APB1_GRP2_DisableClock\n + * APBENR2 TIM15EN LL_APB1_GRP2_DisableClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 @@ -619,6 +680,9 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) @@ -636,7 +700,8 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) * APBRSTR2 TIM14RST LL_APB1_GRP2_ForceReset\n * APBRSTR2 TIM16RST LL_APB1_GRP2_ForceReset\n * APBRSTR2 TIM17RST LL_APB1_GRP2_ForceReset\n - * APBRSTR2 ADCRST LL_APB1_GRP2_ForceReset + * APBRSTR2 ADCRST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 TIM15RST LL_APB1_GRP2_ForceReset (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG @@ -647,6 +712,8 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) @@ -664,7 +731,8 @@ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) * APBRSTR2 TIM14RST LL_APB1_GRP2_ReleaseReset\n * APBRSTR2 TIM16RST LL_APB1_GRP2_ReleaseReset\n * APBRSTR2 TIM17RST LL_APB1_GRP2_ReleaseReset\n - * APBRSTR2 ADCRST LL_APB1_GRP2_ReleaseReset + * APBRSTR2 ADCRST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 TIM15RST LL_APB1_GRP2_ReleaseReset (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG @@ -675,6 +743,8 @@ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) @@ -692,7 +762,8 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * APBSMENR2 TIM14SMEN LL_APB1_GRP2_EnableClockStopSleep\n * APBSMENR2 TIM16SMEN LL_APB1_GRP2_EnableClockStopSleep\n * APBSMENR2 TIM17SMEN LL_APB1_GRP2_EnableClockStopSleep\n - * APBSMENR2 ADCSMEN LL_APB1_GRP2_EnableClockStopSleep + * APBSMENR2 ADCSMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 TIM15SMEN LL_APB1_GRP2_EnableClockStopSleep (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 @@ -702,6 +773,8 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) @@ -723,7 +796,8 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) * APBSMENR2 TIM14SMEN LL_APB1_GRP2_DisableClockStopSleep\n * APBSMENR2 TIM16SMEN LL_APB1_GRP2_DisableClockStopSleep\n * APBSMENR2 TIM17SMEN LL_APB1_GRP2_DisableClockStopSleep\n - * APBSMENR2 ADCSMEN LL_APB1_GRP2_DisableClockStopSleep + * APBSMENR2 ADCSMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 TIM15SMEN LL_APB1_GRP2_DisableClockStopSleep (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 @@ -733,6 +807,8 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_crs.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_crs.h index c20681e0eb..6708b07038 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_crs.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_crs.h @@ -6,29 +6,12 @@ ****************************************************************************** * @attention * - *

        © COPYRIGHT(c) 2016 STMicroelectronics

        + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -105,14 +88,14 @@ extern "C" { /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider * @{ */ -#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ -#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ /** * @} */ @@ -469,7 +452,8 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 * @param Settings This parameter can be a combination of the following values: * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 - * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 + * or @ref LL_CRS_SYNC_DIV_128 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING * @retval None @@ -806,5 +790,3 @@ ErrorStatus LL_CRS_DeInit(void); #endif #endif /* STM32C0xx_LL_CRS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dma.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dma.h index afc16dd05f..16448d8012 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dma.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dma.h @@ -55,6 +55,12 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = #if defined(DMA1_Channel5_BASE) (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), #endif /* DMA1_Channel5_BASE */ +#if defined(DMA1_Channel6_BASE) + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), +#endif /* DMA1_Channel6_BASE */ +#if defined(DMA1_Channel7_BASE) + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE), +#endif /* DMA1_Channel7_BASE */ }; /** * @} @@ -187,6 +193,18 @@ typedef struct #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ #endif /* DMA1_Channel5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +#endif /* DMA1_Channel7 */ /** * @} @@ -220,6 +238,18 @@ typedef struct #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ #endif /* DMA1_Channel5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +#endif /* DMA1_Channel7 */ /** * @} */ @@ -247,6 +277,12 @@ typedef struct #if defined(DMA1_Channel5) #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ #endif /* DMA1_Channel5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#endif /* DMA1_Channel7 */ #if defined(USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ @@ -370,7 +406,16 @@ typedef struct * @param __CHANNEL_INSTANCE__ DMAx_Channely * @retval LL_DMA_CHANNEL_y */ -#if defined(LL_DMA_CHANNEL_5) +#if defined(LL_DMA_CHANNEL_7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#elif defined(LL_DMA_CHANNEL_5) #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ @@ -382,7 +427,7 @@ typedef struct (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ LL_DMA_CHANNEL_3) -#endif /* LL_DMA_CHANNEL_5 */ +#endif /* LL_DMA_CHANNEL_7 */ /** * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely @@ -390,19 +435,40 @@ typedef struct * @param __CHANNEL__ LL_DMA_CHANNEL_y * @retval DMAx_Channely */ -#if defined(LL_DMA_CHANNEL_5) -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ - ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - DMA1_Channel5) +#if defined(LL_DMA_CHANNEL_7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#elif defined(LL_DMA_CHANNEL_5) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + DMA1_Channel5) #else -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ - ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - DMA1_Channel3) -#endif /* LL_DMA_CHANNEL_5 */ +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + DMA1_Channel3) +#endif /* LL_DMA_CHANNEL_7 */ /** * @} @@ -430,10 +496,12 @@ typedef struct * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval None */ -__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_EN); @@ -449,10 +517,12 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval None */ -__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_EN); @@ -468,10 +538,12 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -495,6 +567,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param Configuration This parameter must be a combination of all the following values: * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @@ -508,7 +582,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha * @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -527,6 +601,8 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param Direction This parameter can be one of the following values: * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY @@ -534,7 +610,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -552,13 +628,15 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -577,13 +655,15 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param Mode This parameter can be one of the following values: * @arg @ref LL_DMA_MODE_NORMAL * @arg @ref LL_DMA_MODE_CIRCULAR * @retval None */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_CIRC, @@ -600,12 +680,14 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_MODE_NORMAL * @arg @ref LL_DMA_MODE_CIRCULAR */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -622,13 +704,15 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: * @arg @ref LL_DMA_PERIPH_INCREMENT * @arg @ref LL_DMA_PERIPH_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PINC, @@ -645,12 +729,14 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_PERIPH_INCREMENT * @arg @ref LL_DMA_PERIPH_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -667,13 +753,15 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: * @arg @ref LL_DMA_MEMORY_INCREMENT * @arg @ref LL_DMA_MEMORY_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MINC, @@ -690,12 +778,14 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_MEMORY_INCREMENT * @arg @ref LL_DMA_MEMORY_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -712,6 +802,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: * @arg @ref LL_DMA_PDATAALIGN_BYTE @@ -719,7 +811,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PSIZE, @@ -736,13 +828,15 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_PDATAALIGN_BYTE * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -759,6 +853,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: * @arg @ref LL_DMA_MDATAALIGN_BYTE @@ -766,7 +862,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MSIZE, @@ -783,13 +879,15 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_MDATAALIGN_BYTE * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -806,6 +904,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param Priority This parameter can be one of the following values: * @arg @ref LL_DMA_PRIORITY_LOW @@ -814,7 +914,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PL, @@ -831,6 +931,8 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_PRIORITY_LOW @@ -838,7 +940,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -857,11 +959,13 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR, @@ -880,10 +984,12 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR, @@ -903,6 +1009,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF @@ -912,7 +1020,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -942,11 +1050,13 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress); @@ -964,11 +1074,13 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, PeriphAddress); @@ -985,10 +1097,12 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR)); @@ -1005,10 +1119,12 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR)); @@ -1026,11 +1142,13 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, MemoryAddress); @@ -1048,11 +1166,13 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress); @@ -1069,10 +1189,12 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR)); @@ -1089,10 +1211,12 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR)); @@ -1100,7 +1224,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha /** * @brief Set DMA request for DMA Channels on DMAMUX Channel x. - * @note DMAMUX channel 0 to 4 are mapped to DMA1 channel 1 to 5. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1109,6 +1233,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @param Request This parameter can be one of the following values: * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 @@ -1152,6 +1278,10 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMAMUX_REQ_USART1_TX * @arg @ref LL_DMAMUX_REQ_USART2_RX * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART3_TX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_TX (*) * @note (*) Availability depends on devices * @retval None */ @@ -1164,7 +1294,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel /** * @brief Get DMA request for DMA Channels on DMAMUX Channel x. - * @note DMAMUX channel 0 to 4 are mapped to DMA1 channel 1 to 5. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1173,6 +1303,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @retval Returned value can be one of the following values: * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 @@ -1216,6 +1348,10 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMAMUX_REQ_USART1_TX * @arg @ref LL_DMAMUX_REQ_USART2_RX * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART3_TX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_TX (*) * @note (*) Availability depends on devices */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) @@ -1240,7 +1376,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1251,7 +1387,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1262,7 +1398,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1274,7 +1410,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1287,19 +1423,45 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } #endif /* DMA_ISR_GIF5 */ +#if defined(DMA_ISR_GIF6) +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_GIF6 */ + +#if defined(DMA_ISR_GIF7) +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_GIF7 */ + /** * @brief Get Channel 1 transfer complete flag. * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1310,7 +1472,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1321,7 +1483,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1333,7 +1495,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1346,19 +1508,45 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } #endif /* DMA_ISR_TCIF5 */ +#if defined(DMA_ISR_TCIF6) +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TCIF6 */ + +#if defined(DMA_ISR_TCIF7) +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TCIF7 */ + /** * @brief Get Channel 1 half transfer flag. * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1369,7 +1557,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1380,7 +1568,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1392,7 +1580,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1405,19 +1593,45 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } #endif /* DMA_ISR_HTIF5 */ +#if defined(DMA_ISR_HTIF6) +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_HTIF6 */ + +#if defined(DMA_ISR_HTIF7) +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_HTIF7 */ + /** * @brief Get Channel 1 transfer error flag. * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1428,7 +1642,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1439,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1451,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1464,12 +1678,38 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } #endif /* DMA_ISR_TEIF5 */ +#if defined(DMA_ISR_TEIF6) +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TEIF6 */ + +#if defined(DMA_ISR_TEIF7) +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TEIF7 */ + /** * @brief Clear Channel 1 global interrupt flag. * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. @@ -1549,6 +1789,40 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) } #endif /* DMA_IFCR_CGIF5 */ +#if defined(DMA_IFCR_CGIF6) +/** + * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} +#endif /* DMA_IFCR_CGIF6 */ + +#if defined(DMA_IFCR_CGIF7) +/** + * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} +#endif /* DMA_IFCR_CGIF7 */ + /** * @brief Clear Channel 1 transfer complete flag. * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 @@ -1608,6 +1882,32 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) } #endif /* DMA_IFCR_CTCIF5 */ +#if defined(DMA_IFCR_CTCIF6) +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} +#endif /* DMA_IFCR_CTCIF6 */ + +#if defined(DMA_IFCR_CTCIF7) +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} +#endif /* DMA_IFCR_CTCIF7 */ + /** * @brief Clear Channel 1 half transfer flag. * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 @@ -1667,6 +1967,32 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) } #endif /* DMA_IFCR_CHTIF5 */ +#if defined(DMA_IFCR_CHTIF6) +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} +#endif /* DMA_IFCR_CHTIF6 */ + +#if defined(DMA_IFCR_CHTIF7) +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} +#endif /* DMA_IFCR_CHTIF7 */ + /** * @brief Clear Channel 1 transfer error flag. * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 @@ -1726,6 +2052,32 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) } #endif /* DMA_IFCR_CTEIF5 */ +#if defined(DMA_IFCR_CTEIF6) +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} +#endif /* DMA_IFCR_CTEIF6 */ + +#if defined(DMA_IFCR_CTEIF7) +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} +#endif /* DMA_IFCR_CTEIF7 */ + /** * @} */ @@ -1743,6 +2095,8 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval None */ @@ -1762,10 +2116,12 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE); @@ -1781,10 +2137,12 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE); @@ -1800,10 +2158,12 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE); @@ -1819,10 +2179,12 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE); @@ -1838,10 +2200,12 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE); @@ -1857,10 +2221,12 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -1877,10 +2243,12 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, @@ -1897,10 +2265,12 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h index 5ce9d60ead..874de099e3 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h @@ -159,6 +159,12 @@ extern "C" { #define LL_DMAMUX_REQ_TIM3_CH4 0x00000023U /*!< DMAMUX TIM3 CH4 request */ #define LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U /*!< DMAMUX TIM3 TRIG request */ #define LL_DMAMUX_REQ_TIM3_UP 0x00000025U /*!< DMAMUX TIM3 UP request */ +#if defined(TIM15) +#define LL_DMAMUX_REQ_TIM15_CH1 0x00000028U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQ_TIM15_CH2 0x00000029U /*!< DMAMUX TIM15 CH2 request */ +#define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU /*!< DMAMUX TIM15 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM15_UP 0x0000002BU /*!< DMAMUX TIM15 UP request */ +#endif /* TIM15 */ #define LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU /*!< DMAMUX TIM16 CH1 request */ #define LL_DMAMUX_REQ_TIM16_TRIG_COM 0x0000002DU /*!< DMAMUX TIM16 TRIG COM request */ #define LL_DMAMUX_REQ_TIM16_UP 0x0000002EU /*!< DMAMUX TIM16 UP request */ @@ -169,6 +175,14 @@ extern "C" { #define LL_DMAMUX_REQ_USART1_TX 0x00000033U /*!< DMAMUX USART1 TX request */ #define LL_DMAMUX_REQ_USART2_RX 0x00000034U /*!< DMAMUX USART2 RX request */ #define LL_DMAMUX_REQ_USART2_TX 0x00000035U /*!< DMAMUX USART2 TX request */ +#if defined(USART3) +#define LL_DMAMUX_REQ_USART3_RX 0x00000036U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQ_USART3_TX 0x00000037U /*!< DMAMUX USART3 TX request */ +#endif /* USART3 */ +#if defined(USART4) +#define LL_DMAMUX_REQ_USART4_RX 0x00000038U /*!< DMAMUX USART4 RX request */ +#define LL_DMAMUX_REQ_USART4_TX 0x00000039U /*!< DMAMUX USART4 TX request */ +#endif /* USART4 */ /** * @} */ @@ -185,6 +199,13 @@ extern "C" { #if defined(DMAMUX1_Channel4) #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ #endif /* DMAMUX1_Channel4 */ +#if defined(DMAMUX1_Channel5) +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#endif /* DMAMUX1_Channel5 */ +#if defined(DMAMUX1_Channel6) +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#endif /* DMAMUX1_Channel6 */ + /** * @} */ @@ -334,7 +355,7 @@ extern "C" { */ /** * @brief Set DMAMUX request ID for DMAMUX Channel x. - * @note DMAMUX channel 0 to 4 are mapped to DMA1 channel 1 to 5. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -343,6 +364,8 @@ extern "C" { * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @param Request This parameter can be one of the following values: * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 @@ -386,6 +409,10 @@ extern "C" { * @arg @ref LL_DMAMUX_REQ_USART1_TX * @arg @ref LL_DMAMUX_REQ_USART2_RX * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART3_TX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_TX (*) * @note (*) Availability depends on devices * @retval None */ @@ -397,7 +424,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUX /** * @brief Get DMAMUX request ID for DMAMUX Channel x. - * @note DMAMUX channel 0 to 4 are mapped to DMA1 channel 1 to 5. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -406,6 +433,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @retval Returned value can be one of the following values: * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 @@ -449,6 +478,10 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_USART1_TX * @arg @ref LL_DMAMUX_REQ_USART2_RX * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART3_TX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_TX (*) * @note (*) Availability depends on devices */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -468,6 +501,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None @@ -490,6 +525,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval Between Min_Data = 1 and Max_Data = 32 */ @@ -509,6 +546,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @param Polarity This parameter can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_NO_EVENT @@ -534,6 +573,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval Returned value can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_NO_EVENT @@ -557,6 +598,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval None */ @@ -576,6 +619,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDe * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval None */ @@ -595,6 +640,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ @@ -614,6 +661,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval None */ @@ -633,6 +682,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval None */ @@ -652,6 +703,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ @@ -671,6 +724,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @param SyncID This parameter can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 @@ -712,6 +767,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @retval Returned value can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 @@ -1224,6 +1281,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval None */ @@ -1243,6 +1302,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval None */ @@ -1262,6 +1323,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_CHANNEL_2 * @arg @ref LL_DMAMUX_CHANNEL_3 (*) * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h index 0680eead70..24550fcedb 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h @@ -495,6 +495,26 @@ typedef struct * @} */ #endif /* USB_DRD_FS */ + +#if defined(FDCAN1) +/** @defgroup RCC_LL_EC_FDCAN1_CLKSOURCE Peripheral FDCAN1 clock source selection + * @{ + */ +#define LL_RCC_FDCAN1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FDCAN1 clock source */ +#define LL_RCC_FDCAN1_CLKSOURCE_HSIKER RCC_CCIPR_FDCAN1SEL_0 /*!< HSIKER clock used as FDCAN1 clock source */ +#define LL_RCC_FDCAN1_CLKSOURCE_HSE RCC_CCIPR_FDCAN1SEL_1 /*!< HSE clock used as FDCAN1 clock source */ +/** @defgroup RCC_LL_EC_FDCAN1 Peripheral FDCAN1 get clock source + * @{ + */ +#define LL_RCC_FDCAN1_CLKSOURCE RCC_CCIPR_FDCAN1SEL /*!< FDCAN1 Clock source selection */ +/** + * @} + */ + +/** + * @} + */ +#endif /* FDCAN1 */ /** * @} */ @@ -1468,6 +1488,22 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) } #endif /* USB_DRD_FS */ +#if defined(FDCAN1) +/** + * @brief Configure FDCANx clock source + * @rmtoll CCIPR FDCAN1SEL LL_RCC_SetFDCANClockSource + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_HSIKER + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCAN1SEL, FDCANxSource); +} +#endif /* FDCAN1 */ + /** * @brief Get USARTx clock source * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource @@ -1543,6 +1579,22 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) } #endif /* USB_DRD_FS */ +#if defined(FDCAN1) +/** + * @brief Get FDCANx clock source + * @rmtoll CCIPR FDCAN LL_RCC_GetFDCANClockSource + * @param FDCANx This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_HSIKER + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx)); +} +#endif /* FDCAN1 */ /** * @} */ @@ -2055,6 +2107,9 @@ uint32_t LL_RCC_GetRTCClockFreq(void); #if defined(USB_DRD_FS) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); #endif /* USB_DRD_FS */ +#if defined(FDCAN1) +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +#endif /* FDCAN1 */ /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_spi.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_spi.h index 925e0fb071..5313c814ed 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_spi.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_spi.h @@ -1045,7 +1045,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1061,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -2010,7 +2010,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -2023,7 +2023,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) { LL_SPI_ClearFlag_FRE(SPIx); } diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h index 79154cf1ea..92b18f9388 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h @@ -261,6 +261,73 @@ extern "C" { SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB8 */ #define LL_PINMUX_TSSOP20_PIN1_PB7 LL_PINMUX_WLCSP19_PINB3_PB7 #define LL_PINMUX_TSSOP20_PIN1_PB8 LL_PINMUX_WLCSP19_PINB3_PB8 + +#elif (DEV_ID == 0x44CUL) +#define LL_PINMUX_WLCSP15_PINH3_PF2 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PF2 */ +#define LL_PINMUX_WLCSP15_PINH3_PA0 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PA0 */ +#define LL_PINMUX_WLCSP15_PING2_PA1 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA1 */ +#define LL_PINMUX_WLCSP15_PING2_PA2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA2 */ +#define LL_PINMUX_WLCSP15_PINK3_PA3 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA3 */ +#define LL_PINMUX_WLCSP15_PINK3_PA4 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA4 */ +#define LL_PINMUX_WLCSP15_PINJ2_PA5 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA5 */ +#define LL_PINMUX_WLCSP15_PINJ2_PA6 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA6 */ +#define LL_PINMUX_WLCSP15_PINH1_PA7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA7 */ +#define LL_PINMUX_WLCSP15_PINH1_PA12 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA12 */ +#define LL_PINMUX_WLCSP15_PINE2_PA14 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA14 */ +#define LL_PINMUX_WLCSP15_PINE2_PA15 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX5_0) /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA15 */ +#define LL_PINMUX_WLCSP15_PINB1_PA3 (((SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA3 */ +#define LL_PINMUX_WLCSP15_PINB1_PA4 (((SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX6_0) /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA4 */ +#define LL_PINMUX_WLCSP15_PINB1_PA5 (((SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX6_1) /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA5 */ +#define LL_PINMUX_WLCSP15_PINB1_PA6 (((SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX6_1 | SYSCFG_CFGR3_PINMUX6_0) /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA6 */ +#define LL_PINMUX_TSSOP20_PIN20_PA3 LL_PINMUX_WLCSP15_PINB1_PA3 +#define LL_PINMUX_TSSOP20_PIN20_PA4 LL_PINMUX_WLCSP15_PINB1_PA4 +#define LL_PINMUX_TSSOP20_PIN20_PA5 LL_PINMUX_WLCSP15_PINB1_PA5 +#define LL_PINMUX_TSSOP20_PIN20_PA6 LL_PINMUX_WLCSP15_PINB1_PA6 +#define LL_PINMUX_WLCSP15_PINA2_PB7 (((SYSCFG_CFGR3_PINMUX7_0 | SYSCFG_CFGR3_PINMUX7_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB7 */ +#define LL_PINMUX_WLCSP15_PINA2_PB8 (((SYSCFG_CFGR3_PINMUX7_0 | SYSCFG_CFGR3_PINMUX7_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX7_0) /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB8 */ +#define LL_PINMUX_TSSOP20_PIN1_PB7 LL_PINMUX_WLCSP15_PINB1_PB7 +#define LL_PINMUX_TSSOP20_PIN1_PB8 LL_PINMUX_WLCSP15_PINB1_PB8 + +#elif (DEV_ID == 0x44DUL) +#define LL_PINMUX_TSSOP20_PIN19_PA14 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA14 */ +#define LL_PINMUX_TSSOP20_PIN19_PA15 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA15 */ +#define LL_PINMUX_TSSOP20_PIN15_PA8 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PA8 */ +#define LL_PINMUX_TSSOP20_PIN15_PB0 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB0 */ +#define LL_PINMUX_TSSOP20_PIN15_PB1 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB1 */ +#define LL_PINMUX_TSSOP20_PIN15_PB2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1)) /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB2 */ +#define LL_PINMUX_WLCSP24_PING1_PA8 LL_PINMUX_TSSOP20_PIN15_PA8 +#define LL_PINMUX_WLCSP24_PING1_PB2 LL_PINMUX_TSSOP20_PIN15_PB0 +#define LL_PINMUX_TSSOP20_PIN20_PB6 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB6 */ +#define LL_PINMUX_TSSOP20_PIN20_PB3 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB3 */ +#define LL_PINMUX_TSSOP20_PIN20_PB4 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB4 */ +#define LL_PINMUX_TSSOP20_PIN20_PB5 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB5 */ +#define LL_PINMUX_WLCSP24_PINA5_PB6 LL_PINMUX_TSSOP20_PIN20_PB6 +#define LL_PINMUX_WLCSP24_PINA5_PB4 LL_PINMUX_TSSOP20_PIN20_PB3 +#define LL_PINMUX_WLCSP24_PINA3_PB5 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB5 */ +#define LL_PINMUX_WLCSP24_PINA3_PB3 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB3 */ +#define LL_PINMUX_WLCSP24_PINB4_PB7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB7 */ +#define LL_PINMUX_WLCSP24_PINB4_PB8 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB8 */ +#define LL_PINMUX_TSSOP20_PIN1_PB7 LL_PINMUX_WLCSP24_PINB4_PB7 +#define LL_PINMUX_TSSOP20_PIN1_PB8 LL_PINMUX_WLCSP24_PINB4_PB8 #endif /* DEV_ID == 0x443UL */ /** * @} @@ -290,6 +357,26 @@ extern "C" { #define LL_PINMUX_TSSOP20_PIN20 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C071 TSSOP20 package, GPIO Pin20 multiplexer */ #define LL_PINMUX_WLCSP19_PINB3 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C071 WLCSP19 package, GPIO PinB3 multiplexer */ #define LL_PINMUX_TSSOP20_PIN1 LL_PINMUX_WLCSP19_PINB3 /*!< STM32C071 TSSOP20 package, GPIO Pin1 multiplexer */ +#elif (DEV_ID == 0x44CUL) +#define LL_PINMUX_WLCSP15_PINH3 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C051 WLCSP15 package, GPIO PinH3 multiplexer */ +#define LL_PINMUX_WLCSP15_PING2 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C051 WLCSP15 package, GPIO PinG2 multiplexer */ +#define LL_PINMUX_WLCSP15_PINK3 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C051 WLCSP15 package, GPIO PinK3 multiplexer */ +#define LL_PINMUX_WLCSP15_PINJ2 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C051 WLCSP15 package, GPIO PinJ2 multiplexer */ +#define LL_PINMUX_WLCSP15_PINH1 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C051 WLCSP15 package, GPIO PinH1 multiplexer */ +#define LL_PINMUX_WLCSP15_PINE2 (SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C051 WLCSP15 package, GPIO PinE2 multiplexer */ +#define LL_PINMUX_WLCSP15_PINB1 (SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) /*!< STM32C051 WLCSP15 package, GPIO PinB1 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN20 LL_PINMUX_WLCSP15_PINB1 +#define LL_PINMUX_WLCSP15_PINA2 (SYSCFG_CFGR3_PINMUX7_0 | SYSCFG_CFGR3_PINMUX7_1) /*!< STM32C051 WLCSP15 package, GPIO PinA2 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN1 LL_PINMUX_WLCSP15_PINB1 +#elif (DEV_ID == 0x44DUL) +#define LL_PINMUX_TSSOP20_PIN19 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C091/92 TSSOP20 package, GPIO Pin19 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN15 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C091/92 TSSOP20 package, GPIO Pin15 multiplexer */ +#define LL_PINMUX_WLCSP24_PING1 LL_PINMUX_TSSOP20_PIN15 +#define LL_PINMUX_TSSOP20_PIN20 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C091/92 TSSOP20 package, GPIO Pin20 multiplexer */ +#define LL_PINMUX_WLCSP24_PINA5 LL_PINMUX_TSSOP20_PIN20 +#define LL_PINMUX_WLCSP24_PINA3 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C091/92 WLCSP24 package, GPIO PinA3 multiplexer */ +#define LL_PINMUX_WLCSP24_PINB4 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C091/92 WLCSP24 package, GPIO PinB4 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN1 LL_PINMUX_WLCSP24_PINB4 #endif /* DEV_ID == 0x443UL */ /** * @} @@ -870,6 +957,30 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) } #endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +/** + * @brief Check if DMA1_CH6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +/** + * @brief Check if DMA1_CH7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ + #if defined(SYSCFG_ITLINE12_SR_ADC) /** * @brief Check if ADC interrupt occurred or not. @@ -979,6 +1090,19 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) } #endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ +#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) +/** + * @brief Check if Timer 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == \ + (SYSCFG_ITLINE20_SR_TIM15_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ + #if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) /** * @brief Check if Timer 16 interrupt occurred or not. @@ -1079,6 +1203,58 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) } #endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ +#if defined(SYSCFG_ITLINE29_SR_USART3_GLB) +/** + * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == \ + (SYSCFG_ITLINE29_SR_USART3_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART4_GLB) +/** + * @brief Check if USART4 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == \ + (SYSCFG_ITLINE29_SR_USART4_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ + +#if defined(SYSCFG_ITLINE30_SR_FDCAN1_IT0) +/** + * @brief Check if FDCAN1_IT0 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE30 SR_FDCAN1_IT0 LL_SYSCFG_IsActiveFlag_FDCAN1_IT0 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT0(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_FDCAN1_IT0) == \ + (SYSCFG_ITLINE30_SR_FDCAN1_IT0)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE30_SR_FDCAN1_IT0 */ + +#if defined(SYSCFG_ITLINE31_SR_FDCAN1_IT1) +/** + * @brief Check if FDCAN1_IT1 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE31 SR_FDCAN1_IT1 LL_SYSCFG_IsActiveFlag_FDCAN1_IT1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT1(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_FDCAN1_IT1) == \ + (SYSCFG_ITLINE31_SR_FDCAN1_IT1)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE31_SR_FDCAN1_IT1 */ + /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h index dcfd894e5c..ed61e872d8 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM16) || defined (TIM17) +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) /** @defgroup TIM_LL TIM * @{ @@ -929,6 +929,9 @@ typedef struct #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ +#if defined(USB_BASE) +#define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */ +#endif /* USB_BASE */ #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ @@ -1193,8 +1196,32 @@ typedef struct #define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U /*!< TIM14 input 1 is connected to GPIO */ #define LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0 /*!< TIM14 input 1 is connected to RTC clock */ #define LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM14 input 1 is connected to HSE/32 clock */ -#define LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM14 input 1 is connected to MCO */ -#define LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM14 input 1 is connected to MCO2 */ +#define LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM14 input 1 is connected to MCO */ +#define LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM14 input 1 is connected to MCO2 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap + * @{ + */ +#if defined(TIM15) +#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */ +#define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 input 1 */ +#define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 input 1 */ +#endif /* TIM15 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap + * @{ + */ +#if defined(TIM15) +#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */ +#define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to TIM2 input 2 */ +#define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 2 is connected to TIM3 input 2 */ +#endif /* TIM15 */ /** * @} */ @@ -1202,10 +1229,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */ -#define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to LSI */ -#define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to LSE */ -#define LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to MCO2 */ +#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */ +#define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to LSI */ +#define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to LSE */ +#define LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to MCO2 */ /** * @} */ @@ -1213,10 +1240,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */ -#define LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to HSE/32 clock */ -#define LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to MCO */ -#define LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to MCO2 */ +#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */ +#define LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to HSE/32 clock */ +#define LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to MCO */ +#define LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to MCO2 */ /** * @} */ @@ -3272,7 +3299,7 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) * @param TIMx Timer instance * @param TriggerInput This parameter can be one of the following values: * @arg @ref LL_TIM_TS_ITR0 - * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR1 (*) * @arg @ref LL_TIM_TS_ITR2 * @arg @ref LL_TIM_TS_ITR3 * @arg @ref LL_TIM_TS_ITR7 (*) @@ -3839,6 +3866,8 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n * TIM3_TISEL TI4SEL LL_TIM_SetRemap\n * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n * TIM17_TISEL TI1SEL LL_TIM_SetRemap * @param TIMx Timer instance @@ -3856,6 +3885,15 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO2 * + * TIM15: one of the following values (*) + * + * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_IC1 + * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_IC1 + * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO + * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_IC2 + * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_IC2 + * * TIM16: one of the following values * * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO @@ -3869,6 +3907,9 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO2 + * + * (*) Timer instance not available on all devices \n + * * @retval None */ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) @@ -4911,7 +4952,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM16 || TIM17 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 */ /** * @} diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usart.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usart.h index 181e49a86d..203797335f 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usart.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usart.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined(USART1) || defined(USART2) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART4) /** @defgroup USART_LL USART * @{ @@ -4385,7 +4385,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS * @} */ -#endif /* USART1 || USART2 */ +#endif /* USART1 || USART2 || USART3 || USART4 */ /** * @} diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_utils.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_utils.h index 05059bac9d..9e42bea107 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_utils.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_utils.h @@ -117,6 +117,19 @@ extern "C" { #define LL_UTILS_PACKAGETYPE_LQFP64_N 0x0008U /*!< UFQFPN64 / LQFP64 general purpose (N) package type */ #define LL_UTILS_PACKAGETYPE_UFBGA64_GP 0x000DU /*!< UFBGA64 (GP) package type */ #define LL_UTILS_PACKAGETYPE_UFBGA64_N 0x000EU /*!< UFBGA64 (N) package type */ +#elif defined(STM32C051xx) +#define LL_UTILS_PACKAGETYPE_WLCSP15 0x0001U /*!< WLCSP15 package type */ +#define LL_UTILS_PACKAGETYPE_TSSOP20 0x0002U /*!< TSSOP20 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN28 0x0003U /*!< UFQFPN28 package type */ +#define LL_UTILS_PACKAGETYPE_QFN32 0x0004U /*!< UFQFPN32 / LQFP32 package type */ +#define LL_UTILS_PACKAGETYPE_QFN48 0x0005U /*!< UFQFPN48 / LQFP48 package type */ +#elif defined(STM32C091xx) || defined(STM32C092xx) +#define LL_UTILS_PACKAGETYPE_TSSOP20 0x0001U /*!< TSSOP20 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP24 0x0002U /*!< WLCSP24 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN28 0x0003U /*!< UFQFPN28 package type */ +#define LL_UTILS_PACKAGETYPE_QFN32 0x0004U /*!< UFQFPN32 / LQFP32 package type */ +#define LL_UTILS_PACKAGETYPE_QFN48 0x0005U /*!< UFQFPN48 / LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_QFN64 0x0006U /*!< UFQFPN64 / LQFP64 package type */ #endif /* STM32C0xx */ /** * @} @@ -187,6 +200,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @arg @ref LL_UTILS_PACKAGETYPE_QFN48 (*) * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP19 (*) * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP15 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP24 (*) * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*) * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*) * diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html index b1e3e93cf0..4a584c4099 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html @@ -70,13 +70,14 @@

        Purpose

        Update History

        - +

        Main Changes

        • Official Release of STM32CubeC0 Firmware package supporting -STM32C071xx devices
          • +STM32C051xx and STM32C091/92xx +devices
        • General updates to fix known defects and implementation enhancements
        @@ -84,6 +85,88 @@

        HAL Drivers updates

        • HAL generic driver:
            +
          • Update HAL configuration template file
            • +
          • +
        • HAL ADC driver: +
            +
          • Add missing callbacks in ADC_HandleTypeDef
            • +
          • Rework of const qualifier to be compliant with MISRA rule 8.13
            • +
          • +
        • HAL DMA driver: +
            +
          • Rework of const qualifier to be compliant with MISRA rule 8.13
            • +
          • +
        • HAL FLASH driver: +
            +
          • Fix inverted OB_IRH_ENABLE and OB_IRH_DISABLE definitions
            • +
          • +
        • HAL I2C driver: +
            +
          • Update function HAL_I2C_IsDeviceReady() to take into account the +number of trials
            • +
          • Move the prefetch process in function HAL_I2C_Slave_Transmit
            • +
          • +
        • HAL PCD driver: +
            +
          • Support bulk transfer in double buffer mode
            • +
          • +
        • HAL RCC driver: +
            +
          • Update function HAL_RCC_GetClockConfig() to take into account the +RCC_CR_SYSDIV
            • +
          • +
        • HAL SPI driver: +
            +
          • Rework of const qualifier to be compliant with MISRA rule 8.13
            • +
          • +
        • HAL UART driver: +
            +
          • Correct DMA Rx abort procedure impact on ongoing Tx transfer in +polling mode
            • +
          • +
        +

        LL Drivers updates

        +
          +
        • LL ADC driver: +
            +
          • Rework of const qualifier to be compliant with MISRA rule 8.13
            • +
          • +
        • LL DMA driver: +
            +
          • Rework of const qualifier to be compliant with MISRA rule 8.13
            • +
          • +
        • LL USB driver: +
            +
          • Support bulk transfer in double buffer mode
            • +
          • +
        +

        Note: HAL/LL Backward compatibility ensured by legacy defines.

        +

        Known Limitations

        +
          +
        • None
          • +
        +

        Backward Compatibility

        +
          +
        • Not applicable
          • +
        +
        +
        +
        + + +
        +

        Main Changes

        +
          +
        • Official Release of STM32CubeC0 Firmware package supporting +STM32C071xx devices
          • +
        • General updates to fix known defects and implementation +enhancements
          • +
        +

        HAL Drivers updates

        +
          +
        • HAL generic driver: +
          • Remove invalid HAL_SYSCFG_EnableIOAnalogSwitchBooster() and HAL_SYSCFG_DisableIOAnalogSwitchBooster() APIs
          • Rename __HAL_RCC_APB1_FORCE_RESET and __HAL_RCC_APB2_FORCE_RESET @@ -199,7 +282,7 @@

            HAL Drivers updates

            FIFO reception in Interrupt mode
        -

        LL Drivers updates

        +

        LL Drivers updates

        • LL ADC driver:
            @@ -253,11 +336,11 @@

            LL Drivers updates

        Note: HAL/LL Backward compatibility ensured by legacy defines.

        -

        Known Limitations

        +

        Known Limitations

        • None
        -

        Backward Compatibility

        +

        Backward Compatibility

        • Not applicable
        @@ -268,7 +351,7 @@

        Backward Compatibility

        -

        Main Changes

        +

        Main Changes

        • Maintenance Release of STM32CubeC0 Firmware Package
        @@ -339,9 +422,9 @@

        Main Changes

        setting.
    -

    Known Limitations

    +

    Known Limitations

    N/A

    -

    Backward Compatibility

    +

    Backward Compatibility

    • HAL_SYSCFG_GetPinBinding() and LL_SYSCFG_GetConfigPinMux() are updated.
      • @@ -353,7 +436,7 @@

      Backward Compatibility

      -

      Main Changes

      +

      Main Changes

      • Patch Release of STM32CubeC0 Firmware Package

      • Update ADC HAL driver with proper internal sensor calibration @@ -364,7 +447,7 @@

        Main Changes

    • Update RCC LL driver by adding missing AHB Prescaler.

    -

    Known Limitations

    +

    Known Limitations

    N/A

    @@ -373,10 +456,10 @@

    Known Limitations

    -

    Main Changes

    +

    Main Changes

    First official release of HAL and LL drivers for STM32C031xx / STM32C011xx devices

    -

    Known Limitations

    +

    Known Limitations

    N/A

diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c index d25d2e4188..3cebb01c83 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c @@ -56,7 +56,7 @@ * @brief STM32C0xx HAL Driver version number */ #define __STM32C0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32C0xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32C0xx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32C0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32C0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32C0xx_HAL_VERSION ((__STM32C0xx_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c index 07aa283d1b..ab613f037a 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c @@ -1862,7 +1862,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2255,7 +2255,7 @@ __weak void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc) * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_config_internal_channel; @@ -2455,7 +2455,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpAWDHighThresholdShifted; @@ -2698,7 +2698,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2712,7 +2712,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c index 018a4072ef..dfb24ae5a3 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c @@ -247,7 +247,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) * @param hadc ADC handle. * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c index f8de58f91c..ee16e9028e 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c @@ -395,7 +395,7 @@ void HAL_MPU_DisableRegion(uint32_t RegionNumber) * the initialization and configuration information. * @retval None */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c index 28f8869674..5f67417d20 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c @@ -943,7 +943,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * the configuration information for the specified DMA Channel. * @retval HAL state */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) { /* Return DMA handle state */ return hdma->State; @@ -955,7 +955,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_fdcan.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_fdcan.c new file mode 100644 index 0000000000..ecefef95da --- /dev/null +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_fdcan.c @@ -0,0 +1,3526 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_fdcan.c + * @author MCD Application Team + * @brief FDCAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Flexible DataRate Controller Area Network + * (FDCAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Configuration and Control functions + * + Peripheral State and Error functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function. + + (#) If needed , configure the reception filters and optional features using + the following configuration functions: + (++) HAL_FDCAN_ConfigFilter + (++) HAL_FDCAN_ConfigGlobalFilter + (++) HAL_FDCAN_ConfigExtendedIdMask + (++) HAL_FDCAN_ConfigRxFifoOverwrite + (++) HAL_FDCAN_ConfigRamWatchdog + (++) HAL_FDCAN_ConfigTimestampCounter + (++) HAL_FDCAN_EnableTimestampCounter + (++) HAL_FDCAN_DisableTimestampCounter + (++) HAL_FDCAN_ConfigTimeoutCounter + (++) HAL_FDCAN_EnableTimeoutCounter + (++) HAL_FDCAN_DisableTimeoutCounter + (++) HAL_FDCAN_ConfigTxDelayCompensation + (++) HAL_FDCAN_EnableTxDelayCompensation + (++) HAL_FDCAN_DisableTxDelayCompensation + (++) HAL_FDCAN_EnableISOMode + (++) HAL_FDCAN_DisableISOMode + (++) HAL_FDCAN_EnableEdgeFiltering + (++) HAL_FDCAN_DisableEdgeFiltering + + (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level + the node is active on the bus: it can send and receive messages. + + (#) The following Tx control functions can only be called when the FDCAN + module is started: + (++) HAL_FDCAN_AddMessageToTxFifoQ + (++) HAL_FDCAN_AbortTxRequest + + (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to + get Tx buffer location used to place the Tx request thanks to + HAL_FDCAN_GetLatestTxFifoQRequestBuffer API. + It is then possible to abort later on the corresponding Tx Request using + HAL_FDCAN_AbortTxRequest API. + + (#) When a message is received into the FDCAN message RAM, it can be + retrieved using the HAL_FDCAN_GetRxMessage function. + + (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering + it to initialization mode and re-enabling access to configuration + registers through the configuration functions listed here above. + + (#) All other control functions can be called any time after initialization + phase, no matter if the FDCAN module is started or stopped. + + *** Polling mode operation *** + ============================== + [..] + (#) Reception and transmission states can be monitored via the following + functions: + (++) HAL_FDCAN_IsTxBufferMessagePending + (++) HAL_FDCAN_GetRxFifoFillLevel + (++) HAL_FDCAN_GetTxFifoFreeLevel + + *** Interrupt mode operation *** + ================================ + [..] + (#) There are two interrupt lines: line 0 and 1. + By default, all interrupts are assigned to line 0. Interrupt lines + can be configured using HAL_FDCAN_ConfigInterruptLines function. + + (#) Notifications are activated using HAL_FDCAN_ActivateNotification + function. Then, the process can be controlled through one of the + available user callbacks: HAL_FDCAN_xxxCallback. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() + to register an interrupt callback. + + Function HAL_FDCAN_RegisterCallback() allows to register following callbacks: + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) HighPriorityMessageCallback : High Priority Message Callback. + (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. + (+) TimeoutOccurredCallback : Timeout Occurred Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : FDCAN MspInit. + (+) MspDeInitCallback : FDCAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, + TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated + register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(), + HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), + HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback() + and HAL_FDCAN_RegisterErrorStatusCallback(). + + Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) HighPriorityMessageCallback : High Priority Message Callback. + (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. + (+) TimeoutOccurredCallback : Timeout Occurred Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : FDCAN MspInit. + (+) MspDeInitCallback : FDCAN MspDeInit. + + For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, + TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated + unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(), + HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), + HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback() + and HAL_FDCAN_UnRegisterErrorStatusCallback(). + + By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + examples HAL_FDCAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit() + or HAL_FDCAN_Init() function. + + When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +#if defined(FDCAN1) + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup FDCAN FDCAN + * @brief FDCAN HAL module driver + * @{ + */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FDCAN_Private_Constants + * @{ + */ +#define FDCAN_TIMEOUT_VALUE 10U + +#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN) +#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N) +#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N) +#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA) +#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO) + +#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */ +#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */ +#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */ +#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */ +#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */ +#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */ +#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */ +#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */ +#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */ +#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */ +#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */ +#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */ +#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */ +#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */ + +#define SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */ +#define SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */ +#define SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */ +#define SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */ +#define SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */ +#define SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */ + +#define SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */ +#define SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */ +#define SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */ +#define SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */ +#define SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */ +#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */ + +#define SRAMCAN_FLSSA ((uint32_t)0) /* Filter List Standard Start + Address */ +#define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start + Address */ +#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */ +#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */ +#define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start + Address */ +#define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start + Address */ +#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FDCAN_Private_Variables + * @{ + */ +static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FDCAN_Private_Functions_Prototypes + * @{ + */ +static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions + * @{ + */ + +/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the FDCAN. + (+) De-initialize the FDCAN. + (+) Enter FDCAN peripheral in power down mode. + (+) Exit power down mode. + (+) Register callbacks. + (+) Unregister callbacks. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FDCAN peripheral according to the specified + * parameters in the FDCAN_InitTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Check FDCAN handle */ + if (hfdcan == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_CKDIV(hfdcan->Init.ClockDivider)); + assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat)); + assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException)); + assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler)); + assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth)); + assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1)); + assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2)); + if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) + { + assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler)); + assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth)); + assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1)); + assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, SRAMCAN_FLS_NBR)); + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, SRAMCAN_FLE_NBR)); + assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode)); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Reset callbacks to legacy functions */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */ + + if (hfdcan->MspInitCallback == NULL) + { + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hfdcan->MspInitCallback(hfdcan); + } +#else + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Init the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspInit(hfdcan); + } +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Exit from Sleep mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode acknowledge */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Request initialisation */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the INIT bit into CCCR register is set */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enable configuration change */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); + + /* Configure Clock divider */ + FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider; + + /* Set the no automatic retransmission */ + if (hfdcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); + } + else + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); + } + + /* Set the transmit pause feature */ + if (hfdcan->Init.TransmitPause == ENABLE) + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); + } + else + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); + } + + /* Set the Protocol Exception Handling */ + if (hfdcan->Init.ProtocolException == ENABLE) + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); + } + else + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); + } + + /* Set FDCAN Frame Format */ + MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat); + + /* Reset FDCAN Operation Mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM)); + CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); + + /* Set FDCAN Operating Mode: + | Normal | Restricted | Bus | Internal | External + | | Operation | Monitoring | LoopBack | LoopBack + CCCR.TEST | 0 | 0 | 0 | 1 | 1 + CCCR.MON | 0 | 0 | 1 | 1 | 0 + TEST.LBCK | 0 | 0 | 0 | 1 | 1 + CCCR.ASM | 0 | 1 | 0 | 0 | 0 + */ + if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) + { + /* Enable Restricted Operation mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); + } + else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) + { + if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) + { + /* Enable write access to TEST register */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST); + + /* Enable LoopBack mode */ + SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); + + if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); + } + } + else + { + /* Enable bus monitoring mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); + } + } + else + { + /* Nothing to do: normal mode */ + } + + /* Set the nominal bit timing register */ + hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ + (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ + (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ + (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos)); + + /* If FD operation with BRS is selected, set the data bit timing register */ + if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) + { + hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ + (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ + (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ + (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos)); + } + + /* Select between Tx FIFO and Tx Queue operation modes */ + SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode); + + /* Calculate each RAM block address */ + FDCAN_CalcultateRamBlockAddresses(hfdcan); + + /* Initialize the Latest Tx request buffer index */ + hfdcan->LatestTxFifoQRequest = 0U; + + /* Initialize the error code */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Initialize the FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the FDCAN peripheral registers to their default reset values. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Check FDCAN handle */ + if (hfdcan == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + /* Stop the FDCAN module: return value is voluntary ignored */ + (void)HAL_FDCAN_Stop(hfdcan); + + /* Disable Interrupt lines */ + CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1)); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->MspDeInitCallback == NULL) + { + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hfdcan->MspDeInitCallback(hfdcan); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspDeInit(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the FDCAN MSP. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the FDCAN MSP. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Enter FDCAN peripheral in sleep mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Request clock stop */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FDCAN is ready for power down */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Exit power down mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Reset clock stop request */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FDCAN exits sleep mode */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enter normal operation */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Return function status */ + return HAL_OK; +} + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a FDCAN CallBack. + * To be used instead of the weak predefined callback + * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains + * the configuration information for FDCAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID + * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID + * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID + * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID + * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : + hfdcan->TxFifoEmptyCallback = pCallback; + break; + + case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : + hfdcan->HighPriorityMessageCallback = pCallback; + break; + + case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : + hfdcan->TimestampWraparoundCallback = pCallback; + break; + + case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : + hfdcan->TimeoutOccurredCallback = pCallback; + break; + + case HAL_FDCAN_ERROR_CALLBACK_CB_ID : + hfdcan->ErrorCallback = pCallback; + break; + + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = pCallback; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = pCallback; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a FDCAN CallBack. + * FDCAN callback is redirected to the weak predefined callback + * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains + * the configuration information for FDCAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID + * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID + * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID + * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID + * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; + break; + + case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; + break; + + case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; + break; + + case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; + break; + + case HAL_FDCAN_ERROR_CALLBACK_CB_ID : + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; + break; + + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Event Fifo FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Event Fifo Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxEventFifoCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxEventFifoCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Event Fifo FDCAN Callback + * Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Rx Fifo 0 FDCAN Callback + * To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Rx Fifo 0 Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo0CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo0Callback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Rx Fifo 0 FDCAN Callback + * Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Rx Fifo 1 FDCAN Callback + * To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Rx Fifo 1 Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo1CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo1Callback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Rx Fifo 1 FDCAN Callback + * Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Buffer Complete FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Buffer Complete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferCompleteCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferCompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Buffer Complete FDCAN Callback + * Tx Buffer Complete FDCAN Callback is redirected to + * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Buffer Abort FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Buffer Abort Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferAbortCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferAbortCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Buffer Abort FDCAN Callback + * Tx Buffer Abort FDCAN Callback is redirected to + * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Error Status FDCAN Callback + * To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Error Status Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ErrorStatusCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ErrorStatusCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Error Status FDCAN Callback + * Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions + * @brief FDCAN Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN reception filters + (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global filter + (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID mask + (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode + (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog + (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp counter + (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp counter + (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp counter + (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter value + (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp counter to zero + (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout counter + (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter + (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout counter + (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter value + (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter to its start value + (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation + (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter delay compensation + (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter delay compensation + (+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol mode + (+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol mode + (+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during bus integration + (+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering during bus integration + +@endverbatim + * @{ + */ + +/** + * @brief Configure the FDCAN reception filter according to the specified + * parameters in the FDCAN_FilterTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that + * contains the filter configuration information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig) +{ + uint32_t FilterElementW1; + uint32_t FilterElementW2; + uint32_t *FilterAddress; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType)); + assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig)); + + if (sFilterConfig->IdType == FDCAN_STANDARD_ID) + { + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); + assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); + + /* Build filter element */ + FilterElementW1 = ((sFilterConfig->FilterType << 30U) | + (sFilterConfig->FilterConfig << 27U) | + (sFilterConfig->FilterID1 << 16U) | + sFilterConfig->FilterID2); + + /* Calculate filter address */ + FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE)); + + /* Write filter element to the message RAM */ + *FilterAddress = FilterElementW1; + } + else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ + { + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); + assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); + + /* Build first word of filter element */ + FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1); + + /* Build second word of filter element */ + FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2); + + /* Calculate filter address */ + FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE)); + + /* Write filter element to the message RAM */ + *FilterAddress = FilterElementW1; + FilterAddress++; + *FilterAddress = FilterElementW2; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the FDCAN global filter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param NonMatchingStd Defines how received messages with 11-bit IDs that + * do not match any element of the filter list are treated. + * This parameter can be a value of @arg FDCAN_Non_Matching_Frames. + * @param NonMatchingExt Defines how received messages with 29-bit IDs that + * do not match any element of the filter list are treated. + * This parameter can be a value of @arg FDCAN_Non_Matching_Frames. + * @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames. + * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames. + * @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames. + * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, + uint32_t NonMatchingStd, + uint32_t NonMatchingExt, + uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd)); + assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt)); + assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd)); + assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure global filter */ + MODIFY_REG(hfdcan->Instance->RXGFC, (FDCAN_RXGFC_ANFS | + FDCAN_RXGFC_ANFE | + FDCAN_RXGFC_RRFS | + FDCAN_RXGFC_RRFE), + ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) | + (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) | + (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) | + (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos))); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the extended ID mask. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param Mask Extended ID Mask. + * This parameter must be a number between 0 and 0x1FFFFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure the extended ID mask */ + hfdcan->Instance->XIDAM = Mask; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the Rx FIFO operation mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg FDCAN_RX_FIFO0: Rx FIFO 0 + * @arg FDCAN_RX_FIFO1: Rx FIFO 1 + * @param OperationMode operation mode. + * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxFifo)); + assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + if (RxFifo == FDCAN_RX_FIFO0) + { + /* Select FIFO 0 Operation Mode */ + MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F0OM, (OperationMode << FDCAN_RXGFC_F0OM_Pos)); + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + /* Select FIFO 1 Operation Mode */ + MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F1OM, (OperationMode << FDCAN_RXGFC_F1OM_Pos)); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the RAM watchdog. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param CounterStartValue Start value of the Message RAM Watchdog Counter, + * This parameter must be a number between 0x00 and 0xFF, + * with the reset value of 0x00 the counter is disabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure the RAM watchdog counter start value */ + MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimestampPrescaler Timestamp Counter Prescaler. + * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure prescaler */ + MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimestampOperation Timestamp counter operation. + * This parameter can be a value of @arg FDCAN_Timestamp. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable timestamp counter */ + MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable timestamp counter */ + CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the timestamp counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Timestamp counter value + */ +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan) +{ + return (uint16_t)(hfdcan->Instance->TSCV); +} + +/** + * @brief Reset the timestamp counter to zero. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL) + { + /* Reset timestamp counter. + Actually any write operation to TSCV clears the counter */ + CLEAR_REG(hfdcan->Instance->TSCV); + } + else + { + /* Update error code. + Unable to reset external counter */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimeoutOperation Timeout counter operation. + * This parameter can be a value of @arg FDCAN_Timeout_Operation. + * @param TimeoutPeriod Start value of the timeout down-counter. + * This parameter must be a number between 0x0000 and 0xFFFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, + uint32_t TimeoutPeriod) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation)); + assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Select timeout operation and configure period */ + MODIFY_REG(hfdcan->Instance->TOCC, + (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos))); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable timeout counter */ + SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable timeout counter */ + CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the timeout counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Timeout counter value + */ +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan) +{ + return (uint16_t)(hfdcan->Instance->TOCV); +} + +/** + * @brief Reset the timeout counter to its start value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS) + { + /* Reset timeout counter to start value */ + CLEAR_REG(hfdcan->Instance->TOCV); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Unable to reset counter: controlled only by FIFO empty state */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TdcOffset Transmitter Delay Compensation Offset. + * This parameter must be a number between 0x00 and 0x7F. + * @param TdcFilter Transmitter Delay Compensation Filter Window Length. + * This parameter must be a number between 0x00 and 0x7F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, + uint32_t TdcFilter) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU)); + assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure TDC offset and filter window */ + hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable transmitter delay compensation */ + SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable transmitter delay compensation */ + CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable ISO 11898-1 protocol mode. + * CAN FD frame format is according to ISO 11898-1 standard. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable Non ISO protocol mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable ISO 11898-1 protocol mode. + * CAN FD frame format is according to Bosch CAN FD specification V1.0. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable Non ISO protocol mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable edge filtering during bus integration. + * Two consecutive dominant tq are required to detect an edge for hard synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable edge filtering */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable edge filtering during bus integration. + * One dominant tq is required to detect an edge for hard synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable edge filtering */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_Start : Start the FDCAN module + (+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers + (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding + transmission request + (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request + (+) HAL_FDCAN_AbortTxRequest : Abort transmission request + (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx FIFO zone into the message RAM + (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone + into the message RAM + (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status + (+) HAL_FDCAN_GetProtocolStatus : Get protocol status + (+) HAL_FDCAN_GetErrorCounters : Get error counter values + (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending + on the selected Tx buffer + (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level + (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level + (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode + (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation Mode + +@endverbatim + * @{ + */ + +/** + * @brief Start the FDCAN module. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Change FDCAN peripheral state */ + hfdcan->State = HAL_FDCAN_STATE_BUSY; + + /* Request leave initialisation */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the FDCAN module and enable access to configuration registers. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Request initialisation */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Wait until the INIT bit into CCCR register is set */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Reset counter */ + Counter = 0U; + + /* Exit from Sleep mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Wait until FDCAN exits sleep mode */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable configuration change */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); + + /* Reset Latest Tx FIFO/Queue Request Buffer Index */ + hfdcan->LatestTxFifoQRequest = 0U; + + /* Change FDCAN peripheral state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData) +{ + uint32_t PutIndex; + + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType)); + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU)); + } + assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType)); + assert_param(IS_FDCAN_DLC(pTxHeader->DataLength)); + assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator)); + assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch)); + assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat)); + assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl)); + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Check that the Tx FIFO/Queue is not full */ + if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL; + + return HAL_ERROR; + } + else + { + /* Retrieve the Tx FIFO PutIndex */ + PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos); + + /* Add the message to the Tx FIFO/Queue */ + FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex); + + /* Activate the corresponding transmission request */ + hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex); + + /* Store the Latest Tx FIFO/Queue Request Buffer Index */ + hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get Tx buffer index of latest Tx FIFO/Queue request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Tx buffer index of last Tx FIFO/Queue request + * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted. + * - 0 if no Tx FIFO/Queue request have been submitted. + */ +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return Last Tx FIFO/Queue Request Buffer */ + return hfdcan->LatestTxFifoQRequest; +} + +/** + * @brief Abort transmission request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndex buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndex)); + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Add cancellation request */ + hfdcan->Instance->TXBCR = BufferIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get an FDCAN frame from the Rx FIFO zone into the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxLocation Location of the received message to be read. + * This parameter can be a value of @arg FDCAN_Rx_location. + * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure. + * @param pRxData pointer to a buffer where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, + FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData) +{ + uint32_t *RxAddress; + uint8_t *pData; + uint32_t ByteCounter; + uint32_t GetIndex = 0; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxLocation)); + + if (state == HAL_FDCAN_STATE_BUSY) + { + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + else + { + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 0 element index */ + GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + + /* Calculate Rx FIFO 0 element address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE)); + } + } + else /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + else + { + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 1 element index */ + GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); + /* Calculate Rx FIFO 1 element address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE)); + } + } + + /* Retrieve IdType */ + pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD; + + /* Retrieve Identifier */ + if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U); + } + else /* Extended ID element */ + { + pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID); + } + + /* Retrieve RxFrameType */ + pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR); + + /* Retrieve ErrorStateIndicator */ + pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI); + + /* Increment RxAddress pointer to second word of Rx FIFO element */ + RxAddress++; + + /* Retrieve RxTimestamp */ + pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS); + + /* Retrieve DataLength */ + pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); + + /* Retrieve BitRateSwitch */ + pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS); + + /* Retrieve FDFormat */ + pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF); + + /* Retrieve FilterIndex */ + pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U); + + /* Retrieve NonMatchingFrame */ + pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U); + + /* Increment RxAddress pointer to payload of Rx FIFO element */ + RxAddress++; + + /* Retrieve Rx payload */ + pData = (uint8_t *)RxAddress; + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++) + { + pRxData[ByteCounter] = pData[ByteCounter]; + } + + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->RXF0A = GetIndex; + } + else /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->RXF1A = GetIndex; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent) +{ + uint32_t *TxEventAddress; + uint32_t GetIndex; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if (state == HAL_FDCAN_STATE_BUSY) + { + /* Check that the Tx event FIFO is not empty */ + if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + + /* Calculate Tx event FIFO element address */ + GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos); + TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * SRAMCAN_TEF_SIZE)); + + /* Retrieve IdType */ + pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD; + + /* Retrieve Identifier */ + if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U); + } + else /* Extended ID element */ + { + pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID); + } + + /* Retrieve TxFrameType */ + pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR); + + /* Retrieve ErrorStateIndicator */ + pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI); + + /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */ + TxEventAddress++; + + /* Retrieve TxTimestamp */ + pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS); + + /* Retrieve DataLength */ + pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); + + /* Retrieve BitRateSwitch */ + pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS); + + /* Retrieve FDFormat */ + pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF); + + /* Retrieve EventType */ + pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET); + + /* Retrieve MessageMarker */ + pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U); + + /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->TXEFA = GetIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get high priority message status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_HpMsgStatusTypeDef *HpMsgStatus) +{ + HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos); + HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos); + HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI); + HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get protocol status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus) +{ + uint32_t StatusReg; + + /* Read the protocol status register */ + StatusReg = READ_REG(hfdcan->Instance->PSR); + + /* Fill the protocol status structure */ + ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC); + ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos); + ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT); + ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos); + ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos); + ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos); + ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos); + ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos); + ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos); + ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos); + ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get error counter values. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters) +{ + uint32_t CountersReg; + + /* Read the error counters register */ + CountersReg = READ_REG(hfdcan->Instance->ECR); + + /* Fill the error counters structure */ + ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos); + ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos); + ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos); + ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx buffer. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TxBufferIndex Tx buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval Status + * - 0 : No pending transmission request on TxBufferIndex list. + * - 1 : Pending transmission request on TxBufferIndex. + */ +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex)); + + /* Check pending transmission request on the selected buffer */ + if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U) + { + return 0; + } + return 1; +} + +/** + * @brief Return Rx FIFO fill level. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg FDCAN_RX_FIFO0: Rx FIFO 0 + * @arg FDCAN_RX_FIFO1: Rx FIFO 1 + * @retval Rx FIFO fill level. + */ +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) +{ + uint32_t FillLevel; + + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxFifo)); + + if (RxFifo == FDCAN_RX_FIFO0) + { + FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL; + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL; + } + + /* Return Rx FIFO fill level */ + return FillLevel; +} + +/** + * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO + * elements starting from Tx FIFO GetIndex. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Tx FIFO free level. + */ +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t FreeLevel; + + FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL; + + /* Return Tx FIFO free level */ + return FreeLevel; +} + +/** + * @brief Check if the FDCAN peripheral entered Restricted Operation Mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Status + * - 0 : Normal FDCAN operation. + * - 1 : Restricted Operation Mode active. + */ +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t OperationMode; + + /* Get Operation Mode */ + OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos); + + return OperationMode; +} + +/** + * @brief Exit Restricted Operation Mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Exit Restricted Operation mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either Interrupt line 0 or 1 + (+) HAL_FDCAN_ActivateNotification : Enable interrupts + (+) HAL_FDCAN_DeactivateNotification : Disable interrupts + (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Assign interrupts to either Interrupt line 0 or 1. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ITList indicates which interrupts group will be assigned to the selected interrupt line. + * This parameter can be any combination of @arg FDCAN_Interrupts_Group. + * @param InterruptLine Interrupt line. + * This parameter can be a value of @arg FDCAN_Interrupt_Line. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT_GROUP(ITList)); + assert_param(IS_FDCAN_IT_LINE(InterruptLine)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Assign list of interrupts to the selected line */ + if (InterruptLine == FDCAN_INTERRUPT_LINE0) + { + CLEAR_BIT(hfdcan->Instance->ILS, ITList); + } + else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */ + { + SET_BIT(hfdcan->Instance->ILS, ITList); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @param BufferIndexes Tx Buffer Indexes. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * This parameter is ignored if ActiveITs does not include one of the following: + * - FDCAN_IT_TX_COMPLETE + * - FDCAN_IT_TX_ABORT_COMPLETE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, + uint32_t BufferIndexes) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + uint32_t ITs_lines_selection; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(ActiveITs)); + if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U) + { + assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes)); + } + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Get interrupts line selection */ + ITs_lines_selection = hfdcan->Instance->ILS; + + /* Enable Interrupt lines */ + if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) + { + /* Enable Interrupt line 0 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) + { + /* Enable Interrupt line 1 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + + if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) + { + /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register, + but interrupt will only occur if TC is enabled in IE register */ + SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes); + } + + if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + { + /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register, + but interrupt will only occur if TCF is enabled in IE register */ + SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes); + } + + /* Enable the selected interrupts */ + __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + uint32_t ITs_enabled; + uint32_t ITs_lines_selection; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(InactiveITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Disable the selected interrupts */ + __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs); + + if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U) + { + /* Disable Tx Buffer Transmission Interrupts */ + CLEAR_REG(hfdcan->Instance->TXBTIE); + } + + if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + { + /* Disable Tx Buffer Cancellation Finished Interrupt */ + CLEAR_REG(hfdcan->Instance->TXBCIE); + } + + /* Get interrupts enabled and interrupts line selection */ + ITs_enabled = hfdcan->Instance->IE; + ITs_lines_selection = hfdcan->Instance->ILS; + + /* Check if some interrupts are still enabled on interrupt line 0 */ + if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) + { + /* Do nothing */ + } + else /* no more interrupts enabled on interrupt line 0 */ + { + /* Disable interrupt line 0 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + + /* Check if some interrupts are still enabled on interrupt line 1 */ + if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) + { + /* Do nothing */ + } + else /* no more interrupts enabled on interrupt line 1 */ + { + /* Disable interrupt line 1 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles FDCAN interrupt request. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t TxEventFifoITs; + uint32_t RxFifo0ITs; + uint32_t RxFifo1ITs; + uint32_t Errors; + uint32_t ErrorStatusITs; + uint32_t TransmittedBuffers; + uint32_t AbortedBuffers; + uint32_t itsource; + uint32_t itflag; + + TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK; + TxEventFifoITs &= hfdcan->Instance->IE; + RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK; + RxFifo0ITs &= hfdcan->Instance->IE; + RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK; + RxFifo1ITs &= hfdcan->Instance->IE; + Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK; + Errors &= hfdcan->Instance->IE; + ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; + ErrorStatusITs &= hfdcan->Instance->IE; + itsource = hfdcan->Instance->IE; + itflag = hfdcan->Instance->IR; + + /* High Priority Message interrupt management *******************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) + { + /* Clear the High Priority Message flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->HighPriorityMessageCallback(hfdcan); +#else + /* High Priority Message Callback */ + HAL_FDCAN_HighPriorityMessageCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Transmission Abort interrupt management **********************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) + { + /* List of aborted monitored buffers */ + AbortedBuffers = hfdcan->Instance->TXBCF; + AbortedBuffers &= hfdcan->Instance->TXBCIE; + + /* Clear the Transmission Cancellation flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers); +#else + /* Transmission Cancellation Callback */ + HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Tx event FIFO interrupts management **************************************/ + if (TxEventFifoITs != 0U) + { + /* Clear the Tx Event FIFO flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs); +#else + /* Tx Event FIFO Callback */ + HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Rx FIFO 0 interrupts management ******************************************/ + if (RxFifo0ITs != 0U) + { + /* Clear the Rx FIFO 0 flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs); +#else + /* Rx FIFO 0 Callback */ + HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Rx FIFO 1 interrupts management ******************************************/ + if (RxFifo1ITs != 0U) + { + /* Clear the Rx FIFO 1 flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs); +#else + /* Rx FIFO 1 Callback */ + HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Tx FIFO empty interrupt management ***************************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_FIFO_EMPTY) != RESET) + { + /* Clear the Tx FIFO empty flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxFifoEmptyCallback(hfdcan); +#else + /* Tx FIFO empty Callback */ + HAL_FDCAN_TxFifoEmptyCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Transmission Complete interrupt management *******************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_COMPLETE) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_COMPLETE) != RESET) + { + /* List of transmitted monitored buffers */ + TransmittedBuffers = hfdcan->Instance->TXBTO; + TransmittedBuffers &= hfdcan->Instance->TXBTIE; + + /* Clear the Transmission Complete flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers); +#else + /* Transmission Complete Callback */ + HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Timestamp Wraparound interrupt management ********************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) + { + /* Clear the Timestamp Wraparound flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TimestampWraparoundCallback(hfdcan); +#else + /* Timestamp Wraparound Callback */ + HAL_FDCAN_TimestampWraparoundCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Timeout Occurred interrupt management ************************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) + { + /* Clear the Timeout Occurred flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TimeoutOccurredCallback(hfdcan); +#else + /* Timeout Occurred Callback */ + HAL_FDCAN_TimeoutOccurredCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Message RAM access failure interrupt management **************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) + { + /* Clear the Message RAM access failure flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); + + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS; + } + } + + /* Error Status interrupts management ***************************************/ + if (ErrorStatusITs != 0U) + { + /* Clear the Error flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs); +#else + /* Error Status Callback */ + HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Error interrupts management **********************************************/ + if (Errors != 0U) + { + /* Clear the Error flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors); + + /* Update error code */ + hfdcan->ErrorCode |= Errors; + } + + if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE) + { +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ErrorCallback(hfdcan); +#else + /* Error Callback */ + HAL_FDCAN_ErrorCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group5 Callback functions + * @brief FDCAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_FDCAN_TxEventFifoCallback + (+) HAL_FDCAN_RxFifo0Callback + (+) HAL_FDCAN_RxFifo1Callback + (+) HAL_FDCAN_TxFifoEmptyCallback + (+) HAL_FDCAN_TxBufferCompleteCallback + (+) HAL_FDCAN_TxBufferAbortCallback + (+) HAL_FDCAN_HighPriorityMessageCallback + (+) HAL_FDCAN_TimestampWraparoundCallback + (+) HAL_FDCAN_TimeoutOccurredCallback + (+) HAL_FDCAN_ErrorCallback + (+) HAL_FDCAN_ErrorStatusCallback + +@endverbatim + * @{ + */ + +/** + * @brief Tx Event callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TxEventFifoITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file + */ +} + +/** + * @brief Rx FIFO 0 callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(RxFifo0ITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxFifo0Callback could be implemented in the user file + */ +} + +/** + * @brief Rx FIFO 1 callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(RxFifo1ITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxFifo1Callback could be implemented in the user file + */ +} + +/** + * @brief Tx FIFO Empty callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission Complete callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndexes Indexes of the transmitted buffers. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval None + */ +__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(BufferIndexes); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission Cancellation callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndexes Indexes of the aborted buffers. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval None + */ +__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(BufferIndexes); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file + */ +} + +/** + * @brief Timestamp Wraparound callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout Occurred callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file + */ +} + +/** + * @brief High Priority Message callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Error status callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ErrorStatusITs indicates which Error Status interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(ErrorStatusITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions + * @brief FDCAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_FDCAN_GetState() : Return the FDCAN state. + (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any. + +@endverbatim + * @{ + */ +/** + * @brief Return the FDCAN state + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL state + */ +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return FDCAN state */ + return hfdcan->State; +} + +/** + * @brief Return the FDCAN error code + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval FDCAN Error Code + */ +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return FDCAN error code */ + return hfdcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FDCAN_Private_Functions FDCAN Private Functions + * @{ + */ + +/** + * @brief Calculate each RAM block start address and size + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval none + */ +static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t RAMcounter; + uint32_t SramCanInstanceBase = SRAMCAN_BASE; + + /* Standard filter list start address */ + hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA; + + /* Standard filter elements number */ + MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos)); + + /* Extended filter list start address */ + hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA; + + /* Extended filter elements number */ + MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos)); + + /* Rx FIFO 0 start address */ + hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA; + + /* Rx FIFO 1 start address */ + hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA; + + /* Tx event FIFO start address */ + hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA; + + /* Tx FIFO/queue start address */ + hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA; + + /* Flush the allocated Message RAM area */ + for (RAMcounter = SramCanInstanceBase; RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U) + { + *(uint32_t *)(RAMcounter) = 0x00000000U; + } +} + +/** + * @brief Copy Tx message to the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @param BufferIndex index of the buffer to be configured. + * @retval none + */ +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex) +{ + uint32_t TxElementW1; + uint32_t TxElementW2; + uint32_t *TxAddress; + uint32_t ByteCounter; + + /* Build first word of Tx header element */ + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + TxElementW1 = (pTxHeader->ErrorStateIndicator | + FDCAN_STANDARD_ID | + pTxHeader->TxFrameType | + (pTxHeader->Identifier << 18U)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + TxElementW1 = (pTxHeader->ErrorStateIndicator | + FDCAN_EXTENDED_ID | + pTxHeader->TxFrameType | + pTxHeader->Identifier); + } + + /* Build second word of Tx header element */ + TxElementW2 = ((pTxHeader->MessageMarker << 24U) | + pTxHeader->TxEventFifoControl | + pTxHeader->FDFormat | + pTxHeader->BitRateSwitch | + (pTxHeader->DataLength << 16U)); + + /* Calculate Tx element address */ + TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE)); + + /* Write Tx element header to the message RAM */ + *TxAddress = TxElementW1; + TxAddress++; + *TxAddress = TxElementW2; + TxAddress++; + + /* Write Tx payload to the message RAM */ + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U) + { + *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) | + ((uint32_t)pTxData[ByteCounter + 2U] << 16U) | + ((uint32_t)pTxData[ByteCounter + 1U] << 8U) | + (uint32_t)pTxData[ByteCounter]); + TxAddress++; + } +} + +/** + * @} + */ +#endif /* HAL_FDCAN_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* FDCAN1 */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c index 47877a5574..0739a0dde7 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c @@ -589,7 +589,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32 * @arg @ref OB_RDP_LEVEL_2 Full chip protection * @retval None * - * @note (*) available only on STM32C071xx devices. + * @note (*) available only on STM32C071xx, STM32C051xx and STM32C091/92xx devices. */ static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel) { @@ -787,7 +787,7 @@ static uint32_t FLASH_OB_GetRDP(void) * @ref OB_USER_SECURE_MUXING_EN * @ref OB_USER_HSE_NOT_REMAPPED (*) * - * @note (*) available only on STM32C071xx devices. + * @note (*) available only on STM32C071xx, STM32C051xx and STM32C091/92xx devices. */ static uint32_t FLASH_OB_GetUser(void) { diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c index 6816bc698c..4bdc3e8197 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c @@ -3277,6 +3277,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3334,37 +3336,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -6377,7 +6406,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6533,7 +6562,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6987,7 +7016,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7027,7 +7056,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7066,7 +7095,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7144,7 +7173,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7311,15 +7340,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd.c index 05de1d6943..4ddfc4347f 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd.c @@ -1809,7 +1809,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -1930,7 +1929,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2006,7 +2005,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2038,11 +2037,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2092,6 +2091,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2103,10 +2108,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2137,7 +2144,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2165,6 +2172,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2177,10 +2190,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2210,7 +2225,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2219,7 +2234,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c index ebfb5974cc..f04e954144 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c @@ -1088,6 +1088,8 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF #if defined(RCC_CR_SYSDIV) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CR & RCC_CR_SYSDIV); +#else + RCC_ClkInitStruct->SYSCLKDivider = RCC_SYSCLK_DIV1; #endif /* RCC_CR_SYSDIV */ /* Get the HCLK configuration ----------------------------------------------*/ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c index 547000a581..71660ea61d 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c @@ -85,6 +85,7 @@ * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock (*) * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to RTC domain is enabled. * @note (*) not available on all devices @@ -209,6 +210,18 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *Per } #endif /* USB_DRD_FS */ +#if defined (FDCAN1) + /*-------------------------- FDCAN1 clock source configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == RCC_PERIPHCLK_FDCAN1) + { + /* Check the parameters */ + assert_param(IS_RCC_FDCAN1CLKSOURCE(PeriphClkInit->Fdcan1ClockSelection)); + + /* Configure the FDCAN1 clock source */ + __HAL_RCC_FDCAN1_CONFIG(PeriphClkInit->Fdcan1ClockSelection); + + } +#endif /* FDCAN1 */ /*-------------------------- I2S1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) { @@ -246,6 +259,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) #if defined(USB_DRD_FS) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; #endif /* USB_DRD_FS */ +#if defined(FDCAN1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN1; +#endif /* FDCAN1 */ /* Get the USART1 clock source ---------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); @@ -263,6 +279,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); #endif /* USB_DRD_FS */ +#if defined (FDCAN1) + /* Get the FDCAN1 clock source -------------------------------------------------*/ + PeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE(); +#endif /* FDCAN1 */ + /* Get the I2S1 clock source -----------------------------------------------*/ PeriphClkInit->I2s1ClockSelection = __HAL_RCC_GET_I2S1_SOURCE(); @@ -281,6 +302,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock (*) * @note (*) not available on all devices * @retval Frequency in Hz */ @@ -417,6 +439,31 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Nothing to do as frequency already initialized to 0U */ } break; +#if defined(FDCAN1) + case RCC_PERIPHCLK_FDCAN1: + /* Get the current FDCAN1 source */ + srcclk = __HAL_RCC_GET_FDCAN1_SOURCE(); + + if (srcclk == RCC_FDCAN1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSIKER)) + { + frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + } + else if (srcclk == RCC_FDCAN1CLKSOURCE_HSE) + { + /* External clock used.*/ + frequency = HSE_VALUE; + } + /* Clock not enabled for FDCAN1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* FDCAN1 */ #if defined (USB_DRD_FS) case RCC_PERIPHCLK_USB: /* Get the current USB source */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus.c index 260a3ff20d..af0bcbdd4e 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus.c @@ -1950,7 +1950,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -2378,7 +2378,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c index 296db22d82..691f1d9b39 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c @@ -67,6 +67,15 @@ does not initiate a new transfer the following procedure has to be respected: (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() + [..] + Data buffer address alignment restriction: + (#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer. + But there is no support for unaligned accesses on the Cortex-M0 processor. + So, if the user wants to transfer more than 1 byte, it shall ensure that 16-bit aligned address is used for: + (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT() + (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT() + (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA() + and HAL_SPI_TransmitReceive_DMA(). [..] Callback registration: @@ -823,6 +832,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData uint32_t tickstart; uint16_t initial_TxXferCount; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1013,6 +1029,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 #endif /* USE_SPI_CRC */ uint32_t tickstart; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1266,6 +1289,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData)); + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1597,6 +1628,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1678,6 +1716,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + if (hspi->State != HAL_SPI_STATE_READY) { @@ -1786,6 +1831,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData)); + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c index be65d9a585..a6efe80b5a 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c @@ -1794,7 +1794,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected (*) * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_ITR7: Internal trigger 7 selected (*) @@ -2279,6 +2279,14 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_TIM14_TI1_MCO: TIM14 TI1 is connected to MCO * @arg TIM_TIM14_TI1_MCO2: TIM14 TI1 is connected to MCO2 * + * For TIM15, the parameter is one of the following values: (*) + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1 + * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1 + * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO + * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2 + * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2 + * * For TIM16, the parameter can have the following values: * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI @@ -2290,6 +2298,9 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO * @arg TIM_TIM17_TI1_MCO2: TIM17 TI1 is connected to MCO2 + * + * (*) Timer instance not available on all devices \n + * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c index 1f1b953ab2..27fba786c4 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c @@ -3844,7 +3844,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_adc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_adc.c index 8c0457719c..61bc450a94 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_adc.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_adc.c @@ -248,7 +248,7 @@ ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) { ErrorStatus status = SUCCESS; @@ -519,7 +519,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct) { ErrorStatus status = SUCCESS; @@ -623,7 +623,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_crs.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_crs.c index 1caf19b59a..f015234f69 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_crs.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_crs.c @@ -6,29 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -97,5 +80,3 @@ ErrorStatus LL_CRS_DeInit(void) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_dma.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_dma.c index 80d655a16e..7487c2ddba 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_dma.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_dma.c @@ -74,7 +74,16 @@ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) -#if defined(LL_DMA_CHANNEL_5) +#if defined(LL_DMA_CHANNEL_7) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7)))) +#elif defined(LL_DMA_CHANNEL_5) #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ (((CHANNEL) == LL_DMA_CHANNEL_1) || \ ((CHANNEL) == LL_DMA_CHANNEL_2) || \ @@ -86,7 +95,7 @@ (((CHANNEL) == LL_DMA_CHANNEL_1) || \ ((CHANNEL) == LL_DMA_CHANNEL_2) || \ ((CHANNEL) == LL_DMA_CHANNEL_3)))) -#endif /* LL_DMA_CHANNEL_5 */ +#endif /* LL_DMA_CHANNEL_7 */ /** * @} @@ -112,6 +121,8 @@ * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @arg @ref LL_DMA_CHANNEL_ALL * @note (*) Availability depends on devices * @retval An ErrorStatus enumeration value: @@ -191,6 +202,18 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) LL_DMA_ClearFlag_GI5(DMAx); } #endif /* DMA1_Channel4 */ +#if defined(DMA1_Channel6) + else if (Channel == LL_DMA_CHANNEL_6) + { + /* Reset interrupt pending bits for DMAx Channel6 */ + LL_DMA_ClearFlag_GI6(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_7) + { + /* Reset interrupt pending bits for DMAx Channel7 */ + LL_DMA_ClearFlag_GI7(DMAx); + } +#endif /* DMA1_Channel6 */ else { status = ERROR; @@ -212,6 +235,8 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 (*) * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) * @note (*) Availability depends on devices * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. * @retval An ErrorStatus enumeration value: diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c index af292db997..cf4feadfa4 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c @@ -49,6 +49,9 @@ #if defined (USB_DRD_FS) #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USB_CLKSOURCE) #endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define IS_LL_RCC_FDCAN1_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FDCAN1_CLKSOURCE) +#endif /* FDCAN1 */ /** * @} @@ -435,6 +438,50 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) } #endif /* USB_DRD_FS */ +#if defined(FDCAN1) +/** + * @brief Return FDCANx clock frequency + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE + * @retval FDCAN clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource) +{ + uint32_t fdcan1_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_FDCAN1_CLKSOURCE(FDCANxSource)); + + if (FDCANxSource == LL_RCC_FDCAN1_CLKSOURCE) + { + /* FDCAN1 CLK clock frequency */ + switch (LL_RCC_GetFDCANClockSource(FDCANxSource)) + { + case LL_RCC_FDCAN1_CLKSOURCE_HSIKER: /* FDCAN1 Clock is HSI Kernel */ + if (LL_RCC_HSI_IsReady() == 1U) + { + fdcan1_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + } + break; + + case LL_RCC_FDCAN1_CLKSOURCE_HSE: /* FDCAN1 Clock is External clock */ + if (LL_RCC_HSE_IsReady() != 0U) + { + fdcan1_frequency = HSE_VALUE; + } + break; + + case LL_RCC_FDCAN1_CLKSOURCE_PCLK1: /* FDCAN1 Clock is System Clock */ + default: + fdcan1_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + + return fdcan1_frequency; +} +#endif /* FDCAN1 */ /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c index 37ecf61822..7cf93e996a 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c @@ -31,7 +31,7 @@ * @{ */ -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM16) || defined (TIM17) +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) /** @addtogroup TIM_LL * @{ @@ -248,6 +248,13 @@ ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM14); } +#if defined(TIM15) + else if (TIMx == TIM15) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15); + } +#endif /* TIM15 */ else if (TIMx == TIM16) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); @@ -1320,7 +1327,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM16 || TIM17 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 */ /** * @} diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c index 1295ee0ac7..83a3b96803 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c @@ -31,7 +31,7 @@ * @{ */ -#if defined(USART1) || defined(USART2) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART4) /** @addtogroup USART_LL * @{ @@ -159,6 +159,26 @@ ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) /* Release reset of USART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); } +#if defined(USART3) + else if (USARTx == USART3) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); + } +#endif /* USART3 */ +#if defined(USART4) + else if (USARTx == USART4) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4); + } +#endif /* USART4 */ else { status = ERROR; @@ -242,6 +262,22 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USA LL_RCC_GetSystemClocksFreq(&RCC_Clocks); periphclk = RCC_Clocks.PCLK1_Frequency; } +#if defined(USART3) + else if (USARTx == USART3) + { + /* USART3 clock is PCLK1 */ + LL_RCC_GetSystemClocksFreq(&RCC_Clocks); + periphclk = RCC_Clocks.PCLK1_Frequency; + } +#endif /* USART3 */ +#if defined(USART4) + else if (USARTx == USART4) + { + /* USART4 clock is PCLK1 */ + LL_RCC_GetSystemClocksFreq(&RCC_Clocks); + periphclk = RCC_Clocks.PCLK1_Frequency; + } +#endif /* USART4 */ else { /* Nothing to do, as error code is already assigned to ERROR value */ @@ -382,7 +418,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) * @} */ -#endif /* USART1 || USART2 */ +#endif /* USART1 || USART2 || USART3 || USART4 */ /** * @} diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usb.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usb.c index c53d95a15f..50c4fe36d0 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usb.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usb.c @@ -358,6 +358,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -462,7 +466,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -564,9 +568,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -598,19 +602,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -619,15 +629,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -638,18 +646,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -693,26 +691,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 3b963a2342..b5295a58d4 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -1,6 +1,6 @@ # STM32YYxx HAL Drivers version: - * STM32C0: 1.2.0 + * STM32C0: 1.3.0 * STM32F0: 1.7.8 * STM32F1: 1.1.10 * STM32F2: 1.2.9 From 2d391553553e3239ca3f8a389bc16f2ee6e14618 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 10:58:39 +0100 Subject: [PATCH 007/141] system(C0): update STM32C0xx CMSIS Drivers to v1.3.0 Included in STM32CubeC0 FW v1.3.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32C0xx/Include/stm32c011xx.h | 11 +- .../Device/ST/STM32C0xx/Include/stm32c031xx.h | 11 +- .../Device/ST/STM32C0xx/Include/stm32c051xx.h | 7036 +++++++++++++++ .../Device/ST/STM32C0xx/Include/stm32c071xx.h | 5 + .../Device/ST/STM32C0xx/Include/stm32c091xx.h | 7276 +++++++++++++++ .../Device/ST/STM32C0xx/Include/stm32c092xx.h | 7950 +++++++++++++++++ .../Device/ST/STM32C0xx/Include/stm32c0xx.h | 15 +- .../Device/ST/STM32C0xx/Release_Notes.html | 55 +- .../Templates/gcc/startup_stm32c051xx.s | 267 + .../Templates/gcc/startup_stm32c091xx.s | 273 + .../Templates/gcc/startup_stm32c092xx.s | 279 + .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 12 files changed, 23158 insertions(+), 22 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c091xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c092xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c051xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c091xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c092xx.s diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h index 7ce9b55ca2..c45c968353 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h @@ -570,6 +570,11 @@ typedef struct #define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ + +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF1600UL) + /** * @} */ @@ -3797,12 +3802,6 @@ typedef struct /******************************************************************************/ /******************** Bit definition for RCC_CR register *****************/ -#define RCC_CR_SYSDIV_Pos (2U) -#define RCC_CR_SYSDIV_Msk (0x7UL << RCC_CR_SYSDIV_Pos) /*!< 0x0000001C */ -#define RCC_CR_SYSDIV RCC_CR_SYSDIV_Msk /*!< Clock division factor for system clock */ -#define RCC_CR_SYSDIV_0 (0x1UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000004 */ -#define RCC_CR_SYSDIV_1 (0x2UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000008 */ -#define RCC_CR_SYSDIV_2 (0x4UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000010 */ #define RCC_CR_HSIKERDIV_Pos (5U) #define RCC_CR_HSIKERDIV_Msk (0x7UL << RCC_CR_HSIKERDIV_Pos) /*!< 0x000000E0 */ #define RCC_CR_HSIKERDIV RCC_CR_HSIKERDIV_Msk /*!< HSI48 clock division factor for HSI kernel clocks inputs */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h index 7404631155..5cc3591609 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h @@ -573,6 +573,11 @@ typedef struct #define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ + +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF1600UL) + /** * @} */ @@ -3951,12 +3956,6 @@ typedef struct /******************************************************************************/ /******************** Bit definition for RCC_CR register *****************/ -#define RCC_CR_SYSDIV_Pos (2U) -#define RCC_CR_SYSDIV_Msk (0x7UL << RCC_CR_SYSDIV_Pos) /*!< 0x0000001C */ -#define RCC_CR_SYSDIV RCC_CR_SYSDIV_Msk /*!< Clock division factor for system clock */ -#define RCC_CR_SYSDIV_0 (0x1UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000004 */ -#define RCC_CR_SYSDIV_1 (0x2UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000008 */ -#define RCC_CR_SYSDIV_2 (0x4UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000010 */ #define RCC_CR_HSIKERDIV_Pos (5U) #define RCC_CR_HSIKERDIV_Msk (0x7UL << RCC_CR_HSIKERDIV_Pos) /*!< 0x000000E0 */ #define RCC_CR_HSIKERDIV RCC_CR_HSIKERDIV_Msk /*!< HSI48 clock division factor for HSI kernel clocks inputs */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h new file mode 100644 index 0000000000..fc8e34a0f9 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h @@ -0,0 +1,7036 @@ +/** + ****************************************************************************** + * @file stm32c051xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32c051xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32c051xx + * @{ + */ + +#ifndef STM32C051xx_H +#define STM32C051xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32C0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32C0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32c051xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32C0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMAMUX1_DMA1_CH4_5_IRQn = 11, /*!< DMAMUX and DMA1 Channel 4 to Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32c0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18 */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ + uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t BKP0R; /*!< Backup register 0, Address offset: 0x70 */ + __IO uint32_t BKP1R; /*!< Backup register 1, Address offset: 0x74 */ + __IO uint32_t BKP2R; /*!< Backup register 2, Address offset: 0x78 */ + __IO uint32_t BKP3R; /*!< Backup register 3, Address offset: 0x7C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset: 0x0C -- 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */ + __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */ + __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */ + uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00003000UL) /*!< maximum SRAM size (up to 12 KBytes) */ + +#define FLASH_SIZE_DEFAULT 0x10000U /*!< Flash memory default size */ + +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) + + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ + +/*!< Bootloader Firmware */ + +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF2E00UL) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD3CH_20 (0x100000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD3CH_21 (0x200000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD3CH_22 (0x400000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32C0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32C0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/********************************* DEVICE ID ********************************/ +#define DEV_ID 0x44CUL + +/******************** Bit definition for DBG_IDCODE register *************/ +#define DBG_IDCODE_DEV_ID_Pos (0U) +#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk +#define DBG_IDCODE_REV_ID_Pos (16U) +#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBG_CR register *****************/ +#define DBG_CR_DBG_STOP_Pos (1U) +#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk +#define DBG_CR_DBG_STANDBY_Pos (2U) +#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk + +/******************** Bit definition for DBG_APB_FZ1 register ***********/ +#define DBG_APB_FZ1_DBG_TIM2_STOP_Pos (0U) +#define DBG_APB_FZ1_DBG_TIM2_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBG_APB_FZ1_DBG_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP_Msk +#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) +#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk +#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) +#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk +#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) +#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk + +/******************** Bit definition for DBG_APB_FZ2 register ************/ +#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) +#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ +#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) +#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) +#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ + +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ + +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ + +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ + +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x0288FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x288FFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ + +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ + +#define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */ +#define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */ +#define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk +#define FLASH_ACR_DBG_SWEN_Pos (18U) +#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */ +#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_SEC_PROT_Pos (28U) +#define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */ +#define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_BOR_EN_Pos (8U) +#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk +#define FLASH_OPTR_BORR_LEV_Pos (9U) +#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */ +#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk +#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BORF_LEV_Pos (11U) +#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk +#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_nRST_SHDW_Pos (15U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_HSE_NOT_REMAPPED_Pos (21U) +#define FLASH_OPTR_HSE_NOT_REMAPPED_Msk (0x1UL << FLASH_OPTR_HSE_NOT_REMAPPED_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_HSE_NOT_REMAPPED FLASH_OPTR_HSE_NOT_REMAPPED_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_SECURE_MUXING_EN_Pos (23U) +#define FLASH_OPTR_SECURE_MUXING_EN_Msk (0x1UL << FLASH_OPTR_SECURE_MUXING_EN_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SECURE_MUXING_EN FLASH_OPTR_SECURE_MUXING_EN_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk +#define FLASH_OPTR_NRST_MODE_Pos (27U) +#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ +#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk +#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_IRHEN_Pos (29U) +#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk + + +/****************** Bits definition for FLASH_SECR register *****************/ +#define FLASH_SECR_SEC_SIZE_Pos (0U) +#define FLASH_SECR_SEC_SIZE_Msk (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */ +#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk +#define FLASH_SECR_BOOT_LOCK_Pos (16U) +#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */ +#define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ + +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[22]*/ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18 */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ + uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t BKP0R; /*!< Backup register 0, Address offset: 0x70 */ + __IO uint32_t BKP1R; /*!< Backup register 1, Address offset: 0x74 */ + __IO uint32_t BKP2R; /*!< Backup register 2, Address offset: 0x78 */ + __IO uint32_t BKP3R; /*!< Backup register 3, Address offset: 0x7C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset: 0x0C -- 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */ + __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */ + __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */ + uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00009000UL) /*!< maximum SRAM size (up to 36 KBytes) */ + +#define FLASH_SIZE_DEFAULT 0x40000U /*!< Flash memory default size */ + +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ + +/*!< Bootloader Firmware */ + +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF3E00UL) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD3CH_20 (0x100000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD3CH_21 (0x200000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD3CH_22 (0x400000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32C0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32C0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/********************************* DEVICE ID ********************************/ +#define DEV_ID 0x44DUL + +/******************** Bit definition for DBG_IDCODE register *************/ +#define DBG_IDCODE_DEV_ID_Pos (0U) +#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk +#define DBG_IDCODE_REV_ID_Pos (16U) +#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBG_CR register *****************/ +#define DBG_CR_DBG_STOP_Pos (1U) +#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk +#define DBG_CR_DBG_STANDBY_Pos (2U) +#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk + +/******************** Bit definition for DBG_APB_FZ1 register ***********/ +#define DBG_APB_FZ1_DBG_TIM2_STOP_Pos (0U) +#define DBG_APB_FZ1_DBG_TIM2_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBG_APB_FZ1_DBG_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP_Msk +#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) +#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk +#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) +#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk +#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) +#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk + +/******************** Bit definition for DBG_APB_FZ2 register ************/ +#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) +#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ +#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM15_STOP_Pos (16U) +#define DBG_APB_FZ2_DBG_TIM15_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBG_APB_FZ2_DBG_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) +#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) +#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ + +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ + +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ + +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ + +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x0288FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x288FFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ + +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ + +#define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */ +#define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */ +#define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk +#define FLASH_ACR_DBG_SWEN_Pos (18U) +#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */ +#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_SEC_PROT_Pos (28U) +#define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */ +#define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_BOR_EN_Pos (8U) +#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk +#define FLASH_OPTR_BORR_LEV_Pos (9U) +#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */ +#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk +#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BORF_LEV_Pos (11U) +#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk +#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_nRST_SHDW_Pos (15U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_HSE_NOT_REMAPPED_Pos (21U) +#define FLASH_OPTR_HSE_NOT_REMAPPED_Msk (0x1UL << FLASH_OPTR_HSE_NOT_REMAPPED_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_HSE_NOT_REMAPPED FLASH_OPTR_HSE_NOT_REMAPPED_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_SECURE_MUXING_EN_Pos (23U) +#define FLASH_OPTR_SECURE_MUXING_EN_Msk (0x1UL << FLASH_OPTR_SECURE_MUXING_EN_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SECURE_MUXING_EN FLASH_OPTR_SECURE_MUXING_EN_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk +#define FLASH_OPTR_NRST_MODE_Pos (27U) +#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ +#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk +#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_IRHEN_Pos (29U) +#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x1FFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x1FFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x1FFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x1FFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk + + +/****************** Bits definition for FLASH_SECR register *****************/ +#define FLASH_SECR_SEC_SIZE_Pos (0U) +#define FLASH_SECR_SEC_SIZE_Msk (0x7FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000007F */ +#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk +#define FLASH_SECR_BOOT_LOCK_Pos (16U) +#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */ +#define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ + +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[22]*/ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART3 GLB Interrupt */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18 */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ + uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t BKP0R; /*!< Backup register 0, Address offset: 0x70 */ + __IO uint32_t BKP1R; /*!< Backup register 1, Address offset: 0x74 */ + __IO uint32_t BKP2R; /*!< Backup register 2, Address offset: 0x78 */ + __IO uint32_t BKP3R; /*!< Backup register 3, Address offset: 0x7C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset: 0x0C -- 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */ + __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */ + __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */ + uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00007800UL) /*!< maximum SRAM size (up to 30 KBytes) */ + +#define FLASH_SIZE_DEFAULT 0x40000U /*!< Flash memory default size */ + +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define FDCAN1_BASE (APBPERIPH_BASE + 0x00006400UL) +#define FDCAN_CONFIG_BASE (APBPERIPH_BASE + 0x00006500UL) /*!< FDCAN configuration registers base address */ +#define SRAMCAN_BASE (APBPERIPH_BASE + 0x0000B400UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ + +/*!< Bootloader Firmware */ + +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF3E00UL) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD3CH_20 (0x100000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD3CH_21 (0x200000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD3CH_22 (0x400000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32C0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32C0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/********************************* DEVICE ID ********************************/ +#define DEV_ID 0x44DUL + +/******************** Bit definition for DBG_IDCODE register *************/ +#define DBG_IDCODE_DEV_ID_Pos (0U) +#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk +#define DBG_IDCODE_REV_ID_Pos (16U) +#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBG_CR register *****************/ +#define DBG_CR_DBG_STOP_Pos (1U) +#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk +#define DBG_CR_DBG_STANDBY_Pos (2U) +#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk + +/******************** Bit definition for DBG_APB_FZ1 register ***********/ +#define DBG_APB_FZ1_DBG_TIM2_STOP_Pos (0U) +#define DBG_APB_FZ1_DBG_TIM2_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBG_APB_FZ1_DBG_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP_Msk +#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) +#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk +#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) +#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk +#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) +#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk + +/******************** Bit definition for DBG_APB_FZ2 register ************/ +#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) +#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ +#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM15_STOP_Pos (16U) +#define DBG_APB_FZ2_DBG_TIM15_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBG_APB_FZ2_DBG_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) +#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) +#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ + +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ + +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ + +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ + +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x0288FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x288FFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ + +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + + +/******************************************************************************/ +/* */ +/* Flexible Datarate Controller Area Network */ +/* */ +/******************************************************************************/ +/*! */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ + +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[22]*/ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE30_SR_FDCAN1_IT0_Pos (0U) +#define SYSCFG_ITLINE30_SR_FDCAN1_IT0_Msk (0x1UL << SYSCFG_ITLINE30_SR_FDCAN1_IT0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE30_SR_FDCAN1_IT0 SYSCFG_ITLINE30_SR_FDCAN1_IT0_Msk /*!< FDCAN1 IT0 Interrupt */ +#define SYSCFG_ITLINE31_SR_FDCAN1_IT1_Pos (0U) +#define SYSCFG_ITLINE31_SR_FDCAN1_IT1_Msk (0x1UL << SYSCFG_ITLINE31_SR_FDCAN1_IT1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE31_SR_FDCAN1_IT1 SYSCFG_ITLINE31_SR_FDCAN1_IT1_Msk /*!< FDCAN1 IT1 Interrupt */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!Release Notes for

Update History

- - + +

Main Changes

    +
  • Official release of STM32C0xx CMSIS drivers to support +STM32C051xx and STM32C091/92xx +devices
    • +
  • General updates to fix known defects and enhance implementation
    • +
  • Align version of bit and registers definition with the STM32C0 +reference manual
    • +
+

Contents

+
    +
  • Support of STM32C051xx and STM32C091/92xx devices: +
      +
    • Add “stm32c051xx.h†, “stm32c091xx.hâ€, and “stm32c092xx.h†+files
      • +
    • Add startup files “startup_stm32c051xx.sâ€, “startup_stm32c091xx.s†+and “startup_stm32c092xx.s†for EWARM, STM32CubeIDE and MDK-ARM +toolchains
      • +
    • Add STM32C051xx and STM32C091/92xx devices linker files for EWARM +and STM32CubeIDE toolchains
      • +
    • +
  • Registers and bit field definitions updates : +
      +
    • Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware +addresses
      • +
    • Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS +files as undefined
      • +
    • +
+

Supported Devices

+
    +
  • STM32C011xx, STM32C031xx, STM32C051xx, STM32C071xx +and STM32C091/92xx devices
    • +
+
+
+
+ + +
+

Main Changes

+
  • First official release of STM32C0xx CMSIS drivers to support STM32C071xx devices
  • General updates to fix known defects and enhance implementation
  • Align version of bit and registers definition with the STM32C0 reference manual
-

Contents

+

Contents

  • Support of STM32C071xx devices:
      @@ -102,7 +143,7 @@

      Contents

-

Supported Devices

+

Supported Devices

  • STM32C011xx, STM32C031xx and STM32C071xx devices
@@ -112,14 +153,14 @@

Supported Devices

-

Main Changes

+

Main Changes

Align flash register address with STM32C0 reference manual

-

Main Changes

+

Main Changes

First official release version of bits and registers definition aligned with STM32C0 reference manual

diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c051xx.s b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c051xx.s new file mode 100644 index 0000000000..8cbd4d5db7 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c051xx.s @@ -0,0 +1,267 @@ +/** + ****************************************************************************** + * @file startup_stm32c051xx.s + * @author MCD Application Team + * @brief STM32C051xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMAMUX1_DMA1_CH4_5_IRQHandler /* DMAMUX1, DMA1 Channel 4 and 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C1 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI1 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word 0 /* reserved */ + + .size g_pfnVectors, .-g_pfnVectors +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMAMUX1_DMA1_CH4_5_IRQHandler + .thumb_set DMAMUX1_DMA1_CH4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c091xx.s b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c091xx.s new file mode 100644 index 0000000000..aed28d0cb6 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c091xx.s @@ -0,0 +1,273 @@ +/** + ****************************************************************************** + * @file startup_stm32c091xx.s + * @author MCD Application Team + * @brief STM32C091xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMAMUX1_DMA1_CH4_5_IRQHandler /* DMAMUX1, DMA1 Channel 4 and 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C1 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI1 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_IRQHandler /* USART3 and USART4 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + + .size g_pfnVectors, .-g_pfnVectors +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMAMUX1_DMA1_CH4_5_IRQHandler + .thumb_set DMAMUX1_DMA1_CH4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c092xx.s b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c092xx.s new file mode 100644 index 0000000000..1fa4cd67c0 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c092xx.s @@ -0,0 +1,279 @@ +/** + ****************************************************************************** + * @file startup_stm32c092xx.s + * @author MCD Application Team + * @brief STM32C092xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMAMUX1_DMA1_CH4_5_IRQHandler /* DMAMUX1, DMA1 Channel 4 and 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C1 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI1 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_IRQHandler /* USART3 and USART4 */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt request 0 pending */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt request 1 pending */ + + .size g_pfnVectors, .-g_pfnVectors +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMAMUX1_DMA1_CH4_5_IRQHandler + .thumb_set DMAMUX1_DMA1_CH4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 4cc65c8401..8bb9b810b1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -1,6 +1,6 @@ # STM32YYxx CMSIS version: - * STM32C0: 1.2.0 + * STM32C0: 1.3.0 * STM32F0: 2.3.7 * STM32F1: 4.3.5 * STM32F2: 2.2.6 From af4d1c110832f922af7f0d1fc327284c56230a92 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 10:58:40 +0100 Subject: [PATCH 008/141] core(C0): update wrapped files Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def_build.h | 6 ++++++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c | 4 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 55026e1682..179b810851 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -6,8 +6,14 @@ #define CMSIS_STARTUP_FILE "startup_stm32c011xx.s" #elif defined(STM32C031xx) #define CMSIS_STARTUP_FILE "startup_stm32c031xx.s" + #elif defined(STM32C051xx) + #define CMSIS_STARTUP_FILE "startup_stm32c051xx.s" #elif defined(STM32C071xx) #define CMSIS_STARTUP_FILE "startup_stm32c071xx.s" + #elif defined(STM32C091xx) + #define CMSIS_STARTUP_FILE "startup_stm32c091xx.s" + #elif defined(STM32C092xx) + #define CMSIS_STARTUP_FILE "startup_stm32c092xx.s" #elif defined(STM32F030x6) #define CMSIS_STARTUP_FILE "startup_stm32f030x6.s" #elif defined(STM32F030x8) diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c index e64f1e3f10..2d9a5483b1 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32G0xx +#ifdef STM32C0xx + #include "stm32c0xx_hal_fdcan.c" +#elif STM32G0xx #include "stm32g0xx_hal_fdcan.c" #elif STM32G4xx #include "stm32g4xx_hal_fdcan.c" From 0663d820505c4853370588c5576ecf0c786f6526 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 11:22:32 +0100 Subject: [PATCH 009/141] chore(co): update variants against CubeMX DB release 6.0.130 Signed-off-by: Frederic Pillon --- .../PeripheralPins.c | 2 +- .../STM32C0xx/C011J(4-6)M/PeripheralPins.c | 2 +- .../C031C(4-6)(T-U)/PeripheralPins.c | 2 +- .../STM32C0xx/C031G(4-6)U/PeripheralPins.c | 2 +- .../C031K(4-6)(T-U)/PeripheralPins.c | 2 +- .../C051C(6-8)(T-U)/PeripheralPins.c | 326 ++++++++++++++ .../STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h | 76 ++++ .../C051C(6-8)(T-U)/boards_entry.txt | 41 ++ .../STM32C0xx/C051C(6-8)(T-U)/generic_clock.c | 28 ++ .../C051C(6-8)(T-U)/variant_generic.cpp | 89 ++++ .../C051C(6-8)(T-U)/variant_generic.h | 206 +++++++++ .../C051D8Y_C051F(6-8)P/PeripheralPins.c | 268 ++++++++++++ .../C051D8Y_C051F(6-8)P/PinNamesVar.h | 67 +++ .../C051D8Y_C051F(6-8)P/boards_entry.txt | 32 ++ .../C051D8Y_C051F(6-8)P/generic_clock.c | 28 ++ .../C051D8Y_C051F(6-8)P/variant_generic.cpp | 61 +++ .../C051D8Y_C051F(6-8)P/variant_generic.h | 175 ++++++++ .../STM32C0xx/C051G(6-8)U/PeripheralPins.c | 278 ++++++++++++ variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h | 72 +++ .../STM32C0xx/C051G(6-8)U/boards_entry.txt | 23 + .../STM32C0xx/C051G(6-8)U/generic_clock.c | 27 ++ .../STM32C0xx/C051G(6-8)U/variant_generic.cpp | 65 +++ .../STM32C0xx/C051G(6-8)U/variant_generic.h | 183 ++++++++ .../C051K6(T-U)_C051K8T/PeripheralPins.c | 297 +++++++++++++ .../C051K6(T-U)_C051K8T/PinNamesVar.h | 75 ++++ .../C051K6(T-U)_C051K8T/boards_entry.txt | 32 ++ .../C051K6(T-U)_C051K8T/generic_clock.c | 28 ++ .../C051K6(T-U)_C051K8T/variant_generic.cpp | 71 +++ .../C051K6(T-U)_C051K8T/variant_generic.h | 190 ++++++++ .../C071C(8-B)(T-U)/PeripheralPins.c | 2 +- .../C071C(8-B)(T-U)xN/PeripheralPins.c | 2 +- .../STM32C0xx/C071F(8-B)PxN/PeripheralPins.c | 2 +- .../C071F8P_C071FB(P-Y)/PeripheralPins.c | 2 +- .../STM32C0xx/C071G(8-B)U/PeripheralPins.c | 2 +- .../STM32C0xx/C071G(8-B)UxN/PeripheralPins.c | 2 +- .../C071K(8-B)(T-U)/PeripheralPins.c | 2 +- .../C071K(8-B)(T-U)xN/PeripheralPins.c | 2 +- .../STM32C0xx/C071R(8-B)T/PeripheralPins.c | 2 +- .../C071R8TxN_C071RB(I-T)xN/PeripheralPins.c | 2 +- .../C091C(B-C)(T-U)/PeripheralPins.c | 345 +++++++++++++++ .../STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h | 82 ++++ .../C091C(B-C)(T-U)/boards_entry.txt | 41 ++ .../STM32C0xx/C091C(B-C)(T-U)/generic_clock.c | 28 ++ .../C091C(B-C)(T-U)/variant_generic.cpp | 87 ++++ .../C091C(B-C)(T-U)/variant_generic.h | 212 +++++++++ .../C091ECY_C091F(B-C)P/PeripheralPins.c | 288 ++++++++++++ .../C091ECY_C091F(B-C)P/PinNamesVar.h | 73 ++++ .../C091ECY_C091F(B-C)P/boards_entry.txt | 32 ++ .../C091ECY_C091F(B-C)P/generic_clock.c | 28 ++ .../C091ECY_C091F(B-C)P/variant_generic.cpp | 65 +++ .../C091ECY_C091F(B-C)P/variant_generic.h | 184 ++++++++ .../STM32C0xx/C091G(B-C)U/PeripheralPins.c | 285 ++++++++++++ variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h | 74 ++++ .../STM32C0xx/C091G(B-C)U/boards_entry.txt | 23 + .../STM32C0xx/C091G(B-C)U/generic_clock.c | 27 ++ .../STM32C0xx/C091G(B-C)U/variant_generic.cpp | 63 +++ .../STM32C0xx/C091G(B-C)U/variant_generic.h | 185 ++++++++ .../C091K(B-C)(T-U)/PeripheralPins.c | 306 +++++++++++++ .../STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h | 77 ++++ .../C091K(B-C)(T-U)/boards_entry.txt | 41 ++ .../STM32C0xx/C091K(B-C)(T-U)/generic_clock.c | 28 ++ .../C091K(B-C)(T-U)/variant_generic.cpp | 69 +++ .../C091K(B-C)(T-U)/variant_generic.h | 192 ++++++++ .../C091RBT_C091RC(I-T)/PeripheralPins.c | 383 ++++++++++++++++ .../C091RBT_C091RC(I-T)/PinNamesVar.h | 88 ++++ .../C091RBT_C091RC(I-T)/boards_entry.txt | 32 ++ .../C091RBT_C091RC(I-T)/generic_clock.c | 28 ++ .../C091RBT_C091RC(I-T)/variant_generic.cpp | 105 +++++ .../C091RBT_C091RC(I-T)/variant_generic.h | 234 ++++++++++ .../PeripheralPins.c | 412 ++++++++++++++++++ .../C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h | 88 ++++ .../boards_entry.txt | 41 ++ .../generic_clock.c | 28 ++ .../variant_generic.cpp | 105 +++++ .../variant_generic.h | 234 ++++++++++ .../C092CBU_C092CC(T-U)/PeripheralPins.c | 370 ++++++++++++++++ .../C092CBU_C092CC(T-U)/PinNamesVar.h | 82 ++++ .../C092CBU_C092CC(T-U)/boards_entry.txt | 32 ++ .../C092CBU_C092CC(T-U)/generic_clock.c | 28 ++ .../C092CBU_C092CC(T-U)/variant_generic.cpp | 87 ++++ .../C092CBU_C092CC(T-U)/variant_generic.h | 212 +++++++++ .../C092ECY_C092F(B-C)P/PeripheralPins.c | 308 +++++++++++++ .../C092ECY_C092F(B-C)P/PinNamesVar.h | 73 ++++ .../C092ECY_C092F(B-C)P/boards_entry.txt | 32 ++ .../C092ECY_C092F(B-C)P/generic_clock.c | 28 ++ .../C092ECY_C092F(B-C)P/variant_generic.cpp | 65 +++ .../C092ECY_C092F(B-C)P/variant_generic.h | 184 ++++++++ .../STM32C0xx/C092G(B-C)U/PeripheralPins.c | 305 +++++++++++++ variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h | 74 ++++ .../STM32C0xx/C092G(B-C)U/boards_entry.txt | 23 + .../STM32C0xx/C092G(B-C)U/generic_clock.c | 27 ++ .../STM32C0xx/C092G(B-C)U/variant_generic.cpp | 63 +++ .../STM32C0xx/C092G(B-C)U/variant_generic.h | 185 ++++++++ .../C092K(B-C)(T-U)/PeripheralPins.c | 327 ++++++++++++++ .../STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h | 77 ++++ .../C092K(B-C)(T-U)/boards_entry.txt | 41 ++ .../STM32C0xx/C092K(B-C)(T-U)/generic_clock.c | 28 ++ .../C092K(B-C)(T-U)/variant_generic.cpp | 69 +++ .../C092K(B-C)(T-U)/variant_generic.h | 192 ++++++++ 99 files changed, 10278 insertions(+), 15 deletions(-) create mode 100644 variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c create mode 100644 variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h create mode 100644 variants/STM32C0xx/C051C(6-8)(T-U)/boards_entry.txt create mode 100644 variants/STM32C0xx/C051C(6-8)(T-U)/generic_clock.c create mode 100644 variants/STM32C0xx/C051C(6-8)(T-U)/variant_generic.cpp create mode 100644 variants/STM32C0xx/C051C(6-8)(T-U)/variant_generic.h create mode 100644 variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c create mode 100644 variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h create mode 100644 variants/STM32C0xx/C051D8Y_C051F(6-8)P/boards_entry.txt create mode 100644 variants/STM32C0xx/C051D8Y_C051F(6-8)P/generic_clock.c create mode 100644 variants/STM32C0xx/C051D8Y_C051F(6-8)P/variant_generic.cpp create mode 100644 variants/STM32C0xx/C051D8Y_C051F(6-8)P/variant_generic.h create mode 100644 variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c create mode 100644 variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h create mode 100644 variants/STM32C0xx/C051G(6-8)U/boards_entry.txt create mode 100644 variants/STM32C0xx/C051G(6-8)U/generic_clock.c create mode 100644 variants/STM32C0xx/C051G(6-8)U/variant_generic.cpp create mode 100644 variants/STM32C0xx/C051G(6-8)U/variant_generic.h create mode 100644 variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c create mode 100644 variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h create mode 100644 variants/STM32C0xx/C051K6(T-U)_C051K8T/boards_entry.txt create mode 100644 variants/STM32C0xx/C051K6(T-U)_C051K8T/generic_clock.c create mode 100644 variants/STM32C0xx/C051K6(T-U)_C051K8T/variant_generic.cpp create mode 100644 variants/STM32C0xx/C051K6(T-U)_C051K8T/variant_generic.h create mode 100644 variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c create mode 100644 variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h create mode 100644 variants/STM32C0xx/C091C(B-C)(T-U)/boards_entry.txt create mode 100644 variants/STM32C0xx/C091C(B-C)(T-U)/generic_clock.c create mode 100644 variants/STM32C0xx/C091C(B-C)(T-U)/variant_generic.cpp create mode 100644 variants/STM32C0xx/C091C(B-C)(T-U)/variant_generic.h create mode 100644 variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c create mode 100644 variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h create mode 100644 variants/STM32C0xx/C091ECY_C091F(B-C)P/boards_entry.txt create mode 100644 variants/STM32C0xx/C091ECY_C091F(B-C)P/generic_clock.c create mode 100644 variants/STM32C0xx/C091ECY_C091F(B-C)P/variant_generic.cpp create mode 100644 variants/STM32C0xx/C091ECY_C091F(B-C)P/variant_generic.h create mode 100644 variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c create mode 100644 variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h create mode 100644 variants/STM32C0xx/C091G(B-C)U/boards_entry.txt create mode 100644 variants/STM32C0xx/C091G(B-C)U/generic_clock.c create mode 100644 variants/STM32C0xx/C091G(B-C)U/variant_generic.cpp create mode 100644 variants/STM32C0xx/C091G(B-C)U/variant_generic.h create mode 100644 variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c create mode 100644 variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h create mode 100644 variants/STM32C0xx/C091K(B-C)(T-U)/boards_entry.txt create mode 100644 variants/STM32C0xx/C091K(B-C)(T-U)/generic_clock.c create mode 100644 variants/STM32C0xx/C091K(B-C)(T-U)/variant_generic.cpp create mode 100644 variants/STM32C0xx/C091K(B-C)(T-U)/variant_generic.h create mode 100644 variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c create mode 100644 variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h create mode 100644 variants/STM32C0xx/C091RBT_C091RC(I-T)/boards_entry.txt create mode 100644 variants/STM32C0xx/C091RBT_C091RC(I-T)/generic_clock.c create mode 100644 variants/STM32C0xx/C091RBT_C091RC(I-T)/variant_generic.cpp create mode 100644 variants/STM32C0xx/C091RBT_C091RC(I-T)/variant_generic.h create mode 100644 variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PeripheralPins.c create mode 100644 variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h create mode 100644 variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/boards_entry.txt create mode 100644 variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/generic_clock.c create mode 100644 variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.cpp create mode 100644 variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.h create mode 100644 variants/STM32C0xx/C092CBU_C092CC(T-U)/PeripheralPins.c create mode 100644 variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h create mode 100644 variants/STM32C0xx/C092CBU_C092CC(T-U)/boards_entry.txt create mode 100644 variants/STM32C0xx/C092CBU_C092CC(T-U)/generic_clock.c create mode 100644 variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.cpp create mode 100644 variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.h create mode 100644 variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c create mode 100644 variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h create mode 100644 variants/STM32C0xx/C092ECY_C092F(B-C)P/boards_entry.txt create mode 100644 variants/STM32C0xx/C092ECY_C092F(B-C)P/generic_clock.c create mode 100644 variants/STM32C0xx/C092ECY_C092F(B-C)P/variant_generic.cpp create mode 100644 variants/STM32C0xx/C092ECY_C092F(B-C)P/variant_generic.h create mode 100644 variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c create mode 100644 variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h create mode 100644 variants/STM32C0xx/C092G(B-C)U/boards_entry.txt create mode 100644 variants/STM32C0xx/C092G(B-C)U/generic_clock.c create mode 100644 variants/STM32C0xx/C092G(B-C)U/variant_generic.cpp create mode 100644 variants/STM32C0xx/C092G(B-C)U/variant_generic.h create mode 100644 variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c create mode 100644 variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h create mode 100644 variants/STM32C0xx/C092K(B-C)(T-U)/boards_entry.txt create mode 100644 variants/STM32C0xx/C092K(B-C)(T-U)/generic_clock.c create mode 100644 variants/STM32C0xx/C092K(B-C)(T-U)/variant_generic.cpp create mode 100644 variants/STM32C0xx/C092K(B-C)(T-U)/variant_generic.h diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c index 32b9848ca9..a43f1bdc12 100644 --- a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c +++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C011D6Yx.xml, STM32C011F(4-6)Px.xml * STM32C011F(4-6)Ux.xml, STM32C031F(4-6)Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c index 4a13e0b43a..6d3bd41864 100644 --- a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c +++ b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C011J(4-6)Mx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c index 9a5b7effb3..fedaeb3f35 100644 --- a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031C(4-6)Tx.xml, STM32C031C(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c b/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c index 2924d04af2..d18357da0b 100644 --- a/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c +++ b/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031G(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c index 55105d9ddc..590b93b76f 100644 --- a/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031K(4-6)Tx.xml, STM32C031K(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..7694b712e9 --- /dev/null +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c @@ -0,0 +1,326 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C051C6Tx.xml, STM32C051C6Ux.xml + * STM32C051C8Tx.xml, STM32C051C8Ux.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {PB_10, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC1_IN20 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC1_IN21 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 22, 0)}, // ADC1_IN22 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PB_7_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT4, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT5, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PC_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PC_15_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PD_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PD_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PD_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PD_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PF_0, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..250cef0aa0 --- /dev/null +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h @@ -0,0 +1,76 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_7_ALT5 = PB_7 | ALT5, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, +PC_15_ALT1 = PC_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/boards_entry.txt b/variants/STM32C0xx/C051C(6-8)(T-U)/boards_entry.txt new file mode 100644 index 0000000000..78b23dd99c --- /dev/null +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C051C6Tx +GenC0.menu.pnum.GENERIC_C051C6TX=Generic C051C6Tx +GenC0.menu.pnum.GENERIC_C051C6TX.upload.maximum_size=32768 +GenC0.menu.pnum.GENERIC_C051C6TX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051C6TX.build.board=GENERIC_C051C6TX +GenC0.menu.pnum.GENERIC_C051C6TX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051C6TX.build.variant=STM32C0xx/C051C(6-8)(T-U) +GenC0.menu.pnum.GENERIC_C051C6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051C6Ux +GenC0.menu.pnum.GENERIC_C051C6UX=Generic C051C6Ux +GenC0.menu.pnum.GENERIC_C051C6UX.upload.maximum_size=32768 +GenC0.menu.pnum.GENERIC_C051C6UX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051C6UX.build.board=GENERIC_C051C6UX +GenC0.menu.pnum.GENERIC_C051C6UX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051C6UX.build.variant=STM32C0xx/C051C(6-8)(T-U) +GenC0.menu.pnum.GENERIC_C051C6UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051C8Tx +GenC0.menu.pnum.GENERIC_C051C8TX=Generic C051C8Tx +GenC0.menu.pnum.GENERIC_C051C8TX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C051C8TX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051C8TX.build.board=GENERIC_C051C8TX +GenC0.menu.pnum.GENERIC_C051C8TX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051C8TX.build.variant=STM32C0xx/C051C(6-8)(T-U) +GenC0.menu.pnum.GENERIC_C051C8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051C8Ux +GenC0.menu.pnum.GENERIC_C051C8UX=Generic C051C8Ux +GenC0.menu.pnum.GENERIC_C051C8UX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C051C8UX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051C8UX.build.board=GENERIC_C051C8UX +GenC0.menu.pnum.GENERIC_C051C8UX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051C8UX.build.variant=STM32C0xx/C051C(6-8)(T-U) +GenC0.menu.pnum.GENERIC_C051C8UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/generic_clock.c b/variants/STM32C0xx/C051C(6-8)(T-U)/generic_clock.c new file mode 100644 index 0000000000..ff0377381d --- /dev/null +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C051C6TX) || defined(ARDUINO_GENERIC_C051C6UX) ||\ + defined(ARDUINO_GENERIC_C051C8TX) || defined(ARDUINO_GENERIC_C051C8UX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/variant_generic.cpp b/variants/STM32C0xx/C051C(6-8)(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..7ceeda0dcf --- /dev/null +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/variant_generic.cpp @@ -0,0 +1,89 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C051C6TX) || defined(ARDUINO_GENERIC_C051C6UX) ||\ + defined(ARDUINO_GENERIC_C051C8TX) || defined(ARDUINO_GENERIC_C051C8UX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11/A9 + PA_12, // D12/A10 + PA_13, // D13/A11 + PA_14, // D14/A12 + PA_15, // D15 + PB_0, // D16/A13 + PB_1, // D17/A14 + PB_2, // D18/A15 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26/A16 + PB_11, // D27/A17 + PB_12, // D28/A18 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_6, // D32 + PC_7, // D33 + PC_13, // D34 + PC_14, // D35 + PC_15, // D36 + PD_0, // D37 + PD_1, // D38 + PD_2, // D39 + PD_3, // D40 + PF_0, // D41 + PF_1, // D42 + PF_2, // D43 + PF_3 // D44 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 11, // A9, PA11 + 12, // A10, PA12 + 13, // A11, PA13 + 14, // A12, PA14 + 16, // A13, PB0 + 17, // A14, PB1 + 18, // A15, PB2 + 26, // A16, PB10 + 27, // A17, PB11 + 28 // A18, PB12 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/variant_generic.h b/variants/STM32C0xx/C051C(6-8)(T-U)/variant_generic.h new file mode 100644 index 0000000000..1fefce8eaf --- /dev/null +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/variant_generic.h @@ -0,0 +1,206 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 PIN_A9 +#define PA12 PIN_A10 +#define PA13 PIN_A11 +#define PA14 PIN_A12 +#define PA15 15 +#define PB0 PIN_A13 +#define PB1 PIN_A14 +#define PB2 PIN_A15 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 PIN_A16 +#define PB11 PIN_A17 +#define PB12 PIN_A18 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC6 32 +#define PC7 33 +#define PC13 34 +#define PC14 35 +#define PC15 36 +#define PD0 37 +#define PD1 38 +#define PD2 39 +#define PD3 40 +#define PF0 41 +#define PF1 42 +#define PF2 43 +#define PF3 44 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB7_ALT5 (PB7 | ALT5) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) +#define PC15_ALT1 (PC15 | ALT1) + +#define NUM_DIGITAL_PINS 45 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c new file mode 100644 index 0000000000..2873ba1c45 --- /dev/null +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c @@ -0,0 +1,268 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C051D8Yx.xml, STM32C051F6Px.xml + * STM32C051F8Px.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PB_7_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT4, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT5, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PC_15_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h new file mode 100644 index 0000000000..1ccc645780 --- /dev/null +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h @@ -0,0 +1,67 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_15_ALT1 = PA_15 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_7_ALT5 = PB_7 | ALT5, +PB_8_ALT1 = PB_8 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, +PC_15_ALT1 = PC_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/boards_entry.txt b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/boards_entry.txt new file mode 100644 index 0000000000..32642592b1 --- /dev/null +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C051D8Yx +GenC0.menu.pnum.GENERIC_C051D8YX=Generic C051D8Yx +GenC0.menu.pnum.GENERIC_C051D8YX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C051D8YX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051D8YX.build.board=GENERIC_C051D8YX +GenC0.menu.pnum.GENERIC_C051D8YX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051D8YX.build.variant=STM32C0xx/C051D8Y_C051F(6-8)P +GenC0.menu.pnum.GENERIC_C051D8YX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051F6Px +GenC0.menu.pnum.GENERIC_C051F6PX=Generic C051F6Px +GenC0.menu.pnum.GENERIC_C051F6PX.upload.maximum_size=32768 +GenC0.menu.pnum.GENERIC_C051F6PX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051F6PX.build.board=GENERIC_C051F6PX +GenC0.menu.pnum.GENERIC_C051F6PX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051F6PX.build.variant=STM32C0xx/C051D8Y_C051F(6-8)P +GenC0.menu.pnum.GENERIC_C051F6PX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051F8Px +GenC0.menu.pnum.GENERIC_C051F8PX=Generic C051F8Px +GenC0.menu.pnum.GENERIC_C051F8PX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C051F8PX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051F8PX.build.board=GENERIC_C051F8PX +GenC0.menu.pnum.GENERIC_C051F8PX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051F8PX.build.variant=STM32C0xx/C051D8Y_C051F(6-8)P +GenC0.menu.pnum.GENERIC_C051F8PX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/generic_clock.c b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/generic_clock.c new file mode 100644 index 0000000000..acc129c4c5 --- /dev/null +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C051D8YX) || defined(ARDUINO_GENERIC_C051F6PX) ||\ + defined(ARDUINO_GENERIC_C051F8PX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/variant_generic.cpp b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/variant_generic.cpp new file mode 100644 index 0000000000..7e76a7ef9d --- /dev/null +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/variant_generic.cpp @@ -0,0 +1,61 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C051D8YX) || defined(ARDUINO_GENERIC_C051F6PX) ||\ + defined(ARDUINO_GENERIC_C051F8PX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_11, // D9/A9 + PA_12, // D10/A10 + PA_13, // D11/A11 + PA_14, // D12/A12 + PA_15, // D13 + PB_3, // D14 + PB_4, // D15 + PB_5, // D16 + PB_6, // D17 + PB_7, // D18 + PB_8, // D19 + PC_14, // D20 + PC_15, // D21 + PF_2 // D22 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 9, // A9, PA11 + 10, // A10, PA12 + 11, // A11, PA13 + 12 // A12, PA14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/variant_generic.h b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/variant_generic.h new file mode 100644 index 0000000000..f96f08e508 --- /dev/null +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/variant_generic.h @@ -0,0 +1,175 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA11 PIN_A9 +#define PA12 PIN_A10 +#define PA13 PIN_A11 +#define PA14 PIN_A12 +#define PA15 13 +#define PB3 14 +#define PB4 15 +#define PB5 16 +#define PB6 17 +#define PB7 18 +#define PB8 19 +#define PC14 20 +#define PC15 21 +#define PF2 22 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA15_ALT1 (PA15 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB7_ALT5 (PB7 | ALT5) +#define PB8_ALT1 (PB8 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) +#define PC15_ALT1 (PC15 | ALT1) + +#define NUM_DIGITAL_PINS 23 +#define NUM_ANALOG_INPUTS 13 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c b/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c new file mode 100644 index 0000000000..3cdd7b4ca6 --- /dev/null +++ b/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c @@ -0,0 +1,278 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C051G6Ux.xml, STM32C051G8Ux.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PB_7_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT4, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT5, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PC_15_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h b/variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h new file mode 100644 index 0000000000..6edccbfebb --- /dev/null +++ b/variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h @@ -0,0 +1,72 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_7_ALT5 = PB_7 | ALT5, +PB_8_ALT1 = PB_8 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, +PC_15_ALT1 = PC_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C051G(6-8)U/boards_entry.txt b/variants/STM32C0xx/C051G(6-8)U/boards_entry.txt new file mode 100644 index 0000000000..879ef4fbf2 --- /dev/null +++ b/variants/STM32C0xx/C051G(6-8)U/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C051G6Ux +GenC0.menu.pnum.GENERIC_C051G6UX=Generic C051G6Ux +GenC0.menu.pnum.GENERIC_C051G6UX.upload.maximum_size=32768 +GenC0.menu.pnum.GENERIC_C051G6UX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051G6UX.build.board=GENERIC_C051G6UX +GenC0.menu.pnum.GENERIC_C051G6UX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051G6UX.build.variant=STM32C0xx/C051G(6-8)U +GenC0.menu.pnum.GENERIC_C051G6UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051G8Ux +GenC0.menu.pnum.GENERIC_C051G8UX=Generic C051G8Ux +GenC0.menu.pnum.GENERIC_C051G8UX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C051G8UX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051G8UX.build.board=GENERIC_C051G8UX +GenC0.menu.pnum.GENERIC_C051G8UX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051G8UX.build.variant=STM32C0xx/C051G(6-8)U +GenC0.menu.pnum.GENERIC_C051G8UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + diff --git a/variants/STM32C0xx/C051G(6-8)U/generic_clock.c b/variants/STM32C0xx/C051G(6-8)U/generic_clock.c new file mode 100644 index 0000000000..f48445578a --- /dev/null +++ b/variants/STM32C0xx/C051G(6-8)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C051G6UX) || defined(ARDUINO_GENERIC_C051G8UX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C051G(6-8)U/variant_generic.cpp b/variants/STM32C0xx/C051G(6-8)U/variant_generic.cpp new file mode 100644 index 0000000000..c99a1f1e06 --- /dev/null +++ b/variants/STM32C0xx/C051G(6-8)U/variant_generic.cpp @@ -0,0 +1,65 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C051G6UX) || defined(ARDUINO_GENERIC_C051G8UX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_11, // D9/A9 + PA_12, // D10/A10 + PA_13, // D11/A11 + PA_14, // D12/A12 + PA_15, // D13 + PB_0, // D14/A13 + PB_1, // D15/A14 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PC_6, // D22 + PC_14, // D23 + PC_15, // D24 + PF_2 // D25 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 9, // A9, PA11 + 10, // A10, PA12 + 11, // A11, PA13 + 12, // A12, PA14 + 14, // A13, PB0 + 15 // A14, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C051G(6-8)U/variant_generic.h b/variants/STM32C0xx/C051G(6-8)U/variant_generic.h new file mode 100644 index 0000000000..e77bc76d7d --- /dev/null +++ b/variants/STM32C0xx/C051G(6-8)U/variant_generic.h @@ -0,0 +1,183 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA11 PIN_A9 +#define PA12 PIN_A10 +#define PA13 PIN_A11 +#define PA14 PIN_A12 +#define PA15 13 +#define PB0 PIN_A13 +#define PB1 PIN_A14 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PC6 22 +#define PC14 23 +#define PC15 24 +#define PF2 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB7_ALT5 (PB7 | ALT5) +#define PB8_ALT1 (PB8 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) +#define PC15_ALT1 (PC15 | ALT1) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 15 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c new file mode 100644 index 0000000000..ade81c6eac --- /dev/null +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c @@ -0,0 +1,297 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C051K6Tx.xml, STM32C051K6Ux.xml + * STM32C051K8Tx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PB_7_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT4, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT5, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PC_15_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h new file mode 100644 index 0000000000..f70f83fb2d --- /dev/null +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h @@ -0,0 +1,75 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_7_ALT5 = PB_7 | ALT5, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, +PC_15_ALT1 = PC_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/boards_entry.txt b/variants/STM32C0xx/C051K6(T-U)_C051K8T/boards_entry.txt new file mode 100644 index 0000000000..106fbab69f --- /dev/null +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C051K6Tx +GenC0.menu.pnum.GENERIC_C051K6TX=Generic C051K6Tx +GenC0.menu.pnum.GENERIC_C051K6TX.upload.maximum_size=32768 +GenC0.menu.pnum.GENERIC_C051K6TX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051K6TX.build.board=GENERIC_C051K6TX +GenC0.menu.pnum.GENERIC_C051K6TX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051K6TX.build.variant=STM32C0xx/C051K6(T-U)_C051K8T +GenC0.menu.pnum.GENERIC_C051K6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051K6Ux +GenC0.menu.pnum.GENERIC_C051K6UX=Generic C051K6Ux +GenC0.menu.pnum.GENERIC_C051K6UX.upload.maximum_size=32768 +GenC0.menu.pnum.GENERIC_C051K6UX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051K6UX.build.board=GENERIC_C051K6UX +GenC0.menu.pnum.GENERIC_C051K6UX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051K6UX.build.variant=STM32C0xx/C051K6(T-U)_C051K8T +GenC0.menu.pnum.GENERIC_C051K6UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051K8Tx +GenC0.menu.pnum.GENERIC_C051K8TX=Generic C051K8Tx +GenC0.menu.pnum.GENERIC_C051K8TX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C051K8TX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051K8TX.build.board=GENERIC_C051K8TX +GenC0.menu.pnum.GENERIC_C051K8TX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051K8TX.build.variant=STM32C0xx/C051K6(T-U)_C051K8T +GenC0.menu.pnum.GENERIC_C051K8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/generic_clock.c b/variants/STM32C0xx/C051K6(T-U)_C051K8T/generic_clock.c new file mode 100644 index 0000000000..7f52a45e30 --- /dev/null +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C051K6TX) || defined(ARDUINO_GENERIC_C051K6UX) ||\ + defined(ARDUINO_GENERIC_C051K8TX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/variant_generic.cpp b/variants/STM32C0xx/C051K6(T-U)_C051K8T/variant_generic.cpp new file mode 100644 index 0000000000..c6ccbc3a21 --- /dev/null +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/variant_generic.cpp @@ -0,0 +1,71 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C051K6TX) || defined(ARDUINO_GENERIC_C051K6UX) ||\ + defined(ARDUINO_GENERIC_C051K8TX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11/A9 + PA_12, // D12/A10 + PA_13, // D13/A11 + PA_14, // D14/A12 + PA_15, // D15 + PB_0, // D16/A13 + PB_1, // D17/A14 + PB_2, // D18/A15 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PC_6, // D26 + PC_14, // D27 + PC_15, // D28 + PF_2 // D29 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 11, // A9, PA11 + 12, // A10, PA12 + 13, // A11, PA13 + 14, // A12, PA14 + 16, // A13, PB0 + 17, // A14, PB1 + 18 // A15, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/variant_generic.h b/variants/STM32C0xx/C051K6(T-U)_C051K8T/variant_generic.h new file mode 100644 index 0000000000..aae3feeba3 --- /dev/null +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/variant_generic.h @@ -0,0 +1,190 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 PIN_A9 +#define PA12 PIN_A10 +#define PA13 PIN_A11 +#define PA14 PIN_A12 +#define PA15 15 +#define PB0 PIN_A13 +#define PB1 PIN_A14 +#define PB2 PIN_A15 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PC6 26 +#define PC14 27 +#define PC15 28 +#define PF2 29 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB7_ALT5 (PB7 | ALT5) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) +#define PC15_ALT1 (PC15 | ALT1) + +#define NUM_DIGITAL_PINS 30 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c index 0afb0d1800..e1afb3bfbc 100644 --- a/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071C8Tx.xml, STM32C071C8Ux.xml * STM32C071CBTx.xml, STM32C071CBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c b/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c index 72f7943489..0fbaa25891 100644 --- a/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071C8TxN.xml, STM32C071C8UxN.xml * STM32C071CBTxN.xml, STM32C071CBUxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c b/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c index 9c983265e1..14733f00a5 100644 --- a/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c +++ b/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071F8PxN.xml, STM32C071FBPxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c b/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c index 06a564f0ef..b6ddb25228 100644 --- a/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c +++ b/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071F8Px.xml, STM32C071FBPx.xml * STM32C071FBYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c b/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c index 4fe6d36766..e4b82ff0fc 100644 --- a/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c +++ b/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071G8Ux.xml, STM32C071GBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c b/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c index 5a124487c8..5b1a72336c 100644 --- a/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c +++ b/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071G8UxN.xml, STM32C071GBUxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c index 75295efef4..cff851b78c 100644 --- a/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071K8Tx.xml, STM32C071K8Ux.xml * STM32C071KBTx.xml, STM32C071KBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c b/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c index 90c5147842..492941d956 100644 --- a/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071K8TxN.xml, STM32C071K8UxN.xml * STM32C071KBTxN.xml, STM32C071KBUxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c b/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c index bff035d80c..dba5e55619 100644 --- a/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c +++ b/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071R8Tx.xml, STM32C071RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c b/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c index e698887588..758508d733 100644 --- a/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071R8TxN.xml, STM32C071RBIxN.xml * STM32C071RBTxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..03dfd849d3 --- /dev/null +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c @@ -0,0 +1,345 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C091CBTx.xml, STM32C091CBUx.xml + * STM32C091CCTx.xml, STM32C091CCUx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {PB_10, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC1_IN20 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC1_IN21 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 22, 0)}, // ADC1_IN22 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PC_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PD_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PD_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PD_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PD_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PF_0, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1 + {PF_1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..ccdbd909c2 --- /dev/null +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h @@ -0,0 +1,82 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/boards_entry.txt b/variants/STM32C0xx/C091C(B-C)(T-U)/boards_entry.txt new file mode 100644 index 0000000000..f43792a52d --- /dev/null +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C091CBTx +GenC0.menu.pnum.GENERIC_C091CBTX=Generic C091CBTx +GenC0.menu.pnum.GENERIC_C091CBTX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C091CBTX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091CBTX.build.board=GENERIC_C091CBTX +GenC0.menu.pnum.GENERIC_C091CBTX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091CBTX.build.variant=STM32C0xx/C091C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C091CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091CBUx +GenC0.menu.pnum.GENERIC_C091CBUX=Generic C091CBUx +GenC0.menu.pnum.GENERIC_C091CBUX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C091CBUX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091CBUX.build.board=GENERIC_C091CBUX +GenC0.menu.pnum.GENERIC_C091CBUX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091CBUX.build.variant=STM32C0xx/C091C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C091CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091CCTx +GenC0.menu.pnum.GENERIC_C091CCTX=Generic C091CCTx +GenC0.menu.pnum.GENERIC_C091CCTX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091CCTX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091CCTX.build.board=GENERIC_C091CCTX +GenC0.menu.pnum.GENERIC_C091CCTX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091CCTX.build.variant=STM32C0xx/C091C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C091CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091CCUx +GenC0.menu.pnum.GENERIC_C091CCUX=Generic C091CCUx +GenC0.menu.pnum.GENERIC_C091CCUX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091CCUX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091CCUX.build.board=GENERIC_C091CCUX +GenC0.menu.pnum.GENERIC_C091CCUX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091CCUX.build.variant=STM32C0xx/C091C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C091CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/generic_clock.c b/variants/STM32C0xx/C091C(B-C)(T-U)/generic_clock.c new file mode 100644 index 0000000000..55d31f2262 --- /dev/null +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091CBTX) || defined(ARDUINO_GENERIC_C091CBUX) ||\ + defined(ARDUINO_GENERIC_C091CCTX) || defined(ARDUINO_GENERIC_C091CCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/variant_generic.cpp b/variants/STM32C0xx/C091C(B-C)(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..3fc7844e78 --- /dev/null +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/variant_generic.cpp @@ -0,0 +1,87 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091CBTX) || defined(ARDUINO_GENERIC_C091CBUX) ||\ + defined(ARDUINO_GENERIC_C091CCTX) || defined(ARDUINO_GENERIC_C091CCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13/A9 + PA_14, // D14/A10 + PA_15, // D15 + PB_0, // D16/A11 + PB_1, // D17/A12 + PB_2, // D18/A13 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26/A14 + PB_11, // D27/A15 + PB_12, // D28/A16 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_6, // D32 + PC_7, // D33 + PC_13, // D34 + PC_14, // D35 + PC_15, // D36 + PD_0, // D37 + PD_1, // D38 + PD_2, // D39 + PD_3, // D40 + PF_0, // D41 + PF_1, // D42 + PF_2, // D43 + PF_3 // D44 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 13, // A9, PA13 + 14, // A10, PA14 + 16, // A11, PB0 + 17, // A12, PB1 + 18, // A13, PB2 + 26, // A14, PB10 + 27, // A15, PB11 + 28 // A16, PB12 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/variant_generic.h b/variants/STM32C0xx/C091C(B-C)(T-U)/variant_generic.h new file mode 100644 index 0000000000..429055a757 --- /dev/null +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/variant_generic.h @@ -0,0 +1,212 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 15 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 PIN_A14 +#define PB11 PIN_A15 +#define PB12 PIN_A16 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC6 32 +#define PC7 33 +#define PC13 34 +#define PC14 35 +#define PC15 36 +#define PD0 37 +#define PD1 38 +#define PD2 39 +#define PD3 40 +#define PF0 41 +#define PF1 42 +#define PF2 43 +#define PF3 44 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 45 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c new file mode 100644 index 0000000000..ed54c3d937 --- /dev/null +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c @@ -0,0 +1,288 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C091ECYx.xml, STM32C091FBPx.xml + * STM32C091FCPx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h new file mode 100644 index 0000000000..6f63f893c7 --- /dev/null +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h @@ -0,0 +1,73 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/boards_entry.txt b/variants/STM32C0xx/C091ECY_C091F(B-C)P/boards_entry.txt new file mode 100644 index 0000000000..47d3c7586a --- /dev/null +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C091ECYx +GenC0.menu.pnum.GENERIC_C091ECYX=Generic C091ECYx +GenC0.menu.pnum.GENERIC_C091ECYX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091ECYX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091ECYX.build.board=GENERIC_C091ECYX +GenC0.menu.pnum.GENERIC_C091ECYX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091ECYX.build.variant=STM32C0xx/C091ECY_C091F(B-C)P +GenC0.menu.pnum.GENERIC_C091ECYX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091FBPx +GenC0.menu.pnum.GENERIC_C091FBPX=Generic C091FBPx +GenC0.menu.pnum.GENERIC_C091FBPX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C091FBPX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091FBPX.build.board=GENERIC_C091FBPX +GenC0.menu.pnum.GENERIC_C091FBPX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091FBPX.build.variant=STM32C0xx/C091ECY_C091F(B-C)P +GenC0.menu.pnum.GENERIC_C091FBPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091FCPx +GenC0.menu.pnum.GENERIC_C091FCPX=Generic C091FCPx +GenC0.menu.pnum.GENERIC_C091FCPX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091FCPX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091FCPX.build.board=GENERIC_C091FCPX +GenC0.menu.pnum.GENERIC_C091FCPX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091FCPX.build.variant=STM32C0xx/C091ECY_C091F(B-C)P +GenC0.menu.pnum.GENERIC_C091FCPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/generic_clock.c b/variants/STM32C0xx/C091ECY_C091F(B-C)P/generic_clock.c new file mode 100644 index 0000000000..297155644e --- /dev/null +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091ECYX) || defined(ARDUINO_GENERIC_C091FBPX) ||\ + defined(ARDUINO_GENERIC_C091FCPX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/variant_generic.cpp b/variants/STM32C0xx/C091ECY_C091F(B-C)P/variant_generic.cpp new file mode 100644 index 0000000000..fc74238627 --- /dev/null +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/variant_generic.cpp @@ -0,0 +1,65 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091ECYX) || defined(ARDUINO_GENERIC_C091FBPX) ||\ + defined(ARDUINO_GENERIC_C091FCPX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_11, // D9 + PA_12, // D10 + PA_13, // D11/A9 + PA_14, // D12/A10 + PA_15, // D13 + PB_0, // D14/A11 + PB_1, // D15/A12 + PB_2, // D16/A13 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PC_14, // D23 + PC_15, // D24 + PF_2 // D25 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 11, // A9, PA13 + 12, // A10, PA14 + 14, // A11, PB0 + 15, // A12, PB1 + 16 // A13, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/variant_generic.h b/variants/STM32C0xx/C091ECY_C091F(B-C)P/variant_generic.h new file mode 100644 index 0000000000..f51c0a7554 --- /dev/null +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/variant_generic.h @@ -0,0 +1,184 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA11 9 +#define PA12 10 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 13 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PC14 23 +#define PC15 24 +#define PF2 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 14 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c b/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c new file mode 100644 index 0000000000..0af8c26f6e --- /dev/null +++ b/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c @@ -0,0 +1,285 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C091GBUx.xml, STM32C091GCUx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h b/variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h new file mode 100644 index 0000000000..c9586ee36a --- /dev/null +++ b/variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h @@ -0,0 +1,74 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C091G(B-C)U/boards_entry.txt b/variants/STM32C0xx/C091G(B-C)U/boards_entry.txt new file mode 100644 index 0000000000..af03672731 --- /dev/null +++ b/variants/STM32C0xx/C091G(B-C)U/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C091GBUx +GenC0.menu.pnum.GENERIC_C091GBUX=Generic C091GBUx +GenC0.menu.pnum.GENERIC_C091GBUX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C091GBUX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091GBUX.build.board=GENERIC_C091GBUX +GenC0.menu.pnum.GENERIC_C091GBUX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091GBUX.build.variant=STM32C0xx/C091G(B-C)U +GenC0.menu.pnum.GENERIC_C091GBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091GCUx +GenC0.menu.pnum.GENERIC_C091GCUX=Generic C091GCUx +GenC0.menu.pnum.GENERIC_C091GCUX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091GCUX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091GCUX.build.board=GENERIC_C091GCUX +GenC0.menu.pnum.GENERIC_C091GCUX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091GCUX.build.variant=STM32C0xx/C091G(B-C)U +GenC0.menu.pnum.GENERIC_C091GCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + diff --git a/variants/STM32C0xx/C091G(B-C)U/generic_clock.c b/variants/STM32C0xx/C091G(B-C)U/generic_clock.c new file mode 100644 index 0000000000..8a2dbea33a --- /dev/null +++ b/variants/STM32C0xx/C091G(B-C)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091GBUX) || defined(ARDUINO_GENERIC_C091GCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091G(B-C)U/variant_generic.cpp b/variants/STM32C0xx/C091G(B-C)U/variant_generic.cpp new file mode 100644 index 0000000000..3ff60d48d5 --- /dev/null +++ b/variants/STM32C0xx/C091G(B-C)U/variant_generic.cpp @@ -0,0 +1,63 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091GBUX) || defined(ARDUINO_GENERIC_C091GCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_11, // D9 + PA_12, // D10 + PA_13, // D11/A9 + PA_14, // D12/A10 + PA_15, // D13 + PB_0, // D14/A11 + PB_1, // D15/A12 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PC_6, // D22 + PC_14, // D23 + PC_15, // D24 + PF_2 // D25 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 11, // A9, PA13 + 12, // A10, PA14 + 14, // A11, PB0 + 15 // A12, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091G(B-C)U/variant_generic.h b/variants/STM32C0xx/C091G(B-C)U/variant_generic.h new file mode 100644 index 0000000000..8917d4ad35 --- /dev/null +++ b/variants/STM32C0xx/C091G(B-C)U/variant_generic.h @@ -0,0 +1,185 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA11 9 +#define PA12 10 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 13 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PC6 22 +#define PC14 23 +#define PC15 24 +#define PF2 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 13 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..da1de4fd5f --- /dev/null +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c @@ -0,0 +1,306 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C091KBTx.xml, STM32C091KBUx.xml + * STM32C091KCTx.xml, STM32C091KCUx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..c393d2c004 --- /dev/null +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h @@ -0,0 +1,77 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/boards_entry.txt b/variants/STM32C0xx/C091K(B-C)(T-U)/boards_entry.txt new file mode 100644 index 0000000000..e47ea869b9 --- /dev/null +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C091KBTx +GenC0.menu.pnum.GENERIC_C091KBTX=Generic C091KBTx +GenC0.menu.pnum.GENERIC_C091KBTX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C091KBTX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091KBTX.build.board=GENERIC_C091KBTX +GenC0.menu.pnum.GENERIC_C091KBTX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091KBTX.build.variant=STM32C0xx/C091K(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C091KBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091KBUx +GenC0.menu.pnum.GENERIC_C091KBUX=Generic C091KBUx +GenC0.menu.pnum.GENERIC_C091KBUX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C091KBUX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091KBUX.build.board=GENERIC_C091KBUX +GenC0.menu.pnum.GENERIC_C091KBUX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091KBUX.build.variant=STM32C0xx/C091K(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C091KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091KCTx +GenC0.menu.pnum.GENERIC_C091KCTX=Generic C091KCTx +GenC0.menu.pnum.GENERIC_C091KCTX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091KCTX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091KCTX.build.board=GENERIC_C091KCTX +GenC0.menu.pnum.GENERIC_C091KCTX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091KCTX.build.variant=STM32C0xx/C091K(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C091KCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091KCUx +GenC0.menu.pnum.GENERIC_C091KCUX=Generic C091KCUx +GenC0.menu.pnum.GENERIC_C091KCUX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091KCUX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091KCUX.build.board=GENERIC_C091KCUX +GenC0.menu.pnum.GENERIC_C091KCUX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091KCUX.build.variant=STM32C0xx/C091K(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C091KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/generic_clock.c b/variants/STM32C0xx/C091K(B-C)(T-U)/generic_clock.c new file mode 100644 index 0000000000..7480bfd051 --- /dev/null +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091KBTX) || defined(ARDUINO_GENERIC_C091KBUX) ||\ + defined(ARDUINO_GENERIC_C091KCTX) || defined(ARDUINO_GENERIC_C091KCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/variant_generic.cpp b/variants/STM32C0xx/C091K(B-C)(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..47efb19e62 --- /dev/null +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/variant_generic.cpp @@ -0,0 +1,69 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091KBTX) || defined(ARDUINO_GENERIC_C091KBUX) ||\ + defined(ARDUINO_GENERIC_C091KCTX) || defined(ARDUINO_GENERIC_C091KCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13/A9 + PA_14, // D14/A10 + PA_15, // D15 + PB_0, // D16/A11 + PB_1, // D17/A12 + PB_2, // D18/A13 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PC_6, // D26 + PC_14, // D27 + PC_15, // D28 + PF_2 // D29 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 13, // A9, PA13 + 14, // A10, PA14 + 16, // A11, PB0 + 17, // A12, PB1 + 18 // A13, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/variant_generic.h b/variants/STM32C0xx/C091K(B-C)(T-U)/variant_generic.h new file mode 100644 index 0000000000..fb0180f7fe --- /dev/null +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/variant_generic.h @@ -0,0 +1,192 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 15 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PC6 26 +#define PC14 27 +#define PC15 28 +#define PF2 29 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 30 +#define NUM_ANALOG_INPUTS 14 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c new file mode 100644 index 0000000000..0515ec0b01 --- /dev/null +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c @@ -0,0 +1,383 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C091RBTx.xml, STM32C091RCIx.xml + * STM32C091RCTx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {PB_10, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC1_IN20 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC1_IN21 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 22, 0)}, // ADC1_IN22 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 2, 0)}, // TIM15_CH2 + {PC_1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PC_2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 2, 0)}, // TIM15_CH2 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PC_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PC_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PC_8_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PC_9_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PC_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PC_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PC_12, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PD_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PD_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PD_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PD_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PD_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PF_0, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1 + {PF_1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PC_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PC_4_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_10_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_0, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PC_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PC_5_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_11_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PD_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PD_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PD_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h new file mode 100644 index 0000000000..38f8b30764 --- /dev/null +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h @@ -0,0 +1,88 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PC_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/boards_entry.txt b/variants/STM32C0xx/C091RBT_C091RC(I-T)/boards_entry.txt new file mode 100644 index 0000000000..ebe1ffbeb5 --- /dev/null +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C091RBTx +GenC0.menu.pnum.GENERIC_C091RBTX=Generic C091RBTx +GenC0.menu.pnum.GENERIC_C091RBTX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C091RBTX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091RBTX.build.board=GENERIC_C091RBTX +GenC0.menu.pnum.GENERIC_C091RBTX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091RBTX.build.variant=STM32C0xx/C091RBT_C091RC(I-T) +GenC0.menu.pnum.GENERIC_C091RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091RCIx +GenC0.menu.pnum.GENERIC_C091RCIX=Generic C091RCIx +GenC0.menu.pnum.GENERIC_C091RCIX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091RCIX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091RCIX.build.board=GENERIC_C091RCIX +GenC0.menu.pnum.GENERIC_C091RCIX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091RCIX.build.variant=STM32C0xx/C091RBT_C091RC(I-T) +GenC0.menu.pnum.GENERIC_C091RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + +# Generic C091RCTx +GenC0.menu.pnum.GENERIC_C091RCTX=Generic C091RCTx +GenC0.menu.pnum.GENERIC_C091RCTX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C091RCTX.upload.maximum_data_size=36864 +GenC0.menu.pnum.GENERIC_C091RCTX.build.board=GENERIC_C091RCTX +GenC0.menu.pnum.GENERIC_C091RCTX.build.product_line=STM32C091xx +GenC0.menu.pnum.GENERIC_C091RCTX.build.variant=STM32C0xx/C091RBT_C091RC(I-T) +GenC0.menu.pnum.GENERIC_C091RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C091.svd + diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/generic_clock.c b/variants/STM32C0xx/C091RBT_C091RC(I-T)/generic_clock.c new file mode 100644 index 0000000000..c0e14c4289 --- /dev/null +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091RBTX) || defined(ARDUINO_GENERIC_C091RCIX) ||\ + defined(ARDUINO_GENERIC_C091RCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/variant_generic.cpp b/variants/STM32C0xx/C091RBT_C091RC(I-T)/variant_generic.cpp new file mode 100644 index 0000000000..32dac6e20d --- /dev/null +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/variant_generic.cpp @@ -0,0 +1,105 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C091RBTX) || defined(ARDUINO_GENERIC_C091RCIX) ||\ + defined(ARDUINO_GENERIC_C091RCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13/A9 + PA_14, // D14/A10 + PA_15, // D15 + PB_0, // D16/A11 + PB_1, // D17/A12 + PB_2, // D18/A13 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26/A14 + PB_11, // D27/A15 + PB_12, // D28/A16 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32 + PC_1, // D33 + PC_2, // D34 + PC_3, // D35 + PC_4, // D36/A17 + PC_5, // D37/A18 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_3, // D51 + PD_4, // D52 + PD_5, // D53 + PD_6, // D54 + PD_8, // D55 + PD_9, // D56 + PF_0, // D57 + PF_1, // D58 + PF_2, // D59 + PF_3 // D60 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 13, // A9, PA13 + 14, // A10, PA14 + 16, // A11, PB0 + 17, // A12, PB1 + 18, // A13, PB2 + 26, // A14, PB10 + 27, // A15, PB11 + 28, // A16, PB12 + 36, // A17, PC4 + 37 // A18, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/variant_generic.h b/variants/STM32C0xx/C091RBT_C091RC(I-T)/variant_generic.h new file mode 100644 index 0000000000..20a0ea46fc --- /dev/null +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/variant_generic.h @@ -0,0 +1,234 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 15 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 PIN_A14 +#define PB11 PIN_A15 +#define PB12 PIN_A16 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 PIN_A17 +#define PC5 PIN_A18 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD8 55 +#define PD9 56 +#define PF0 57 +#define PF1 58 +#define PF2 59 +#define PF3 60 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 61 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PeripheralPins.c b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PeripheralPins.c new file mode 100644 index 0000000000..2340b5a0b0 --- /dev/null +++ b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PeripheralPins.c @@ -0,0 +1,412 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C092CBTx.xml, STM32C092RBTx.xml + * STM32C092RCIx.xml, STM32C092RCTx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {PB_10, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC1_IN20 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC1_IN21 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 22, 0)}, // ADC1_IN22 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 2, 0)}, // TIM15_CH2 + {PC_1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PC_2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 2, 0)}, // TIM15_CH2 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PC_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PC_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PC_8_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PC_9_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PC_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PC_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PC_12, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PD_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PD_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PD_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PD_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PD_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PF_0, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1 + {PF_1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PC_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PC_4_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_10_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_0, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PC_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PC_5_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_11_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PD_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PD_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PD_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_FDCAN1)}, + {PB_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PC_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PC_4, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_EVENTOUT)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_FDCAN1)}, + {PB_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PC_3, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PC_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_FDCAN1)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h new file mode 100644 index 0000000000..38f8b30764 --- /dev/null +++ b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h @@ -0,0 +1,88 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PC_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/boards_entry.txt b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/boards_entry.txt new file mode 100644 index 0000000000..c043a2e699 --- /dev/null +++ b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C092CBTx +GenC0.menu.pnum.GENERIC_C092CBTX=Generic C092CBTx +GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CBTX.build.board=GENERIC_C092CBTX +GenC0.menu.pnum.GENERIC_C092CBTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092RBTx +GenC0.menu.pnum.GENERIC_C092RBTX=Generic C092RBTx +GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092RBTX.build.board=GENERIC_C092RBTX +GenC0.menu.pnum.GENERIC_C092RBTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092RBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092RCIx +GenC0.menu.pnum.GENERIC_C092RCIX=Generic C092RCIx +GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092RCIX.build.board=GENERIC_C092RCIX +GenC0.menu.pnum.GENERIC_C092RCIX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092RCIX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092RCTx +GenC0.menu.pnum.GENERIC_C092RCTX=Generic C092RCTx +GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092RCTX.build.board=GENERIC_C092RCTX +GenC0.menu.pnum.GENERIC_C092RCTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092RCTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/generic_clock.c b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/generic_clock.c new file mode 100644 index 0000000000..e9ca7b29a8 --- /dev/null +++ b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092CBTX) || defined(ARDUINO_GENERIC_C092RBTX) ||\ + defined(ARDUINO_GENERIC_C092RCIX) || defined(ARDUINO_GENERIC_C092RCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.cpp b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.cpp new file mode 100644 index 0000000000..abfce8b085 --- /dev/null +++ b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.cpp @@ -0,0 +1,105 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092CBTX) || defined(ARDUINO_GENERIC_C092RBTX) ||\ + defined(ARDUINO_GENERIC_C092RCIX) || defined(ARDUINO_GENERIC_C092RCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13/A9 + PA_14, // D14/A10 + PA_15, // D15 + PB_0, // D16/A11 + PB_1, // D17/A12 + PB_2, // D18/A13 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26/A14 + PB_11, // D27/A15 + PB_12, // D28/A16 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32 + PC_1, // D33 + PC_2, // D34 + PC_3, // D35 + PC_4, // D36/A17 + PC_5, // D37/A18 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_3, // D51 + PD_4, // D52 + PD_5, // D53 + PD_6, // D54 + PD_8, // D55 + PD_9, // D56 + PF_0, // D57 + PF_1, // D58 + PF_2, // D59 + PF_3 // D60 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 13, // A9, PA13 + 14, // A10, PA14 + 16, // A11, PB0 + 17, // A12, PB1 + 18, // A13, PB2 + 26, // A14, PB10 + 27, // A15, PB11 + 28, // A16, PB12 + 36, // A17, PC4 + 37 // A18, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.h b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.h new file mode 100644 index 0000000000..20a0ea46fc --- /dev/null +++ b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.h @@ -0,0 +1,234 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 15 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 PIN_A14 +#define PB11 PIN_A15 +#define PB12 PIN_A16 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 PIN_A17 +#define PC5 PIN_A18 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD8 55 +#define PD9 56 +#define PF0 57 +#define PF1 58 +#define PF2 59 +#define PF3 60 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 61 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/PeripheralPins.c b/variants/STM32C0xx/C092CBU_C092CC(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..0012436e44 --- /dev/null +++ b/variants/STM32C0xx/C092CBU_C092CC(T-U)/PeripheralPins.c @@ -0,0 +1,370 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C092CBUx.xml, STM32C092CCTx.xml + * STM32C092CCUx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {PB_10, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC1_IN20 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC1_IN21 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 22, 0)}, // ADC1_IN22 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PC_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PD_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PD_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PD_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PD_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PF_0, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1 + {PF_1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_FDCAN1)}, + {PB_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_EVENTOUT)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_FDCAN1)}, + {PB_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_FDCAN1)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h b/variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..ccdbd909c2 --- /dev/null +++ b/variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h @@ -0,0 +1,82 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/boards_entry.txt b/variants/STM32C0xx/C092CBU_C092CC(T-U)/boards_entry.txt new file mode 100644 index 0000000000..ea08295a93 --- /dev/null +++ b/variants/STM32C0xx/C092CBU_C092CC(T-U)/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C092CBUx +GenC0.menu.pnum.GENERIC_C092CBUX=Generic C092CBUx +GenC0.menu.pnum.GENERIC_C092CBUX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092CBUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CBUX.build.board=GENERIC_C092CBUX +GenC0.menu.pnum.GENERIC_C092CBUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CBUX.build.variant=STM32C0xx/C092CBU_C092CC(T-U) +GenC0.menu.pnum.GENERIC_C092CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092CCTx +GenC0.menu.pnum.GENERIC_C092CCTX=Generic C092CCTx +GenC0.menu.pnum.GENERIC_C092CCTX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092CCTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CCTX.build.board=GENERIC_C092CCTX +GenC0.menu.pnum.GENERIC_C092CCTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CCTX.build.variant=STM32C0xx/C092CBU_C092CC(T-U) +GenC0.menu.pnum.GENERIC_C092CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092CCUx +GenC0.menu.pnum.GENERIC_C092CCUX=Generic C092CCUx +GenC0.menu.pnum.GENERIC_C092CCUX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092CCUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CCUX.build.board=GENERIC_C092CCUX +GenC0.menu.pnum.GENERIC_C092CCUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CCUX.build.variant=STM32C0xx/C092CBU_C092CC(T-U) +GenC0.menu.pnum.GENERIC_C092CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/generic_clock.c b/variants/STM32C0xx/C092CBU_C092CC(T-U)/generic_clock.c new file mode 100644 index 0000000000..a96fd6df0c --- /dev/null +++ b/variants/STM32C0xx/C092CBU_C092CC(T-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092CBUX) || defined(ARDUINO_GENERIC_C092CCTX) ||\ + defined(ARDUINO_GENERIC_C092CCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.cpp b/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..4802cae09e --- /dev/null +++ b/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.cpp @@ -0,0 +1,87 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092CBUX) || defined(ARDUINO_GENERIC_C092CCTX) ||\ + defined(ARDUINO_GENERIC_C092CCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13/A9 + PA_14, // D14/A10 + PA_15, // D15 + PB_0, // D16/A11 + PB_1, // D17/A12 + PB_2, // D18/A13 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26/A14 + PB_11, // D27/A15 + PB_12, // D28/A16 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_6, // D32 + PC_7, // D33 + PC_13, // D34 + PC_14, // D35 + PC_15, // D36 + PD_0, // D37 + PD_1, // D38 + PD_2, // D39 + PD_3, // D40 + PF_0, // D41 + PF_1, // D42 + PF_2, // D43 + PF_3 // D44 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 13, // A9, PA13 + 14, // A10, PA14 + 16, // A11, PB0 + 17, // A12, PB1 + 18, // A13, PB2 + 26, // A14, PB10 + 27, // A15, PB11 + 28 // A16, PB12 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.h b/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.h new file mode 100644 index 0000000000..429055a757 --- /dev/null +++ b/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.h @@ -0,0 +1,212 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 15 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 PIN_A14 +#define PB11 PIN_A15 +#define PB12 PIN_A16 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC6 32 +#define PC7 33 +#define PC13 34 +#define PC14 35 +#define PC15 36 +#define PD0 37 +#define PD1 38 +#define PD2 39 +#define PD3 40 +#define PF0 41 +#define PF1 42 +#define PF2 43 +#define PF3 44 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 45 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c new file mode 100644 index 0000000000..b70b8533fc --- /dev/null +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c @@ -0,0 +1,308 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C092ECYx.xml, STM32C092FBPx.xml + * STM32C092FCPx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_EVENTOUT)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h new file mode 100644 index 0000000000..6f63f893c7 --- /dev/null +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h @@ -0,0 +1,73 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/boards_entry.txt b/variants/STM32C0xx/C092ECY_C092F(B-C)P/boards_entry.txt new file mode 100644 index 0000000000..665af612e7 --- /dev/null +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C092ECYx +GenC0.menu.pnum.GENERIC_C092ECYX=Generic C092ECYx +GenC0.menu.pnum.GENERIC_C092ECYX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092ECYX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092ECYX.build.board=GENERIC_C092ECYX +GenC0.menu.pnum.GENERIC_C092ECYX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092ECYX.build.variant=STM32C0xx/C092ECY_C092F(B-C)P +GenC0.menu.pnum.GENERIC_C092ECYX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092FBPx +GenC0.menu.pnum.GENERIC_C092FBPX=Generic C092FBPx +GenC0.menu.pnum.GENERIC_C092FBPX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092FBPX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092FBPX.build.board=GENERIC_C092FBPX +GenC0.menu.pnum.GENERIC_C092FBPX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092FBPX.build.variant=STM32C0xx/C092ECY_C092F(B-C)P +GenC0.menu.pnum.GENERIC_C092FBPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092FCPx +GenC0.menu.pnum.GENERIC_C092FCPX=Generic C092FCPx +GenC0.menu.pnum.GENERIC_C092FCPX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092FCPX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092FCPX.build.board=GENERIC_C092FCPX +GenC0.menu.pnum.GENERIC_C092FCPX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092FCPX.build.variant=STM32C0xx/C092ECY_C092F(B-C)P +GenC0.menu.pnum.GENERIC_C092FCPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/generic_clock.c b/variants/STM32C0xx/C092ECY_C092F(B-C)P/generic_clock.c new file mode 100644 index 0000000000..f88ee5cec2 --- /dev/null +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092ECYX) || defined(ARDUINO_GENERIC_C092FBPX) ||\ + defined(ARDUINO_GENERIC_C092FCPX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/variant_generic.cpp b/variants/STM32C0xx/C092ECY_C092F(B-C)P/variant_generic.cpp new file mode 100644 index 0000000000..9b1d3bf658 --- /dev/null +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/variant_generic.cpp @@ -0,0 +1,65 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092ECYX) || defined(ARDUINO_GENERIC_C092FBPX) ||\ + defined(ARDUINO_GENERIC_C092FCPX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_11, // D9 + PA_12, // D10 + PA_13, // D11/A9 + PA_14, // D12/A10 + PA_15, // D13 + PB_0, // D14/A11 + PB_1, // D15/A12 + PB_2, // D16/A13 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PC_14, // D23 + PC_15, // D24 + PF_2 // D25 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 11, // A9, PA13 + 12, // A10, PA14 + 14, // A11, PB0 + 15, // A12, PB1 + 16 // A13, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/variant_generic.h b/variants/STM32C0xx/C092ECY_C092F(B-C)P/variant_generic.h new file mode 100644 index 0000000000..f51c0a7554 --- /dev/null +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/variant_generic.h @@ -0,0 +1,184 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA11 9 +#define PA12 10 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 13 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PC14 23 +#define PC15 24 +#define PF2 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 14 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c b/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c new file mode 100644 index 0000000000..056695cea3 --- /dev/null +++ b/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c @@ -0,0 +1,305 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C092GBUx.xml, STM32C092GCUx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_EVENTOUT)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h b/variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h new file mode 100644 index 0000000000..c9586ee36a --- /dev/null +++ b/variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h @@ -0,0 +1,74 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C092G(B-C)U/boards_entry.txt b/variants/STM32C0xx/C092G(B-C)U/boards_entry.txt new file mode 100644 index 0000000000..7f4ac7fcfa --- /dev/null +++ b/variants/STM32C0xx/C092G(B-C)U/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C092GBUx +GenC0.menu.pnum.GENERIC_C092GBUX=Generic C092GBUx +GenC0.menu.pnum.GENERIC_C092GBUX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092GBUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092GBUX.build.board=GENERIC_C092GBUX +GenC0.menu.pnum.GENERIC_C092GBUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092GBUX.build.variant=STM32C0xx/C092G(B-C)U +GenC0.menu.pnum.GENERIC_C092GBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092GCUx +GenC0.menu.pnum.GENERIC_C092GCUX=Generic C092GCUx +GenC0.menu.pnum.GENERIC_C092GCUX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092GCUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092GCUX.build.board=GENERIC_C092GCUX +GenC0.menu.pnum.GENERIC_C092GCUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092GCUX.build.variant=STM32C0xx/C092G(B-C)U +GenC0.menu.pnum.GENERIC_C092GCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + diff --git a/variants/STM32C0xx/C092G(B-C)U/generic_clock.c b/variants/STM32C0xx/C092G(B-C)U/generic_clock.c new file mode 100644 index 0000000000..3e3e7162b9 --- /dev/null +++ b/variants/STM32C0xx/C092G(B-C)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092GBUX) || defined(ARDUINO_GENERIC_C092GCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092G(B-C)U/variant_generic.cpp b/variants/STM32C0xx/C092G(B-C)U/variant_generic.cpp new file mode 100644 index 0000000000..64969d6176 --- /dev/null +++ b/variants/STM32C0xx/C092G(B-C)U/variant_generic.cpp @@ -0,0 +1,63 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092GBUX) || defined(ARDUINO_GENERIC_C092GCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_11, // D9 + PA_12, // D10 + PA_13, // D11/A9 + PA_14, // D12/A10 + PA_15, // D13 + PB_0, // D14/A11 + PB_1, // D15/A12 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PC_6, // D22 + PC_14, // D23 + PC_15, // D24 + PF_2 // D25 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 11, // A9, PA13 + 12, // A10, PA14 + 14, // A11, PB0 + 15 // A12, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092G(B-C)U/variant_generic.h b/variants/STM32C0xx/C092G(B-C)U/variant_generic.h new file mode 100644 index 0000000000..8917d4ad35 --- /dev/null +++ b/variants/STM32C0xx/C092G(B-C)U/variant_generic.h @@ -0,0 +1,185 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA11 9 +#define PA12 10 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 13 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PC6 22 +#define PC14 23 +#define PC15 24 +#define PF2 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 13 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..31bad4aa5e --- /dev/null +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c @@ -0,0 +1,327 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C092KBTx.xml, STM32C092KBUx.xml + * STM32C092KCTx.xml, STM32C092KCUx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_0_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2 + {PA_1_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3 + {PA_2_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4 + {PA_3_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1 + {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PA_5_ALT2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N + {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N + {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3 + {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4 + {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2 + {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1 + {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PC_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2 + {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3 + {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PC_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PA_15_ALT2, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)}, + {PB_7_ALT1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART4)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PB_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)}, + {PB_6_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)}, + {PB_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_8_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_FDCAN1)}, + {PB_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_EVENTOUT)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_FDCAN1)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF15_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..c393d2c004 --- /dev/null +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h @@ -0,0 +1,77 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_0_ALT2 = PA_0 | ALT2, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_1_ALT3 = PA_1 | ALT3, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_2_ALT3 = PA_2 | ALT3, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_8_ALT4 = PA_8 | ALT4, +PA_8_ALT5 = PA_8 | ALT5, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_1_ALT3 = PB_1 | ALT3, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_6_ALT3 = PB_6 | ALT3, +PB_6_ALT4 = PB_6 | ALT4, +PB_6_ALT5 = PB_6 | ALT5, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_7_ALT3 = PB_7 | ALT3, +PB_7_ALT4 = PB_7 | ALT4, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_14_ALT1 = PC_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* No USB */ diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/boards_entry.txt b/variants/STM32C0xx/C092K(B-C)(T-U)/boards_entry.txt new file mode 100644 index 0000000000..dba937e9cd --- /dev/null +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C092KBTx +GenC0.menu.pnum.GENERIC_C092KBTX=Generic C092KBTx +GenC0.menu.pnum.GENERIC_C092KBTX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092KBTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092KBTX.build.board=GENERIC_C092KBTX +GenC0.menu.pnum.GENERIC_C092KBTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092KBTX.build.variant=STM32C0xx/C092K(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092KBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092KBUx +GenC0.menu.pnum.GENERIC_C092KBUX=Generic C092KBUx +GenC0.menu.pnum.GENERIC_C092KBUX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092KBUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092KBUX.build.board=GENERIC_C092KBUX +GenC0.menu.pnum.GENERIC_C092KBUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092KBUX.build.variant=STM32C0xx/C092K(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092KCTx +GenC0.menu.pnum.GENERIC_C092KCTX=Generic C092KCTx +GenC0.menu.pnum.GENERIC_C092KCTX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092KCTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092KCTX.build.board=GENERIC_C092KCTX +GenC0.menu.pnum.GENERIC_C092KCTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092KCTX.build.variant=STM32C0xx/C092K(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092KCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092KCUx +GenC0.menu.pnum.GENERIC_C092KCUX=Generic C092KCUx +GenC0.menu.pnum.GENERIC_C092KCUX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092KCUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092KCUX.build.board=GENERIC_C092KCUX +GenC0.menu.pnum.GENERIC_C092KCUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092KCUX.build.variant=STM32C0xx/C092K(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/generic_clock.c b/variants/STM32C0xx/C092K(B-C)(T-U)/generic_clock.c new file mode 100644 index 0000000000..2f35caf569 --- /dev/null +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092KBTX) || defined(ARDUINO_GENERIC_C092KBUX) ||\ + defined(ARDUINO_GENERIC_C092KCTX) || defined(ARDUINO_GENERIC_C092KCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/variant_generic.cpp b/variants/STM32C0xx/C092K(B-C)(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..51ae08830b --- /dev/null +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/variant_generic.cpp @@ -0,0 +1,69 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092KBTX) || defined(ARDUINO_GENERIC_C092KBUX) ||\ + defined(ARDUINO_GENERIC_C092KCTX) || defined(ARDUINO_GENERIC_C092KCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13/A9 + PA_14, // D14/A10 + PA_15, // D15 + PB_0, // D16/A11 + PB_1, // D17/A12 + PB_2, // D18/A13 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PC_6, // D26 + PC_14, // D27 + PC_15, // D28 + PF_2 // D29 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 13, // A9, PA13 + 14, // A10, PA14 + 16, // A11, PB0 + 17, // A12, PB1 + 18 // A13, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/variant_generic.h b/variants/STM32C0xx/C092K(B-C)(T-U)/variant_generic.h new file mode 100644 index 0000000000..fb0180f7fe --- /dev/null +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/variant_generic.h @@ -0,0 +1,192 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 PIN_A9 +#define PA14 PIN_A10 +#define PA15 15 +#define PB0 PIN_A11 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PC6 26 +#define PC14 27 +#define PC15 28 +#define PF2 29 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA1_ALT3 (PA1 | ALT3) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA2_ALT3 (PA2 | ALT3) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA8_ALT4 (PA8 | ALT4) +#define PA8_ALT5 (PA8 | ALT5) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB1_ALT3 (PB1 | ALT3) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB6_ALT3 (PB6 | ALT3) +#define PB6_ALT4 (PB6 | ALT4) +#define PB6_ALT5 (PB6 | ALT5) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB7_ALT3 (PB7 | ALT3) +#define PB7_ALT4 (PB7 | ALT4) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC14_ALT1 (PC14 | ALT1) + +#define NUM_DIGITAL_PINS 30 +#define NUM_ANALOG_INPUTS 14 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA8 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA14 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA2 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA6 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM14 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 1c8ce8c9e29df0eb774912e420faff8f659dd345 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 11:24:49 +0100 Subject: [PATCH 010/141] chore(c0): update cmake after variants update Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 244 +++++++++++++++++- .../STM32C0xx/C051C(6-8)(T-U)/CMakeLists.txt | 31 +++ .../C051D8Y_C051F(6-8)P/CMakeLists.txt | 31 +++ variants/STM32C0xx/C051G(6-8)U/CMakeLists.txt | 31 +++ .../C051K6(T-U)_C051K8T/CMakeLists.txt | 31 +++ .../STM32C0xx/C091C(B-C)(T-U)/CMakeLists.txt | 31 +++ .../C091ECY_C091F(B-C)P/CMakeLists.txt | 31 +++ variants/STM32C0xx/C091G(B-C)U/CMakeLists.txt | 31 +++ .../STM32C0xx/C091K(B-C)(T-U)/CMakeLists.txt | 31 +++ .../C091RBT_C091RC(I-T)/CMakeLists.txt | 31 +++ .../CMakeLists.txt | 31 +++ .../C092CBU_C092CC(T-U)/CMakeLists.txt | 31 +++ .../C092ECY_C092F(B-C)P/CMakeLists.txt | 31 +++ variants/STM32C0xx/C092G(B-C)U/CMakeLists.txt | 31 +++ .../STM32C0xx/C092K(B-C)(T-U)/CMakeLists.txt | 31 +++ .../CMakeLists.txt | 1 + 16 files changed, 677 insertions(+), 2 deletions(-) create mode 100644 variants/STM32C0xx/C051C(6-8)(T-U)/CMakeLists.txt create mode 100644 variants/STM32C0xx/C051D8Y_C051F(6-8)P/CMakeLists.txt create mode 100644 variants/STM32C0xx/C051G(6-8)U/CMakeLists.txt create mode 100644 variants/STM32C0xx/C051K6(T-U)_C051K8T/CMakeLists.txt create mode 100644 variants/STM32C0xx/C091C(B-C)(T-U)/CMakeLists.txt create mode 100644 variants/STM32C0xx/C091ECY_C091F(B-C)P/CMakeLists.txt create mode 100644 variants/STM32C0xx/C091G(B-C)U/CMakeLists.txt create mode 100644 variants/STM32C0xx/C091K(B-C)(T-U)/CMakeLists.txt create mode 100644 variants/STM32C0xx/C091RBT_C091RC(I-T)/CMakeLists.txt create mode 100644 variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt create mode 100644 variants/STM32C0xx/C092CBU_C092CC(T-U)/CMakeLists.txt create mode 100644 variants/STM32C0xx/C092ECY_C092F(B-C)P/CMakeLists.txt create mode 100644 variants/STM32C0xx/C092G(B-C)U/CMakeLists.txt create mode 100644 variants/STM32C0xx/C092K(B-C)(T-U)/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 660aa29fa5..5a7465fbc5 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -6481,6 +6481,22 @@ add_library(GENERIC_C011D6YX_serial_none INTERFACE) target_compile_options(GENERIC_C011D6YX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C011D6YX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C011D6YX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C011D6YX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C011D6YX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C011D6YX_usb_HID INTERFACE) +target_compile_options(GENERIC_C011D6YX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C011D6YX_usb_none INTERFACE) +target_compile_options(GENERIC_C011D6YX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C011F4PX # ----------------------------------------------------------------------------- @@ -6535,6 +6551,22 @@ add_library(GENERIC_C011F4PX_serial_none INTERFACE) target_compile_options(GENERIC_C011F4PX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C011F4PX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C011F4PX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C011F4PX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C011F4PX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C011F4PX_usb_HID INTERFACE) +target_compile_options(GENERIC_C011F4PX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C011F4PX_usb_none INTERFACE) +target_compile_options(GENERIC_C011F4PX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C011F4UX # ----------------------------------------------------------------------------- @@ -6589,6 +6621,22 @@ add_library(GENERIC_C011F4UX_serial_none INTERFACE) target_compile_options(GENERIC_C011F4UX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C011F4UX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C011F4UX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C011F4UX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C011F4UX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C011F4UX_usb_HID INTERFACE) +target_compile_options(GENERIC_C011F4UX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C011F4UX_usb_none INTERFACE) +target_compile_options(GENERIC_C011F4UX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C011F6PX # ----------------------------------------------------------------------------- @@ -6643,6 +6691,22 @@ add_library(GENERIC_C011F6PX_serial_none INTERFACE) target_compile_options(GENERIC_C011F6PX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C011F6PX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C011F6PX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C011F6PX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C011F6PX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C011F6PX_usb_HID INTERFACE) +target_compile_options(GENERIC_C011F6PX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C011F6PX_usb_none INTERFACE) +target_compile_options(GENERIC_C011F6PX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C011F6UX # ----------------------------------------------------------------------------- @@ -6697,6 +6761,22 @@ add_library(GENERIC_C011F6UX_serial_none INTERFACE) target_compile_options(GENERIC_C011F6UX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C011F6UX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C011F6UX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C011F6UX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C011F6UX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C011F6UX_usb_HID INTERFACE) +target_compile_options(GENERIC_C011F6UX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C011F6UX_usb_none INTERFACE) +target_compile_options(GENERIC_C011F6UX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C011J4MX # ----------------------------------------------------------------------------- @@ -6751,6 +6831,22 @@ add_library(GENERIC_C011J4MX_serial_none INTERFACE) target_compile_options(GENERIC_C011J4MX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C011J4MX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C011J4MX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C011J4MX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C011J4MX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C011J4MX_usb_HID INTERFACE) +target_compile_options(GENERIC_C011J4MX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C011J4MX_usb_none INTERFACE) +target_compile_options(GENERIC_C011J4MX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C011J6MX # ----------------------------------------------------------------------------- @@ -6805,6 +6901,22 @@ add_library(GENERIC_C011J6MX_serial_none INTERFACE) target_compile_options(GENERIC_C011J6MX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C011J6MX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C011J6MX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C011J6MX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C011J6MX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C011J6MX_usb_HID INTERFACE) +target_compile_options(GENERIC_C011J6MX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C011J6MX_usb_none INTERFACE) +target_compile_options(GENERIC_C011J6MX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C031C4TX # ----------------------------------------------------------------------------- @@ -6859,6 +6971,22 @@ add_library(GENERIC_C031C4TX_serial_none INTERFACE) target_compile_options(GENERIC_C031C4TX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C031C4TX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C031C4TX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C031C4TX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C031C4TX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C031C4TX_usb_HID INTERFACE) +target_compile_options(GENERIC_C031C4TX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C031C4TX_usb_none INTERFACE) +target_compile_options(GENERIC_C031C4TX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C031C4UX # ----------------------------------------------------------------------------- @@ -6913,6 +7041,22 @@ add_library(GENERIC_C031C4UX_serial_none INTERFACE) target_compile_options(GENERIC_C031C4UX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C031C4UX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C031C4UX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C031C4UX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C031C4UX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C031C4UX_usb_HID INTERFACE) +target_compile_options(GENERIC_C031C4UX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C031C4UX_usb_none INTERFACE) +target_compile_options(GENERIC_C031C4UX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C031C6TX # ----------------------------------------------------------------------------- @@ -6967,6 +7111,22 @@ add_library(GENERIC_C031C6TX_serial_none INTERFACE) target_compile_options(GENERIC_C031C6TX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C031C6TX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C031C6TX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C031C6TX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C031C6TX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C031C6TX_usb_HID INTERFACE) +target_compile_options(GENERIC_C031C6TX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C031C6TX_usb_none INTERFACE) +target_compile_options(GENERIC_C031C6TX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C031C6UX # ----------------------------------------------------------------------------- @@ -7021,6 +7181,22 @@ add_library(GENERIC_C031C6UX_serial_none INTERFACE) target_compile_options(GENERIC_C031C6UX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C031C6UX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C031C6UX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C031C6UX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C031C6UX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C031C6UX_usb_HID INTERFACE) +target_compile_options(GENERIC_C031C6UX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C031C6UX_usb_none INTERFACE) +target_compile_options(GENERIC_C031C6UX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C031F4PX # ----------------------------------------------------------------------------- @@ -7075,6 +7251,22 @@ add_library(GENERIC_C031F4PX_serial_none INTERFACE) target_compile_options(GENERIC_C031F4PX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C031F4PX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C031F4PX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C031F4PX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C031F4PX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C031F4PX_usb_HID INTERFACE) +target_compile_options(GENERIC_C031F4PX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C031F4PX_usb_none INTERFACE) +target_compile_options(GENERIC_C031F4PX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C031F6PX # ----------------------------------------------------------------------------- @@ -7129,6 +7321,22 @@ add_library(GENERIC_C031F6PX_serial_none INTERFACE) target_compile_options(GENERIC_C031F6PX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C031F6PX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C031F6PX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C031F6PX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C031F6PX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C031F6PX_usb_HID INTERFACE) +target_compile_options(GENERIC_C031F6PX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C031F6PX_usb_none INTERFACE) +target_compile_options(GENERIC_C031F6PX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C071R8TX # ----------------------------------------------------------------------------- @@ -7183,6 +7391,22 @@ add_library(GENERIC_C071R8TX_serial_none INTERFACE) target_compile_options(GENERIC_C071R8TX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C071R8TX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C071R8TX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C071R8TX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C071R8TX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C071R8TX_usb_HID INTERFACE) +target_compile_options(GENERIC_C071R8TX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C071R8TX_usb_none INTERFACE) +target_compile_options(GENERIC_C071R8TX_usb_none INTERFACE + "SHELL:" +) # GENERIC_C071RBTX # ----------------------------------------------------------------------------- @@ -7237,6 +7461,22 @@ add_library(GENERIC_C071RBTX_serial_none INTERFACE) target_compile_options(GENERIC_C071RBTX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +add_library(GENERIC_C071RBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C071RBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C071RBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C071RBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C071RBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_C071RBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C071RBTX_usb_none INTERFACE) +target_compile_options(GENERIC_C071RBTX_usb_none INTERFACE + "SHELL:" +) # GENERIC_F030C6TX # ----------------------------------------------------------------------------- @@ -103497,7 +103737,7 @@ set(NUCLEO_F429ZI_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F429ZI INTERFACE) target_compile_options(NUCLEO_F429ZI INTERFACE "SHELL:-DSTM32F429xx " - "SHELL:" + "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F429ZI_MCU} @@ -103579,7 +103819,7 @@ set(NUCLEO_F439ZI_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F439ZI INTERFACE) target_compile_options(NUCLEO_F439ZI INTERFACE "SHELL:-DSTM32F439xx " - "SHELL:" + "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F439ZI_MCU} diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/CMakeLists.txt b/variants/STM32C0xx/C051C(6-8)(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/CMakeLists.txt b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C051G(6-8)U/CMakeLists.txt b/variants/STM32C0xx/C051G(6-8)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C051G(6-8)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/CMakeLists.txt b/variants/STM32C0xx/C051K6(T-U)_C051K8T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/CMakeLists.txt b/variants/STM32C0xx/C091C(B-C)(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/CMakeLists.txt b/variants/STM32C0xx/C091ECY_C091F(B-C)P/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C091G(B-C)U/CMakeLists.txt b/variants/STM32C0xx/C091G(B-C)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C091G(B-C)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/CMakeLists.txt b/variants/STM32C0xx/C091K(B-C)(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/CMakeLists.txt b/variants/STM32C0xx/C091RBT_C091RC(I-T)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/CMakeLists.txt b/variants/STM32C0xx/C092CBU_C092CC(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C092CBU_C092CC(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/CMakeLists.txt b/variants/STM32C0xx/C092ECY_C092F(B-C)P/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C092G(B-C)U/CMakeLists.txt b/variants/STM32C0xx/C092G(B-C)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C092G(B-C)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/CMakeLists.txt b/variants/STM32C0xx/C092K(B-C)(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/CMakeLists.txt b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/CMakeLists.txt index 036e45f38c..3c0d9e8d62 100644 --- a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/CMakeLists.txt +++ b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/CMakeLists.txt @@ -21,6 +21,7 @@ target_link_libraries(variant INTERFACE variant_usage) add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c + PeripheralPins_NUCLEO_F4x9ZI.c variant_generic.cpp variant_NUCLEO_F4x9ZI.cpp ) From bd82281c6c723cf1c4f6391883416320913b3005 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 14:17:30 +0100 Subject: [PATCH 011/141] system(c0): update STM32C0xx hal default config Signed-off-by: Frederic Pillon --- system/STM32C0xx/stm32c0xx_hal_conf_default.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/system/STM32C0xx/stm32c0xx_hal_conf_default.h b/system/STM32C0xx/stm32c0xx_hal_conf_default.h index a40896999b..421bd57e16 100644 --- a/system/STM32C0xx/stm32c0xx_hal_conf_default.h +++ b/system/STM32C0xx/stm32c0xx_hal_conf_default.h @@ -44,6 +44,7 @@ extern "C" { #define HAL_CRC_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED +#define HAL_FDCAN_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED @@ -146,7 +147,7 @@ extern "C" { */ #if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ + The real value may vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ /** @@ -246,12 +247,16 @@ in voltage and temperature.*/ #include "stm32c0xx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32c0xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32c0xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_HCD_MODULE_ENABLED - #include "stm32c0xx_hal_hcd.h" +#include "stm32c0xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED @@ -271,7 +276,7 @@ in voltage and temperature.*/ #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED - #include "stm32c0xx_hal_pcd.h" +#include "stm32c0xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED From 62168c06fc0d7c85384193a13556f768e92130fc Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 14:58:15 +0100 Subject: [PATCH 012/141] chore(h5): update variants against CubeMX DB release 6.0.130 Signed-off-by: Frederic Pillon --- .../STM32H5xx/H503CB(T-U)/PeripheralPins.c | 2 +- variants/STM32H5xx/H503EBY/PeripheralPins.c | 2 +- variants/STM32H5xx/H503KBU/PeripheralPins.c | 2 +- variants/STM32H5xx/H503RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H523HEY_H533HEY/PeripheralPins.c | 2 +- .../H523R(C-E)T_H533RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32H5xx/H562A(G-I)I/PeripheralPins.c | 2 +- .../H562I(G-I)(K-T)/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)V/PeripheralPins.c | 2 +- .../STM32H5xx/H562V(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562Z(G-I)T/PeripheralPins.c | 2 +- .../H563A(G-I)I_H573AII/PeripheralPins.c | 2 +- .../H563AIIxQ_H573AIIxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H563IIKxQ_H573IIKxQ/PeripheralPins.c | 2 +- .../H563IITxQ_H573IITxQ/PeripheralPins.c | 2 +- .../H563MIYxQ_H573MIYxQ/PeripheralPins.c | 2 +- .../H563R(G-I)T_H573RIT/PeripheralPins.c | 2 +- .../H563R(G-I)V_H573RIV/PeripheralPins.c | 2 +- .../H563V(G-I)T_H573VIT/PeripheralPins.c | 2 +- .../H563VITxQ_H573VITxQ/PeripheralPins.c | 31 ++-------------- .../H563VITxQ_H573VITxQ/variant_generic.h | 3 -- .../H563Z(G-I)T_H573ZIT/PeripheralPins.c | 2 +- .../H563ZITxQ_H573ZITxQ/PeripheralPins.c | 35 ++----------------- .../H563ZITxQ_H573ZITxQ/variant_generic.h | 3 -- 29 files changed, 29 insertions(+), 93 deletions(-) diff --git a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c index d47a6b438a..2d770273f9 100644 --- a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503CBTx.xml, STM32H503CBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503EBY/PeripheralPins.c b/variants/STM32H5xx/H503EBY/PeripheralPins.c index 26fb3b4e7c..54caaf2adf 100644 --- a/variants/STM32H5xx/H503EBY/PeripheralPins.c +++ b/variants/STM32H5xx/H503EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503EBYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503KBU/PeripheralPins.c b/variants/STM32H5xx/H503KBU/PeripheralPins.c index c63fcede33..d2081ebf37 100644 --- a/variants/STM32H5xx/H503KBU/PeripheralPins.c +++ b/variants/STM32H5xx/H503KBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503KBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503RBT/PeripheralPins.c b/variants/STM32H5xx/H503RBT/PeripheralPins.c index ba086ec5d7..a93b6dca19 100644 --- a/variants/STM32H5xx/H503RBT/PeripheralPins.c +++ b/variants/STM32H5xx/H503RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c index 07ccb7f9e1..e13d588280 100644 --- a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523CCTx.xml, STM32H523CCUx.xml * STM32H523CETx.xml, STM32H523CEUx.xml * STM32H533CETx.xml, STM32H533CEUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c b/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c index 6198bf0b42..3c43680d67 100644 --- a/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c +++ b/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H523HEYx.xml, STM32H533HEYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c b/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c index a9b1f805e9..e79912c09b 100644 --- a/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H523RCTx.xml, STM32H523RETx.xml * STM32H533RETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c index 1da50ce321..7b566cf354 100644 --- a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523VCIx.xml, STM32H523VCTx.xml * STM32H523VEIx.xml, STM32H523VETx.xml * STM32H533VEIx.xml, STM32H533VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c index ad327f81f2..118d501d93 100644 --- a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523ZCJx.xml, STM32H523ZCTx.xml * STM32H523ZEJx.xml, STM32H523ZETx.xml * STM32H533ZEJx.xml, STM32H533ZETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c index ccdc1c466d..2164ce7c93 100644 --- a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c +++ b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562AGIx.xml, STM32H562AIIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c index a98bd5fb83..1480e85bf7 100644 --- a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H562IGKx.xml, STM32H562IGTx.xml * STM32H562IIKx.xml, STM32H562IITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c index f6012fe029..23cdd28a9c 100644 --- a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGTx.xml, STM32H562RITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c index 26d812b5ff..d5a63146f0 100644 --- a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGVx.xml, STM32H562RIVx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c index 53e9184bde..4142a1cb59 100644 --- a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562VGTx.xml, STM32H562VITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c index 46e3fe64b8..5210cd72b4 100644 --- a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562ZGTx.xml, STM32H562ZITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c index 1031384800..62436fda55 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563AGIx.xml, STM32H563AIIx.xml * STM32H573AIIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c index 51450803fb..ad930cad6b 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563AIIxQ.xml, STM32H573AIIxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c index 3b56aadd3c..d1e3fd904a 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H563IGKx.xml, STM32H563IGTx.xml * STM32H563IIKx.xml, STM32H563IITx.xml * STM32H573IIKx.xml, STM32H573IITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c index 6c5542e5b5..83e6959201 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563IIKxQ.xml, STM32H573IIKxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c index 342f9fb7ba..b5c84dbd81 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563IITxQ.xml, STM32H573IITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c index 778bceb4f8..0e2b9fb93a 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563MIYxQ.xml, STM32H573MIYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c index 6c4e385ed6..817e408ae0 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563RGTx.xml, STM32H563RITx.xml * STM32H573RITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c index 9f703d605a..49b7c20107 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563RGVx.xml, STM32H563RIVx.xml * STM32H573RIVx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c index dfc8d5cef0..b4edd95852 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563VGTx.xml, STM32H563VITx.xml * STM32H573VITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c index aef5d2039f..51c5c44915 100644 --- a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563VITxQ.xml, STM32H573VITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -427,34 +427,7 @@ WEAK const PinMap PinMap_CAN_TD[] = { }; #endif -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {NC, NP, 0} -}; -#endif +//*** No ETHERNET *** //*** OCTOSPI *** diff --git a/variants/STM32H5xx/H563VITxQ_H573VITxQ/variant_generic.h b/variants/STM32H5xx/H563VITxQ_H573VITxQ/variant_generic.h index f48587c4f8..43598b1e2d 100644 --- a/variants/STM32H5xx/H563VITxQ_H573VITxQ/variant_generic.h +++ b/variants/STM32H5xx/H563VITxQ_H573VITxQ/variant_generic.h @@ -216,9 +216,6 @@ #if !defined(HAL_DAC_MODULE_DISABLED) #define HAL_DAC_MODULE_ENABLED #endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif #if !defined(HAL_OSPI_MODULE_DISABLED) #define HAL_OSPI_MODULE_ENABLED #endif diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c index 446b400d5b..6ccf6c0d2b 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563ZGTx.xml, STM32H563ZITx.xml * STM32H573ZITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c index 1acb3fb79e..f8ac2494a7 100644 --- a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563ZITxQ.xml, STM32H573ZITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -483,38 +483,7 @@ WEAK const PinMap PinMap_CAN_TD[] = { }; #endif -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {NC, NP, 0} -}; -#endif +//*** No ETHERNET *** //*** OCTOSPI *** diff --git a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/variant_generic.h b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/variant_generic.h index d9e873676d..802ba6287b 100644 --- a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/variant_generic.h +++ b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/variant_generic.h @@ -251,9 +251,6 @@ #if !defined(HAL_DAC_MODULE_DISABLED) #define HAL_DAC_MODULE_ENABLED #endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif #if !defined(HAL_OSPI_MODULE_DISABLED) #define HAL_OSPI_MODULE_ENABLED #endif From 39e47864dbc07eafe052cd4e8547d200415eca34 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 15:05:55 +0100 Subject: [PATCH 013/141] system(U0) update STM32U0xx HAL Drivers to v1.2.0 Included in STM32CubeU0 FW v1.2.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 63 ++++++++++++--- .../Inc/stm32u0xx_hal_pcd.h | 8 ++ .../Inc/stm32u0xx_hal_pcd_ex.h | 1 - .../Inc/stm32u0xx_hal_rcc.h | 2 +- .../Inc/stm32u0xx_ll_usb.h | 39 +++++---- .../Inc/stm32u0xx_ll_utils.h | 1 + .../STM32U0xx_HAL_Driver/Release_Notes.html | 50 ++++++++++-- .../STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c | 2 +- .../Src/stm32u0xx_hal_i2c.c | 79 +++++++++++++------ .../Src/stm32u0xx_hal_pcd.c | 41 ++++++---- .../Src/stm32u0xx_hal_pcd_ex.c | 2 - .../Src/stm32u0xx_hal_timebase_tim_template.c | 69 +++++++++------- .../Src/stm32u0xx_hal_uart.c | 4 +- .../Src/stm32u0xx_ll_usb.c | 73 ++++++++--------- .../Src/stm32u0xx_ll_utils.c | 5 ++ .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 16 files changed, 290 insertions(+), 151 deletions(-) diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 0d7e9cf34b..afaa855825 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -875,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -1012,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1264,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1279,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1466,7 +1481,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) || defined(STM32MP2) +#if defined(STM32U5) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -2014,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -3680,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3931,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4225,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h index b2fe0973ed..e0a9c8da97 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h @@ -462,6 +462,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h index 0a36580a53..141a0838e1 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h index 8a7be48930..7a76870a8e 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h @@ -619,7 +619,7 @@ typedef struct */ /* Flags in the CR register */ #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIDY_Pos)) /*!< HSI Ready flag */ +#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h index a467f73c93..2beeb65b37 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h @@ -53,26 +53,26 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; typedef struct @@ -526,20 +526,17 @@ typedef USB_EPTypeDef USB_DRD_EPTypeDef; \ (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h index b22934c2ed..1cd9ecbacb 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h @@ -294,6 +294,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); /** * @} diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html index 156268ff8b..5d84d76cc0 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html @@ -40,11 +40,45 @@

Purpose

Update History

- +

Main Changes

-

Maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

+

Second maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

Contents

+

HAL and LL driver second maintenance release

+
    +
  • HAL drivers: +
      +
    • HAL UART driver: +
        +
      • Fix DMA Rx abort procedure impact on ongoing UART Tx transfer in polling mode.
        • +
      • +
    • HAL RCC driver: +
        +
      • Minors implementation enhancements.
        • +
      • +
    • LL UTILS driver: +
        +
      • Add LL_SetFlashLatency API based on a call of UTILS_SetFlashLatency.
        • +
      • +
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Backward Compatibility

+
    +
  • Not applicable
    • +
+
+
+
+ +
+

Main Changes

+

Maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

+

Contents

HAL and LL driver maintenance release

  • HAL drivers: @@ -67,11 +101,11 @@

    Contents

-

Known Limitations

+

Known Limitations

  • None
-

Backward Compatibility

+

Backward Compatibility

  • Not applicable
@@ -80,19 +114,19 @@

Backward Compatibility

-

Main Changes

+

Main Changes

First official release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

-

Contents

+

Contents

HAL and LL driver beta version for all peripherals

  • HAL: ADC, CORTEX, COMP, CRC, CRYP, DAC, DMA, EXTI, GPIO, I2C, I2S, IRDA, IWDG, LPTIM, OPAMP, LTDC, PCD, PWR, RCC, RNG, RTC, SMARTCARD, SPI, TIM, UART, USART, WWDG

  • LL: ADC, COMP, CRC, CRS, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, TIM, USART, USB, UTILS

-

Known Limitations

+

Known Limitations

  • None
-

Backward Compatibility

+

Backward Compatibility

  • Not applicable
diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c index dc48e79e7e..1b8961257e 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c @@ -55,7 +55,7 @@ * @brief STM32U0xx HAL Driver version number */ #define __STM32U0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U0xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32U0xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32U0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32U0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U0xx_HAL_VERSION ((__STM32U0xx_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_i2c.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_i2c.c index 6b9c8690ba..efa40a4cce 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_i2c.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_i2c.c @@ -3220,6 +3220,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3277,37 +3279,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -6263,7 +6292,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6419,7 +6448,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6873,7 +6902,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -6913,7 +6942,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -6952,7 +6981,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7030,7 +7059,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7197,15 +7226,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd.c index 61b42db81f..0341786d8b 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd.c @@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1404,7 +1404,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -1809,7 +1809,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -1930,7 +1929,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2006,7 +2005,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2038,11 +2037,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2092,6 +2091,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2103,10 +2108,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2137,7 +2144,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2165,6 +2172,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2177,10 +2190,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2210,7 +2225,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2219,7 +2234,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; @@ -2227,13 +2242,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd_ex.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd_ex.c index cb66616f11..42b6ac0b64 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd_ex.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd_ex.c @@ -242,7 +242,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -279,7 +278,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } - /** * @brief Send LPM message to user layer callback. * @param hpcd PCD handle diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c index aed8fe44bc..fe6e04cc06 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c @@ -53,14 +53,14 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -extern TIM_HandleTypeDef TimHandle; -TIM_HandleTypeDef TimHandle; +static TIM_HandleTypeDef TimHandle; + /* Private function prototypes -----------------------------------------------*/ -void TIM6_DAC_LPTIM1_IRQHandler(void); +void TIM16_IRQHandler(void); /* Private functions ---------------------------------------------------------*/ /** - * @brief This function configures the TIM6 as a time base source. + * @brief This function configures the TIM16 as a time base source. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after @@ -75,15 +75,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uint32_t uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; + HAL_StatusTypeDef status; - /*Configure the TIM6 IRQ priority */ - HAL_NVIC_SetPriority(TIM6_DAC_LPTIM1_IRQn, TickPriority, 0U); - - /* Enable the TIM6 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM6_DAC_LPTIM1_IRQn); - - /* Enable TIM6 clock */ - __HAL_RCC_TIM6_CLK_ENABLE(); + /* Enable TIM16 clock */ + __HAL_RCC_TIM16_CLK_ENABLE(); /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); @@ -91,7 +86,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; - /* Compute TIM6 clock */ + /* Compute TIM16 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) { uwTimclock = HAL_RCC_GetPCLK1Freq(); @@ -101,14 +96,14 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uwTimclock = 2U * HAL_RCC_GetPCLK1Freq(); } - /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + /* Compute the prescaler value to have TIM16 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U); - /* Initialize TIM6 */ - TimHandle.Instance = TIM6; + /* Initialize TIM16 */ + TimHandle.Instance = TIM16; /* Initialize TIMx peripheral as follow: - + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up @@ -117,42 +112,59 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.Prescaler = uwPrescalerValue; TimHandle.Init.ClockDivision = 0U; TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) + + status = HAL_TIM_Base_Init(&TimHandle); + if (status == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ - return HAL_TIM_Base_Start_IT(&TimHandle); + status = HAL_TIM_Base_Start_IT(&TimHandle); + if (status == HAL_OK) + { + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Enable the TIM16 global Interrupt */ + HAL_NVIC_SetPriority(TIM16_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } } - /* Return function status */ - return HAL_ERROR; + /* Enable the TIM16 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM16_IRQn); + + /* Return function status */ + return status; } /** * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling TIM6 update interrupt. + * @note Disable the tick increment by disabling TIM16 update interrupt. * @retval None */ void HAL_SuspendTick(void) { - /* Disable TIM6 update interrupt */ + /* Disable TIM16 update interrupt */ __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE); } /** * @brief Resume Tick increment. - * @note Enable the tick increment by enabling TIM6 update interrupt. + * @note Enable the tick increment by enabling TIM16 update interrupt. * @retval None */ void HAL_ResumeTick(void) { - /* Enable TIM6 update interrupt */ + /* Enable TIM16 update interrupt */ __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE); } /** * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM6 interrupt took place, inside + * @note This function is called when TIM16 interrupt took place, inside * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment * a global variable "uwTick" used as application time base. * @param htim TIM handle @@ -165,9 +177,10 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /** * @brief This function handles TIM interrupt request. + * @param None * @retval None */ -void TIM6_DAC_LPTIM1_IRQHandler(void) +void TIM16_IRQHandler(void) { HAL_TIM_IRQHandler(&TimHandle); } diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c index 88a274288f..6618689f90 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c @@ -1080,6 +1080,9 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) reception services: (+) HAL_UARTEx_RxEventCallback() + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is @@ -3880,7 +3883,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_usb.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_usb.c index 1c84370e4b..d23da79bbf 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_usb.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_usb.c @@ -344,6 +344,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -448,7 +452,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -550,9 +554,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -584,19 +588,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -605,15 +615,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -624,18 +632,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -679,26 +677,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_utils.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_utils.c index 11c6718e91..3743cb55af 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_utils.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_utils.c @@ -558,6 +558,11 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) return status; } +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) +{ + return UTILS_SetFlashLatency(HCLK_Frequency); +} + /** * @brief Function to check that PLL can be modified * @param PLL_InputFrequency PLL input frequency (in Hz) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 3b963a2342..e701797f82 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.13.5 * STM32L5: 1.0.6 * STM32MP1: 1.6.0 - * STM32U0: 1.1.0 + * STM32U0: 1.2.0 * STM32U5: 1.6.0 * STM32WB: 1.14.3 * STM32WBA: 1.4.0 From 6d0d9561a174cd481b550e8425c8d4683abf7712 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 15:05:55 +0100 Subject: [PATCH 014/141] system(U0): update STM32U0xx CMSIS Drivers to v1.2.0 Included in STM32CubeU0 FW v1.2.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32U0xx/Include/stm32u031xx.h | 4 ++++ .../Device/ST/STM32U0xx/Include/stm32u073xx.h | 4 ++++ .../Device/ST/STM32U0xx/Include/stm32u083xx.h | 4 ++++ .../Device/ST/STM32U0xx/Include/stm32u0xx.h | 12 +++++----- .../Device/ST/STM32U0xx/Release_Notes.html | 23 +++++++++++++++---- .../Source/Templates/system_stm32u0xx.c | 2 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 7 files changed, 39 insertions(+), 12 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h index 342d2d408b..30773e1225 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h @@ -706,6 +706,10 @@ typedef struct #define UID_BASE (0x1FFF3E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF3EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF3500UL) + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h index e3d494d543..0d969053e4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h @@ -775,6 +775,10 @@ typedef struct #define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL) + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h index c7da4e5ffb..4c092084e7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h @@ -809,6 +809,10 @@ typedef struct #define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL) + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h index 836da3fdb7..fceae34817 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32U0xx device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * @@ -76,10 +76,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.0.0 + * @brief CMSIS Device version number 1.2.0 */ #define __STM32U0_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32U0_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32U0_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32U0_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32U0_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32U0_CMSIS_VERSION ((__STM32U0_CMSIS_VERSION_MAIN << 24)\ @@ -127,8 +127,8 @@ typedef enum typedef enum { - ERROR = 0, - SUCCESS = !ERROR + SUCCESS = 0, + ERROR = !SUCCESS } ErrorStatus; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html index 4f916bc6cf..d59b66c2a0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html @@ -30,27 +30,42 @@

Release Notes for  STM32U0xx C

Update History

- +

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
      +
    • Fixed the right CFGR_HPRE shift in the SystemCoreClockUpdate API.
      • +
    • Align the ErrorStatus typedef declaration with HAL_StatusTypeDef.
      • +
    • Add the address to use for the bootloader jump service.
      • +
    • +
+

+
+
+
+ +
+

Main Changes

+
    +
  • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual). +
    • Add I2C_CR1_SBC bit definition.
    • Removed the I2C_CR1_SWRST bit definition.
-

+

-

Main Changes

+

Main Changes

  • First official release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
-

+

diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c index 3d01a3cfbf..ab4b081111 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c @@ -327,7 +327,7 @@ void SystemCoreClockUpdate(void) } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U) & 0xFU]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 4cc65c8401..9f902c90db 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.7.4 * STM32L5: 1.0.6 * STM32MP1: 1.6.0 - * STM32U0: 1.0.0 + * STM32U0: 1.2.0 * STM32U5: 1.4.0 * STM32WB: 1.12.2 * STM32WBA: 1.4.0 From f671ecf42d14ee06ff76cf7723a4b96ae052b68a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 15:15:52 +0100 Subject: [PATCH 015/141] chore(U0): update variants against CubeMX DB release 6.0.130 Signed-off-by: Frederic Pillon --- variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c | 2 +- variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c | 2 +- variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c | 2 +- variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c | 2 +- variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c | 2 +- .../STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c | 2 +- variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c | 2 +- variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c | 2 +- variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c | 2 +- variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c | 2 +- .../STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c b/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c index 8139f2df39..bbcd077193 100644 --- a/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031C6Tx.xml, STM32U031C6Ux.xml * STM32U031C8Tx.xml, STM32U031C8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c b/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c index 910afaeee4..c0d26545a9 100644 --- a/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c +++ b/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031F4Px.xml, STM32U031F6Px.xml * STM32U031F8Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c b/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c index 62ce1874de..5f4c81356b 100644 --- a/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c +++ b/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U031G6Yx.xml, STM32U031G8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c b/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c index 5a68d3d7c5..3eb2d757b8 100644 --- a/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c +++ b/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031K4Ux.xml, STM32U031K6Ux.xml * STM32U031K8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c b/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c index 7b64347cb9..af55e3797f 100644 --- a/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c +++ b/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031R6Ix.xml, STM32U031R6Tx.xml * STM32U031R8Ix.xml, STM32U031R8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c index 1421817484..b0cbb2806f 100644 --- a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c +++ b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U073CBTx.xml, STM32U073CBUx.xml * STM32U073CCTx.xml, STM32U073CCUx.xml * STM32U083CCTx.xml, STM32U083CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c index f4b5cb0f02..c6b61ba6e9 100644 --- a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c +++ b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073H8Yx.xml, STM32U073HBYx.xml * STM32U073HCYx.xml, STM32U083HCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c index b43617fe59..fc44d4504d 100644 --- a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c +++ b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073K8Ux.xml, STM32U073KBUx.xml * STM32U073KCUx.xml, STM32U083KCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c index c8488fc360..6dc6fa1841 100644 --- a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c +++ b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073M8Ix.xml, STM32U073MBIx.xml * STM32U073MCIx.xml, STM32U083MCIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c index 64db7f4623..68d8910556 100644 --- a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c +++ b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073M8Tx.xml, STM32U073MBTx.xml * STM32U073MCTx.xml, STM32U083MCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c index a68200a729..29391f2991 100644 --- a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c +++ b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U073RBIx.xml, STM32U073RBTx.xml * STM32U073RCIx.xml, STM32U073RCTx.xml * STM32U083RCIx.xml, STM32U083RCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" From ffb23d6b748001dfd3f8111d37610bb51022bc81 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 4 Dec 2024 15:22:21 +0100 Subject: [PATCH 016/141] fix(openocd): path on windows Fixes #2590 Signed-off-by: Frederic Pillon --- platform.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.txt b/platform.txt index 8858440c3a..3b687213d2 100644 --- a/platform.txt +++ b/platform.txt @@ -244,7 +244,7 @@ tools.openocd_upload.cmd=bin/openocd tools.openocd_upload.cmd.windows=bin/openocd.exe tools.openocd_upload.upload.params.verbose=-d2 tools.openocd_upload.upload.params.quiet=-d0 -tools.openocd_upload.upload.pattern="{path}/{cmd}" {upload.verbose} -f interface/{upload.protocol}.cfg -f target/{openocd.target}.cfg -c "program {build.path}/{build.project_name}.elf verify reset exit" +tools.openocd_upload.upload.pattern="{path}/{cmd}" {upload.verbose} -f interface/{upload.protocol}.cfg -f target/{openocd.target}.cfg -c "program {{build.path}/{build.project_name}.elf} verify reset exit" # # Debugger From aa37c0324fc3a77aadf19fdc7d5ecf23f4e51fe3 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 10:06:52 +0100 Subject: [PATCH 017/141] chore: allow to not disable UCPD dead battery Closes #2576. Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/hw_config.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libraries/SrcWrapper/src/stm32/hw_config.c b/libraries/SrcWrapper/src/stm32/hw_config.c index efdb1dcb5a..8b7f7c61cc 100644 --- a/libraries/SrcWrapper/src/stm32/hw_config.c +++ b/libraries/SrcWrapper/src/stm32/hw_config.c @@ -45,6 +45,7 @@ void hw_config_init(void) { configIPClock(); +#if !defined (SKIP_DISABLING_UCPD_DEAD_BATTERY) #if defined(PWR_CR3_UCPD_DBDIS) || defined(PWR_UCPDR_UCPD_DBDIS) /* Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_PWREx_DisableUCPDDeadBattery(); @@ -53,6 +54,7 @@ void hw_config_init(void) /* Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE); #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ +#endif /* !SKIP_DISABLING_UCPD_DEAD_BATTERY */ #if defined(PWR_SVMCR_ASV) HAL_PWREx_EnableVddA(); From a132e20b9e0d177c1ac2a171a17a9e928d5e3028 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 17:09:17 +0100 Subject: [PATCH 018/141] system(H7) update STM32H7xx HAL Drivers to v1.11.5 Included in STM32CubeH7 FW v1.12.1 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 84 +- .../STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h | 6 + .../Inc/stm32h7xx_hal_adc.h | 6 +- .../Inc/stm32h7xx_hal_adc_ex.h | 82 +- .../Inc/stm32h7xx_hal_comp.h | 6 +- .../Inc/stm32h7xx_hal_conf_template.h | 8 + .../Inc/stm32h7xx_hal_cordic.h | 21 +- .../Inc/stm32h7xx_hal_cortex.h | 2 +- .../Inc/stm32h7xx_hal_cryp.h | 4 +- .../Inc/stm32h7xx_hal_cryp_ex.h | 4 +- .../Inc/stm32h7xx_hal_dac.h | 11 +- .../Inc/stm32h7xx_hal_dcmi.h | 4 +- .../Inc/stm32h7xx_hal_dma.h | 4 +- .../Inc/stm32h7xx_hal_dma2d.h | 8 +- .../Inc/stm32h7xx_hal_dts.h | 2 +- .../Inc/stm32h7xx_hal_eth.h | 37 +- .../Inc/stm32h7xx_hal_exti.h | 10 +- .../Inc/stm32h7xx_hal_fdcan.h | 4 +- .../Inc/stm32h7xx_hal_fmac.h | 12 +- .../Inc/stm32h7xx_hal_gfxmmu.h | 8 +- .../Inc/stm32h7xx_hal_gpio.h | 4 +- .../Inc/stm32h7xx_hal_hash.h | 82 +- .../Inc/stm32h7xx_hal_hash_ex.h | 74 +- .../Inc/stm32h7xx_hal_hrtim.h | 1550 ++++----- .../Inc/stm32h7xx_hal_hsem.h | 12 +- .../Inc/stm32h7xx_hal_i2s.h | 5 + .../Inc/stm32h7xx_hal_ltdc.h | 7 +- .../Inc/stm32h7xx_hal_mdios.h | 8 +- .../Inc/stm32h7xx_hal_mdma.h | 6 +- .../Inc/stm32h7xx_hal_mmc.h | 130 +- .../Inc/stm32h7xx_hal_mmc_ex.h | 3 +- .../Inc/stm32h7xx_hal_nand.h | 2 +- .../Inc/stm32h7xx_hal_opamp.h | 4 +- .../Inc/stm32h7xx_hal_otfdec.h | 8 +- .../Inc/stm32h7xx_hal_pcd_ex.h | 1 - .../Inc/stm32h7xx_hal_pwr.h | 2 +- .../Inc/stm32h7xx_hal_pwr_ex.h | 4 +- .../Inc/stm32h7xx_hal_qspi.h | 3 + .../Inc/stm32h7xx_hal_ramecc.h | 18 +- .../Inc/stm32h7xx_hal_rcc.h | 2 +- .../Inc/stm32h7xx_hal_rcc_ex.h | 2 +- .../Inc/stm32h7xx_hal_rng.h | 3 + .../Inc/stm32h7xx_hal_rng_ex.h | 34 +- .../Inc/stm32h7xx_hal_rtc.h | 44 +- .../Inc/stm32h7xx_hal_rtc_ex.h | 109 +- .../Inc/stm32h7xx_hal_sd.h | 16 +- .../Inc/stm32h7xx_hal_sd_ex.h | 2 + .../Inc/stm32h7xx_hal_sdio.h | 600 ++++ .../Inc/stm32h7xx_hal_sdram.h | 2 +- .../Inc/stm32h7xx_hal_swpmi.h | 36 +- .../Inc/stm32h7xx_hal_uart.h | 5 +- .../Inc/stm32h7xx_hal_usart.h | 3 +- .../Inc/stm32h7xx_hal_wwdg.h | 2 +- .../Inc/stm32h7xx_ll_adc.h | 232 +- .../Inc/stm32h7xx_ll_bdma.h | 160 +- .../Inc/stm32h7xx_ll_comp.h | 30 +- .../Inc/stm32h7xx_ll_cordic.h | 28 +- .../Inc/stm32h7xx_ll_dma.h | 216 +- .../Inc/stm32h7xx_ll_dma2d.h | 129 +- .../Inc/stm32h7xx_ll_dmamux.h | 154 +- .../Inc/stm32h7xx_ll_fmac.h | 6 - .../Inc/stm32h7xx_ll_fmc.h | 55 +- .../Inc/stm32h7xx_ll_gpio.h | 26 +- .../Inc/stm32h7xx_ll_hrtim.h | 449 ++- .../Inc/stm32h7xx_ll_hsem.h | 24 +- .../Inc/stm32h7xx_ll_iwdg.h | 14 +- .../Inc/stm32h7xx_ll_lpuart.h | 15 + .../Inc/stm32h7xx_ll_mdma.h | 220 +- .../Inc/stm32h7xx_ll_opamp.h | 22 +- .../Inc/stm32h7xx_ll_rng.h | 2 +- .../Inc/stm32h7xx_ll_rtc.h | 218 +- .../Inc/stm32h7xx_ll_sdmmc.h | 313 +- .../Inc/stm32h7xx_ll_swpmi.h | 90 +- .../Inc/stm32h7xx_ll_wwdg.h | 12 +- .../STM32H7xx_HAL_Driver/Release_Notes.html | 244 +- .../STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c | 2 +- .../Src/stm32h7xx_hal_adc.c | 13 +- .../Src/stm32h7xx_hal_adc_ex.c | 12 +- .../Src/stm32h7xx_hal_comp.c | 6 +- .../Src/stm32h7xx_hal_cordic.c | 2 +- .../Src/stm32h7xx_hal_cortex.c | 2 +- .../Src/stm32h7xx_hal_crc_ex.c | 2 - .../Src/stm32h7xx_hal_cryp.c | 8 +- .../Src/stm32h7xx_hal_cryp_ex.c | 4 +- .../Src/stm32h7xx_hal_dac.c | 8 + .../Src/stm32h7xx_hal_dac_ex.c | 15 +- .../Src/stm32h7xx_hal_dcmi.c | 4 +- .../Src/stm32h7xx_hal_dma.c | 8 +- .../Src/stm32h7xx_hal_dma2d.c | 13 +- .../Src/stm32h7xx_hal_dts.c | 2 +- .../Src/stm32h7xx_hal_eth.c | 35 +- .../Src/stm32h7xx_hal_exti.c | 12 +- .../Src/stm32h7xx_hal_flash_ex.c | 8 +- .../Src/stm32h7xx_hal_fmac.c | 24 +- .../Src/stm32h7xx_hal_gfxmmu.c | 8 +- .../Src/stm32h7xx_hal_gpio.c | 4 +- .../Src/stm32h7xx_hal_hash.c | 123 +- .../Src/stm32h7xx_hal_hash_ex.c | 79 +- .../Src/stm32h7xx_hal_hcd.c | 6 + .../Src/stm32h7xx_hal_hrtim.c | 2094 ++++++------ .../Src/stm32h7xx_hal_i2c.c | 107 +- .../Src/stm32h7xx_hal_i2s.c | 101 + .../Src/stm32h7xx_hal_iwdg.c | 3 +- .../Src/stm32h7xx_hal_ltdc.c | 28 +- .../Src/stm32h7xx_hal_mdios.c | 8 +- .../Src/stm32h7xx_hal_mdma.c | 6 +- .../Src/stm32h7xx_hal_mmc.c | 1749 +++++++++- .../Src/stm32h7xx_hal_mmc_ex.c | 4 +- .../Src/stm32h7xx_hal_nand.c | 2 +- .../Src/stm32h7xx_hal_opamp.c | 6 +- .../Src/stm32h7xx_hal_ospi.c | 13 +- .../Src/stm32h7xx_hal_otfdec.c | 38 +- .../Src/stm32h7xx_hal_pcd.c | 9 +- .../Src/stm32h7xx_hal_pwr.c | 2 +- .../Src/stm32h7xx_hal_pwr_ex.c | 8 +- .../Src/stm32h7xx_hal_qspi.c | 45 +- .../Src/stm32h7xx_hal_ramecc.c | 18 +- .../Src/stm32h7xx_hal_rcc.c | 2 +- .../Src/stm32h7xx_hal_rcc_ex.c | 10 +- .../Src/stm32h7xx_hal_rng.c | 12 +- .../Src/stm32h7xx_hal_rng_ex.c | 21 +- .../Src/stm32h7xx_hal_rtc.c | 71 +- .../Src/stm32h7xx_hal_rtc_ex.c | 76 +- .../Src/stm32h7xx_hal_sd.c | 162 +- .../Src/stm32h7xx_hal_sd_ex.c | 2 + .../Src/stm32h7xx_hal_sdio.c | 2877 +++++++++++++++++ .../Src/stm32h7xx_hal_sdram.c | 5 +- .../Src/stm32h7xx_hal_smartcard.c | 2 +- .../Src/stm32h7xx_hal_smbus_ex.c | 2 + .../Src/stm32h7xx_hal_spi.c | 12 +- .../Src/stm32h7xx_hal_spi_ex.c | 1 - .../Src/stm32h7xx_hal_sram.c | 3 + .../Src/stm32h7xx_hal_swpmi.c | 93 +- .../Src/stm32h7xx_hal_tim.c | 13 +- .../Src/stm32h7xx_hal_uart.c | 28 +- .../Src/stm32h7xx_hal_uart_ex.c | 2 +- .../Src/stm32h7xx_hal_usart.c | 17 +- .../Src/stm32h7xx_hal_usart_ex.c | 2 +- .../Src/stm32h7xx_hal_wwdg.c | 7 +- .../Src/stm32h7xx_ll_adc.c | 2 +- .../Src/stm32h7xx_ll_dma2d.c | 11 +- .../Src/stm32h7xx_ll_fmac.c | 2 - .../Src/stm32h7xx_ll_fmc.c | 54 +- .../Src/stm32h7xx_ll_gpio.c | 2 +- .../Src/stm32h7xx_ll_hrtim.c | 2 +- .../Src/stm32h7xx_ll_rng.c | 2 +- .../Src/stm32h7xx_ll_sdmmc.c | 248 +- .../Src/stm32h7xx_ll_swpmi.c | 14 +- .../Src/stm32h7xx_ll_usb.c | 20 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 150 files changed, 10268 insertions(+), 3917 deletions(-) create mode 100644 system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdio.h create mode 100644 system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdio.c diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index b4dbed31c1..2308881813 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +817,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1817,7 +1847,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1999,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2731,6 +2761,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3659,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3910,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4204,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h index c3760b1735..222a4e9d26 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h @@ -59,8 +59,14 @@ typedef enum * @{ */ #define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ +#define REV_ID_Z ((uint32_t)0x1001) /*!< STM32H7 rev.Z */ +#define REV_ID_A ((uint32_t)0x1000) /*!< STM32H7 rev.A */ #define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ +#if (STM32H7_DEV_ID == 0x450UL) #define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ +#else +#define REV_ID_X ((uint32_t)0x1007) /*!< STM32H7 rev.X */ +#endif /* STM32H7_DEV_ID */ #define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h index 861324a382..7cde9f1e7f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h @@ -1962,7 +1962,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); @@ -1990,8 +1990,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h index 2da227fa97..d2900314bd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h @@ -1011,6 +1011,80 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15) ) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC1. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_12) ? ADC_CHANNEL_13 : \ + ((__CHANNEL__) == ADC_CHANNEL_16) ? ADC_CHANNEL_17 : \ + ((__CHANNEL__) == ADC_CHANNEL_18) ? ADC_CHANNEL_19 : 0UL) + +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC2. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_12) ? ADC_CHANNEL_13 : \ + ((__CHANNEL__) == ADC_CHANNEL_18) ? ADC_CHANNEL_19 : 0UL) + +#if defined(ADC_VER_V5_V90) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC3. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC3(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_13) ? ADC_CHANNEL_14 : \ + ((__CHANNEL__) == ADC_CHANNEL_14) ? ADC_CHANNEL_15 : 0UL) +#endif /* ADC_VER_V5_V90 */ + +#if defined(ADC_VER_V5_V90) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input on the ADC instance selected. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ This parameter can be one of the following values: + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC2) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC3) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC3(__CHANNEL__) : 0UL) +#else +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input on the ADC instance selected. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ This parameter can be one of the following values: + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC2) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) : 0UL) +#endif /* ADC_VER_V5_V90 */ + /** * @brief Verify the ADC single-ended input or differential mode setting. * @param __SING_DIFF__ programmed channel setting. @@ -1311,7 +1385,7 @@ typedef struct /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); @@ -1328,12 +1402,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); /* ADC multimode */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h index 9d16f6aad9..83265b0149 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h @@ -915,7 +915,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); /* Callback in Interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @@ -926,8 +926,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @addtogroup COMP_Exported_Functions_Group4 * @{ */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h index d79bca3646..1be478bd2c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h @@ -85,6 +85,7 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED +#define HAL_SDIO_MODULE_ENABLED #define HAL_SDRAM_MODULE_ENABLED #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED @@ -169,6 +170,8 @@ #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ #define USE_SPI_CRC 1U /*!< use CRC in SPI */ #define USE_FLASH_ECC 0U /*!< use ECC error management in FLASH */ +#define USE_SDIO_TRANSCEIVER 0U /*!< use SDIO Transceiver */ +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ @@ -209,6 +212,7 @@ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ @@ -439,6 +443,10 @@ #include "stm32h7xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32h7xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32h7xx_hal_sdram.h" #endif /* HAL_SDRAM_MODULE_ENABLED */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h index 0aa08c4316..28949bedee 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h index 134fc483f4..cc4c24c755 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h @@ -309,7 +309,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_EnableRegion(uint32_t RegionNumber); void HAL_MPU_DisableRegion(uint32_t RegionNumber); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h index a6802ed6ba..59bf9cd5a7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h @@ -454,11 +454,11 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ /* Interrupt Handler functions **********************************************/ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp); void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h index 8820e0b7aa..3c193cde8d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h @@ -91,8 +91,8 @@ extern "C" { /** @addtogroup CRYPEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h index 65e5fd938c..90590387b6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h @@ -286,10 +286,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h index a21afc09d5..672d5de0f8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h @@ -569,8 +569,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_ * @{ */ /* Peripheral State functions *************************************************/ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi); +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h index 82f6f215e5..59ad97a8fe 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h @@ -1211,8 +1211,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * @brief Peripheral State functions * @{ */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h index 00f205bc0c..dd32a99b28 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h @@ -511,9 +511,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); @@ -550,8 +550,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t */ /* Peripheral State functions ***************************************************/ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h index f9bff1703e..3bb262faf5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h @@ -423,7 +423,7 @@ HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Tempe HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts); HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts); void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts); -HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts); +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts); /* Callback in Interrupt mode */ void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts); void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h index 726127ea68..b3d9eefbbc 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h @@ -105,7 +105,7 @@ typedef struct uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h index 9e93c22951..1a1e984989 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h @@ -344,16 +344,16 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @{ */ /* Operation functions ********************************************************/ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address); -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber); -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam); @@ -373,7 +373,7 @@ void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); * @{ */ /* State function *************************************************************/ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu); uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h index 1cd9178bbd..e0b75b7039 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h @@ -252,7 +252,7 @@ typedef enum * @{ */ /* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} @@ -262,7 +262,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); * @{ */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h index 15b1213f15..54df4670a2 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h @@ -117,13 +117,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -476,15 +476,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -497,15 +499,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -517,9 +519,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -531,9 +533,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -544,9 +548,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -558,8 +562,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -571,13 +575,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /* Peripheral State methods **************************************************/ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash); +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash); /** * @} @@ -594,19 +598,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h index 78fc650fc3..2ac9297a91 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h @@ -50,15 +50,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -69,15 +69,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); /** @@ -87,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -99,9 +101,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -111,9 +113,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -124,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -135,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h index 7b709f3e7b..a6841ada0e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h @@ -21,7 +21,7 @@ #define STM32H7xx_HAL_HRTIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -60,7 +60,7 @@ */ typedef struct { - uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. + uint32_t HRTIMInterruptRequests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. The HRTIM instance can be configured to act as a slave (waiting for a trigger @@ -119,7 +119,7 @@ typedef struct __HRTIM_HandleTypeDef typedef struct #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ { - HRTIM_TypeDef * Instance; /*!< Register base address */ + HRTIM_TypeDef *Instance; /*!< Register base address */ HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ @@ -129,12 +129,12 @@ typedef struct __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ - DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ + DMA_HandleTypeDef *hdmaMaster; /*!< Master timer DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerA; /*!< Timer A DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerB; /*!< Timer B DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerC; /*!< Timer C DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerD; /*!< Timer D DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerE; /*!< Timer E DMA handle parameters */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ @@ -481,7 +481,8 @@ typedef struct /** * @brief HAL HRTIM Callback ID enumeration definition */ -typedef enum { +typedef enum +{ HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ @@ -510,7 +511,7 @@ typedef enum { HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ -}HAL_HRTIM_CallbackIDTypeDef; +} HAL_HRTIM_CallbackIDTypeDef; /** * @brief HAL HRTIM Callback function pointer definitions @@ -556,8 +557,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ /** - * @} - */ + * @} + */ /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit * @{ @@ -567,9 +568,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit * @{ @@ -609,10 +610,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ - (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) + (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) /** * @} */ @@ -649,10 +650,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ - /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio +/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio * @{ * @brief Constants defining timer high-resolution clock prescaler ratio. - */ + */ #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ @@ -934,9 +935,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ - (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) + (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) /** * @} */ @@ -1040,9 +1041,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level * @{ @@ -1267,9 +1268,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle * @{ @@ -1804,8 +1805,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ - (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ - ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) + (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ + ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) /** * @} */ @@ -1999,169 +2000,169 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @} */ - /* Private macros --------------------------------------------------------*/ +/* Private macros --------------------------------------------------------*/ /** @addtogroup HRTIM_Private_Macros * @{ */ #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U) #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ - (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ - ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) + (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ + ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ - ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE2)))) + ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ + (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ + (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ + (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ + (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ + (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TE2)))) #define IS_HRTIM_EVENT(EVENT)\ - (((EVENT) == HRTIM_EVENT_NONE)|| \ - ((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5) || \ - ((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) + (((EVENT) == HRTIM_EVENT_NONE)|| \ + ((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5) || \ + ((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) #define IS_HRTIM_FAULT(FAULT)\ - (((FAULT) == HRTIM_FAULT_1) || \ - ((FAULT) == HRTIM_FAULT_2) || \ - ((FAULT) == HRTIM_FAULT_3) || \ - ((FAULT) == HRTIM_FAULT_4) || \ - ((FAULT) == HRTIM_FAULT_5)) + (((FAULT) == HRTIM_FAULT_1) || \ + ((FAULT) == HRTIM_FAULT_2) || \ + ((FAULT) == HRTIM_FAULT_3) || \ + ((FAULT) == HRTIM_FAULT_4) || \ + ((FAULT) == HRTIM_FAULT_5)) #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) + (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) #define IS_HRTIM_MODE(MODE)\ - (((MODE) == HRTIM_MODE_CONTINUOUS) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_CONTINUOUS) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_MODE_ONEPULSE(MODE)\ - (((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_HALFMODE(HALFMODE)\ - (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ - ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) + (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ + ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) #define IS_HRTIM_SYNCSTART(SYNCSTART)\ - (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ - ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) + (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ + ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) #define IS_HRTIM_SYNCRESET(SYNCRESET)\ - (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ - ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) + (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ + ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) #define IS_HRTIM_DACSYNC(DACSYNC)\ - (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) + (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) #define IS_HRTIM_PRELOAD(PRELOAD)\ - (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ - ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) + (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ + ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) #define IS_HRTIM_TIMERBURSTMODE(MODE) \ - (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ - ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) + (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ + ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ - (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ - ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) + (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ + ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ - ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ + ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ - (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ - ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) + (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ + ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ - ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ - ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) + ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ + ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ - ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) + ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) @@ -2169,128 +2170,128 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ - (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ - ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) + (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ + ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) /* Auto delayed mode is only available for compare units 2 and 4U */ #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ - ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) + ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ + || \ + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ - (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ - ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) + (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ + ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ - (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) + (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ - (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) + (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ - (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ - ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) + (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ + ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ - (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ - ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) + (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ + ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ - (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) + (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ - (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ - ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) + (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ + ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ - (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ - ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) + (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ + ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ @@ -2304,420 +2305,420 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ - (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) + (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ - (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ - ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) + (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ + ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) + (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ - (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ - ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) + (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ + ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ - (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ - ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) + (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ + ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ - (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ - ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) + (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ + ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ - (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ - ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) + (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ + ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ - (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ - ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) + (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ + ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ - (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ - ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) + (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ + ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) + (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ - (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) + (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ - (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) + (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ - (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) + (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ - (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) + (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ - (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) + (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) #define IS_HRTIM_EVENTSRC(EVENTSRC)\ - (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_4)) + (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_4)) #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ - ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ - (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ - ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ - || \ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) + ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ + (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ + ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ + || \ + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ - (((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) && \ - (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ - ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ - || \ - (((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10))) + (((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) && \ + (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ + ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ + || \ + (((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10))) #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ - ((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) \ - || \ - ((((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) && \ - (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ - ((FILTER) == HRTIM_EVENTFILTER_1) || \ - ((FILTER) == HRTIM_EVENTFILTER_2) || \ - ((FILTER) == HRTIM_EVENTFILTER_3) || \ - ((FILTER) == HRTIM_EVENTFILTER_4) || \ - ((FILTER) == HRTIM_EVENTFILTER_5) || \ - ((FILTER) == HRTIM_EVENTFILTER_6) || \ - ((FILTER) == HRTIM_EVENTFILTER_7) || \ - ((FILTER) == HRTIM_EVENTFILTER_8) || \ - ((FILTER) == HRTIM_EVENTFILTER_9) || \ - ((FILTER) == HRTIM_EVENTFILTER_10) || \ - ((FILTER) == HRTIM_EVENTFILTER_11) || \ - ((FILTER) == HRTIM_EVENTFILTER_12) || \ - ((FILTER) == HRTIM_EVENTFILTER_13) || \ - ((FILTER) == HRTIM_EVENTFILTER_14) || \ - ((FILTER) == HRTIM_EVENTFILTER_15)))) + ((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) \ + || \ + ((((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) && \ + (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ + ((FILTER) == HRTIM_EVENTFILTER_1) || \ + ((FILTER) == HRTIM_EVENTFILTER_2) || \ + ((FILTER) == HRTIM_EVENTFILTER_3) || \ + ((FILTER) == HRTIM_EVENTFILTER_4) || \ + ((FILTER) == HRTIM_EVENTFILTER_5) || \ + ((FILTER) == HRTIM_EVENTFILTER_6) || \ + ((FILTER) == HRTIM_EVENTFILTER_7) || \ + ((FILTER) == HRTIM_EVENTFILTER_8) || \ + ((FILTER) == HRTIM_EVENTFILTER_9) || \ + ((FILTER) == HRTIM_EVENTFILTER_10) || \ + ((FILTER) == HRTIM_EVENTFILTER_11) || \ + ((FILTER) == HRTIM_EVENTFILTER_12) || \ + ((FILTER) == HRTIM_EVENTFILTER_13) || \ + ((FILTER) == HRTIM_EVENTFILTER_14) || \ + ((FILTER) == HRTIM_EVENTFILTER_15)))) #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ - (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) + (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ - (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) + (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ + ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ - (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ - ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) + (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ + ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ - (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ - ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) + (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ + ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ - (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) + (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ - (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ - ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) + (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ + ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ - (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) + (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) #define IS_HRTIM_BURSTMODE(BURSTMODE)\ - (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ - ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) + (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ + ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ - (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) + (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ - (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) + (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ - (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ - ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) + (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ + ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ - (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) + (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ - (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) + (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ - (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) + (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ - ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) + ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ - (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ - ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) + (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ + ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) @@ -2750,10 +2751,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) #endif @@ -2782,44 +2783,44 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ - }\ + {\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ }\ + }\ } while(0U) @@ -2852,8 +2853,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval None */ -#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) -#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + |= (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + &= ~(__INTERRUPT__)) /** @brief Enables or disables the specified HRTIM Timerx interrupts. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2892,7 +2895,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2907,7 +2911,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2937,7 +2942,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clears the specified HRTIM common pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2967,7 +2973,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag * @retval None */ -#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR\ + = (__INTERRUPT__)) /** @brief Clears the specified HRTIM Timerx pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2990,7 +2997,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag * @retval None */ -#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) +#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__INTERRUPT__)) /* DMA HANDLING */ /** @brief Enables or disables the specified HRTIM Master timer DMA requests. @@ -3033,14 +3041,18 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) -#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) -#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) -#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) -#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) +#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\ + (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__FLAG__)) /** @brief Sets the HRTIM timer Counter Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3136,16 +3148,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval None */ #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) /** @brief Gets the HRTIM timer Compare Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3161,16 +3173,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval Compare value */ #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) /** * @} @@ -3178,17 +3190,17 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /* Exported functions --------------------------------------------------------*/ /** @addtogroup HRTIM_Exported_Functions -* @{ -*/ + * @{ + */ /** @addtogroup HRTIM_Exported_Functions_Group1 -* @{ -*/ + * @{ + */ /* Initialization and Configuration functions ********************************/ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim); void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); @@ -3196,244 +3208,244 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group2 -* @{ -*/ + * @{ + */ /* Simple time base related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group3 -* @{ -*/ + * @{ + */ /* Simple output compare related functions ************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group4 -* @{ -*/ + * @{ + */ /* Simple PWM output related functions ****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group5 -* @{ -*/ + * @{ + */ /* Simple capture related functions *******************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group6 -* @{ -*/ + * @{ + */ /* Simple one pulse related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group7 -* @{ -*/ + * @{ + */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg); HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg); + const HRTIM_FaultCfgTypeDef *pFaultCfg); HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable); HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group8 -* @{ -*/ + * @{ + */ /* Waveform related functions *************************************************/ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg); + const HRTIM_CompareCfgTypeDef *pCompareCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg); + const HRTIM_CaptureCfgTypeDef *pCaptureCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef *pOutputCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3443,15 +3455,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg); HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg); HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg); HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3459,22 +3471,22 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart); @@ -3503,7 +3515,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferLength); HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); @@ -3513,12 +3525,12 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group9 -* @{ -*/ + * @{ + */ /* HRTIM peripheral state functions */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); @@ -3526,7 +3538,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); @@ -3547,8 +3559,8 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group10 -* @{ -*/ + * @{ + */ /* IRQ handler */ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); @@ -3565,50 +3577,50 @@ void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); /* Timer events related callback functions */ void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h index 45f6e07d97..45cf33d7f4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h @@ -57,7 +57,7 @@ extern "C" { (HSEM->C1IER |= (__SEM_MASK__)) : \ (HSEM->C2IER |= (__SEM_MASK__))) #else -#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__)) +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->C1IER |= (__SEM_MASK__)) #endif /* DUAL_CORE */ /** * @brief Disables the specified HSEM interrupts. @@ -69,7 +69,7 @@ extern "C" { (HSEM->C1IER &= ~(__SEM_MASK__)) : \ (HSEM->C2IER &= ~(__SEM_MASK__))) #else -#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__)) +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->C1IER &= ~(__SEM_MASK__)) #endif /* DUAL_CORE */ /** @@ -80,9 +80,9 @@ extern "C" { #if defined(DUAL_CORE) #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ ((__SEM_MASK__) & HSEM->C1MISR) : \ - ((__SEM_MASK__) & HSEM->C2MISR1)) + ((__SEM_MASK__) & HSEM->C2MISR)) #else -#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR) +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1MISR) #endif /* DUAL_CORE */ /** @@ -95,7 +95,7 @@ extern "C" { (__SEM_MASK__) & HSEM->C1ISR : \ (__SEM_MASK__) & HSEM->C2ISR) #else -#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR) +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1ISR) #endif /* DUAL_CORE */ /** @@ -108,7 +108,7 @@ extern "C" { (HSEM->C1ICR |= (__SEM_MASK__)) : \ (HSEM->C2ICR |= (__SEM_MASK__))) #else -#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__)) +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->C1ICR |= (__SEM_MASK__)) #endif /* DUAL_CORE */ /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h index 407bf2ccb3..40f321f8e4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h @@ -505,6 +505,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); +/* IO Swap feature */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s); + /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h index 3e792bc9d6..b0df0bd0ac 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h @@ -592,7 +592,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); @@ -625,8 +626,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * @{ */ /* Peripheral State functions *************************************************/ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h index 50c61f41d1..fecf9fe2af 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h @@ -509,8 +509,8 @@ HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_ HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data); HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData); -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios); -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios); HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); @@ -527,8 +527,8 @@ void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios); /** @addtogroup MDIOS_Exported_Functions_Group3 * @{ */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios); -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios); +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h index a39cc0d755..fb61178648 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h @@ -655,7 +655,7 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM */ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); -HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); @@ -687,8 +687,8 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); * @brief Peripheral State functions * @{ */ -HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); -uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma); +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h index ed4e5e5ade..3b242bae0e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMC * @{ @@ -121,7 +122,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< MMC locking object */ - const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ uint32_t TxXferSize; /*!< MMC Tx Transfer size */ @@ -135,6 +136,8 @@ typedef struct __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + __IO uint16_t RPMBErrorCode; /*!< MMC RPMB Area Error codes */ + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ uint32_t CSD[4U]; /*!< MMC card specific data table */ @@ -276,45 +279,55 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition * @{ */ -#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ -#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ -#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ -#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ -#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ -#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ -#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ -#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ /*!< number of transferred bytes does not match the block length */ -#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ -#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ -#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ /*!< command or if there was an attempt to access a locked card */ -#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ -#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ -#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ -#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ -#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ -#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ -#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ -#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ -#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ -#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ /*!< of erase sequence command was received */ -#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ -#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ -#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ -#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ -#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ -#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ -#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ -#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +/*!< response results after operating with RPMB partition */ +#define HAL_MMC_ERROR_RPMB_OPERATION_OK 0x0000U /*!< Operation OK */ +#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE 0x0001U /*!< General failure */ +#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE 0x0002U /*!< Authentication failure */ +#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE 0x0003U /*!< Counter failure */ +#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE 0x0004U /*!< Address failure */ +#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE 0x0005U /*!< Write failure */ +#define HAL_MMC_ERROR_RPMB_READ_FAILURE 0x0006U /*!< Read failure */ +#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG 0x0007U /*!< Authentication Key not yet programmed */ +#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED 0x0080U /*!< Write Counter has expired i.e. reached its max value */ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} @@ -399,6 +412,19 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); * @} */ +/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types + * @{ + */ +typedef uint32_t HAL_MMC_PartitionTypeDef; + +#define HAL_MMC_USER_AREA_PARTITION 0x00000000U /*!< User area partition */ +#define HAL_MMC_BOOT_PARTITION1 0x00000100U /*!< Boot partition 1 */ +#define HAL_MMC_BOOT_PARTITION2 0x00000200U /*!< Boot partition 2 */ +#define HAL_MMC_RPMB_PARTITION 0x00000300U /*!< RPMB partition */ +/** + * @} + */ + /** * @} */ @@ -686,6 +712,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition); /** * @} */ @@ -694,9 +721,9 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} @@ -705,8 +732,9 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC /** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions * @{ */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc); /** * @} */ @@ -740,6 +768,29 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ + +/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, + uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC); + +/** + * @} + */ + /* Private types -------------------------------------------------------------*/ /** @defgroup MMC_Private_Types MMC Private Types * @{ @@ -812,6 +863,7 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h index 215749583f..c610a2bdf1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMCEx * @brief SD HAL extended module driver * @{ @@ -100,6 +100,7 @@ void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h index 7290893bd4..b0b31b91bb 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h @@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h index ef354861f5..cac0948402 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h @@ -417,7 +417,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** * @} @@ -428,7 +428,7 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop */ /* Peripheral State functions **************************************************/ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h index bfdfb0b456..9aa5e3ab6b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h @@ -342,8 +342,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode); HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey); + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); /** @@ -353,8 +353,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 /** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions * @{ */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec); -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec); +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h index 9cfa0125e6..221e2af375 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h @@ -45,7 +45,6 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h index 91a905409f..c1d7222366 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h @@ -692,7 +692,7 @@ void HAL_PWR_DisableBkUpAccess (void); */ /* Peripheral Control functions **********************************************/ /* PVD configuration */ -void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD (void); void HAL_PWR_DisablePVD (void); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h index 61c76092cd..e8455d8d22 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h @@ -544,7 +544,7 @@ void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); #endif /* defined(PWR_CR1_SRDRAMSO) */ /* Wakeup Pins control functions */ -void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams); void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); @@ -599,7 +599,7 @@ uint32_t HAL_PWREx_GetVBATLevel (void); PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); #endif /* PWR_CSR1_MMCVDO */ /* Power AVD configuration functions */ -void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD); void HAL_PWREx_EnableAVD (void); void HAL_PWREx_DisableAVD (void); /* Power PVD/AVD IRQ Handler */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h index 98b2c5cf19..321f05f52b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h @@ -26,6 +26,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#if defined (DLYB_QUADSPI) +#include "stm32h7xx_ll_delayblock.h" +#endif /* DLYB_QUADSPI */ #if defined(QUADSPI) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h index f9444ebc87..b681c8dee6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h @@ -303,12 +303,12 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc); * @brief Error information functions * @{ */ -uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc); /** * @} */ @@ -317,9 +317,9 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc); * @brief State and Error Functions * @{ */ -HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc); +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetRAMECCError(const RAMECC_HandleTypeDef *hramecc); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h index 1626c6d050..564a8a09f6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -7968,7 +7968,7 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h index 2fb1fd2906..d39df84c7a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -3936,7 +3936,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); * @{ */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h index e7dd55a1e1..409ac73bd1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h @@ -178,6 +178,9 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#if defined(RNG_CR_CONDRST) +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ +#endif /* RNG_CR_CONDRST */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h index ee43ec107b..05c83d073a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,9 +55,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -65,11 +65,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -108,7 +108,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -132,7 +132,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -141,7 +141,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -150,7 +150,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -187,7 +187,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -196,11 +196,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -211,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h index ad0fa135f4..0777b955a7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h @@ -181,39 +181,41 @@ typedef struct __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ - void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ + void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ - void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ + void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ - void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ + void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ - void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ - void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ +#if defined(RTC_TAMPER2_SUPPORT) + void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ +#endif /* RTC_TAMPER2_SUPPORT */ - void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ + void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ #if defined(TAMP) - void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */ + void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */ - void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */ + void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */ - void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ + void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ - void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */ + void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */ - void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ + void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ - void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */ + void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */ - void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ + void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ #endif /* TAMP */ - void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ - void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ @@ -230,7 +232,9 @@ typedef enum HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2u, /*!< RTC TimeStamp Event Callback ID */ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3u, /*!< RTC WakeUp Timer Event Callback ID */ HAL_RTC_TAMPER1_EVENT_CB_ID = 4u, /*!< RTC Tamper 1 Callback ID */ +#if defined(RTC_TAMPER2_SUPPORT) HAL_RTC_TAMPER2_EVENT_CB_ID = 5u, /*!< RTC Tamper 2 Callback ID */ +#endif /* RTC_TAMPER2_SUPPORT */ HAL_RTC_TAMPER3_EVENT_CB_ID = 6u, /*!< RTC Tamper 3 Callback ID */ #if defined(TAMP) HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 12u, /*!< RTC Internal Tamper 1 Callback ID */ @@ -935,9 +939,9 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); /** * @} */ @@ -949,7 +953,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -970,7 +974,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h index bb29abe868..d66729467a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h @@ -56,10 +56,14 @@ typedef struct This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ uint32_t NoErase; /*!< Specifies the Tamper no erase mode. - This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions + This parameter is not applicable to the STM32H723/33, STM32H725/35 and STM32H730 + devices, and has been kept for backward compatibility */ - uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. - This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions + This parameter is not applicable to the STM32H723/33, STM32H725/35 and STM32H730 + devices, and has been kept for backward compatibility */ uint32_t Filter; /*!< Specifies the TAMP Filter Tamper. This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ @@ -265,11 +269,17 @@ typedef struct #define RTC_TAMPER_3 TAMP_CR1_TAMP3E #else #define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E +#endif /* RTC_TAMPER2_SUPPORT */ #define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E #endif /* TAMP */ +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3) +#else +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_3) +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ @@ -282,9 +292,13 @@ typedef struct #define RTC_IT_TAMP2 TAMP_IER_TAMP2IE /*!< Enable Tamper 2 Interrupt */ #define RTC_IT_TAMP3 TAMP_IER_TAMP3IE /*!< Enable Tamper 3 Interrupt */ #else +#if defined(RTC_TAMPxIE_SUPPORT) #define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE /*!< Enable Tamper 1 Interrupt */ #define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE /*!< Enable Tamper 2 Interrupt */ #define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE /*!< Enable Tamper 3 Interrupt */ +#else +#define RTC_IT_TAMP1 RTC_TAFCR_TAMPIE /*!< Enable Tamper Interrupt */ +#endif /* RTC_TAMPxIE_SUPPORT */ #endif /* TAMP */ #if defined(TAMP) @@ -349,13 +363,20 @@ typedef struct #define RTC_TAMPER_3_TRIGGER TAMP_CR2_TAMP3TRG #else #define RTC_TAMPER_1_TRIGGER RTC_TAMPCR_TAMP1TRG +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_2_TRIGGER RTC_TAMPCR_TAMP2TRG +#endif /* RTC_TAMPER2_SUPPORT */ #define RTC_TAMPER_3_TRIGGER RTC_TAMPCR_TAMP3TRG #endif /* TAMP */ +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_X_TRIGGER (RTC_TAMPER_1_TRIGGER |\ RTC_TAMPER_2_TRIGGER |\ RTC_TAMPER_3_TRIGGER) +#else +#define RTC_TAMPER_X_TRIGGER (RTC_TAMPER_1_TRIGGER |\ + RTC_TAMPER_3_TRIGGER) +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ @@ -367,8 +388,15 @@ typedef struct #define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u #define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u #else -#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00000000u +#if defined(RTC_TAMPNOERASE_SUPPORT) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u #define RTC_TAMPER_ERASE_BACKUP_DISABLE RTC_TAMPCR_TAMP1NOERASE +#else +/*!< These values are not applicable to the STM32H723/33, STM32H725/35 and STM32H730 + devices, and have been kept for backward compatibility */ +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +#endif /* RTC_TAMPNOERASE_SUPPORT */ #endif /* TAMP */ #if defined(TAMP) @@ -376,14 +404,18 @@ typedef struct #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 TAMP_CR2_TAMP2NOERASE #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 TAMP_CR2_TAMP3NOERASE #else +#if defined(RTC_TAMPNOERASE_SUPPORT) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 RTC_TAMPCR_TAMP1NOERASE #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 RTC_TAMPCR_TAMP2NOERASE #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 RTC_TAMPCR_TAMP3NOERASE +#endif /* RTC_TAMPNOERASE_SUPPORT */ #endif /* TAMP */ +#if defined(RTC_TAMPNOERASE_SUPPORT) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK (RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 |\ RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 |\ RTC_DISABLE_BKP_ERASE_ON_TAMPER_3) +#endif /* RTC_TAMPNOERASE_SUPPORT */ /** * @} */ @@ -395,8 +427,15 @@ typedef struct #define RTC_TAMPERMASK_FLAG_DISABLE 0x00u #define RTC_TAMPERMASK_FLAG_ENABLE 0x01u #else -#define RTC_TAMPERMASK_FLAG_DISABLE 0x00000000u +#if defined(RTC_TAMPMASKFLAG_SUPPORT) +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u #define RTC_TAMPERMASK_FLAG_ENABLE RTC_TAMPCR_TAMP1MF +#else +/*!< These values are not applicable to the STM32H723/33, STM32H725/35 and STM32H730 + devices, and have been kept for backward compatibility */ +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ #endif /* TAMP */ #if defined(TAMP) @@ -404,14 +443,18 @@ typedef struct #define RTC_TAMPER_2_MASK_FLAG TAMP_CR2_TAMP2MSK #define RTC_TAMPER_3_MASK_FLAG TAMP_CR2_TAMP3MSK #else +#if defined(RTC_TAMPMASKFLAG_SUPPORT) #define RTC_TAMPER_1_MASK_FLAG RTC_TAMPCR_TAMP1MF #define RTC_TAMPER_2_MASK_FLAG RTC_TAMPCR_TAMP2MF #define RTC_TAMPER_3_MASK_FLAG RTC_TAMPCR_TAMP3MF +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ #endif /* TAMP */ +#if defined(RTC_TAMPMASKFLAG_SUPPORT) #define RTC_TAMPER_X_MASK_FLAG (RTC_TAMPER_1_MASK_FLAG |\ RTC_TAMPER_2_MASK_FLAG |\ RTC_TAMPER_3_MASK_FLAG) +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ /** * @} */ @@ -575,7 +618,9 @@ typedef struct #define RTC_FLAG_TAMP3F TAMP_SR_TAMP3F #else #define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F +#endif /* RTC_TAMPER2_SUPPORT */ #define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F #endif /* TAMP */ /** @@ -865,7 +910,9 @@ typedef struct #if defined(TAMP) #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E)) #else +#if defined(RTC_TAMPER2_SUPPORT) #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) +#endif /* RTC_TAMPER2_SUPPORT */ #endif /* TAMP */ /** @@ -876,7 +923,9 @@ typedef struct #if defined(TAMP) #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E)) #else +#if defined(RTC_TAMPER2_SUPPORT) #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) +#endif /* RTC_TAMPER2_SUPPORT */ #endif /* TAMP */ /** @@ -908,8 +957,9 @@ typedef struct * This parameter can be any combination of the following values: * @arg RTC_IT_TAMPALL: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) * @arg RTC_IT_TAMP3: Tamper3 interrupt + * (*) Not applicable to all devices. * @retval None */ #if defined(TAMP) @@ -925,8 +975,9 @@ typedef struct * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) * @arg RTC_IT_TAMP3: Tamper3 interrupt + * (*) Not applicable to all devices. * @retval None */ #if defined(TAMP) @@ -942,8 +993,9 @@ typedef struct * This parameter can be: * @arg RTC_IT_TAMPALL: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) * @arg RTC_IT_TAMP3: Tamper3 interrupt + * (*) Not applicable to all devices. * @retval Flag status */ #if defined(TAMP) @@ -958,8 +1010,9 @@ typedef struct * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag (*) * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * (*) Not applicable to all devices. * @retval Flag status */ #if defined(TAMP) @@ -974,8 +1027,9 @@ typedef struct * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag (*) * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * (*) Not applicable to all devices. * @retval None */ #if defined(TAMP) @@ -1658,18 +1712,22 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions * @{ */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#if defined(RTC_TAMPER2_SUPPORT) HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* RTC_TAMPER2_SUPPORT */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +#if defined(RTC_TAMPER2_SUPPORT) void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* RTC_TAMPER2_SUPPORT */ void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); #if defined(TAMP) -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper); HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout); void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc); @@ -1679,8 +1737,8 @@ void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper); -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed); +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed); HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); #endif /* TAMP */ @@ -1700,7 +1758,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -1717,8 +1775,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions * @{ */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); /** * @} */ @@ -1742,7 +1800,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); #if defined(TAMP) HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance); -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); #endif /* TAMP */ /** * @} @@ -1774,8 +1832,17 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC Wakeup event */ /* Masks Definition */ +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_X ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3)) +#else +#define RTC_TAMPER_X ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_3)) +#endif /* RTC_TAMPER2_SUPPORT */ + +#if defined(RTC_TAMPxIE_SUPPORT) #define RTC_TAMPER_X_INTERRUPT ((uint32_t) (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3)) +#else +#define RTC_TAMPER_X_INTERRUPT RTC_IT_TAMPALL +#endif /* RTC_TAMPxIE_SUPPORT */ /** * @} @@ -1850,7 +1917,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_X) != 0x00U) && \ (((__TAMPER__) & ~RTC_TAMPER_X) == 0x00U)) -#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) \ +#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) \ ((((__INTERRUPT__) & ( RTC_TAMPER_X_INTERRUPT | RTC_IT_TAMPALL )) != 0x00U) && \ (((__INTERRUPT__) & (~(RTC_TAMPER_X_INTERRUPT | RTC_IT_TAMPALL))) == 0x00U)) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h index 83fa74fded..a2536da2de 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h @@ -33,6 +33,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @defgroup SD SD * @brief SD HAL module driver @@ -315,12 +316,12 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ #define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ - /*!< number of transferred bytes does not match the block length */ +/*!< number of transferred bytes does not match the block length */ #define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ #define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ - /*!< command or if there was an attempt to access a locked card */ +/*!< command or if there was an attempt to access a locked card */ #define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -332,7 +333,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ #define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ - /*!< of erase sequence command was received */ +/*!< of erase sequence command was received */ #define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -690,10 +691,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ @@ -701,8 +702,8 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInf /** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions * @{ */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd); /** * @} */ @@ -787,6 +788,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h index 450e7dfad1..050005b0e3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDEx * @brief SD HAL extended module driver @@ -98,6 +99,7 @@ void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdio.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdio.h new file mode 100644 index 0000000000..77cb250ebd --- /dev/null +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdio.h @@ -0,0 +1,600 @@ +/** + ********************************************************************************************************************** + * @file stm32h7xx_hal_sdio.h + * @author MCD Application Team + * @brief Header file of SDIO HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7xx_HAL_SDIO_H +#define STM32H7xx_HAL_SDIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7xx_ll_sdmmc.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) + +/** @defgroup SDIO SDIO + * @brief SDIO HAL module driver + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Types SDIO Exported Types + * @{ + */ + +/** @defgroup SDIO_Exported_Types_Group1 SDIO State enumeration structure + * @{ + + */ +typedef enum +{ + HAL_SDIO_STATE_RESET = 0x00U, /*!< SDIO not yet initialized or disabled */ + HAL_SDIO_STATE_READY = 0x01U, /*!< SDIO initialized and ready for us */ + HAL_SDIO_STATE_BUSY = 0x02U, /*!< SDIO process ongoing */ +} HAL_SDIO_StateTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Types_Group2 SDIO Handle and Structure definition + * @{ + */ +/** + * @brief SDIO Card Common Control Register Structure definition + */ +typedef struct +{ + uint8_t sdio_revision; /*!< SDIO revision */ + uint8_t cccr_revision; /*!< CCCR version */ + uint8_t sd_spec_revision; /*!< SD revision */ + uint8_t bus_width_8Bit; /*!< SDIO bus width 8 bit support */ + uint32_t card_capability; /*!< SDIO card capability */ + uint32_t commonCISPointer; /*!< point to common CIS */ +} HAL_SDIO_CCCR_TypeDef; + +/** + * @brief sdio card FBR register(Function Basic Register) + */ +typedef struct +{ + uint8_t flags; /*!< SDIO current IO flags */ + uint8_t ioStdFunctionCode; /*!< SDIO current IO standard function code */ + uint8_t ioExtFunctionCode; /*!< SDIO current IO extended function code */ + uint32_t ioPointerToCIS; /*!< SDIO current IO pointer to CIS */ + uint32_t ioPointerToCSA; /*!< SDIO current IO pointer to CSA */ +} HAL_SDIO_FBR_t; + +/** + * @brief SDIO CMD52 Structure definition + */ +typedef struct +{ + uint32_t Reg_Addr; /*!< This is the address of the byte of data inside of the selected function to read or write */ + uint8_t ReadAfterWrite; /*!< This is the read after write flag, it is used for write access only. */ + uint8_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write */ +} HAL_SDIO_DirectCmd_TypeDef; + +/** + * @brief SDIO CMD53 Structure definition + */ +typedef struct +{ + uint32_t Reg_Addr; /*!< This is the address of the byte of data inside of the selected function to read or write */ + uint32_t OpCode; /*!< Read/Write operation mode */ + uint32_t Block_Mode; /*!< Bytes or Blocks mode */ + uint32_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write */ +} HAL_SDIO_ExtendedCmd_TypeDef; + +#define SDIO_InitTypeDef SDMMC_InitTypeDef +#define SDIO_TypeDef SDMMC_TypeDef + +/** + * @brief SDIO handle Structure definition + */ +typedef struct __SDIO_HandleTypeDef +{ + SDIO_TypeDef *Instance; /*!< SDIO registers base address */ + + SDIO_InitTypeDef Init; /*!< SDIO required parameters */ + + HAL_LockTypeDef Lock; /*!< SDIO locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SDIO Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SDIO Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SDIO Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SDIO Rx Transfer size */ + + uint32_t remaining_data; /*!< Remaining data to transfer */ + + uint32_t next_data_addr; /*!< SDIO Next data address */ + + __IO uint32_t next_reg_addr; /*!< SDIO Next register address */ + + uint16_t block_size; /*!< SDIO Block size */ + + __IO uint32_t Context; /*!< SDIO transfer context */ + + __IO HAL_SDIO_StateTypeDef State; /*!< SDIO card State */ + + __IO uint32_t ErrorCode; /*!< SDIO Card Error codes */ + + uint8_t IOFunctionMask; /*!< SDIO used to record current enabled io interrupt */ + + volatile uint8_t IOInterruptNbr; /*!< SDIO used to record total enabled io interrupt numbers */ + + void (* SDIO_IOFunction_Callback[SDIO_MAX_IO_NUMBER])(struct __SDIO_HandleTypeDef *hsdio, uint32_t func); + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* RxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) + void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + + HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio); + +} SDIO_HandleTypeDef; + +/** + * @} + */ +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +/** @defgroup SDIO_Exported_Types_Group3 SDIO Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SDIO_TX_CPLT_CB_ID = 0x00U, /*!< SDIO Tx Complete Callback ID */ + HAL_SDIO_RX_CPLT_CB_ID = 0x01U, /*!< SDIO Rx Complete Callback ID */ + HAL_SDIO_ERROR_CB_ID = 0x02U, /*!< SDIO Error Callback ID */ + HAL_SDIO_MSP_INIT_CB_ID = 0x10U, /*!< SDIO MspInit Callback ID */ + HAL_SDIO_MSP_DEINIT_CB_ID = 0x11U /*!< SDIO MspDeInit Callback ID */ +} HAL_SDIO_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SDIO_Exported_Types_Group4 SDIO Callback pointer definition + * @{ + */ +typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio); +typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func); +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Constants SDIO Exported Constants + * @{ + */ + +/** @defgroup SDIO_Exported_Constansts_Group1 SDIO Error status Structure definition + * @{ + */ +#define HAL_SDIO_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SDIO_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SDIO_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SDIO_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SDIO_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SDIO_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group2 SDIO context enumeration + * @{ + */ +#define SDIO_CONTEXT_NONE 0x00U /*!< None */ +#define SDIO_CONTEXT_READ_SINGLE_BLOCK 0x01U /*!< Read single block operation */ +#define SDIO_CONTEXT_READ_MULTIPLE_BLOCK 0x02U /*!< Read multiple blocks operation */ +#define SDIO_CONTEXT_WRITE_SINGLE_BLOCK 0x10U /*!< Write single block operation */ +#define SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK 0x20U /*!< Write multiple blocks operation */ +#define SDIO_CONTEXT_IT 0x08U /*!< Process in Interrupt mode */ +#define SDIO_CONTEXT_DMA 0x80U /*!< Process in DMA mode */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group3 SDIO Block mode enumeration + * @{ + */ +#define HAL_SDIO_MODE_BYTE SDMMC_SDIO_MODE_BYTE +#define HAL_SDIO_MODE_BLOCK SDMMC_SDIO_MODE_BLOCK +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group4 SDIO operation code enumeration + * @{ + */ +#define HAL_SDIO_OP_CODE_NO_INC SDMMC_SDIO_NO_INC +#define HAL_SDIO_OP_CODE_AUTO_INC SDMMC_SDIO_AUTO_INC +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group5 SDIO Read After Write(RAW) enumeration + * @{ + */ +#define HAL_SDIO_WRITE_ONLY SDMMC_SDIO_WO /*!< SDIO Write only */ +#define HAL_SDIO_READ_AFTER_WRITE SDMMC_SDIO_RAW /*!< SDIO Read after write */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group6 SDIO wire mode enumeration + * @{ + */ +#define HAL_SDIO_1_WIRE_MODE 0U /*!< SDIO wire support 1 wire */ +#define HAL_SDIO_4_WIRES_MODE 1U /*!< SDIO wire support 4 wires */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group7 SDIO Data block size enumeration + * @{ + */ +#define HAL_SDIO_DATA_BLOCK_SIZE_1BYTE 1U /*!< SDIO data block size 1 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_2BYTE 2U /*!< SDIO data block size 2 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_4BYTE 4U /*!< SDIO data block size 4 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_8BYTE 8U /*!< SDIO data block size 8 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_16BYTE 16U /*!< SDIO data block size 16 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_32BYTE 32U /*!< SDIO data block size 32 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_64BYTE 64U /*!< SDIO data block size 64 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_128BYTE 128U /*!< SDIO data block size 128 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_256BYTE 256U /*!< SDIO data block size 256 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_512BYTE 512U /*!< SDIO data block size 512 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE 1024U /*!< SDIO data block size 1024 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE 2048U /*!< SDIO data block size 2048 byte */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration + * @{ + */ +#define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */ +#define HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED 1U /*!< SDIO bus width 8 bit is supported */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group9 SDIO Data rate definitions + * @{ + */ +#define HAL_SDIOS_DATA_RATE_SDR12 0U /*!< SDIO Data rate SDR12 */ +#define HAL_SDIOS_DATA_RATE_SDR25 1U /*!< SDIO Data rate SDR25 */ +#define HAL_SDIOS_DATA_RATE_SDR50 2U /*!< SDIO Data rate SDR50 */ +#define HAL_SDIOS_DATA_RATE_DDR50 3U /*!< SDIO Data rate DDR50 */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group10 SDIO Functions definitions + * @{ + */ +#define HAL_SDIO_FUNCTION_0 0U /*!< SDIO function 0 */ +#define HAL_SDIO_FUNCTION_1 1U /*!< SDIO function 1 */ +#define HAL_SDIO_FUNCTION_2 2U /*!< SDIO function 2 */ +#define HAL_SDIO_FUNCTION_3 3U /*!< SDIO function 3 */ +#define HAL_SDIO_FUNCTION_4 4U /*!< SDIO function 4 */ +#define HAL_SDIO_FUNCTION_5 5U /*!< SDIO function 5 */ +#define HAL_SDIO_FUNCTION_6 6U /*!< SDIO function 6 */ +#define HAL_SDIO_FUNCTION_7 7U /*!< SDIO function 7 */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group11 SDIO FBR definitions + * @{ + */ +#define HAL_SDIO_FBR_SUPPORT_CSA 1U /*!< SDIO function support CSA */ +#define HAL_SDIO_FBR_SUPPORT_POWER_SELECTION 1U /*!< SDIO function support power selection */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_macros SDIO Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** + * @brief Enable the SDIO device interrupt. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. + * @retval None + */ +#define __HAL_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the SDIO device interrupt. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. + * @retval None + */ +#define __HAL_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified SDIO flag is set or not. + * @param __HANDLE__ SDIO Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @ref SDMMC_LL_Flags. + * @retval The new state of SDIO FLAG (SET or RESET). + */ +#define __HAL_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the SDIO's pending flags. + * @param __HANDLE__ SDIO Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one or a combination of @ref SDMMC_LL_Flags. + * @retval None + */ +#define __HAL_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified SDIO interrupt has occurred or not. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of @ref SDMMC_LL_Interrupt_sources. + * @retval The new state of SDIO IT (SET or RESET). + */ +#define __HAL_SDIO_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDIO interrupt is enabled or not. + * @param __HANDLE__ : SDIO handle. + * @param __INTERRUPT__ : specifies the SDMMC interrupt source to check. + * @retval The state of SDIO IT (SET or RESET). + */ +#define __HAL_SDIO_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + __SDMMC_GET_IT_SOURCE((__HANDLE__)->Instance, (__INTERRUPT__)) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Functions SDIO Exported Functions + * @{ + */ +/** @defgroup SDIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio); + +void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide); +HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed); + +HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize); +HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate); + +HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr); +HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group3 Process functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData); +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data); + +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); + +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); + +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte); + +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group4 IRQHandler and callback functions + * @{ + */ +void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio); + +void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func); +#if (USE_SDIO_TRANSCEIVER != 0U) +/* Callback to switch in 1.8V mode */ +void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID, + pSDIO_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio); +#endif /* USE_SDIO_TRANSCEIVER */ + +HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, + HAL_SDIO_IOFunction_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio); +uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group6 Peripheral IO interrupt + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Types SDIO Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines ---------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Defines SDIO Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Variables SDIO Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Constants SDIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Macros SDIO Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes --------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions_Prototypes SDIO Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions SDIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_SDIO_H */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h index cee1ffdd39..e90d546c25 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h @@ -211,7 +211,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); * @{ */ /* SDRAM State functions ********************************************************/ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h index 4180c713c3..0a9e11ae26 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h @@ -92,7 +92,7 @@ typedef struct SWPMI_InitTypeDef Init; /*!< SWPMI communication parameters */ - uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ + const uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ uint32_t TxXferSize; /*!< SWPMI Tx Transfer size */ @@ -122,7 +122,7 @@ typedef struct void (*ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */ void (*MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */ void (*MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */ -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } SWPMI_HandleTypeDef; @@ -145,7 +145,7 @@ typedef enum * @brief SWPMI callback pointer definition */ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @} @@ -170,7 +170,7 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); #define HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080) /*!< Transceiver not ready */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) #define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100) /*!< Invalid callback error */ -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @} */ @@ -258,14 +258,14 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); * @retval None */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) -#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET) -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @brief Enable the SWPMI peripheral. @@ -401,7 +401,8 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET) +#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__))\ + == (__IT__)) ? SET : RESET) /** * @} @@ -424,14 +425,15 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, pSWPMI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi); HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi); @@ -444,8 +446,8 @@ void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi); /* Peripheral Control and State functions ************************************/ -HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi); -uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); +HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(const SWPMI_HandleTypeDef *hswpmi); +uint32_t HAL_SWPMI_GetError(const SWPMI_HandleTypeDef *hswpmi); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h index c6fced0281..5f0db22055 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h @@ -1233,7 +1233,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1248,8 +1248,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h index 518c0aa35b..28ba1ed155 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h @@ -706,8 +706,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h index 8f2e4dc190..bee4437edb 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h index c8f38afa43..8ca787b35c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h @@ -386,12 +386,12 @@ extern "C" { #endif /* ADC_VER_V5_3 */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) +#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) #define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor , temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR 110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */ #else -#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been +#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */ #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ @@ -2600,7 +2600,7 @@ typedef struct * (1) Available on devices with several ADC instances. * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { uint32_t data_reg_addr; @@ -2688,7 +2688,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); } @@ -2750,7 +2750,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); } @@ -2887,7 +2887,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Retrieve bits with position in register depending on parameter */ /* "SingleDiff". */ @@ -3059,7 +3059,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * (1): Specific to ADC instance: ADC1, ADC2 * (2): Specific to ADC instance: ADC3 */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { #if defined (ADC_VER_V5_3) @@ -3204,7 +3204,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); } @@ -3285,7 +3285,7 @@ __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_19 * @retval the preselection state of Channel (!= 0 : pre-selected, == 0 : not pre-selected) */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) if (ADCx != ADC3) @@ -3458,7 +3458,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3484,7 +3484,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off * @arg @ref LL_ADC_OFFSET_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3526,7 +3526,7 @@ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offset * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(const ADC_TypeDef *ADCx, uint32_t Offsety) { return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL)); } @@ -3581,7 +3581,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { #if defined(ADC_VER_V5_V90) if (ADCx == ADC3) @@ -3649,7 +3649,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offs * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { if (ADCx == ADC3) { @@ -3713,7 +3713,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety) { if (ADCx == ADC3) { @@ -3787,7 +3787,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); if (ADCx == ADC3) @@ -3898,7 +3898,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); @@ -3925,7 +3925,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } @@ -3960,7 +3960,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } @@ -4105,7 +4105,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); } @@ -4160,7 +4160,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); } @@ -4354,7 +4354,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); @@ -4400,7 +4400,7 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); } @@ -4438,7 +4438,7 @@ __STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx) CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN); } -__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL); } @@ -4515,7 +4515,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t D * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(const ADC_TypeDef *ADCx) { if (ADCx == ADC3) { @@ -4544,7 +4544,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED * @arg @ref LL_ADC_REG_DFSDM_TRANSFER */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT)); } @@ -4584,7 +4584,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); } @@ -4685,7 +4685,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); @@ -4712,7 +4712,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } @@ -4747,7 +4747,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); } @@ -4794,7 +4794,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); } @@ -4827,7 +4827,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); } @@ -4962,7 +4962,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) @@ -5014,7 +5014,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); } @@ -5075,7 +5075,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMo * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); } @@ -5491,7 +5491,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); @@ -5623,7 +5623,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_19 * @retval 0: channel in single-ended mode, else: channel in differential mode */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); @@ -5910,7 +5910,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * * (0) On STM32H7, parameter available only on analog watchdog number: AWD1. */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); @@ -6085,7 +6085,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { #if defined(ADC_VER_V5_V90) if (ADCx == ADC3) @@ -6245,7 +6245,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES */ -__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) { if (ADCx == ADC3) { @@ -6318,7 +6318,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); } @@ -6364,7 +6364,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); } @@ -6441,7 +6441,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { #if defined(ADC_VER_V5_V90) if(ADCx==ADC3) @@ -6478,7 +6478,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } @@ -6536,7 +6536,7 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode) * @param ADCx ADC instance * @retval 0: Boost disabled 1: Boost enabled */ -__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(const ADC_TypeDef *ADCx) { if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */ { @@ -6598,7 +6598,7 @@ __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint3 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ -__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); } @@ -6689,7 +6689,7 @@ __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF)); } @@ -6767,7 +6767,7 @@ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_C * (6) Parameter available only if ADC resolution is 12 bits. * (7) Parameter available only if ADC resolution is 16 or 14 bits. */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); } @@ -6829,7 +6829,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } @@ -6878,7 +6878,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -6938,7 +6938,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -6949,7 +6949,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -7003,7 +7003,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t Calibra * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -7070,7 +7070,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -7081,7 +7081,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -7095,7 +7095,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7110,7 +7110,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7125,7 +7125,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7140,7 +7140,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7155,7 +7155,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7170,7 +7170,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7195,7 +7195,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_MULTI_MASTER_SLAVE * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) @@ -7265,7 +7265,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } @@ -7276,7 +7276,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } @@ -7298,7 +7298,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7325,7 +7325,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7352,7 +7352,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7379,7 +7379,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7406,7 +7406,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7433,7 +7433,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7459,7 +7459,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -7470,7 +7470,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -7481,7 +7481,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -7492,7 +7492,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -7503,7 +7503,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -7514,7 +7514,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } @@ -7525,7 +7525,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } @@ -7536,7 +7536,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } @@ -7547,7 +7547,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); } @@ -7558,7 +7558,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -7569,7 +7569,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -7580,7 +7580,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -7716,7 +7716,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } @@ -7728,7 +7728,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } @@ -7740,7 +7740,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7752,7 +7752,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7764,7 +7764,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } @@ -7776,7 +7776,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } @@ -7788,7 +7788,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } @@ -7800,7 +7800,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } @@ -7812,7 +7812,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } @@ -7824,7 +7824,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } @@ -7836,7 +7836,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } @@ -7848,7 +7848,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } @@ -7860,7 +7860,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } @@ -7872,7 +7872,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } @@ -7884,7 +7884,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } @@ -7896,7 +7896,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } @@ -7908,7 +7908,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } @@ -7920,7 +7920,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } @@ -7932,7 +7932,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } @@ -7944,7 +7944,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } @@ -7956,7 +7956,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } @@ -7968,7 +7968,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } @@ -8230,7 +8230,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -8242,7 +8242,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -8254,7 +8254,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -8266,7 +8266,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -8278,7 +8278,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -8290,7 +8290,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } @@ -8302,7 +8302,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } @@ -8314,7 +8314,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } @@ -8326,7 +8326,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -8338,7 +8338,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -8350,7 +8350,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -8365,7 +8365,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) */ /* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h index 8db1b7cc6f..72b747a64e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h @@ -132,7 +132,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX2_Request_selection + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */ @@ -499,7 +499,7 @@ LL_BDMA_CHANNEL_7) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -521,7 +521,7 @@ __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -543,7 +543,7 @@ __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channe * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -584,7 +584,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_BDMA_ConfigTransfer(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -613,7 +613,7 @@ __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channe * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) +__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -640,7 +640,7 @@ __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint3 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -668,7 +668,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, u * @arg @ref LL_BDMA_MODE_CIRCULAR * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) +__STATIC_INLINE void LL_BDMA_SetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -693,7 +693,7 @@ __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint * @arg @ref LL_BDMA_MODE_NORMAL * @arg @ref LL_BDMA_MODE_CIRCULAR */ -__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -719,7 +719,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_PERIPH_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -744,7 +744,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_PERIPH_INCREMENT * @arg @ref LL_BDMA_PERIPH_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -770,7 +770,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_MEMORY_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -795,7 +795,7 @@ __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_MEMORY_INCREMENT * @arg @ref LL_BDMA_MEMORY_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -822,7 +822,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +__STATIC_INLINE void LL_BDMA_SetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -848,7 +848,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD * @arg @ref LL_BDMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -875,7 +875,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +__STATIC_INLINE void LL_BDMA_SetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -901,7 +901,7 @@ __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD * @arg @ref LL_BDMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -929,7 +929,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -956,7 +956,7 @@ __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_PRIORITY_HIGH * @arg @ref LL_BDMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -982,7 +982,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, ui * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) +__STATIC_INLINE void LL_BDMA_SetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1007,7 +1007,7 @@ __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1033,7 +1033,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) +__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1057,7 +1057,7 @@ __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t C * @arg @ref LL_BDMA_CURRENTTARGETMEM0 * @arg @ref LL_BDMA_CURRENTTARGETMEM1 */ -__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1101,7 +1101,7 @@ __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_ * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1123,7 +1123,7 @@ __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { register uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1154,7 +1154,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, +__STATIC_INLINE void LL_BDMA_ConfigAddresses(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1191,7 +1191,7 @@ __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Chann * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1216,7 +1216,7 @@ __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) +__STATIC_INLINE void LL_BDMA_SetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1239,7 +1239,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1262,7 +1262,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1287,7 +1287,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1312,7 +1312,7 @@ __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1335,7 +1335,7 @@ __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1358,7 +1358,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1381,7 +1381,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t * @param Address Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) +__STATIC_INLINE void LL_BDMA_SetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1403,7 +1403,7 @@ __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1449,7 +1449,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_BDMA_SetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) { UNUSED(BDMAx); MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -1493,7 +1493,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Chan * * @note (*) Availability depends on devices. */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel) { UNUSED(BDMAx); return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -1513,7 +1513,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL); } @@ -1524,7 +1524,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1535,7 +1535,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1546,7 +1546,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1557,7 +1557,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1568,7 +1568,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1579,7 +1579,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1590,7 +1590,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL); } @@ -1611,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1622,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1633,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1644,7 +1644,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1655,7 +1655,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1677,7 +1677,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1688,7 +1688,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL); } @@ -1699,7 +1699,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1710,7 +1710,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1721,7 +1721,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1743,7 +1743,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1754,7 +1754,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1765,7 +1765,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1776,7 +1776,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL); } @@ -1787,7 +1787,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1798,7 +1798,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1809,7 +1809,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1820,7 +1820,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1831,7 +1831,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1842,7 +1842,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -2264,7 +2264,7 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2286,7 +2286,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2308,7 +2308,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2330,7 +2330,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2352,7 +2352,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2374,7 +2374,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2396,7 +2396,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2418,7 +2418,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Ch * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2440,7 +2440,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Ch * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h index 44fd717d1c..0a0ba77701 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h @@ -341,7 +341,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM * @arg @ref LL_COMP_WINDOWMODE_DISABLE * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON) { return (uint32_t)(READ_BIT(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE)); } @@ -378,7 +378,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER */ -__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_PWRMODE)); } @@ -480,7 +480,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) { #if defined (COMP_CFGRx_INP2SEL) return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INPSEL | COMP_CFGRx_INP2SEL)); @@ -549,7 +549,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 * @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP */ -__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INMSEL | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)); } @@ -580,7 +580,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_MEDIUM * @arg @ref LL_COMP_HYSTERESIS_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_HYST)); } @@ -615,7 +615,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED * @arg @ref LL_COMP_OUTPUTPOL_INVERTED */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_POLARITY)); } @@ -660,7 +660,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5 * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_BLANKING)); } @@ -685,7 +685,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_AF_PK2 * @retval None */ -__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uint32_t CompAFx) +__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(const COMP_TypeDef *COMPx, uint32_t CompAFx) { MODIFY_REG(COMP12->OR, 0x7FFUL, (COMPx == COMP1) ? ((~CompAFx) & 0x7FFUL) : CompAFx); } @@ -706,7 +706,7 @@ __STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uin * @arg @ref LL_COMP_AF_PI4 * @arg @ref LL_COMP_AF_PK2 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(COMP_TypeDef *COMPx ) +__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(const COMP_TypeDef *COMPx ) { return (uint32_t) ((COMPx == COMP1) ? ((~COMP12->OR) & 0x7FFUL) : (COMP12->OR & 0x7FFUL)); } @@ -751,7 +751,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_EN) == (COMP_CFGRx_EN)) ? 1UL : 0UL); } @@ -778,7 +778,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_LOCK) == (COMP_CFGRx_LOCK)) ? 1UL : 0UL); } @@ -803,7 +803,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -829,7 +829,7 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -847,7 +847,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval None */ -__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -895,7 +895,7 @@ __STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_ITEN) == (COMP_CFGRx_ITEN)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h index fe1f6f9efc..f36ebfc0ef 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h index c05815a94f..5195c3b7e6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h @@ -140,7 +140,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX1_Request_selection + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ @@ -486,7 +486,7 @@ typedef struct * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -508,7 +508,7 @@ __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -530,7 +530,7 @@ __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -571,7 +571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1 *@retval None */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -599,7 +599,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -624,7 +624,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -651,7 +651,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint * @arg @ref LL_DMA_MODE_PFCTRL * @retval None */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -677,7 +677,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t * @arg @ref LL_DMA_MODE_CIRCULAR * @arg @ref LL_DMA_MODE_PFCTRL */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -702,7 +702,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_PERIPH_INCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -726,7 +726,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_PERIPH_NOINCREMENT * @arg @ref LL_DMA_PERIPH_INCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -751,7 +751,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_MEMORY_INCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -775,7 +775,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_MEMORY_NOINCREMENT * @arg @ref LL_DMA_MEMORY_INCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -801,7 +801,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -826,7 +826,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -877,7 +877,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 * @retval None */ -__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -926,7 +926,7 @@ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_OFFSETSIZE_PSIZE * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 */ -__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -953,7 +953,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -979,7 +979,7 @@ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1001,7 +1001,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1023,7 +1023,7 @@ __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1048,7 +1048,7 @@ __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_ * @param NbData Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1072,7 +1072,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1396,7 +1396,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, * * @note (*) Availability depends on devices. */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Stream) { return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1421,7 +1421,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t St * @arg @ref LL_DMA_MBURST_INC16 * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1447,7 +1447,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_MBURST_INC8 * @arg @ref LL_DMA_MBURST_INC16 */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1474,7 +1474,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_PBURST_INC16 * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1500,7 +1500,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_PBURST_INC8 * @arg @ref LL_DMA_PBURST_INC16 */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1525,7 +1525,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1549,7 +1549,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_CURRENTTARGETMEM0 * @arg @ref LL_DMA_CURRENTTARGETMEM1 */ -__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1571,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1593,7 +1593,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1615,9 +1615,9 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL); } @@ -1643,7 +1643,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uin * @arg @ref LL_DMA_FIFOSTATUS_EMPTY * @arg @ref LL_DMA_FIFOSTATUS_FULL */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1665,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1687,7 +1687,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1714,7 +1714,7 @@ __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @retval None */ -__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1740,7 +1740,7 @@ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +__STATIC_INLINE void LL_DMA_ConfigFifo(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1801,7 +1801,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint3 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1837,7 +1837,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1862,7 +1862,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @param PeriphAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1885,7 +1885,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1908,7 +1908,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1933,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Str * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1981,7 +1981,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2004,7 +2004,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2027,7 +2027,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Str * @param Address Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +__STATIC_INLINE void LL_DMA_SetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2049,7 +2049,7 @@ __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2070,7 +2070,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t St * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); } @@ -2081,7 +2081,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); } @@ -2092,7 +2092,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); } @@ -2103,7 +2103,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); } @@ -2114,7 +2114,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); } @@ -2125,7 +2125,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); } @@ -2136,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); } @@ -2147,7 +2147,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); } @@ -2158,7 +2158,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); } @@ -2169,7 +2169,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); } @@ -2180,7 +2180,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); } @@ -2191,7 +2191,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); } @@ -2202,7 +2202,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); } @@ -2213,7 +2213,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); } @@ -2224,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); } @@ -2235,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); } @@ -2246,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); } @@ -2257,7 +2257,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); } @@ -2268,7 +2268,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); } @@ -2279,7 +2279,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); } @@ -2290,7 +2290,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); } @@ -2301,7 +2301,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); } @@ -2312,7 +2312,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); } @@ -2323,7 +2323,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); } @@ -2334,7 +2334,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); } @@ -2345,7 +2345,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); } @@ -2356,7 +2356,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); } @@ -2367,7 +2367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); } @@ -2378,7 +2378,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); } @@ -2389,7 +2389,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); } @@ -2400,7 +2400,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); } @@ -2411,7 +2411,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); } @@ -2422,7 +2422,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); } @@ -2433,7 +2433,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); } @@ -2444,7 +2444,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); } @@ -2455,7 +2455,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); } @@ -2466,7 +2466,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); } @@ -2477,7 +2477,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); } @@ -2488,7 +2488,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); } @@ -2499,7 +2499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); } @@ -2967,7 +2967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2989,7 +2989,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3011,7 +3011,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3033,7 +3033,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3055,7 +3055,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3077,7 +3077,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3099,7 +3099,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3121,7 +3121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3143,7 +3143,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3165,7 +3165,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3187,7 +3187,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3209,7 +3209,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3231,7 +3231,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3253,7 +3253,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3275,7 +3275,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h index daea475843..905cbc7eaf 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h @@ -582,7 +582,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); } @@ -619,7 +619,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); } @@ -644,7 +644,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); } @@ -679,7 +679,7 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG */ -__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); } @@ -712,7 +712,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); } @@ -739,7 +739,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_ * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); } @@ -766,7 +766,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } @@ -794,7 +794,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); } @@ -821,7 +821,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); } @@ -844,7 +844,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line * @param DMA2Dx DMA2D Instance * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); } @@ -867,7 +867,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint * @param DMA2Dx DMA2D Instance * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); } @@ -890,7 +890,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrO * @param DMA2Dx DMA2D Instance * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); } @@ -913,7 +913,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t O * @param DMA2Dx DMA2D Instance * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); } @@ -934,8 +934,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) { - MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ - OutputColor); + WRITE_REG(DMA2Dx->OCOLR, OutputColor); } /** @@ -950,7 +949,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t Out * @param DMA2Dx DMA2D Instance * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); @@ -974,7 +973,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t L * @param DMA2Dx DMA2D Instance * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); } @@ -997,7 +996,7 @@ __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTi * @param DMA2Dx DMA2D Instance * @retval Dead time value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); } @@ -1030,7 +1029,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); } @@ -1057,7 +1056,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); } @@ -1079,7 +1078,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); } @@ -1124,7 +1123,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); } @@ -1153,7 +1152,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); } @@ -1176,7 +1175,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); } @@ -1203,7 +1202,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); } @@ -1230,7 +1229,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); } @@ -1253,7 +1252,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); } @@ -1293,7 +1292,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); } @@ -1316,7 +1315,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); } @@ -1339,7 +1338,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); } @@ -1362,7 +1361,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); } @@ -1385,7 +1384,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); } @@ -1412,7 +1411,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); } @@ -1441,7 +1440,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint * @arg @ref LL_DMA2D_CSS_422 * @arg @ref LL_DMA2D_CSS_420 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); } @@ -1471,7 +1470,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); } @@ -1493,7 +1492,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); } @@ -1538,7 +1537,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); } @@ -1567,7 +1566,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); } @@ -1590,7 +1589,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); } @@ -1617,7 +1616,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); } @@ -1644,7 +1643,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); } @@ -1667,7 +1666,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); } @@ -1707,7 +1706,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); } @@ -1730,7 +1729,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); } @@ -1753,7 +1752,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); } @@ -1776,7 +1775,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); } @@ -1799,7 +1798,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); } @@ -1826,7 +1825,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); } @@ -1850,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); } @@ -1861,7 +1860,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); } @@ -1872,7 +1871,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); } @@ -1883,7 +1882,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); } @@ -1894,7 +1893,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); } @@ -1905,7 +1904,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); } @@ -2122,7 +2121,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); } @@ -2133,7 +2132,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); } @@ -2144,7 +2143,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); } @@ -2155,7 +2154,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); } @@ -2166,7 +2165,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); } @@ -2177,7 +2176,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); } @@ -2193,16 +2192,16 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) * @{ */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx); ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h index bf4cffa0bc..be9b2fc40f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h @@ -726,7 +726,7 @@ extern "C" { * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -919,7 +919,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -950,7 +950,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -980,7 +980,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1015,7 +1015,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_SYNC_POL_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1109,7 +1109,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1139,7 +1139,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1169,7 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1199,7 +1199,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1229,7 +1229,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1284,7 +1284,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX2_SYNC_EXTI2 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1338,7 +1338,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI2 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1360,7 +1360,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1400,7 +1400,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1427,7 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1453,7 +1453,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1477,7 +1477,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1561,7 +1561,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1607,7 +1607,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI2 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1628,7 +1628,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1641,7 +1641,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1654,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1667,7 +1667,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1680,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1693,7 +1693,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1706,7 +1706,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1719,7 +1719,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1745,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1758,7 +1758,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1784,7 +1784,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1797,7 +1797,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1810,7 +1810,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1823,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1836,7 +1836,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1849,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1862,7 +1862,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1875,7 +1875,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1888,7 +1888,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1901,7 +1901,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1914,7 +1914,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1927,7 +1927,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1940,7 +1940,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1953,7 +1953,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1966,7 +1966,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1979,7 +1979,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1992,7 +1992,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2005,7 +2005,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2018,7 +2018,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2031,7 +2031,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2044,7 +2044,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2057,7 +2057,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2070,7 +2070,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2083,7 +2083,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2109,7 +2109,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2122,7 +2122,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2135,7 +2135,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2148,7 +2148,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2161,7 +2161,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2174,7 +2174,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2187,7 +2187,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2200,7 +2200,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2213,7 +2213,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2226,7 +2226,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2239,7 +2239,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2277,7 +2277,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2307,7 +2307,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2337,7 +2337,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2359,7 +2359,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2381,7 +2381,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2403,7 +2403,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h index 8e92c3d4d1..5edb287d86 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h index 3d34898e39..7509bcedbf 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h @@ -190,61 +190,62 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ } FMC_NORSRAM_InitTypeDef; /** @@ -288,7 +289,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; /** @@ -1056,11 +1057,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -1086,11 +1087,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -1101,7 +1102,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -1117,9 +1118,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1131,7 +1132,7 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h index b51f9d3bf9..b099741d98 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h @@ -309,7 +309,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); } @@ -377,7 +377,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); } @@ -450,7 +450,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); } @@ -515,7 +515,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); } @@ -591,7 +591,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); @@ -669,7 +669,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * @@ -741,7 +741,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -752,7 +752,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) { return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } @@ -771,7 +771,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) * @param GPIOx GPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } @@ -800,7 +800,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -823,7 +823,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV * @param GPIOx GPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -954,7 +954,7 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @{ */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h index d3f3608fe1..741d758b9d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h @@ -1972,7 +1972,7 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT { uint32_t shift = ((3U * ADCTrig) & 0x1FU); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); WRITE_REG(*pReg, Src); } @@ -2247,7 +2247,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); WRITE_REG(*pReg, Src); } @@ -2464,7 +2464,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); return (*pReg); } @@ -3138,7 +3138,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3158,7 +3158,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3178,7 +3178,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -3209,7 +3209,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -3238,7 +3238,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -3268,7 +3268,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -3290,7 +3290,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -3313,7 +3313,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -3335,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -3358,7 +3358,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -3380,7 +3380,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -3405,7 +3405,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -3429,7 +3429,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -3454,7 +3454,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -3478,7 +3478,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -3503,7 +3503,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -3527,7 +3527,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -3552,7 +3552,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -3576,7 +3576,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -3663,7 +3663,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -3743,7 +3743,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3763,7 +3763,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3783,7 +3783,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3871,7 +3871,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); WRITE_REG(*pReg, CaptureTrig); } @@ -3957,7 +3957,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); return (READ_REG(*pReg)); } @@ -3977,7 +3977,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -3997,7 +3997,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4017,7 +4017,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRT { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); } @@ -4062,7 +4062,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -4103,7 +4103,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -4124,7 +4124,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4145,7 +4145,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4165,7 +4165,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -4195,7 +4195,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -4225,7 +4225,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -4255,7 +4255,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); } @@ -4277,7 +4277,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -4442,7 +4442,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeD { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -4464,7 +4464,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -4524,7 +4524,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4581,7 +4581,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4627,7 +4627,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4670,7 +4670,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *H uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4704,7 +4704,7 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -4733,7 +4733,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -4761,7 +4761,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -4782,7 +4782,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -4802,7 +4802,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -4825,7 +4825,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -4847,7 +4847,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -4868,7 +4868,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -4888,7 +4888,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -4911,7 +4911,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -4933,7 +4933,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -4953,7 +4953,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -4973,7 +4973,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -4993,7 +4993,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -5013,7 +5013,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -5049,7 +5049,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -5089,7 +5089,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -5125,7 +5125,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -5157,7 +5157,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -5185,7 +5185,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -5224,7 +5224,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -5260,7 +5260,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -5389,7 +5389,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -5509,7 +5509,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIM { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5630,7 +5630,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -5750,7 +5750,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRT { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5793,7 +5793,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5823,7 +5823,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5851,7 +5851,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5881,7 +5881,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } @@ -5909,7 +5909,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5940,7 +5940,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5968,7 +5968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6001,7 +6001,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6031,7 +6031,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6061,7 +6061,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6089,7 +6089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6119,7 +6119,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6147,7 +6147,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6176,7 +6176,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HR { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); } @@ -6214,7 +6214,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -6242,7 +6242,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); } @@ -6323,7 +6323,7 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6363,7 +6363,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6401,7 +6401,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6440,7 +6440,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6476,7 +6476,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6516,7 +6516,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6554,7 +6554,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6587,7 +6587,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6618,7 +6618,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6770,7 +6770,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6799,7 +6799,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6824,8 +6824,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6853,7 +6853,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6878,8 +6878,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6921,7 +6921,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6960,8 +6960,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7017,7 +7017,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7041,7 +7041,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7065,7 +7065,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7089,7 +7089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); } @@ -7765,7 +7765,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -7787,7 +7787,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); } @@ -7810,7 +7810,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); } @@ -7833,7 +7833,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); } @@ -7856,7 +7856,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -7878,7 +7878,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); } @@ -7901,7 +7901,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -7923,7 +7923,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); } @@ -7946,7 +7946,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -7968,7 +7968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); } @@ -7991,7 +7991,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -8013,7 +8013,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); } @@ -8034,7 +8034,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -8054,7 +8054,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); } @@ -8075,7 +8075,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -8095,7 +8095,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); } @@ -8116,7 +8116,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -8136,7 +8136,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); } @@ -8157,7 +8157,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -8177,7 +8177,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); } @@ -8198,7 +8198,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -8218,7 +8218,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); } @@ -8239,7 +8239,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -8259,7 +8259,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); } @@ -8280,7 +8280,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -8300,7 +8300,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); } @@ -8321,7 +8321,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -8341,7 +8341,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); } @@ -8636,7 +8636,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8658,7 +8658,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8680,7 +8680,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); } @@ -8703,7 +8703,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8725,7 +8725,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8747,7 +8747,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); } @@ -8770,7 +8770,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8792,7 +8792,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8814,7 +8814,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); } @@ -8837,7 +8837,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8859,7 +8859,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8881,7 +8881,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); } @@ -8904,7 +8904,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -8926,7 +8926,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -8948,7 +8948,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); } @@ -8971,7 +8971,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -8993,7 +8993,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9015,7 +9015,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); } @@ -9036,7 +9036,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9056,7 +9056,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9076,7 +9076,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); } @@ -9097,7 +9097,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9117,7 +9117,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9137,7 +9137,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); } @@ -9158,7 +9158,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9178,7 +9178,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9198,7 +9198,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); } @@ -9219,7 +9219,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9239,7 +9239,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9259,7 +9259,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); } @@ -9280,7 +9280,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9300,7 +9300,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9320,7 +9320,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); } @@ -9341,7 +9341,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9361,7 +9361,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9381,7 +9381,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); } @@ -9402,7 +9402,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9422,7 +9422,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9442,7 +9442,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); } @@ -9463,7 +9463,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9483,7 +9483,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9503,7 +9503,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); } @@ -9567,7 +9567,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9589,7 +9589,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9611,7 +9611,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); } @@ -9634,7 +9634,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9656,7 +9656,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9678,7 +9678,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); } @@ -9701,7 +9701,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9723,7 +9723,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9745,7 +9745,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); } @@ -9768,7 +9768,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9790,7 +9790,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9812,7 +9812,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); } @@ -9835,7 +9835,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9857,7 +9857,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9879,7 +9879,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); } @@ -9902,7 +9902,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9924,7 +9924,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9946,7 +9946,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); } @@ -9967,7 +9967,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -9987,7 +9987,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10007,7 +10007,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); } @@ -10028,7 +10028,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10048,7 +10048,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10068,7 +10068,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); } @@ -10089,7 +10089,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10109,7 +10109,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10129,7 +10129,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); } @@ -10150,7 +10150,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10170,7 +10170,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10190,7 +10190,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); } @@ -10211,7 +10211,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10231,7 +10231,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10251,7 +10251,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); } @@ -10272,7 +10272,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10292,7 +10292,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10312,7 +10312,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); } @@ -10333,7 +10333,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10353,7 +10353,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10373,7 +10373,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); } @@ -10394,7 +10394,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10414,7 +10414,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10434,7 +10434,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); } @@ -10447,7 +10447,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions * @{ */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx); /** * @} */ @@ -10473,4 +10473,3 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); #endif /* STM32H7xx_LL_HRTIM_H */ - diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h index cff88b5cd5..689b7e57e8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h @@ -163,7 +163,7 @@ extern "C" { * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); } @@ -178,7 +178,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_COREID_CPU1 * @arg @ref LL_HSEM_COREID_CPU2 */ -__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); } @@ -190,7 +190,7 @@ __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval Process number. Value between Min_Data=0 and Max_Data=255 */ -__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); } @@ -236,7 +236,7 @@ __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 1 lock fail, 0 lock successful or already locked by same core */ -__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); } @@ -261,7 +261,7 @@ __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore * @param HSEMx HSEM Instance. * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 0 semaphore is free, 1 semaphore is locked */ -__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) * @param HSEMx HSEM Instance. * @retval key to unlock all semaphore from the same core */ -__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) +__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx) { return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); } @@ -450,7 +450,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semap * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -586,7 +586,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -689,7 +689,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -736,7 +736,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_ * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -827,7 +827,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -872,7 +872,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_ * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h index d34acc2622..743c91730e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h @@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } @@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h index fe66becb5b..2f362a4e74 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h @@ -2605,6 +2605,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h index 8b80c7d811..a55cb82897 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h @@ -688,7 +688,7 @@ typedef struct * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -718,7 +718,7 @@ __STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -748,7 +748,7 @@ __STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -778,7 +778,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_GenerateSWRequest(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -814,7 +814,7 @@ __STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE or @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -848,7 +848,7 @@ __STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -881,7 +881,7 @@ __STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -914,7 +914,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -947,7 +947,7 @@ __STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -980,7 +980,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetByteEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1013,7 +1013,7 @@ __STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1048,7 +1048,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1083,7 +1083,7 @@ __STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1143,7 +1143,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, ui * @param BufferXferLength This parameter can be a value Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength) +__STATIC_INLINE void LL_MDMA_ConfigTransfer(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1174,7 +1174,7 @@ __STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1204,7 +1204,7 @@ __STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1234,7 +1234,7 @@ __STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1267,7 +1267,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, * @arg @ref LL_MDMA_REQUEST_MODE_SW * @retval None */ -__STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode) +__STATIC_INLINE void LL_MDMA_SetRequestMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1300,7 +1300,7 @@ __STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_REQUEST_MODE_SW * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1335,7 +1335,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_FULL_TRANSFER * @retval None */ -__STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode) +__STATIC_INLINE void LL_MDMA_SetTriggerMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1370,7 +1370,7 @@ __STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_FULL_TRANSFER * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1404,7 +1404,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_DATAALIGN_LEFT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment) +__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_DATAALIGN_LEFT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1469,7 +1469,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnablePacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisablePacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1529,7 +1529,7 @@ __STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1560,7 +1560,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t * @param Length Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length) +__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1592,7 +1592,7 @@ __STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32 * @retval Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1631,7 +1631,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, ui * @arg @ref LL_MDMA_DEST_BURST_128BEATS * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst) +__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1670,7 +1670,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_DEST_BURST_128BEATS * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, ui * @arg @ref LL_MDMA_SRC_BURST_128BEATS * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst) +__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1748,7 +1748,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BURST_128BEATS * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1783,7 +1783,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) +__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1818,7 +1818,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) +__STATIC_INLINE void LL_MDMA_SetSourceIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1888,7 +1888,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Chan * @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1923,7 +1923,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize) +__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1993,7 +1993,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize) +__STATIC_INLINE void LL_MDMA_SetSourceDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2028,7 +2028,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2062,7 +2062,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode) +__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2130,7 +2130,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_SRC_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode) +__STATIC_INLINE void LL_MDMA_SetSourceIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2164,7 +2164,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Chan * @arg @ref LL_MDMA_SRC_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2197,7 +2197,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t * @param BlkDataLength Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength) +__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2230,7 +2230,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Cha * @param BlkDataLength Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength) +__STATIC_INLINE void LL_MDMA_SetBlkDataLength(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2261,7 +2261,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Chan * @retval Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2292,7 +2292,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t * @param BlockRepeatCount Between 0 to 0x00000FFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2324,7 +2324,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Cha * @retval Between 0 to 0x00000FFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2358,7 +2358,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT or @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2393,7 +2393,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2426,7 +2426,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2459,7 +2459,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2492,7 +2492,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2526,7 +2526,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress) +__STATIC_INLINE void LL_MDMA_ConfigAddresses(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2557,7 +2557,7 @@ __STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Chann * @param SrcAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress) +__STATIC_INLINE void LL_MDMA_SetSourceAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2588,7 +2588,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Chan * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2619,7 +2619,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t * @param DestAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress) +__STATIC_INLINE void LL_MDMA_SetDestinationAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2650,7 +2650,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2684,7 +2684,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint * @param DestAdrUpdateValue Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2716,7 +2716,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, ui * @param DestAdrUpdateValue Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2748,7 +2748,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, u * @retval Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2779,7 +2779,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMA * @param SrcAdrUpdateValue Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2810,7 +2810,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, ui * @retval Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2841,7 +2841,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx * @param LinkAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress) +__STATIC_INLINE void LL_MDMA_SetLinkAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2872,7 +2872,7 @@ __STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channe * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2906,7 +2906,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI or @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2941,7 +2941,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_DEST_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus) +__STATIC_INLINE void LL_MDMA_SetDestBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2974,7 +2974,7 @@ __STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_DEST_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3007,7 +3007,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus) +__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3040,7 +3040,7 @@ __STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3108,7 +3108,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_ * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest) +__STATIC_INLINE void LL_MDMA_SetHWTrigger(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3176,7 +3176,7 @@ __STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3207,7 +3207,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Chan * @param MaskAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress) +__STATIC_INLINE void LL_MDMA_SetMaskAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3238,7 +3238,7 @@ __STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channe * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3269,7 +3269,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Ch * @param MaskData Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData) +__STATIC_INLINE void LL_MDMA_SetMaskData(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3300,7 +3300,7 @@ __STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3333,7 +3333,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Chann * @arg @ref LL_MDMA_WRITE_ERROR * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3364,7 +3364,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint * @retval Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3402,7 +3402,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(const MDMA_TypeDef *MDMAx, uint32_t Channel) { return ((READ_BIT(MDMAx->GISR0 ,(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU)))==(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } @@ -3430,7 +3430,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3460,7 +3460,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3490,7 +3490,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3520,7 +3520,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3550,7 +3550,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3580,7 +3580,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3610,7 +3610,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3640,7 +3640,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3670,7 +3670,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3700,7 +3700,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3730,7 +3730,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3760,7 +3760,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3790,7 +3790,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3820,7 +3820,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3850,7 +3850,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3888,7 +3888,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3918,7 +3918,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3948,7 +3948,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3978,7 +3978,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4008,7 +4008,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4038,7 +4038,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4068,7 +4068,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4098,7 +4098,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4128,7 +4128,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4158,7 +4158,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4188,7 +4188,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4218,7 +4218,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4248,7 +4248,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4278,7 +4278,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4308,7 +4308,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h index 03ab42c701..abd81e3e43 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h @@ -392,7 +392,7 @@ __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode) * @arg @ref LL_OPAMP_MODE_FUNCTIONAL * @arg @ref LL_OPAMP_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON)); } @@ -434,7 +434,7 @@ __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS * @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS */ -__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL)); } @@ -469,7 +469,7 @@ __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain * @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 * @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)); } @@ -498,7 +498,7 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power * @arg @ref LL_OPAMP_POWERMODE_NORMAL * @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(const OPAMP_TypeDef *OPAMPx) { uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAHSM)); @@ -536,7 +536,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2) */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL)); } @@ -572,7 +572,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(const OPAMP_TypeDef *OPAMPx) { uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL); @@ -611,7 +611,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t Tr * @arg @ref LL_OPAMP_TRIMMING_FACTORY * @arg @ref LL_OPAMP_TRIMMING_USER */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM)); } @@ -658,7 +658,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin * using two trimming steps (one with each transistors differential * pair NMOS and PMOS) */ -__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(const OPAMP_TypeDef *OPAMPx) { uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); @@ -675,7 +675,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT)?1UL:0UL); } @@ -728,7 +728,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t P * @arg @ref LL_OPAMP_TRIMMING_PMOS * @retval 0x0...0x1F */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(const OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) { const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); @@ -779,7 +779,7 @@ __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN))?1UL:0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h index 62039d0e6b..cf1ab84f12 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h @@ -680,7 +680,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h index 85e6fadda7..d792373e92 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h @@ -252,7 +252,9 @@ typedef struct #define LL_RTC_ISR_ITSF RTC_ISR_ITSF #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF #define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F +#endif /* RTC_TAMPER2_SUPPORT */ #define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F #define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF #define LL_RTC_ISR_TSF RTC_ISR_TSF @@ -280,9 +282,11 @@ typedef struct #define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE #define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE #if !defined(TAMP) +#if defined(RTC_TAMPxIE_SUPPORT) #define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE #define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE #define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE +#endif /* RTC_TAMPxIE_SUPPORT */ #define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE #endif /* !TAMP */ /** @@ -527,13 +531,17 @@ typedef struct * @{ */ #define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */ +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */ +#endif /* RTC_TAMPER2_SUPPORT */ #define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */ /** * @} */ /** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @note These values are not applicable to the STM32H723/33, STM32H725/35 and STM32H730 devices, + * and have been kept for backward compatibility. * @{ */ #define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ @@ -544,6 +552,8 @@ typedef struct */ /** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @note These values are not applicable to the STM32H723/33, STM32H725/35 and STM32H730 devices, + * and have been kept for backward compatibility. * @{ */ #define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ @@ -903,7 +913,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat * @arg @ref LL_RTC_HOURFORMAT_24HOUR * @arg @ref LL_RTC_HOURFORMAT_AMPM */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); } @@ -935,7 +945,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu * @arg @ref LL_RTC_ALARMOUT_ALMB * @arg @ref LL_RTC_ALARMOUT_WAKEUP */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } @@ -992,7 +1002,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); } @@ -1078,7 +1088,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); } @@ -1112,7 +1122,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); } @@ -1173,7 +1183,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } @@ -1184,7 +1194,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); } @@ -1376,7 +1386,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 * @arg @ref LL_RTC_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); } @@ -1411,7 +1421,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } @@ -1446,7 +1456,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } @@ -1481,7 +1491,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); } @@ -1535,7 +1545,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1575,7 +1585,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); } @@ -1617,7 +1627,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Sub second value (number between 0 and 65535) */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); } @@ -1674,7 +1684,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } @@ -1713,7 +1723,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } @@ -1767,7 +1777,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } @@ -1797,7 +1807,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } @@ -1865,7 +1875,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1944,7 +1954,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMA_MASK_SECONDS * @arg @ref LL_RTC_ALMA_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); } @@ -1994,7 +2004,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } @@ -2031,7 +2041,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } @@ -2058,7 +2068,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); } @@ -2086,7 +2096,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } @@ -2114,7 +2124,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } @@ -2142,7 +2152,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } @@ -2214,7 +2224,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } @@ -2237,7 +2247,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); } @@ -2310,7 +2320,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMB_MASK_SECONDS * @arg @ref LL_RTC_ALMB_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); } @@ -2360,7 +2370,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } @@ -2397,7 +2407,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); } @@ -2424,7 +2434,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); } @@ -2452,7 +2462,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } @@ -2480,7 +2490,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } @@ -2508,7 +2518,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } @@ -2580,7 +2590,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); } @@ -2603,7 +2613,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); } @@ -2689,7 +2699,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); } @@ -2702,7 +2712,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TS_TIME_FORMAT_AM * @arg @ref LL_RTC_TS_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); } @@ -2715,7 +2725,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } @@ -2728,7 +2738,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } @@ -2741,7 +2751,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); } @@ -2759,7 +2769,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); @@ -2778,7 +2788,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } @@ -2803,7 +2813,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } @@ -2816,7 +2826,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2833,7 +2843,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2844,7 +2854,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } @@ -2916,13 +2926,14 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) /** * @brief Enable RTC_TAMPx input detection * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable - * TAMPCR TAMP2E LL_RTC_TAMPER_Enable + * TAMPCR TAMP2E LL_RTC_TAMPER_Enable (*) * TAMPCR TAMP3E LL_RTC_TAMPER_Enable * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_2 (*) * @arg @ref LL_RTC_TAMPER_3 + * (*) Not applicable to all devices. * * @retval None */ @@ -2934,13 +2945,14 @@ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) /** * @brief Clear RTC_TAMPx input detection * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Disable - * TAMPCR TAMP2E LL_RTC_TAMPER_Disable + * TAMPCR TAMP2E LL_RTC_TAMPER_Disable (*) * TAMPCR TAMP3E LL_RTC_TAMPER_Disable * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_2 (*) * @arg @ref LL_RTC_TAMPER_3 + * (*) Not applicable to all devices. * * @retval None */ @@ -2951,6 +2963,8 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) /** * @brief Enable Tamper mask flag + * @note This API shall not be used with STM32H723/33, STM32H725/35 and STM32H730 devices, + * and has been kept for backward compatibility. * @note Associated Tamper IT must not enabled when tamper mask is set. * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask * TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask @@ -2970,6 +2984,8 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) /** * @brief Disable Tamper mask flag + * @note This API shall not be used with STM32H723/33, STM32H725/35 and STM32H730 devices, + * and has been kept for backward compatibility. * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask * TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask @@ -2988,6 +3004,8 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) /** * @brief Enable backup register erase after Tamper event detection + * @note This API shall not be used with STM32H723/33, STM32H725/35 and STM32H730 devices, + * and has been kept for backward compatibility. * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP @@ -3006,6 +3024,8 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Ta /** * @brief Disable backup register erase after Tamper event detection + * @note This API shall not be used with STM32H723/33, STM32H725/35 and STM32H730 devices, + * and has been kept for backward compatibility. * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP @@ -3070,7 +3090,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Dura * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); } @@ -3101,7 +3121,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t Fi * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); } @@ -3140,7 +3160,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t S * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); } @@ -3148,13 +3168,14 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) /** * @brief Enable Active level for Tamper input * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel - * TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel + * TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel (*) * TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*) * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * (*) Not applicable to all devices. * * @retval None */ @@ -3166,13 +3187,14 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t /** * @brief Disable Active level for Tamper input * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel - * TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel + * TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel (*) * TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*) * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * (*) Not applicable to all devices. * * @retval None */ @@ -3490,7 +3512,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); } @@ -3527,7 +3549,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupCl * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } @@ -3551,7 +3573,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Val * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); } @@ -3656,7 +3678,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe * @arg @ref LL_RTC_BKP_DR31 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) { uint32_t tmp; @@ -3707,7 +3729,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -3805,7 +3827,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); } @@ -3832,7 +3854,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); } @@ -3865,7 +3887,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) * @arg @ref LL_RTC_CALIB_PERIOD_16SEC * @arg @ref LL_RTC_CALIB_PERIOD_8SEC */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); } @@ -3890,7 +3912,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); } @@ -3911,7 +3933,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL); } @@ -3922,7 +3944,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL); } @@ -3933,21 +3955,23 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL); } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Get RTC_TAMP2 detection flag * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2 * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL); } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Get RTC_TAMP1 detection flag @@ -3955,7 +3979,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL); } @@ -3966,7 +3990,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL); } @@ -3977,7 +4001,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL); } @@ -3988,7 +4012,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL); } @@ -3999,7 +4023,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL); } @@ -4010,7 +4034,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL); } @@ -4037,6 +4061,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Clear RTC_TAMP2 detection flag * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2 @@ -4047,6 +4072,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) { WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Clear RTC_TAMP1 detection flag @@ -4120,7 +4146,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL); } @@ -4131,7 +4157,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL); } @@ -4153,7 +4179,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL); } @@ -4164,7 +4190,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL); } @@ -4175,7 +4201,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL); } @@ -4186,7 +4212,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL); } @@ -4197,7 +4223,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); } @@ -4706,6 +4732,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) } #if !defined(TAMP) +#if defined(RTC_TAMPxIE_SUPPORT) /** * @brief Enable Tamper 3 interrupt * @rmtoll TAMPCR TAMP3IE LL_RTC_EnableIT_TAMP3 @@ -4728,6 +4755,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Enable Tamper 2 interrupt * @rmtoll TAMPCR TAMP2IE LL_RTC_EnableIT_TAMP2 @@ -4749,6 +4777,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Enable Tamper 1 interrupt @@ -4771,6 +4800,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); } +#endif /* RTC_TAMPxIE_SUPPORT */ /** * @brief Enable all Tamper Interrupt @@ -4801,7 +4831,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); } @@ -4812,7 +4842,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); } @@ -4823,7 +4853,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); } @@ -4834,19 +4864,20 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); } #if !defined(TAMP) +#if defined(RTC_TAMPxIE_SUPPORT) /** * @brief Check if Tamper 3 interrupt is enabled or not * @rmtoll TAMPCR TAMP3IE LL_RTC_IsEnabledIT_TAMP3 * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL); } @@ -4857,7 +4888,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL); @@ -4869,10 +4900,11 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL); } +#endif /* RTC_TAMPxIE_SUPPORT */ /** * @brief Check if all the TAMPER interrupts are enabled or not @@ -4880,7 +4912,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h index 6e12084e4b..9887fe0ec6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDMMC_LL * @{ */ @@ -61,10 +61,10 @@ typedef struct uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ -#if (USE_SD_TRANSCEIVER != 0U) +#if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U) uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ -#endif /* USE_SD_TRANSCEIVER */ +#endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */ } SDMMC_InitTypeDef; @@ -160,84 +160,128 @@ typedef struct #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ +/** + * @brief Masks for R5 Response + */ +/** this is the reserved for future use in spec RFU */ +#define SDMMC_SDIO_R5_ERROR ((uint32_t)0x00000400U) +/** Out of range error */ +#define SDMMC_SDIO_R5_OUT_OF_RANGE ((uint32_t)0x00000100U) +/** Invalid function number */ +#define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER ((uint32_t)0x00000200U) +/** General or an unknown error */ +#define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00000800U) +/** SDIO Card current state + * 00=DIS (card not selected) + * 01=CMD (data line free) + * 10=TRN (transfer on data lines) */ +#define SDMMC_SDIO_R5_IO_CURRENT_STATE ((uint32_t)0x00003000U) +/** Illegal command error */ +#define SDMMC_SDIO_R5_ILLEGAL_CMD ((uint32_t)0x00004000U) +/** CRC check of previous cmd failed */ +#define SDMMC_SDIO_R5_COM_CRC_FAILED ((uint32_t)0x00008000U) + +#define SDMMC_SDIO_R5_ERRORBITS (SDMMC_SDIO_R5_COM_CRC_FAILED | \ + SDMMC_SDIO_R5_ILLEGAL_CMD | \ + SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR | \ + SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \ + SDMMC_SDIO_R5_OUT_OF_RANGE) +/** + * @brief SDIO_CMD53_MODE + */ +#define SDMMC_SDIO_MODE_BYTE 0x00U /*!< Byte Mode */ +#define SDMMC_SDIO_MODE_BLOCK 0x01U /*!< Block Mode */ + +/** + * @brief SDIO_CMD53_OP_CODE + */ +#define SDMMC_SDIO_NO_INC 0x00U /*!< No auto indentation */ +#define SDMMC_SDIO_AUTO_INC 0x01U /*!< Auto indentation */ + +/** + * @brief SDIO_CMD53_RAW + */ +#define SDMMC_SDIO_WO 0x00U /*!< Write only Flag */ +#define SDMMC_SDIO_RAW 0x01U /*!< Read after write Flag */ + /** * @brief SDMMC Commands Index */ -#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ -#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ -#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ -#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ -#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ -#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ -#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ -#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ -#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_VOLTAGE_SWITCH 11U /*!< SD card Voltage switch to 1.8V mode. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ /*!< for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ -#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ -#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ -#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ -#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ -#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ -#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ -#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ -#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ -#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ -#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ -#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are MMC Specific commands. */ -#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ +#define SDMMC_CMD_MMC_SLEEP_AWAKE 5U /*!< Toggle the device between Sleep state and Standby state. */ /** * @brief Following commands are SD Card Specific security commands. * SDMMC_CMD_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) -#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) -#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) -#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) -#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) -#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) -#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) -#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) -#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U /** * @brief Masks for errors Card Status R1 (OCR Register) @@ -291,9 +335,14 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#endif /* SDMMC_SWDATATIMEOUT */ + #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) @@ -303,6 +352,8 @@ typedef struct #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) +/* SDMMC FIFO Size */ +#define SDMMC_FIFO_SIZE 32U /** * @brief Command Class supported */ @@ -543,9 +594,11 @@ typedef struct * @{ */ #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \ ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} @@ -657,6 +710,82 @@ typedef struct * @} */ +/** @defgroup SDMMC_SDIO_CCCR_Registers + * @{ + */ +/*-------------------------------- CCCR0 ----------------------------------*/ +#define SDMMC_SDIO_CCCR0 0x000U /*!< SDIOS Card Common Control Register 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE0 0x000U /*!< SDIOS Card Common Control Register 0 Byte 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE1 0x001U /*!< SDIOS Card Common Control Register 0 Byte 1 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE2 0x002U /*!< SDIOS Card Common Control Register 0 Byte 2 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE3 0x003U /*!< SDIOS Card Common Control Register 0 Byte 3 */ + +/*-------------------------------- CCCR4 ----------------------------------*/ +#define SDMMC_SDIO_CCCR4 0x004U /*!< SDIOS Card Common Control Register 4 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE0 0x004U /*!< SDIOS Card Common Control Register 4 Byte 0 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE1 0x005U /*!< SDIOS Card Common Control Register 4 Byte 1 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE2 0x006U /*!< SDIOS Card Common Control Register 4 Byte 2 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE3 0x007U /*!< SDIOS Card Common Control Register 4 Byte 3 */ + +/*-------------------------------- CCCR8 ----------------------------------*/ +#define SDMMC_SDIO_CCCR8 0x008U /*!< SDIOS Card Common Control Register 8 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE0 0x008U /*!< SDIOS Card Common Control Register 8 Byte 0 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE1 0x009U /*!< SDIOS Card Common Control Register 8 Byte 1 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE2 0x00AU /*!< SDIOS Card Common Control Register 8 Byte 2 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE3 0x00BU /*!< SDIOS Card Common Control Register 8 Byte 3 */ + +/*-------------------------------- CCCR12 ---------------------------------*/ +#define SDMMC_SDIO_CCCR12 0x00CU /*!< SDIOS Card Common Control Register 12 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE0 0x00CU /*!< SDIOS Card Common Control Register 12 Byte 0 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE1 0x00DU /*!< SDIOS Card Common Control Register 12 Byte 1 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE2 0x00EU /*!< SDIOS Card Common Control Register 12 Byte 2 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE3 0x00FU /*!< SDIOS Card Common Control Register 12 Byte 3 */ + +/*-------------------------------- CCCR16 ---------------------------------*/ +#define SDMMC_SDIO_CCCR16 0x010U /*!< SDIOS Card Common Control Register 16 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE0 0x010U /*!< SDIOS Card Common Control Register 16 Byte 0 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE1 0x011U /*!< SDIOS Card Common Control Register 16 Byte 1 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE2 0x012U /*!< SDIOS Card Common Control Register 16 Byte 2 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE3 0x013U /*!< SDIOS Card Common Control Register 16 Byte 3 */ + +/*-------------------------------- CCCR20 ---------------------------------*/ +#define SDMMC_SDIO_CCCR20 0x014U /*!< SDIOS Card Common Control Register 20 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE0 0x014U /*!< SDIOS Card Common Control Register 20 Byte 0 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE1 0x015U /*!< SDIOS Card Common Control Register 20 Byte 1 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE2 0x016U /*!< SDIOS Card Common Control Register 20 Byte 2 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE3 0x017U /*!< SDIOS Card Common Control Register 20 Byte 3 */ + +/*-------------------------------- F1BR0 ----------------------------------*/ +#define SDMMC_SDIO_F1BR0 0x100U /*!< SDIOS Function 1 Basic Register 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE0 0x100U /*!< SDIOS Function 1 Basic Register 0 Byte 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE1 0x101U /*!< SDIOS Function 1 Basic Register 0 Byte 1 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE2 0x102U /*!< SDIOS Function 1 Basic Register 0 Byte 2 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE3 0x103U /*!< SDIOS Function 1 Basic Register 0 Byte 3 */ + +/*-------------------------------- F1BR8 ----------------------------------*/ +#define SDMMC_SDIO_F1BR8 0x108U /*!< SDIOS Function 1 Basic Register 8 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE0 0x108U /*!< SDIOS Function 1 Basic Register 8 Byte 0 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE1 0x109U /*!< SDIOS Function 1 Basic Register 8 Byte 1 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE2 0x10AU /*!< SDIOS Function 1 Basic Register 8 Byte 2 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE3 0x10BU /*!< SDIOS Function 1 Basic Register 8 Byte 3 */ + +/*-------------------------------- F1BR12 ---------------------------------*/ +#define SDMMC_SDIO_F1BR12 0x10CU /*!< SDIOS Function 1 Basic Register 12 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE0 0x10CU /*!< SDIOS Function 1 Basic Register 12 Byte 0 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE1 0x10DU /*!< SDIOS Function 1 Basic Register 12 Byte 1 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE2 0x10EU /*!< SDIOS Function 1 Basic Register 12 Byte 2 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE3 0x10FU /*!< SDIOS Function 1 Basic Register 12 Byte 3 */ + +/*-------------------------------- F1BR16 ---------------------------------*/ +#define SDMMC_SDIO_F1BR16 0x110U /*!< SDIOS Function 1 Basic Register 16 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE0 0x110U /*!< SDIOS Function 1 Basic Register 16 Byte 0 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE1 0x111U /*!< SDIOS Function 1 Basic Register 16 Byte 1 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE2 0x112U /*!< SDIOS Function 1 Basic Register 16 Byte 2 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE3 0x113U /*!< SDIOS Function 1 Basic Register 16 Byte 3 */ +/** + * @} + */ + /** * @} */ @@ -871,6 +1000,38 @@ typedef struct */ #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) +/** + * @brief Checks the source of specified interrupt. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of SDMMC_IT (SET or RESET). + */ +#define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__))) + /** * @brief Clears the SDMMC's interrupt pending bits. * @param __INSTANCE__ Pointer to SDMMC register base @@ -1009,7 +1170,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); /** @addtogroup HAL_SDMMC_LL_Group2 * @{ */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); /** * @} @@ -1022,17 +1183,17 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); /* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); /* SDMMC Cards mode management functions */ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); @@ -1073,6 +1234,10 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse); +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp); /** * @} */ @@ -1084,6 +1249,8 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp); +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData); uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** @@ -1106,7 +1273,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** * @} */ - +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h index c2b31d604f..06568c7b10 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h @@ -63,24 +63,30 @@ typedef struct uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class. This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ + This feature can be modified afterwards using unitary + function @ref LL_SWPMI_SetVoltageClass. */ uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. - This parameter must be a number between Min_Data=0 and Max_Data=255U. + This parameter must be a number between Min_Data=0 + and Max_Data=255U. - The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER + The value can be calculated thanks to helper + macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */ + This feature can be modified afterwards using unitary + function @ref LL_SWPMI_SetBitRatePrescaler. */ uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode. This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */ + This feature can be modified afterwards using + unitary function @ref LL_SWPMI_SetTransmissionMode. */ uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode. This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */ + This feature can be modified afterwards using + unitary function @ref LL_SWPMI_SetReceptionMode. */ } LL_SWPMI_InitTypeDef; /** @@ -266,7 +272,7 @@ __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t R * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI */ -__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE)); } @@ -294,7 +300,7 @@ __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_ * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI */ -__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE)); } @@ -351,7 +357,7 @@ __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL); } @@ -381,7 +387,7 @@ __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL); } @@ -428,7 +434,7 @@ __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_ * @param SWPMIx SWPMI Instance * @retval A number between Min_Data=0 and Max_Data=255U */ -__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR)); } @@ -455,7 +461,7 @@ __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t Vo * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B */ -__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS)); } @@ -474,7 +480,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL); } @@ -485,7 +491,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL); } @@ -496,7 +502,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL); } @@ -507,7 +513,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL); } @@ -518,7 +524,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL); } @@ -530,7 +536,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL); } @@ -542,7 +548,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL); } @@ -554,7 +560,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL); } @@ -566,7 +572,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL); } @@ -577,7 +583,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL); } @@ -588,7 +594,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL); } @@ -599,7 +605,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL); } @@ -926,7 +932,7 @@ __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL); } @@ -937,7 +943,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL); } @@ -948,7 +954,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL); } @@ -959,7 +965,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL); } @@ -970,7 +976,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL); } @@ -981,7 +987,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL); } @@ -992,7 +998,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL); } @@ -1003,7 +1009,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL); } @@ -1014,7 +1020,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL); } @@ -1025,7 +1031,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL); } @@ -1066,7 +1072,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL); } @@ -1099,7 +1105,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL); } @@ -1114,19 +1120,19 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(const SWPMI_TypeDef *SWPMIx, uint32_t Direction) { uint32_t data_reg_addr; if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t)&(SWPMIx->TDR); + data_reg_addr = (uint32_t) &(SWPMIx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t)&(SWPMIx->RDR); + data_reg_addr = (uint32_t) &(SWPMIx->RDR); } return data_reg_addr; @@ -1146,7 +1152,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t * @param SWPMIx SWPMI Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1F */ -__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL)); } @@ -1210,8 +1216,8 @@ __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx) * @{ */ -ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx); -ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct); +ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx); +ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct); void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h index eef033dd61..a8625e967b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale * @arg @ref LL_WWDG_PRESCALER_64 * @arg @ref LL_WWDG_PRESCALER_128 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html index 02124608f5..4e0c79d1d9 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html @@ -40,10 +40,159 @@

Purpose

Update History

- +

Main Changes

    +
  • HAL PWR +
      +
    • Add a note to the HAL_PWREx_ConfigSupply() API documentation to clarify that this API comes obsolete after deploying "how to exit from Run* recommended sequence.
      • +
    • +
  • HAL QSPI +
      +
    • Fix possible race condition with QSPI data transfer when using DMA.
      • +
    • +
  • HAL/LL RTC +
      +
    • Alignment with new RTC TAMPER register and bitfields naming in the CMSIS.
      • +
    • Add new restrictions to manage specific Tamper features.
      • +
    • +
  • HAL HSEM +
      +
    • Update __HAL_HSEM_ENABLE_IT(), __HAL_HSEM_DISABLE_IT(), __HAL_HSEM_GET_IT(), __HAL_HSEM_GET_FLAG() and __HAL_HSEM_CLEAR_FLAG() macros to be aligned with registers’ names in the CMSIS.
      • +
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const qualifiers.
    • +
  • General updates to fix known defects and enhancements implementation.
    • +
  • HAL Generic +
      +
    • Add new REV_ID_x to cover all supported STM32H7 device revisions.
      • +
    • +
  • HAL ADC +
      +
    • Fix Misra-C 2012 Rule-12.1 related issues.
      • +
    • +
  • HAL DAC +
      +
    • Fix HAL DAC calibration procedure (HAL_DACEx_SelfCalibrate() API) to manage case of calibration factor equal to range maximum value (previously, in this case calibration factor was reset, leading to voltage accuracy not optimal).
      • +
    • +
  • LL DMA +
      +
    • Remove deprecated ‘register’ storage class specifier from LL_DMA_IsEnabledDoubleBufferMode() API to fix GCC compiler issue.
      • +
    • +
  • HAL CRYP +
      +
    • Update CRYP HAL driver to fix the issue of writing out the outputbuffer when the size is not multiple of 4.
      • +
    • +
  • HAL HASH +
      +
    • Update the HAL HASH driver to support data in case of buffer smaller than 4 bytes in mode IT.
      • +
    • +
  • HAL RNG +
      +
    • Update the HAL RNG driver to support error coming from RecoverSeedError.
      • +
    • +
  • HAL HRTIM +
      +
    • Correct the typo in the “HRTIMInterruptRequests†structure member and add the legacy define in the stm32_hal_legacy.h file.
      • +
    • +
  • HAL USART +
      +
    • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM.
      • +
    • Improve the visibility of the SPI API support in HAL USART description.
      • +
    • +
  • HAL SWPMI +
      +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • +
  • HAL/LL UART +
      +
    • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring just after TC event.
      • +
    • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.
      • +
    • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode.
      • +
    • Ensure UART Rx buffer is not written beyond boundaries in case of RX FIFO reception in Interrupt mode.
      • +
    • Add LL LPUART API allowing TX FIFO flush request.
      • +
    • +
  • HAL/LL SWPMI driver +
      +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • +
  • HAL SDMMC driver +
      +
    • Add new HAL SDIO driver.
      • +
    • +
  • HAL I2C +
      +
    • Add a temporary variable to get the value to check before comparison.
      • +
    • Add abort memory management to HAL_I2C_Master_Abort_IT() API.
      • +
    • Move the prefetch process in HAL_I2C_Slave_Transmit() API.
      • +
    • Move variable tmp declaration at the beginning in I2C_TransferCofig function.
      • +
    • Update function HAL_I2C_IsDeviceReady() API to take into account the number of trials.
      • +
    • +
  • HAL I2S +
      +
    • Add HAL IOSwap APIs: +
        +
      • HAL_I2S_EnableIOSwap()to enable the SDO/SDI alternate functions inversion feature.
        • +
      • HAL_I2S_DisableIOSwap() to disable the SDO/SDI alternate functions inversion feature.
        • +
      • HAL_I2S_IsEnabledIOSwap() to retrieve the SDO/SDI alternate functions inversion feature.
        • +
      • +
    • +
  • HAL ETH +
      +
    • Fix undefined Macro usage in ETH DMA Status Flags.
      • +
    • Fix the calculation of the tail pointer so that it points to the last updated descriptor.
      • +
    • Add new API HAL_ETH_GetTxBuffersNumber() to get Buffers in use number.
      • +
    • +
  • HAL SPI +
      +
    • Add protection against wrong transfer size during transmission.
      • +
    • Check coherence between data size and DMA TX configuration.
      • +
    • +
  • HAL OSPI +
      +
    • Fix wrong parameters passed to HAL_MDMA_Start_IT() API.
      • +
    • +
  • HAL QSPI +
      +
    • Clear AR register after CCR to avoid new transfer when address is not needed.
      • +
    • +
  • HAL USB +
      +
    • Fix MisraC 2012 Rule-10.7 related issues.
      • +
    • hal_hcd.c: ensure to reactivate the usb channel in case of transfer error.
      • +
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+
  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
  • HAL Generic
      @@ -54,7 +203,6 @@

      Main Changes

    • HAL PWR
      • Add macro UNUSED() to avoid the generation of a warning related to the unused argument ‘Regulator’.
        • -
      • Update HAL_PWREx_PVD_AVD_IRQHandle() API to call right callbacks before performing the clear.
    • HAL GPIO
        @@ -232,11 +380,11 @@

        Main Changes

      • Fix a note about Ticks parameter.
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Backward compatibility

    +

    Backward compatibility

    • None
    @@ -245,18 +393,18 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • HAL ETH
      • Update on Rx descriptor Tail pointer management to avoid race condition.
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Backward compatibility

    +

    Backward compatibility

    • None
    @@ -265,7 +413,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • General updates to fix known defects and implementation enhancements.
    • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
      • @@ -351,6 +499,20 @@

      Main Changes

      • Change argument order in SPI_WaitOnFlagUntilTimeout to be aligned with declaration.
      • Fix dereferencing pointer warning on GNU compiler inside LL_SPI_ReceiveData16() function.
        • +
      • Add SuspendCallback(), useful to avoid data overrun in case transfer is interrupted. +
          +
        • NOTE: SuspendCallback() is called only when MasterReceiverAutoSusp is enabled and EOT interrupt is activated.
          • +
        • +
      • Add support of Simplex Transmitter and Simplex Receiver modes.
        • +
      • Remove the call to HAL_SPI_TransmitReceive() from HAL_SPI_Receive(). +
          +
        • NOTES: +
            +
          • When the HAL_SPI_Receive() is called in Master mode, only the RX Line is active.
            • +
          • In case of a Master using the Full-Duplex mode, HAL_SPI_TransmitReceive() shall be called instead of HAL_SPI_Receive() at user application level.
            • +
          • +
        • +
      • Clear EOT and SUSP flags in the HAL_SPI_Abort_IT().
    • HAL ETH
        @@ -378,11 +540,11 @@

        Main Changes

      • Remove redundant word from @note of HAL_InitTick() header description, which may cause confusion when reading the note.
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Backward compatibility

    +

    Backward compatibility

    • None
    @@ -391,7 +553,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • General updates to fix known defects and implementation enhancements.
    • The following changes done on the HAL drivers require an update of the application code based on older HAL versions @@ -474,11 +636,11 @@

      Main Changes

    • Fix USB BCD data contact timeout
-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Compatibility break with HAL ETH driver V1.10.0 available within STM32CubeFW_H7 V1.9.0
@@ -487,7 +649,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements.
  • All source files: update disclaimer to add reference to the new license agreement.
    • @@ -646,14 +808,14 @@

    Main Changes

  • Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).
-

Known Limitations

+

Known Limitations

  • HAL/ETH
    • A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP
-

Backward compatibility

+

Backward compatibility

  • None
@@ -662,7 +824,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements

  • Fix minor issues related to English typo in comments

    • @@ -948,14 +1110,14 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL/ETH
    • A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP
-

Backward compatibility

+

Backward compatibility

  • None
@@ -964,7 +1126,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First official release of the STM32CubeH7 Firmware Package supporting STM32H72x/3x new devices
  • General updates to fix known defects and implementation enhancements
    • @@ -1558,11 +1720,11 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 families)
@@ -1571,7 +1733,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements
  • HAL: generic @@ -1805,7 +1967,7 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL I2S:
      @@ -1815,7 +1977,7 @@

      Known Limitations

-

Backward compatibility

+

Backward compatibility

  • None
@@ -1824,7 +1986,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Official release with support of STM32H7A3/B3xx/B0xx new devices
    • @@ -2379,7 +2541,7 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL I2S:
      @@ -2393,7 +2555,7 @@

      Known Limitations

    • New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.
-

Backward compatibility

+

Backward compatibility

  • HAL I2S:
      @@ -2417,7 +2579,7 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and implementation enhancements
      • HAL: generic @@ -2692,11 +2854,11 @@

        Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • HAL TIM:
      @@ -2714,7 +2876,7 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and implementation enhancements
      • Add support for VOS0 power regulator voltage scaling with 480MHz over clock
        • @@ -3184,7 +3346,7 @@

        Main Changes

      • Update LL_Init1msTick and LL_SetSystemCoreClock description for DUAL CORE lines
    -

    Known Limitations

    +

    Known Limitations

    • HAL SD:
        @@ -3198,7 +3360,7 @@

        Known Limitations

      • Full duplex Transmit/receive feature not available
    -

    Backward compatibility

    +

    Backward compatibility

    • HAL ADC:
        @@ -3250,7 +3412,7 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • General updates to fix known defects and implementation enhancements
        • Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG
          • @@ -3519,7 +3681,7 @@

          Main Changes

        • Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled
      -

      Known Limitations

      +

      Known Limitations

      • HAL I2S:
          @@ -3527,7 +3689,7 @@

          Known Limitations

        • A new version of this driver will be available in next release with full features tested
      -

      Backward compatibility

      +

      Backward compatibility

      • HAL ADC:
          @@ -3567,7 +3729,7 @@

          Backward compatibility

          -

          Main Changes

          +

          Main Changes

          • Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers
          • HAL Cortex: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15
            • @@ -3579,7 +3741,7 @@

            Main Changes

            -

            Main Changes

            +

            Main Changes

            • General updates to fix known defects and enhancements implementation
            • HAL SPI: Driver reworked to fix critical issues
              • @@ -3590,7 +3752,7 @@

              Main Changes

              -

              Main Changes

              +

              Main Changes

              • General updates to fix known defects and enhancements implementation
              • HAL FLASH: Add Mass Erase for both banks
                • @@ -3605,7 +3767,7 @@

                Main Changes

                -

                Main Changes

                +

                Main Changes

                • First official release for STM32H743xx/753xx devices
                diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c index 468fd83a0e..6ddbeee45b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -51,7 +51,7 @@ */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ #define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ -#define __STM32H7xx_HAL_VERSION_SUB2 (0x03UL) /*!< [15:8] sub2 version */ +#define __STM32H7xx_HAL_VERSION_SUB2 (0x05UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c index 74cf03aec0..855ea82de4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c @@ -2341,7 +2341,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3022,11 +3022,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Set sampling time of the selected ADC channel */ - /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), - sConfig->SamplingTime); + /* Set ADC channel preselection of corresponding negative channel */ + LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel)); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ @@ -3494,7 +3491,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3508,7 +3505,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c index 749473f773..b2dc363b89 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c @@ -197,7 +197,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1016,7 +1016,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; ADC_HandleTypeDef tmphadcSlave; @@ -1277,7 +1277,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc) { const ADC_Common_TypeDef *tmpADC_Common; @@ -1323,7 +1323,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; @@ -2296,8 +2296,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); + /* Set ADC channel preselection of corresponding negative channel */ + LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfigInjected->InjectedChannel)); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c index 165c09e37c..621a0a05d0 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c @@ -1148,7 +1148,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -1201,7 +1201,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval HAL state */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ if(hcomp == NULL) @@ -1221,7 +1221,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval COMP error code */ -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp) { /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c index 7eea29cb6c..da6b810bb7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c @@ -164,12 +164,12 @@ static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); + /** * @} */ /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions * @{ */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c index e272cfc2db..5c158d532b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c @@ -327,7 +327,7 @@ void HAL_MPU_DisableRegion(uint32_t RegionNumber) * the initialization and configuration information. * @retval None */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c index b4ba3de352..c814b28715 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c index 61d732e4be..942c1e0138 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c @@ -74,7 +74,7 @@ the CRYP peripheral is configured and processes the buffer in input. At second call, no need to Initialize the CRYP, user have to get current configuration via HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. + new parameters, finally user can start encryption/decryption. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @@ -1741,7 +1741,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) * the configuration information for the CRYP IP * @retval CRYP error code */ -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp) { return hcryp->ErrorCode; } @@ -1752,7 +1752,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module. * @retval HAL state */ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp) { return hcryp->State; } @@ -4434,7 +4434,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; + const uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; /***************************** Header phase for GCM/GMAC or CCM *********************************/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c index ddce86e43b..5dee88e2f8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c @@ -108,7 +108,7 @@ * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout) { uint32_t tickstart; uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ @@ -274,7 +274,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout) { uint32_t tagaddr = (uint32_t)AuthTag; uint32_t ctr0 [4] = {0}; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c index a5e6225186..0207677006 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c @@ -1065,6 +1065,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c index 15d998a430..e2b8e6aea5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c @@ -666,8 +666,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16UL; - delta = 8UL; + trimmingvalue = 0x10UL; + delta = 0x08UL; while (delta != 0UL) { /* Set candidate trimming */ @@ -713,8 +713,12 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* Trimming is actually one value more */ - trimmingvalue++; + /* Check trimming value below maximum */ + if (trimmingvalue < 0x1FU) + { + /* Trimming is actually one value more */ + trimmingvalue++; + } /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } @@ -787,8 +791,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval Trimming value : range: 0->31 - * + * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c index e1549e2473..980270258f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c @@ -914,7 +914,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn * the configuration information for DCMI. * @retval HAL state */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->State; } @@ -925,7 +925,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) * the configuration information for DCMI. * @retval DCMI Error Code */ -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c index dada223e62..8714741055 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -174,7 +174,7 @@ typedef struct */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); @@ -1733,7 +1733,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * the configuration information for the specified DMA Stream. * @retval HAL state */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) { return hdma->State; } @@ -1744,7 +1744,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Stream. * @retval DMA Error Code */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } @@ -1893,7 +1893,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Stream. * @retval HAL status */ -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c index 520841c9f3..e85122ce71 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c @@ -323,7 +323,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /* Before aborting any DMA2D transfer or CLUT loading, check first whether or not DMA2D clock is enabled */ - if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) + if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U) { /* Abort DMA2D transfer if any */ if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) @@ -1013,7 +1013,8 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); @@ -1067,7 +1068,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ @@ -1770,7 +1771,7 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - DMA2D_LayerCfgTypeDef *pLayerCfg; + const DMA2D_LayerCfgTypeDef *pLayerCfg; uint32_t regMask; uint32_t regValue; @@ -2062,7 +2063,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t * the configuration information for the DMA2D. * @retval HAL state */ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->State; } @@ -2073,7 +2074,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) * the configuration information for DMA2D. * @retval DMA2D Error Code */ -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c index 9f122a49bd..3b9b85a202 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c @@ -948,7 +948,7 @@ __weak void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts) * @param hdts DTS handle * @retval HAL state */ -HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts) +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts) { /* Check the DTS handle allocation */ if (hdts == NULL) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c index 2536a73b12..b9e26fa7b7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c @@ -1081,7 +1081,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) heth->RxDescList.RxDataLength = 0; } - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + /* Get the Frame Length of the received packet */ bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; /* Check if last descriptor */ @@ -1209,7 +1209,7 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { /* Set the tail pointer index */ - tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT; /* DMB instruction to avoid race condition */ __DMB(); @@ -1429,7 +1429,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) #ifdef HAL_ETH_USE_PTP /* Disable Ptp transmission */ - CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); + CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE); if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD) && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS)) @@ -1506,6 +1506,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT return HAL_ERROR; } + /* Mask the Timestamp Trigger interrupt */ + CLEAR_BIT(heth->Instance->MACIER, ETH_MACIER_TSIE); + tmpTSCR = ptpconfig->Timestamp | ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) | ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) | @@ -1539,8 +1542,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT } } - /* Ptp Init */ - SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) + { + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT); + } /* Set PTP Configuration done */ heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED; @@ -1552,6 +1558,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT HAL_ETH_PTP_SetTime(heth, &time); + /* Ptp Init */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Return function status */ return HAL_OK; } @@ -2491,7 +2500,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_ ((uint32_t)pFilterConfig->HashMulticast << 2) | ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | ((uint32_t)pFilterConfig->PassAllMulticast << 4) | - ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) | ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | @@ -2524,7 +2533,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_ pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; - pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE; pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; @@ -2772,6 +2781,16 @@ uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) return heth->MACWakeUpEvent; } +/** + * @brief Returns the ETH Tx Buffers in use number + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH Tx Buffers in use number + */ +uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth) +{ + return heth->TxDescList.BuffersInUse; +} /** * @} */ @@ -3056,7 +3075,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param pTxConfig: Tx packet configuration - * @param ItMode: Enable or disable Tx EOT interrept + * @param ItMode: Enable or disable Tx EOT interrupt * @retval Status */ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c index fe54a0374f..07825da414 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c @@ -509,7 +509,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param hexti Exti handle. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -682,7 +682,7 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @param hexti Exti handle. * @retval none. */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -734,9 +734,9 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) * This parameter is kept for compatibility with other series. * @retval 1 if interrupt is pending else 0. */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -785,7 +785,7 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * This parameter is kept for compatibility with other series. * @retval None. */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; @@ -827,7 +827,7 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @param hexti Exti handle. * @retval None. */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t maskline; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c index bed7b5e753..7a1e2d76fd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c @@ -1020,26 +1020,26 @@ void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) */ void HAL_FLASHEx_BusFault_IRQHandler(void) { - /* Check if the ECC double error occured*/ + /* Check if the ECC double error occurred*/ if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0) { /* FLASH ECC detection user callback */ HAL_FLASHEx_EccDetectionCallback(); /* Clear Bank 1 ECC double detection error flag - note : this step will clear all the informations related to the flash ECC detection + note : this step will clear all the information related to the flash ECC detection */ __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1); } #if defined (DUAL_BANK) - /* Check if the ECC double error occured*/ + /* Check if the ECC double error occurred*/ if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0) { /* FLASH ECC detection user callback */ HAL_FLASHEx_EccDetectionCallback(); /* Clear Bank 2 ECC double detection error flag - note : this step will clear all the informations related to the flash ECC detection + note : this step will clear all the information related to the flash ECC detection */ __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c index f4cebd05d9..306073b601 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c @@ -204,7 +204,6 @@ not defined, the callback registration feature is not available and weak callbacks are used. - @endverbatim * */ @@ -229,7 +228,6 @@ /** @defgroup FMAC_Private_Constants FMAC Private Constants * @{ */ - #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) #define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U @@ -322,7 +320,6 @@ /* Private variables ---------------------------------------------------------*/ /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); @@ -348,7 +345,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /* Functions Definition ------------------------------------------------------*/ - /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ */ @@ -1203,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1222,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1239,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ @@ -2410,7 +2417,6 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) #else HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ - } /** @@ -2516,11 +2522,11 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ } + /** * @} */ - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c index 7e771a7925..f6961785f0 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c @@ -518,7 +518,7 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @param Address Start address of LUT in flash. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address) @@ -570,7 +570,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber) { @@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, * @param lutLine LUT line parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) { HAL_StatusTypeDef status = HAL_OK; @@ -841,7 +841,7 @@ __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) * @param hgfxmmu GFXMMU handle. * @retval GFXMMU state. */ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu) { /* Return GFXMMU handle state */ return hgfxmmu->State; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c index 3580f78a5b..7133e81e73 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c @@ -162,7 +162,7 @@ * the configuration information for the specified GPIO peripheral. * @retval None */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { uint32_t position = 0x00U; uint32_t iocurrent; @@ -386,7 +386,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c index 8bc984da55..27513cfa76 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c @@ -272,10 +272,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -764,7 +764,8 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -790,7 +791,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -805,7 +806,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -822,7 +823,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -848,7 +850,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -863,7 +865,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -911,7 +913,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -935,7 +937,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -949,7 +951,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -965,7 +967,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -990,7 +992,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1004,7 +1006,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1077,7 +1079,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1107,7 +1109,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1164,7 +1166,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1183,7 +1186,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1225,7 +1229,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1243,7 +1247,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1254,7 +1258,6 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ - /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode * @brief HMAC processing functions using DMA modes. * @@ -1297,7 +1300,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1322,7 +1325,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1369,7 +1372,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @param hhash HASH handle. * @retval HAL HASH state */ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash) { return hhash->State; } @@ -1382,7 +1385,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) * @param hhash HASH handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash) { return hhash->Status; } @@ -1400,7 +1403,7 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. * @retval None */ -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1441,7 +1444,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) * beforehand). * @retval None */ -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1620,7 +1623,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) * @param hhash pointer to a HASH_HandleTypeDef structure. * @retval HASH Error Code */ -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash) { /* Return HASH Error Code */ return hhash->ErrorCode; @@ -1821,7 +1824,7 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -1917,8 +1920,8 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB if ((Size % 4U) == 3U) { tmp = *(uint8_t *)inputaddr; - tmp |= (uint32_t)*(uint8_t *)(inputaddr + 1U) << 8U; - tmp |= (uint32_t)*(uint8_t *)(inputaddr + 2U) << 16U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 1U) << 8U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 2U) << 16U; HASH->DIN = tmp; } @@ -1927,7 +1930,6 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB { HASH->DIN = *(uint32_t *)inputaddr; } - /*hhash->HashInCount += 4U;*/ } @@ -1940,7 +1942,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -2005,7 +2007,6 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) } - /** * @brief Handle HASH processing Timeout. * @param hhash HASH handle. @@ -2491,10 +2492,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2526,7 +2528,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2542,7 +2544,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2550,7 +2552,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2628,9 +2630,10 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2662,7 +2665,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2673,7 +2676,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2731,7 +2734,8 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2841,7 +2845,6 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff } - /** * @brief Initialize the HASH peripheral, next process pInBuffer then * read the computed digest in interruption mode. @@ -2853,7 +2856,8 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2902,6 +2906,19 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } + else if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) && (SizeVar < 4U)) + { + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + { + /* It remains data to enter and the Peripheral is ready to trigger DINIE,carry on as usual. + Update HashInCount and pHashInBuffPtr accordingly. */ + hhash->HashInCount = SizeVar; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + } + } else { initialization_skipped = 1; /* info user later on in case of multi-buffer */ @@ -3011,7 +3028,8 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3188,7 +3206,8 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3252,7 +3271,6 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint } - /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then * read the computed digest in interruption mode. @@ -3266,7 +3284,8 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3361,7 +3380,6 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u } - /** * @brief Initialize the HASH peripheral in HMAC mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -3377,7 +3395,8 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c index 86b7030c59..00c4340c98 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c @@ -86,8 +86,6 @@ #include "stm32h7xx_hal.h" - - /** @addtogroup STM32H7xx_HAL_Driver * @{ */ @@ -148,7 +146,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -174,7 +172,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -189,7 +187,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -206,7 +204,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -232,7 +230,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -247,7 +245,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -290,7 +288,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -314,7 +312,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -328,7 +326,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -344,7 +343,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -368,7 +367,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -382,7 +381,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -422,8 +422,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin */ - - /** * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer * to feed the input buffer to the Peripheral. @@ -434,7 +432,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -464,7 +462,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -507,7 +505,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then * read the computed digest. @@ -521,7 +518,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -540,7 +537,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -570,7 +567,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then * read the computed digest in interrupt mode. @@ -583,7 +579,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -601,15 +597,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } - - /** * @} */ @@ -639,7 +633,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -659,7 +652,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -683,7 +676,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -759,7 +752,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -780,7 +773,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -806,7 +799,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -829,7 +822,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -850,7 +843,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -876,7 +869,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -898,7 +891,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -919,7 +913,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -945,7 +939,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -967,7 +962,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -988,7 +984,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -1014,7 +1010,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c index 17f99edb5b..e1fbd00433 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c @@ -1693,6 +1693,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c index 2e11610e89..65efda0016 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c @@ -83,7 +83,6 @@ any restriction. HRTIM waveform modes are managed through the set of functions named HAL_HRTIM_Waveform -============================================================================== ##### How to use this driver ##### ============================================================================== [..] @@ -423,62 +422,62 @@ static uint32_t TimerIdxToTimerId[] = /** @defgroup HRTIM_Private_Functions HRTIM Private Functions * @{ */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg); +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event); -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg); -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef * pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event); -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma); +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma); -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma); @@ -497,7 +496,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); */ /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions @verbatim =============================================================================== ##### Initialization and Time Base Configuration functions ##### @@ -518,20 +517,20 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim) { uint8_t timer_idx; uint32_t hrtim_mcr; /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance)); - assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests)); + assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptRequests)); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) if (hhrtim->State == HAL_HRTIM_STATE_RESET) @@ -660,10 +659,10 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim) { /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } @@ -696,7 +695,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -711,7 +710,7 @@ __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -743,16 +742,16 @@ __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) */ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio)); assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Set the HRTIM state */ @@ -780,7 +779,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions - * @brief Simple time base mode functions. + * @brief Simple time base mode functions. @verbatim =============================================================================== ##### Simple time base mode functions ##### @@ -812,10 +811,10 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -847,10 +846,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -883,10 +882,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -929,10 +928,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -978,24 +977,24 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @param Length The length of data items (data size) to be transferred * from source to destination */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1013,12 +1012,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA transfer completed callback */ @@ -1036,14 +1035,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer repetition DMA request */ if (TimerIdx == HRTIM_TIMERINDEX_MASTER) @@ -1080,10 +1079,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -1098,7 +1097,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP); @@ -1119,12 +1118,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hdma) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP); - } + } } /* Disable the timer counter */ @@ -1135,11 +1134,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -1148,7 +1147,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions - * @brief Simple output compare functions + * @brief Simple output compare functions @verbatim =============================================================================== ##### Simple output compare functions ##### @@ -1202,10 +1201,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, * Inactive: SETxy =0, RSTxy = CMPy * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg) { uint32_t CompareUnit = (uint32_t)RESET; HRTIM_OutputCfgTypeDef OutputCfg; @@ -1217,9 +1216,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -1231,27 +1230,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { CompareUnit = HRTIM_COMPAREUNIT_1; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { CompareUnit = HRTIM_COMPAREUNIT_2; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -1262,9 +1261,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ @@ -1277,7 +1276,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, switch (pSimpleOCChannelCfg->Mode) { - case HRTIM_BASICOCMODE_TOGGLE: + case HRTIM_BASICOCMODE_TOGGLE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1291,7 +1290,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_ACTIVE: + case HRTIM_BASICOCMODE_ACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1305,7 +1304,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_INACTIVE: + case HRTIM_BASICOCMODE_INACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1319,7 +1318,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -1333,9 +1332,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } HRTIM_OutputConfig(hhrtim, @@ -1376,11 +1375,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1426,11 +1425,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1481,13 +1480,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset interrupt is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1540,13 +1539,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1607,26 +1606,26 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset DMA request is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; uint32_t dma_request; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1639,7 +1638,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Process Locked */ __HAL_LOCK(hhrtim); - /* Enable the timer output */ + /* Enable the timer output */ hhrtim->Instance->sCommonRegs.OENR |= OCChannel; /* Get the DMA request to enable */ @@ -1650,12 +1649,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -1666,14 +1665,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request); @@ -1714,9 +1713,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t dma_request; @@ -1765,7 +1764,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions - * @brief Simple PWM output functions + * @brief Simple PWM output functions @verbatim =============================================================================== ##### Simple PWM output functions ##### @@ -1822,10 +1821,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, * enabled (otherwise the behavior is not guaranteed). * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; uint32_t hrtim_timcr; @@ -1836,9 +1835,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -1849,28 +1848,28 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -1884,14 +1883,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1); - OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1); + OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; @@ -1940,11 +1939,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -1990,11 +1989,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2041,11 +2040,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2059,27 +2058,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2090,9 +2089,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2131,11 +2130,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2149,27 +2148,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2180,9 +2179,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2225,25 +2224,25 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -2280,39 +2279,39 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2323,9 +2322,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2364,9 +2363,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); @@ -2394,27 +2393,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2425,9 +2424,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2446,7 +2445,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions - * @brief Simple input capture functions + * @brief Simple input capture functions @verbatim =============================================================================== ##### Simple input capture functions ##### @@ -2488,10 +2487,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, * edges on event channel. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg) { HRTIM_EventCfgTypeDef EventCfg; @@ -2505,9 +2504,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event, pSimpleCaptureChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -2559,11 +2558,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr * units. It can be used directly and is active as soon as the timing * unit counter is enabled. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2575,19 +2574,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2598,9 +2597,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2630,14 +2629,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2649,19 +2648,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2672,9 +2671,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -2712,11 +2711,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2728,7 +2727,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -2737,7 +2736,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -2746,7 +2745,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2757,9 +2756,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2790,15 +2789,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2810,7 +2809,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -2819,7 +2818,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -2828,7 +2827,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2839,9 +2838,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -2883,16 +2882,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2906,12 +2905,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -2922,18 +2921,18 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -2942,7 +2941,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -2952,7 +2951,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2961,11 +2960,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2996,9 +2995,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; @@ -3017,17 +3016,17 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3037,7 +3036,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3047,7 +3046,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3058,9 +3057,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -3086,7 +3085,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions - * @brief Simple one pulse functions + * @brief Simple one pulse functions @verbatim =============================================================================== ##### Simple one pulse functions ##### @@ -3143,10 +3142,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, * second call will override the reset event related configuration data * provided in the first call. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; HRTIM_EventCfgTypeDef EventCfg; @@ -3163,9 +3162,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event, pSimpleOnePulseChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3176,29 +3175,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh /* Configure timer compare unit */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -3212,13 +3211,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ - OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); + OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; @@ -3235,7 +3234,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F); EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1); - EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS); + EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS); EventCfg.Source = HRTIM_EVENTSRC_1; HRTIM_EventConfig(hhrtim, @@ -3279,7 +3278,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel) { @@ -3329,9 +3328,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3380,9 +3379,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3398,27 +3397,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3429,9 +3428,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -3470,9 +3469,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3488,27 +3487,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3519,9 +3518,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -3540,7 +3539,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions - * @brief HRTIM configuration functions + * @brief HRTIM configuration functions @verbatim =============================================================================== ##### HRTIM configuration functions ##### @@ -3567,8 +3566,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the burst mode * controller */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) +HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg) { uint32_t hrtim_bmcr; @@ -3579,9 +3578,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable)); assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3647,9 +3646,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg) + const HRTIM_EventCfgTypeDef *pEventCfg) { /* Check parameters */ assert_param(IS_HRTIM_EVENT(Event)); @@ -3659,9 +3658,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode)); assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3692,15 +3691,15 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3734,9 +3733,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * enabling faults inputs * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg) + const HRTIM_FaultCfgTypeDef *pFaultCfg) { uint32_t hrtim_fltinr1; uint32_t hrtim_fltinr2; @@ -3748,9 +3747,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter)); assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3764,7 +3763,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, switch (Fault) { - case HRTIM_FAULT_1: + case HRTIM_FAULT_1: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P); @@ -3774,7 +3773,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_2: + case HRTIM_FAULT_2: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P); @@ -3784,7 +3783,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_3: + case HRTIM_FAULT_3: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P); @@ -3792,9 +3791,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F); hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK); break; - } + } - case HRTIM_FAULT_4: + case HRTIM_FAULT_4: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P); @@ -3804,7 +3803,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_5: + case HRTIM_FAULT_5: { hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P); @@ -3814,7 +3813,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3825,9 +3824,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers except LOCK bit */ @@ -3835,8 +3834,8 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK))); /* Update the HRTIM registers LOCK bit */ - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1, (hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2, (hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -3859,15 +3858,15 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer and before * enabling faults inputs */ -HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3902,9 +3901,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled * @retval None */ -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, - uint32_t Faults, - uint32_t Enable) +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, + uint32_t Faults, + uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Faults)); @@ -3946,9 +3945,9 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg) { uint32_t hrtim_cr1; @@ -3956,9 +3955,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger)); assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3971,7 +3970,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, switch (ADCTrigger) { - case HRTIM_ADCTRIGGER_1: + case HRTIM_ADCTRIGGER_1: { hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC); hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC); @@ -3981,7 +3980,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_2: + case HRTIM_ADCTRIGGER_2: { hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC); @@ -3991,7 +3990,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_3: + case HRTIM_ADCTRIGGER_3: { hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC); @@ -4001,7 +4000,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_4: + case HRTIM_ADCTRIGGER_4: { hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC); @@ -4011,7 +4010,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4022,9 +4021,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers */ @@ -4044,7 +4043,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions - * @brief HRTIM timer configuration and control functions + * @brief HRTIM timer configuration and control functions @verbatim =============================================================================== ##### HRTIM timer configuration and control functions ##### @@ -4098,9 +4097,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -4114,9 +4113,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode)); assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4199,10 +4198,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); @@ -4211,9 +4210,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4224,75 +4223,85 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt /* Configure timer event filtering capabilities */ switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1); CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2); break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -4302,9 +4311,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4329,9 +4338,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg) { uint32_t hrtim_dtr; @@ -4345,9 +4354,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock)); assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4368,9 +4377,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, /* Update the HRTIM registers */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, ( - HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | - HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | - HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); + HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | + HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | + HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4394,9 +4403,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before configuring the timer output(s) */ -HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg) { uint32_t hrtim_chpr; @@ -4406,9 +4415,9 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle)); assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4471,16 +4480,16 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t RegistersToUpdate) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4491,44 +4500,44 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, /* Set the burst DMA timer update register */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate; break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -4538,9 +4547,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4578,17 +4587,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg) + const HRTIM_CompareCfgTypeDef *pCompareCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4602,43 +4611,43 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, switch (CompareUnit) { case HRTIM_COMPAREUNIT_1: - { + { hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_2: - { + { hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_3: - { + { hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_4: - { + { hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; break; - } + } default: - { + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); break; - } + } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } } @@ -4646,14 +4655,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, { switch (CompareUnit) { - case HRTIM_COMPAREUNIT_1: + case HRTIM_COMPAREUNIT_1: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_2: + case HRTIM_COMPAREUNIT_2: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -4688,17 +4697,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U); } - break; + break; } - case HRTIM_COMPAREUNIT_3: + case HRTIM_COMPAREUNIT_3: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_4: + case HRTIM_COMPAREUNIT_4: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -4733,24 +4742,24 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U); } - break; + break; } - default: - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + default: + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - break; - } - } + break; + } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return HAL_ERROR; - } + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) + { + return HAL_ERROR; + } } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4779,18 +4788,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg) + const HRTIM_CaptureCfgTypeDef *pCaptureCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4801,19 +4810,19 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure the capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4824,9 +4833,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } @@ -4865,10 +4874,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before configuring the timer and after * configuring the deadtime insertion feature (if required). */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -4879,9 +4888,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable)); assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4933,7 +4942,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, * @note The 'software set/reset trigger' bit in the output set/reset registers * is automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel) @@ -4942,9 +4951,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4955,16 +4964,16 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, /* Force timer output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { /* Force output to its active state */ - SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST); + SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R, HRTIM_SET1R_SST); } else { @@ -4974,11 +4983,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { @@ -4993,7 +5002,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -5004,9 +5013,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5035,10 +5044,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStart)); /* Process Locked */ @@ -5075,10 +5084,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStop)); /* Process Locked */ @@ -5111,8 +5120,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERID_TIMER_E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -5148,8 +5157,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -5188,8 +5197,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, * function. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -5202,7 +5211,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Enable HRTIM interrupts (if required) */ - __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Enable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -5232,7 +5241,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - return HAL_OK;} + return HAL_OK; +} /** * @brief Stop the counter of the designated timer(s) operating in waveform mode @@ -5250,8 +5260,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related interrupts are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* ++ WA */ __IO uint32_t delai = (uint32_t)(0x17FU); @@ -5268,7 +5278,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Disable HRTIM interrupts (if required) */ - __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Disable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -5322,18 +5332,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, * size of each DMA transfer are specified at timer configuration time * (see HAL_HRTIM_WaveformTimerConfig) */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } hhrtim->State = HAL_HRTIM_STATE_BUSY; @@ -5344,29 +5354,29 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) && (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U)) { - /* Set the DMA error callback */ - hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; + /* Set the DMA error callback */ + hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; - /* Set the DMA transfer completed callback */ - hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; + /* Set the DMA transfer completed callback */ + hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } - /* Enable the timer DMA request */ - __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + /* Enable the timer DMA request */ + __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ; @@ -5374,7 +5384,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, timer_idx++) { if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) && - (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) + (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); @@ -5389,7 +5399,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, return HAL_ERROR; } - /* Set the DMA error callback */ + /* Set the DMA error callback */ hdma->XferErrorCallback = HRTIM_DMAError ; /* Set the DMA transfer completed callback */ @@ -5397,17 +5407,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - hhrtim->TimerParam[timer_idx].DMASrcAddress, - hhrtim->TimerParam[timer_idx].DMADstAddress, - hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->TimerParam[timer_idx].DMASrcAddress, + hhrtim->TimerParam[timer_idx].DMADstAddress, + hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, @@ -5443,8 +5453,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related DMA requests are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -5459,14 +5469,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } else { - hhrtim->State = HAL_HRTIM_STATE_READY; - /* Disable the DMA request(s) */ - __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + hhrtim->State = HAL_HRTIM_STATE_READY; + /* Disable the DMA request(s) */ + __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } } @@ -5500,11 +5510,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -5518,15 +5528,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called after starting the timer(s) */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_BURSTMODECTL(Enable)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5552,9 +5562,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim) { - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5591,7 +5601,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim * @note The 'software capture' bit in the capure configuration register is * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -5599,9 +5609,9 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5612,32 +5622,32 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, /* Force a software capture on concerned capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - break; + break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5663,15 +5673,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, * @note The 'software update' bits in the HRTIM control register 2 register are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5705,15 +5715,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, * @note The 'software reset' bits in the HRTIM control register 2 are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERRESET(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5761,18 +5771,18 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferAddress, uint32_t BurstBufferLength) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) + if ((BurstBufferAddress == 0U) || (BurstBufferLength == 0U)) { return HAL_ERROR; } @@ -5806,17 +5816,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - BurstBufferAddress, - (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR), - BurstBufferLength) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + BurstBufferAddress, + (uint32_t) &(hhrtim->Instance->sCommonRegs.BDMADR), + BurstBufferLength) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5841,9 +5851,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers) + uint32_t Timers) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); /* Process Locked */ @@ -5860,7 +5870,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @brief Disable the transfer from preload to active registers for one @@ -5896,14 +5906,14 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @} */ /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions - * @brief Peripheral State functions + * @brief Peripheral State functions @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -5928,7 +5938,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval HAL state */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim) { /* Return HRTIM state */ return hhrtim->State; @@ -5950,7 +5960,7 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval Captured value */ -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -5963,21 +5973,21 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, /* Read captured value */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR; break; } - default: - { - captured_value = 0xFFFFFFFFUL; + default: + { + captured_value = 0xFFFFFFFFUL; break; } @@ -6013,7 +6023,7 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, * @note Returned output level is taken before the output stage (chopper, * polarity). */ -uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6025,11 +6035,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, /* Read the output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET) { @@ -6039,14 +6049,14 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, { output_level = HRTIM_OUTPUTLEVEL_INACTIVE; } - break; + break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET) { @@ -6059,7 +6069,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { output_level = 0xFFFFFFFFUL; break; @@ -6093,7 +6103,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Output state */ -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6109,67 +6119,67 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, /* Set output state according to output control status and output disable status */ switch (Output) { - case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TA1: { output_bit = HRTIM_OENR_TA1OEN; break; } - case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TA2: { output_bit = HRTIM_OENR_TA2OEN; break; } - case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TB1: { output_bit = HRTIM_OENR_TB1OEN; break; } - case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TB2: { output_bit = HRTIM_OENR_TB2OEN; break; } - case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TC1: { output_bit = HRTIM_OENR_TC1OEN; break; } - case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TC2: { output_bit = HRTIM_OENR_TC2OEN; break; } - case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TD1: { output_bit = HRTIM_OENR_TD1OEN; break; } - case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TD2: { output_bit = HRTIM_OENR_TD2OEN; break; } - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TE1: { output_bit = HRTIM_OENR_TE1OEN; break; } - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TE2: { output_bit = HRTIM_OENR_TE2OEN; break; } - default: + default: { output_bit = 0UL; break; @@ -6195,7 +6205,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, } } - return(output_state); + return (output_state); } /** @@ -6223,7 +6233,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Delayed protection status */ -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6235,11 +6245,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim /* Read the delayed protection status */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET) { @@ -6254,11 +6264,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET) { @@ -6273,7 +6283,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - default: + default: { delayed_protection_status = 0xFFFFFFFFUL; break; @@ -6288,7 +6298,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim * @param hhrtim pointer to HAL HRTIM handle * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim) { uint32_t burst_mode_status; @@ -6311,7 +6321,7 @@ uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t current_pushpull_status; @@ -6339,7 +6349,7 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Idle Push Pull Status */ -uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t idle_pushpull_status; @@ -6358,24 +6368,24 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling - * @brief Functions called when HRTIM generates an interrupt - * 7 interrupts can be generated by the master timer: - * - Master timer registers update - * - Synchronization event received - * - Master timer repetition event - * - Master Compare 1 to 4 event - * 14 interrupts can be generated by each timing unit: - * - Delayed protection triggered - * - Counter reset or roll-over event - * - Output 1 and output 2 reset (transition active to inactive) - * - Output 1 and output 2 set (transition inactive to active) - * - Capture 1 and 2 events - * - Timing unit registers update - * - Repetition event - * - Compare 1 to 4 event - * 7 global interrupts are generated for the whole HRTIM: - * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) - * - Burst mode period completed + * @brief Functions called when HRTIM generates an interrupt + * 7 interrupts can be generated by the master timer: + * - Master timer registers update + * - Synchronization event received + * - Master timer repetition event + * - Master Compare 1 to 4 event + * 14 interrupts can be generated by each timing unit: + * - Delayed protection triggered + * - Counter reset or roll-over event + * - Output 1 and output 2 reset (transition active to inactive) + * - Output 1 and output 2 set (transition inactive to active) + * - Capture 1 and 2 events + * - Timing unit registers update + * - Repetition event + * - Compare 1 to 4 event + * 7 global interrupts are generated for the whole HRTIM: + * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) + * - Burst mode period completed @verbatim =============================================================================== ##### HRTIM interrupts handling ##### @@ -6424,7 +6434,7 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * This parameter can be any value of HRTIM_Timer_Index * @retval None */ -void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* HRTIM interrupts handling */ @@ -6450,7 +6460,7 @@ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None * @retval None */ -__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6465,7 +6475,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6480,7 +6490,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6495,7 +6505,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6510,7 +6520,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6525,7 +6535,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6540,7 +6550,7 @@ __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6555,7 +6565,7 @@ __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6578,7 +6588,7 @@ __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6603,7 +6613,7 @@ __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6629,8 +6639,8 @@ __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6655,8 +6665,8 @@ __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E */ -__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6681,8 +6691,8 @@ __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6707,8 +6717,8 @@ __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6731,8 +6741,8 @@ __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6755,8 +6765,8 @@ __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6780,8 +6790,8 @@ __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6805,8 +6815,8 @@ __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6829,8 +6839,8 @@ __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6853,8 +6863,8 @@ __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6877,8 +6887,8 @@ __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6901,8 +6911,8 @@ __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6926,7 +6936,7 @@ __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6973,7 +6983,7 @@ __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim) * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback) { @@ -7102,7 +7112,7 @@ HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_MSPDEINIT_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -7114,79 +7124,79 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, { switch (CallbackID) { - case HAL_HRTIM_FAULT1CALLBACK_CB_ID : - hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; - break; + case HAL_HRTIM_FAULT1CALLBACK_CB_ID : + hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; + break; - case HAL_HRTIM_FAULT2CALLBACK_CB_ID : - hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; - break; + case HAL_HRTIM_FAULT2CALLBACK_CB_ID : + hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; + break; - case HAL_HRTIM_FAULT3CALLBACK_CB_ID : - hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; - break; + case HAL_HRTIM_FAULT3CALLBACK_CB_ID : + hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; + break; - case HAL_HRTIM_FAULT4CALLBACK_CB_ID : - hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; - break; + case HAL_HRTIM_FAULT4CALLBACK_CB_ID : + hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; + break; - case HAL_HRTIM_FAULT5CALLBACK_CB_ID : - hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; - break; + case HAL_HRTIM_FAULT5CALLBACK_CB_ID : + hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; + break; - case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : - hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; - break; + case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : + hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; + break; - case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : - hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; - break; + case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : + hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; + break; - case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : - hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; - break; + case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : + hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; + break; - case HAL_HRTIM_ERRORCALLBACK_CB_ID : - hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; - break; + case HAL_HRTIM_ERRORCALLBACK_CB_ID : + hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; + break; - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_HRTIM_STATE_RESET == hhrtim->State) { switch (CallbackID) { - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -7227,7 +7237,7 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback) { @@ -7308,7 +7318,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = pCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -7354,7 +7364,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -7426,7 +7436,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -7468,8 +7478,8 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_mcr; @@ -7497,9 +7507,9 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx , - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_timcr; @@ -7526,8 +7536,8 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg) +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_mcr; uint32_t hrtim_bmcr; @@ -7580,9 +7590,9 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_timcr; uint32_t hrtim_timfltr; @@ -7662,11 +7672,11 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, Delayed Idle is available whatever the timer operating mode (regular, push-pull) Balanced Idle is only available in push-pull mode */ - if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) + if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)) - || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) + || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) { - hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN); + hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN); hrtim_timoutr |= pTimerCfg->DelayedProtectionMode; } @@ -7676,43 +7686,43 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, /* Set the timer burst mode */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hrtim_bmcr &= ~(HRTIM_BMCR_TABM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 1U); break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hrtim_bmcr &= ~(HRTIM_BMCR_TBBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 2U); break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hrtim_bmcr &= ~(HRTIM_BMCR_TCBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 3U); break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hrtim_bmcr &= ~(HRTIM_BMCR_TDBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 4U); break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hrtim_bmcr &= ~(HRTIM_BMCR_TEBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 5U); break; } - default: - break; + default: + break; } /* Update the HRTIM registers */ @@ -7731,7 +7741,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param Event Event reference * @retval None */ -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event) @@ -7740,86 +7750,86 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10; break; } - default: - break; + default: + break; } switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger; break; } - default: - break; + default: + break; } } @@ -7831,10 +7841,10 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, * @param pOutputCfg pointer to the output configuration data structure * @retval None */ -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef *pOutputCfg) { uint32_t hrtim_outr; uint32_t hrtim_dtr; @@ -7846,11 +7856,11 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource; @@ -7858,11 +7868,11 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource; @@ -7871,15 +7881,15 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } /* Clear output config */ hrtim_outr &= ~((HRTIM_OUTR_POL1 | HRTIM_OUTR_IDLM1 | - HRTIM_OUTR_IDLES1| - HRTIM_OUTR_FAULT1| + HRTIM_OUTR_IDLES1 | + HRTIM_OUTR_FAULT1 | HRTIM_OUTR_CHP1 | HRTIM_OUTR_DIDL1) << shift); @@ -7922,7 +7932,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, * @param pEventCfg pointer to the event channel configuration data structure * @retval None */ -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, const HRTIM_EventCfgTypeDef *pEventCfg) { @@ -7937,7 +7947,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR1 = 0U; @@ -7946,7 +7956,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC); @@ -7960,7 +7970,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC); @@ -7974,7 +7984,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC); @@ -7988,7 +7998,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC); @@ -8002,7 +8012,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC); @@ -8016,7 +8026,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS); hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC); @@ -8030,7 +8040,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC); @@ -8044,21 +8054,21 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC); hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL); hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS); hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); - hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F ); + hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC); @@ -8072,7 +8082,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC); @@ -8086,8 +8096,8 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } } @@ -8098,74 +8108,74 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @param Event Event channel identifier * @retval None */ -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event) { switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10; break; } - default: - break; + default: + break; } } @@ -8188,7 +8198,7 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Interrupt to enable or disable */ -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8198,13 +8208,13 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -8217,29 +8227,29 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -8252,24 +8262,24 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return interrupt; @@ -8294,7 +8304,7 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval DMA request to enable or disable */ -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8304,13 +8314,13 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -8323,29 +8333,29 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -8358,81 +8368,81 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return dma_request; } -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL; + DMA_HandleTypeDef *hdma = (DMA_HandleTypeDef *)NULL; switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hdma = hhrtim->hdmaMaster; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hdma = hhrtim->hdmaTimerA; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hdma = hhrtim->hdmaTimerB; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hdma = hhrtim->hdmaTimerC; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hdma = hhrtim->hdmaTimerD; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hdma = hhrtim->hdmaTimerE; break; } - default: - break; + default: + break; } return hdma; } -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma) +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma) { uint32_t timed_idx = 0xFFFFFFFFU; @@ -8474,49 +8484,49 @@ static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, * @param TimerIdx Timer index * @retval None */ -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU; break; } - default: - break; + default: + break; } } @@ -8526,15 +8536,15 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); /* Fault 1 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1); @@ -8548,9 +8558,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 2 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2); @@ -8564,9 +8574,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 3 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3); @@ -8580,9 +8590,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 4 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4); @@ -8596,9 +8606,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 5 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5); @@ -8612,9 +8622,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* System fault event */ - if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT); @@ -8629,11 +8639,11 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /** -* @brief Master timer interrupts service routine -* @param hhrtim pointer to HAL HRTIM handle -* @retval None -*/ -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) + * @brief Master timer interrupts service routine + * @param hhrtim pointer to HAL HRTIM handle + * @retval None + */ +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); @@ -8641,9 +8651,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); /* Burst mode period event */ - if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER); @@ -8657,9 +8667,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 1 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1); @@ -8673,9 +8683,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 2 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2); @@ -8689,9 +8699,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 3 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3); @@ -8705,9 +8715,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 4 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4); @@ -8721,9 +8731,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer repetition event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP); @@ -8737,9 +8747,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Synchronization input event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC); @@ -8753,9 +8763,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer registers update event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD); @@ -8780,17 +8790,17 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None -*/ -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) + */ +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR); uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER); /* Timer compare 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); @@ -8804,9 +8814,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); @@ -8820,9 +8830,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 3 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3); @@ -8836,9 +8846,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 4 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4); @@ -8852,9 +8862,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer repetition event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP); @@ -8868,9 +8878,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer registers update event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD); @@ -8884,9 +8894,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1); @@ -8900,9 +8910,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); @@ -8916,9 +8926,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1); @@ -8932,9 +8942,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1); @@ -8948,9 +8958,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2); @@ -8964,9 +8974,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2); @@ -8980,9 +8990,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST); @@ -8996,9 +9006,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Delayed protection event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT); @@ -9019,7 +9029,7 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET) { @@ -9092,11 +9102,11 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) { uint8_t timer_idx; - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma); - if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;} + if (!IS_HRTIM_TIMING_UNIT(timer_idx)) {return;} if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET) { @@ -9217,16 +9227,16 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) } /** -* @brief DMA error callback -* @param hdma pointer to DMA handle. -* @retval None -*/ + * @brief DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->ErrorCallback(hrtim); + hrtim->ErrorCallback(hrtim); #else HAL_HRTIM_ErrorCallback(hrtim); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ @@ -9239,10 +9249,10 @@ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) */ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); + hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #else HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c index 39b2d68dd5..665cab0631 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1407,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1428,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1439,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1451,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -3255,6 +3267,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3312,37 +3326,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -4552,7 +4593,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4561,7 +4602,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -7284,15 +7327,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c index d449267694..0cd61d309b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c @@ -1835,6 +1835,107 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) return errorcode; } +/** + * @brief Enable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDO and original SDO pin becomes SDI (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature enabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Enable IO Swap feature */ + SET_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Disable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDI and original SDO pin becomes SDO (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature disabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Disable the IO Swap feature */ + CLEAR_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Retrieve the SDO/SDI alternate functions inversion feature status for the dedicated I2Sx. + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval 1 when I2S IO swap feature is enabled, 0 otherwise, or when hi2s pointer is null. + */ +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return 0; + } + + return ((READ_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + /** * @brief This function handles I2S interrupt request. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c index 2ec2829876..23955db40f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c @@ -127,7 +127,8 @@ The timeout value is multiplied by 1000 to be converted in milliseconds. LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c index ac257fab62..662519a8a4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c @@ -279,24 +279,20 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); /* Set Synchronization size */ - hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); tmp = (hltdc->Init.HorizontalSync << 16U); - hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync)); /* Set Accumulated Back porch */ - hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); tmp = (hltdc->Init.AccumulatedHBP << 16U); - hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP)); /* Set Accumulated Active Width */ - hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); tmp = (hltdc->Init.AccumulatedActiveW << 16U); - hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH)); /* Set Total Width */ - hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); tmp = (hltdc->Init.TotalWidth << 16U); - hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh)); /* Set the background color value */ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); @@ -916,11 +912,12 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx) { uint32_t tmp; uint32_t counter; - uint32_t *pcolorlut = pCLUT; + const uint32_t *pcolorlut = pCLUT; /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -2092,7 +2089,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * the configuration information for the LTDC. * @retval HAL state */ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc) { return hltdc->State; } @@ -2103,7 +2100,7 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @retval LTDC Error Code */ -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc) { return hltdc->ErrorCode; } @@ -2154,9 +2151,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | - LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2)); /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); @@ -2167,8 +2162,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); /* Configure the color frame buffer start address */ - LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress); if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c index dc7b722acf..50b04a985a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c @@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum * @param hmdios: mdios handle * @retval bit map of written registers addresses */ -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios) { return hmdios->Instance->WRFR; } @@ -645,7 +645,7 @@ uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval bit map of read registers addresses */ -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios) { return hmdios->Instance->RDFR; } @@ -916,7 +916,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval mdios error code */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios) { /* return the error code */ return hmdios->ErrorCode; @@ -927,7 +927,7 @@ uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval HAL state */ -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios) { /* Return MDIOS state */ return hmdios->State; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c index 089d9fbb1d..064949bc54 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c @@ -708,7 +708,7 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD * * @retval HAL status */ -HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode) +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode) { MDMA_LinkNodeTypeDef *pNode; uint32_t counter = 0, nodeInserted = 0; @@ -1719,7 +1719,7 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) * the configuration information for the specified MDMA Channel. * @retval HAL state */ -HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma) { return hmdma->State; } @@ -1730,7 +1730,7 @@ HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) * the configuration information for the specified MDMA Channel. * @retval MDMA Error Code */ -uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma) +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma) { return hmdma->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c index 0aa5d66313..b67bdef9a7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization - *** MMC Card Initialization and configuration *** ================================================ [..] @@ -93,6 +92,7 @@ (#) Select the corresponding MMC Card according to the address read with the step 2. (#) Configure the MMC Card in wide bus mode: 4-bits data. + (#) Select the MMC Card partition using HAL_MMC_SwitchPartition() *** MMC Card Read operation *** ============================== @@ -169,6 +169,64 @@ (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. Some of the CID parameters are useful for card initialization and identification. + *** MMC Card Reply Protected Memory Block (RPMB) Key Programming operation *** + ============================== + [..] + (+) You can program the authentication key of RPMB area in polling mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can program the authentication key of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey_IT(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) write counter operation *** + ============================== + [..] + (+) You can get the write counter value of RPMB area in polling mode by using function + HAL_MMC_RPMB_GetWriteCounter(). + (+) You can get the write counter value of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_GetWriteCounter_IT(). + + *** MMC Card Reply Protected Memory Block (RPMB) write operation *** + ============================== + [..] + (+) You can write to the RPMB area of MMC card in polling mode by using function + HAL_MMC_WriteBlocks(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can write to the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_WriteBlocks_IT(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) read operation *** + ============================== + [..] + (+) You can read from the RPMB area of MMC card in polling mode by using function + HAL_MMC_RPMB_ReadBlocks(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + (+) You can read from the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_RPMB_ReadBlocks_IT(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + *** MMC HAL driver macros list *** ================================== [..] @@ -204,7 +262,7 @@ and a pointer to the user callback function. Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. (+) ErrorCallback : callback when error occurs. @@ -218,9 +276,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + reset to the legacy weak (overridden) functions in the HAL_MMC_Init and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -235,7 +293,7 @@ When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -253,6 +311,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_MMC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -290,6 +349,12 @@ /* Frequencies used in the driver for clock divider calculation */ #define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ #define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ + +/* The Data elements' postitions in the frame Frame for RPMB area */ +#define MMC_RPMB_KEYMAC_POSITION 196U +#define MMC_RPMB_DATA_POSITION 228U +#define MMC_RPMB_NONCE_POSITION 484U +#define MMC_RPMB_WRITE_COUNTER_POSITION 500U /** * @} */ @@ -538,7 +603,6 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) return HAL_OK; } - /** * @brief Initializes the MMC MSP. * @param hmmc: Pointer to MMC handle @@ -655,7 +719,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -697,10 +761,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -712,7 +776,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -850,7 +914,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -892,10 +956,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -907,7 +971,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD tempbuff++; (void)SDMMC_WriteFIFO(hmmc->Instance, &data); } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -1044,7 +1108,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1157,7 +1221,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1271,7 +1335,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1386,7 +1450,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1504,8 +1568,8 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - start_add *= 512U; - end_add *= 512U; + start_add *= MMC_BLOCKSIZE; + end_add *= MMC_BLOCKSIZE; } /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ @@ -1793,7 +1857,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) * @param hmmc: Pointer to mmc handle * @retval HAL state */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc) { return hmmc->State; } @@ -1804,7 +1868,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) * the configuration information. * @retval MMC Error Code */ -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc) { return hmmc->ErrorCode; } @@ -1872,7 +1936,7 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) /** * @brief Register a User MMC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @note The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID * and HAL_MMC_MSP_DEINIT_CB_ID. @@ -1977,7 +2041,7 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call /** * @brief Unregister a User MMC Callback - * MMC Callback is redirected to the weak (surcharged) predefined callback + * MMC Callback is redirected to the weak (overridden) predefined callback * @note The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID * and HAL_MMC_MSP_DEINIT_CB_ID. @@ -2099,7 +2163,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); @@ -2185,14 +2249,14 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); - hmmc->MmcCard.LogBlockSize = 512U; + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / MMC_BLOCKSIZE); + hmmc->MmcCard.LogBlockSize = MMC_BLOCKSIZE; } else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) { hmmc->MmcCard.BlockNbr = block_nbr; hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; - hmmc->MmcCard.BlockSize = 512U; + hmmc->MmcCard.BlockSize = MMC_BLOCKSIZE; hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; } else @@ -2250,7 +2314,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp * will contain the MMC card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); @@ -2300,7 +2364,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512U; + config.DataLength = MMC_BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -2326,7 +2390,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance); tmp_buf++; @@ -2707,7 +2771,8 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); /*we will send the CMD12 in all cases in order to stop the data transfers*/ - /*In case the data transfer just finished , the external memory will not respond and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer just finished, the external memory will not respond + and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/ /*Other scenario will return HAL_ERROR*/ @@ -2723,40 +2788,40 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) { if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } } else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } else @@ -2764,13 +2829,15 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) /* Nothing to do*/ } - /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear the appropriate flags that will be set depending of the abort/non abort of the memory */ - /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result in next SDMMC read/write operation to fail */ + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear + the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result + in next SDMMC read/write operation to fail */ /*SDMMC ready for clear data flags*/ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - /* If IDMA Context, disable Internal DMA */ + /* If IDMA Context, disable Internal DMA */ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; hmmc->State = HAL_MMC_STATE_READY; @@ -2902,8 +2969,8 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT /* In case of low capacity card, the address is not block number but bytes */ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - start_add *= 512U; - end_add *= 512U; + start_add *= MMC_BLOCKSIZE; + end_add *= MMC_BLOCKSIZE; } /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */ @@ -3562,7 +3629,6 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc) * @{ */ - /** * @brief Initializes the mmc card. * @param hmmc: Pointer to MMC handle @@ -3646,7 +3712,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->ErrorCode |= errorstate; } - /* Get Extended CSD parameters */ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) { @@ -3789,7 +3854,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512U; + config.DataLength = MMC_BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -3814,7 +3879,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { tmp_data = SDMMC_ReadFIFO(hmmc->Instance); /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ @@ -3896,10 +3961,10 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pRxBuffPtr; - if (hmmc->RxXferSize >= 32U) + if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3913,7 +3978,7 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) } hmmc->pRxBuffPtr = tmp; - hmmc->RxXferSize -= 32U; + hmmc->RxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3931,10 +3996,10 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pTxBuffPtr; - if (hmmc->TxXferSize >= 32U) + if (hmmc->TxXferSize >= SDMMC_FIFO_SIZE) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tmp); tmp++; @@ -3948,7 +4013,7 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) } hmmc->pTxBuffPtr = tmp; - hmmc->TxXferSize -= 32U; + hmmc->TxXferSize -= SDMMC_FIFO_SIZE; } } @@ -4276,6 +4341,1553 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 return errorstate; } +/** + * @brief Used to select the partition. + * @param hmmc: Pointer to MMC handle + * @param Partition: Partition type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) +{ + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; + uint32_t tickstart = HAL_GetTick(); + uint32_t arg = Partition | 0x03B30000U; + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Index : 179 - Value : partition */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, arg); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) + { + errorstate = HAL_MMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Allows to program the authentication key within the RPMB partition + * @param hmmc: Pointer to MMC handle + * @param pKey: pointer to the authentication key (32 bytes) + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + + tail_pack[11] = 0x01; + + if (NULL == pKey) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x80000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pKey; + } + else if ((byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) && \ + (byte_count >= MMC_RPMB_DATA_POSITION)) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x01U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to get the value of write counter within the RPMB partition. + * @param hmmc: Pointer to MMC handle + * @param pNonce: pointer to the value of nonce (16 bytes) + * @param Timeout: Specify timeout value + * @retval write counter value. + */ +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint8_t *tempbuff = zero_pack; + + tail_pack[11] = 0x02; + + if (NULL == pNonce) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = (uint8_t *)pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + + return ((uint32_t)tail_pack[3] | ((uint32_t)tail_pack[2] << 8) | ((uint32_t)tail_pack[1] << 16) | \ + ((uint32_t)tail_pack[0] << 24)); + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } +} + +/** + * @brief Allows to write block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @param pMAC: Pointer to the authentication MAC buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout) +{ + + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + const uint8_t local_nonce[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x00, 0x01, 0x02, + 0x03, 0x04, 0x00, 0x01, 0x02, 0x03, 0x04, 0x08 + }; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0x80000000U; + uint32_t offset = 0; + + if ((NumberOfBlocks != 0x1U) && (NumberOfBlocks != 0x2U) && (NumberOfBlocks != 0x20U)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if ((NULL == pData) || (NULL == pMAC)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + tail_pack[11] = 0x02; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = local_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (local_nonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } + tail_pack[11] = 0x03; + tail_pack[10] = 0x00; + tail_pack[7] = (uint8_t)(NumberOfBlocks) & 0xFFU; + tail_pack[6] = (uint8_t)(NumberOfBlocks >> 8) & 0xFFU; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + + rtempbuff = zero_pack; + byte_count = 0; + arg |= NumberOfBlocks; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pMAC; + } + if (byte_count == MMC_RPMB_DATA_POSITION) + { + rtempbuff = &pData[offset]; + } + if ((byte_count >= MMC_RPMB_NONCE_POSITION) && \ + (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)) + { + rtempbuff = zero_pack; + } + if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + offset += (uint32_t)256U; + byte_count = 0; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Response Packet */ + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if (((tail_pack[9] & (uint8_t)0xFEU) != 0x00U) || (tail_pack[10] != 0x03U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to read block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @param pNonce: Pointer to the buffer that will contain the nonce to transmit + * @param pMAC: Pointer to the authentication MAC buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint32_t dataremaining; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0; + uint32_t offset = 0; + + arg |= NumberOfBlocks; + + tail_pack[11] = 0x04; + tail_pack[10] = 0x00; + tail_pack[7] = 0x00; + tail_pack[6] = 0x00; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + tail_pack[3] = 0x00; + tail_pack[2] = 0x00; + tail_pack[1] = 0x00; + tail_pack[0] = 0x00; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 1); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = (uint8_t *)pMAC; + } + else if (byte_count == MMC_RPMB_DATA_POSITION) + { + tempbuff = &pData[offset]; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + byte_count = 0; + offset += (uint32_t)256U; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x04U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + + /** * @brief Read DMA Buffer 0 Transfer completed callbacks * @param hmmc: MMC handle @@ -4341,6 +5953,7 @@ __weak void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc) */ #endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c index 10acaf3610..8723867067 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c @@ -45,6 +45,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_MMC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -59,7 +60,6 @@ */ - /** @addtogroup MMCEx_Exported_Functions_Group1 * @brief Multibuffer functions * @@ -333,7 +333,6 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D return HAL_OK; } - /** * @} */ @@ -343,6 +342,7 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D */ #endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c index 87c492d0f1..370d123d52 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c index 688ff3e7af..5bb8080317 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c @@ -902,10 +902,10 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp) * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available * */ -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) { HAL_OPAMP_TrimmingValueTypeDef trimmingvalue; - __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ + __IO const uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ /* Check the OPAMP handle allocation */ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ @@ -1122,7 +1122,7 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL * @param hopamp OPAMP handle * @retval HAL state */ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp) { /* Check the OPAMP handle allocation */ if(hopamp == NULL) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c index 46474bfe11..332f08082e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c @@ -1177,7 +1177,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1270,7 +1271,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1597,7 +1599,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData } /* Enable the transmit MDMA Channel */ - if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize, 1) == \ + if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == \ HAL_OK) { /* Enable the transfer error interrupt */ @@ -2581,8 +2583,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || + ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c index af78206b19..f34f396116 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c @@ -69,11 +69,11 @@ The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions HAL_OTFDEC_RegisterCallback() + Use Functions @ref HAL_OTFDEC_RegisterCallback() to register an interrupt callback. [..] - Function HAL_OTFDEC_RegisterCallback() allows to register following callbacks: + Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : OTFDEC error callback (+) MspInitCallback : OTFDEC Msp Init callback (+) MspDeInitCallback : OTFDEC Msp DeInit callback @@ -81,11 +81,11 @@ and a pointer to the user callback function. [..] - Use function HAL_OTFDEC_UnRegisterCallback to reset a callback to the default + Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default weak function. [..] - HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle, + @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : OTFDEC error callback @@ -93,27 +93,27 @@ (+) MspDeInitCallback : OTFDEC Msp DeInit callback [..] - By default, after the HAL_OTFDEC_Init() and when the state is HAL_OTFDEC_STATE_RESET + By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET all callbacks are set to the corresponding weak functions: - example HAL_OTFDEC_ErrorCallback(). + example @ref HAL_OTFDEC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_OTFDEC_Init()HAL_OTFDEC_DeInit() only when + reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/HAL_OTFDEC_DeInit() + If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in HAL_OTFDEC_STATE_READY state only. + Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_OTFDEC_STATE_READY or HAL_OTFDEC_STATE_RESET state, + in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_OTFDEC_RegisterCallback() before calling HAL_OTFDEC_DeInit() - or HAL_OTFDEC_Init() function. + using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit() + or @ref HAL_OTFDEC_Init() function. [..] When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or @@ -693,7 +693,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32 * @retval HAL state */ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) { OTFDEC_Region_TypeDef *region; uint32_t address; @@ -753,16 +753,16 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_ * @param pKey pointer at set of keys * @retval CRC value */ -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey) +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey) { uint8_t crc7_poly = 0x7; - uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; + const uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; uint8_t i; uint8_t crc = 0; uint32_t j; uint32_t keyval; uint32_t k; - uint32_t *temp = pKey; + const uint32_t *temp = pKey; for (j = 0U; j < 4U; j++) { @@ -901,7 +901,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 * the configuration information for OTFDEC module * @retval HAL state */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec) +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec) { return hotfdec->State; } @@ -914,9 +914,9 @@ HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec) * @param RegionIndex index of region the keys CRC of which is read * @retval Key CRC */ -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) { - OTFDEC_Region_TypeDef *region; + const OTFDEC_Region_TypeDef *region; uint32_t address; uint32_t keycrc; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c index 221cdfc082..a50cac24be 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c @@ -1453,7 +1453,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -1766,7 +1766,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1781,7 +1781,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; if (ep->is_in != 0U) @@ -2101,6 +2101,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t tes case TEST_SE0_NAK: case TEST_PACKET: case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7U << 4); USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; break; @@ -2331,13 +2332,11 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - /** * @} */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c index 60fb841d8b..4262725490 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c @@ -412,7 +412,7 @@ void HAL_PWR_DisableBkUpAccess (void) * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ -void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD) { /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c index 4b1a86e7c5..6faff7386c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c @@ -308,6 +308,10 @@ * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. + * @note This API is deprecated and is kept only for backward compatibility's sake. + * The power supply configuration is handled as part of the system initialization + * process during startup. + * For more details, please refer to the power control chapter in the reference manual * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) @@ -1299,7 +1303,7 @@ void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock) * Cortex-M4. * @retval None. */ -void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams) +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams) { uint32_t pinConfig; uint32_t regMask; @@ -1973,7 +1977,7 @@ PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void) * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ -void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD) { /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c index 1d8fa10e68..48554f57a3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c @@ -1325,21 +1325,24 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat status = HAL_ERROR; } + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Use DMAEN bit with no impact on H7 HW to record MDMA transfer request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Enable the QSPI transmit MDMA */ if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved" - but no impact on H7 HW and it minimize the cost in the footprint */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } else { + /* Clear DMAEN bit with no impact on H7 HW to cancel MDMA transfer request */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + status = HAL_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; hqspi->State = HAL_QSPI_STATE_READY; @@ -1440,21 +1443,23 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Use DMAEN bit with no impact on H7 HW to record MDMA transfer request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + /* Enable the MDMA */ if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved" - but no impact on H7 HW and it minimize the cost in the footprint */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } else { + /* Clear DMAEN bit with no impact on H7 HW to cancel MDMA transfer request */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + status = HAL_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; hqspi->State = HAL_QSPI_STATE_READY; @@ -2550,6 +2555,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2577,6 +2585,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } @@ -2611,6 +2622,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2640,6 +2654,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c index d59992a95f..ec1e1f34a7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c @@ -613,7 +613,7 @@ __weak void HAL_RAMECC_DetectErrorCallback(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing address offset. */ -uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -629,7 +629,7 @@ uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing data low. */ -uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -645,7 +645,7 @@ uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing data high. */ -uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -661,7 +661,7 @@ uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Hamming bits injected. */ -uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -677,7 +677,7 @@ uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval State of bit (1 or 0). */ -uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -693,7 +693,7 @@ uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval State of bit (1 or 0). */ -uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -734,7 +734,7 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC state. */ -HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc) +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC state */ return hramecc->State; @@ -747,7 +747,7 @@ HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC error code. */ -uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC error code */ return hramecc->ErrorCode; @@ -760,7 +760,7 @@ uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC error code detected. */ -uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetRAMECCError(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC error code detected*/ return hramecc->RAMECCErrorCode; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c index 8c987ac8ef..dad88545fd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -919,7 +919,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { HAL_StatusTypeDef halstatus; uint32_t tickstart; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c index 96517ce083..b619c4ae5e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -58,8 +58,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider); -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider); /* Exported functions --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions @@ -3379,7 +3379,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) * @param pInit Pointer on RCC_CRSInitTypeDef structure * @retval None */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) { uint32_t value; @@ -3690,7 +3690,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { uint32_t tickstart; @@ -3795,7 +3795,7 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c index ef602992f4..7f5142d28d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c @@ -116,9 +116,9 @@ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x000CAA74U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x00007274U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} @@ -216,7 +216,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -257,12 +257,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -673,6 +673,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c index 70c5540524..0bcb1add39 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -45,16 +45,16 @@ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x000CAA74U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x00007274U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -66,11 +66,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -141,7 +141,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -283,7 +283,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -320,6 +320,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c index 140826c0fd..0216e438db 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c @@ -112,10 +112,20 @@ (+) TimeStampEventCallback : RTC TimeStamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. (*) (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) InternalTamper1EventCallback : RTC Internal Tamper 1 Callback ID (*) + (+) InternalTamper2EventCallback : RTC Internal Tamper 2 Callback ID (*) + (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Callback ID (*) + (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Callback ID (*) + (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Callback ID (*) + (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Callback ID (*) + (+) InternalTamper8EventCallback : RTC Internal Tamper 8 Callback ID (*) (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. + + (*) Not applicable to all devices. + This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -129,11 +139,20 @@ (+) TimeStampEventCallback : RTC TimeStamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. (*) (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) InternalTamper1EventCallback : RTC Internal Tamper 1 Callback ID (*) + (+) InternalTamper2EventCallback : RTC Internal Tamper 2 Callback ID (*) + (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Callback ID (*) + (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Callback ID (*) + (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Callback ID (*) + (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Callback ID (*) + (+) InternalTamper8EventCallback : RTC Internal Tamper 8 Callback ID (*) (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. + (*) Not applicable to all devices. + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, all callbacks are set to the corresponding weak functions : examples AlarmAEventCallback(), WakeUpTimerEventCallback(). @@ -254,7 +273,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ +#if defined(RTC_TAMPER2_SUPPORT) hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ +#endif /* RTC_TAMPER2_SUPPORT */ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ #if defined(TAMP) @@ -483,17 +504,18 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID (*) * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID (*) * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * (*) Not applicable to all devices. * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -533,9 +555,11 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call hrtc->Tamper1EventCallback = pCallback; break; +#if defined(RTC_TAMPER2_SUPPORT) case HAL_RTC_TAMPER2_EVENT_CB_ID : hrtc->Tamper2EventCallback = pCallback; break; +#endif /* RTC_TAMPER2_SUPPORT */ case HAL_RTC_TAMPER3_EVENT_CB_ID : hrtc->Tamper3EventCallback = pCallback; @@ -626,17 +650,18 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID (*) * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID (*) * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * (*) Not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) @@ -670,9 +695,11 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ break; +#if defined(RTC_TAMPER2_SUPPORT) case HAL_RTC_TAMPER2_EVENT_CB_ID : hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ break; +#endif /* RTC_TAMPER2_SUPPORT */ case HAL_RTC_TAMPER3_EVENT_CB_ID : hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ @@ -920,7 +947,7 @@ HAL_StatusTypeDef status; * to ensure consistency between the time and date values. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg; @@ -1052,7 +1079,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * Reading RTC current time locks the values in calendar shadow registers until Current date is read. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg; @@ -1604,7 +1631,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { uint32_t tmpreg; uint32_t subsecondtmpreg; @@ -1883,7 +1910,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval HAL state */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc) { /* Return RTC handle state */ return hrtc->State; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c index 252dce91b8..aef0524bc7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c @@ -115,7 +115,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#if defined(TAMP) #define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) +#endif /* TAMP */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -469,7 +471,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -537,7 +539,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -576,6 +578,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); } +#if defined(RTC_TAMPNOERASE_SUPPORT) /* Configure the tamper backup registers erasure bit */ if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { @@ -607,7 +610,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE); } } +#endif /* RTC_TAMPNOERASE_SUPPORT */ +#if defined(RTC_TAMPMASKFLAG_SUPPORT) /* Configure the tamper flags masking bit */ if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { @@ -639,6 +644,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF); } } +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ /* Clearing remaining fields before setting them */ tmpreg &= ~(RTC_TAMPERFILTER_MASK | RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ @@ -671,7 +677,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -748,7 +754,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -788,6 +794,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); } +#if defined(RTC_TAMPNOERASE_SUPPORT) /* Configure the tamper backup registers erasure bit */ if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { @@ -819,7 +826,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE); } } +#endif /* RTC_TAMPNOERASE_SUPPORT */ +#if defined(RTC_TAMPMASKFLAG_SUPPORT) /* Configure the tamper flags masking bit */ if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { @@ -851,6 +860,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF); } } +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ /* Clearing remaining fields before setting them */ tmpreg &= ~(RTC_TAMPERFILTER_MASK | RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ @@ -933,8 +943,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t * @param Tamper Selected tamper pin. * This parameter can be any combination of the following values: * @arg RTC_TAMPER_1 - * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_2 (*) * @arg RTC_TAMPER_3 + * (*) Not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t Tamper) @@ -949,21 +960,28 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t /* Disable the selected Tamper pin */ hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); +#if defined(RTC_TAMPxIE_SUPPORT) /* Disable the selected Tamper interrupt */ if ((Tamper & RTC_TAMPER_1) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); } +#if defined(RTC_TAMPER2_SUPPORT) if ((Tamper & RTC_TAMPER_2) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); } +#endif /* RTC_TAMPER2_SUPPORT */ if ((Tamper & RTC_TAMPER_3) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); } +#else + /* Disable the Tamper interrupt */ + hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP); +#endif /* RTC_TAMPxIE_SUPPORT */ hrtc->State = HAL_RTC_STATE_READY; @@ -981,7 +999,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t * @param sIntTamper Pointer to Internal Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper) { /* Check the parameters */ assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); @@ -1007,7 +1025,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_Inter * @param sIntTamper Pointer to Internal Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper) { /* Check the parameters */ assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); @@ -1063,7 +1081,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, ui * @param sAllTamper Pointer to active Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper) +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper) { uint32_t IER, CR1, CR2, ATCR1, CR, i, tickstart; @@ -1177,7 +1195,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active * @param pSeed Pointer to active tamper seed values. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed) +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed) { uint32_t i, tickstart; @@ -1295,6 +1313,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } +#if defined(RTC_TAMPER2_SUPPORT) /* Check Tamper 2 status */ if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) { @@ -1306,6 +1325,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_Tamper2EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } +#endif /* RTC_TAMPER2_SUPPORT */ /* Check Tamper 3 status */ if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) @@ -1442,7 +1462,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } /* Get the Tamper 1 interrupt source enable status */ +#if defined(RTC_TAMPxIE_SUPPORT) if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U) +#else + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) +#endif /* RTC_TAMPxIE_SUPPORT */ { /* Get the pending status of the Tamper 1 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) @@ -1460,7 +1484,12 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } /* Get the Tamper 2 interrupt source enable status */ +#if defined(RTC_TAMPER2_SUPPORT) +#if defined(RTC_TAMPxIE_SUPPORT) if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U) +#else + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) +#endif /* RTC_TAMPxIE_SUPPORT */ { /* Get the pending status of the Tamper 2 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) @@ -1476,9 +1505,14 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } } +#endif /* RTC_TAMPER2_SUPPORT */ /* Get the Tamper 3 interrupts source enable status */ +#if defined(RTC_TAMPxIE_SUPPORT) if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U) +#else + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) +#endif /* RTC_TAMPxIE_SUPPORT */ { /* Get the pending status of the Tamper 3 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U) @@ -1540,6 +1574,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef * hrtc) */ } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Tamper 2 callback. * @param hrtc RTC handle @@ -1554,6 +1589,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef * hrtc) the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file */ } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Tamper 3 callback. @@ -1768,6 +1804,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef * hrtc, uint32 return HAL_OK; } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Handle Tamper2 Polling. * @param hrtc RTC handle @@ -1799,6 +1836,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef * hrtc, uint32 return HAL_OK; } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Handle Tamper3 Polling. @@ -2129,7 +2167,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval Counter value */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc) { /* Get the counter value */ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); @@ -2273,7 +2311,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef * hrtc, ui * @param Data Data to be written in the specified Backup data register. * @retval None */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint32_t Data) +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -2282,9 +2320,9 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint /* Point on address of first backup register */ #if defined(TAMP) - tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); + tmp = (uint32_t) &(((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); #else - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); #endif /* TAMP */ tmp += (BackupRegister * 4U); @@ -2302,7 +2340,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint * specify the register. * @retval Read value */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) { uint32_t tmp; @@ -2311,9 +2349,9 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) /* Point on address of first backup register */ #if defined(TAMP) - tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); + tmp = (uint32_t) &(((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); #else - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); #endif /* TAMP */ tmp += (BackupRegister * 4U); @@ -2709,7 +2747,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef * hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + hrtc->Instance->CR |= (uint32_t)RTC_CR_BYPSHAD; /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -2741,7 +2779,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef * hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BYPSHAD); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -2784,7 +2822,7 @@ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, * @param Counter monotonic counter value * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance) +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance) { UNUSED(hrtc); UNUSED(Instance); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c index fea0680856..ae33c68277 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization - *** SD Card Initialization and configuration *** ================================================ [..] @@ -211,7 +210,7 @@ respectively HAL_SD_RegisterTransceiverCallback(). Use function HAL_SD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. (+) ErrorCallback : callback when error occurs. @@ -227,9 +226,9 @@ respectively HAL_SD_UnRegisterTransceiverCallback(). By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SD_Init + reset to the legacy weak (overridden) functions in the HAL_SD_Init and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -244,7 +243,7 @@ When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -261,6 +260,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -439,7 +439,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -607,7 +607,6 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Initializes the SD MSP. * @param hsd: Pointer to SD handle @@ -704,7 +703,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -746,10 +745,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 dataremaining = config.DataLength; while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -761,7 +760,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -889,7 +888,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -932,10 +931,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -947,7 +946,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData tempbuff++; (void)SDMMC_WriteFIFO(hsd->Instance, &data); } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -1074,7 +1073,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1169,7 +1168,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pD if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1266,7 +1265,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1310,7 +1309,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Enable transfer interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - return HAL_OK; } else @@ -1365,7 +1363,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1377,7 +1375,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASE0 = (uint32_t) pData ; @@ -1474,8 +1471,8 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Get start and end block for high capacity cards */ if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - start_add *= 512U; - end_add *= 512U; + start_add *= BLOCKSIZE; + end_add *= BLOCKSIZE; } /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ @@ -1765,7 +1762,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) * @param hsd: Pointer to sd handle * @retval HAL state */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd) { return hsd->State; } @@ -1776,7 +1773,7 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) * the configuration information. * @retval SD Error Code */ -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd) { return hsd->ErrorCode; } @@ -1860,7 +1857,7 @@ __weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /** * @brief Register a User SD Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @note The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID * and HAL_SD_MSP_DEINIT_CB_ID. @@ -1965,7 +1962,7 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback /** * @brief Unregister a User SD Callback - * SD Callback is redirected to the weak (surcharged) predefined callback + * SD Callback is redirected to the weak (overridden) predefined callback * @note The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID * and HAL_SD_MSP_DEINIT_CB_ID. @@ -2062,7 +2059,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba #if (USE_SD_TRANSCEIVER != 0U) /** * @brief Register a User SD Transceiver Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hsd : SD handle * @param pCallback : pointer to the Callback function * @retval status @@ -2100,7 +2097,7 @@ HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_ /** * @brief Unregister a User SD Transceiver Callback - * SD Callback is redirected to the weak (surcharged) predefined callback + * SD Callback is redirected to the weak (overridden) predefined callback * @param hsd : SD handle * @retval status */ @@ -2157,7 +2154,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); @@ -2236,8 +2233,8 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); - hsd->SdCard.LogBlockSize = 512U; + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / BLOCKSIZE); + hsd->SdCard.LogBlockSize = BLOCKSIZE; } else if (hsd->SdCard.CardType == CARD_SDHC_SDXC) { @@ -2246,7 +2243,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; - hsd->SdCard.BlockSize = 512U; + hsd->SdCard.BlockSize = BLOCKSIZE; hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; } else @@ -2363,7 +2360,6 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT status = HAL_ERROR; } - return status; } @@ -2374,7 +2370,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); @@ -2404,6 +2400,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t SDMMC_InitTypeDef Init; uint32_t errorstate; uint32_t sdmmc_clk; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2833,7 +2830,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -2893,11 +2890,12 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { /* DIsable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); __SDMMC_CMDTRANS_DISABLE(hsd->Instance); /*we will send the CMD12 in all cases in order to stop the data transfers*/ - /*In case the data transfer just finished , the external memory will not respond and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer just finished , the external memory will not respond + and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/ /*Other scenario will return HAL_ERROR*/ @@ -2913,40 +2911,40 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { if (hsd->ErrorCode == HAL_SD_ERROR_NONE) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } } else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } else @@ -2962,7 +2960,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /*SDMMC ready for clear data flags*/ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END); __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - /* If IDMA Context, disable Internal DMA */ + /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; hsd->State = HAL_SD_STATE_READY; @@ -2973,7 +2971,6 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Abort the current transfer and disable the SD (IT mode). * @param hsd: pointer to a SD_HandleTypeDef structure that contains @@ -3031,7 +3028,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) * @{ */ - /** * @brief Initializes the sd card. * @param hsd: Pointer to SD handle @@ -3237,7 +3233,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check to CKSTOP */ while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3267,7 +3263,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check VSWEND Flag */ while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3375,7 +3371,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } } - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3403,7 +3399,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) *pData = SDMMC_ReadFIFO(hsd->Instance); pData++; - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3538,7 +3534,6 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) } } - /** * @brief Finds the SD card SCR register value. * @param hsd: Pointer to SD handle @@ -3593,8 +3588,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) index++; } - - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3624,11 +3618,11 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ - ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1] & SDMMC_8TO15BITS) << 8U) | \ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24U)); scr++; - *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ - ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0] & SDMMC_8TO15BITS) << 8U) | \ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24U)); } @@ -3649,10 +3643,10 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) tmp = hsd->pRxBuffPtr; - if (hsd->RxXferSize >= 32U) + if (hsd->RxXferSize >= SDMMC_FIFO_SIZE) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3666,7 +3660,7 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) } hsd->pRxBuffPtr = tmp; - hsd->RxXferSize -= 32U; + hsd->RxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3684,10 +3678,10 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) tmp = hsd->pTxBuffPtr; - if (hsd->TxXferSize >= 32U) + if (hsd->TxXferSize >= SDMMC_FIFO_SIZE) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tmp); tmp++; @@ -3701,7 +3695,7 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) } hsd->pTxBuffPtr = tmp; - hsd->TxXferSize -= 32U; + hsd->TxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3750,7 +3744,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { @@ -3768,8 +3761,7 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) } loop ++; } - - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -3885,7 +3877,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeed loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -4015,7 +4007,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -4142,12 +4134,12 @@ __weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd) */ } - /** * @} */ #endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c index 1cc19e3135..aa50d0bf39 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c @@ -44,6 +44,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -303,6 +304,7 @@ HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABu */ #endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdio.c new file mode 100644 index 0000000000..ddde94eb91 --- /dev/null +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdio.c @@ -0,0 +1,2877 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_sdio.c + * @author MCD Application Team + * @brief SDIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital Input Output (SDIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this SDIO card. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_SDIO_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with SDIO cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implementing the HAL_SDIO_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for SDIO card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) NVIC configuration if you need to use interrupt process (HAL_SDIO_ReadExtended_DMA() + and HAL_SDIO_WriteExtended_DMA() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_SDIO_ENABLE_IT() + and __HAL_SDIO_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SDIO_GET_IT(). + (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used. + + (#) At this stage, you can perform SDIO read/write/erase operations after SDIO card initialization. + + *** SDIO Card Initialization and configuration *** + ================================================ + [..] + To initialize the SDIO Card, use the HAL_SDIO_Init() function. It Initializes + SDMMC Peripheral(STM32 side) and the SDIO Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Apply the SDIO Card initialization process at 400KHz. You can change or adapt this + frequency by adjusting the "ClockDiv" field. + The SDIO Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (2 * ClockDiv) + + In initialization mode and according to the SDIO Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the SDIO card. The API used is HAL_SDIO_Init(). + This phase allows the card initialization and identification. + + (#) Configure the SDIO Card Data transfer frequency. You can change or adapt this + frequency by adjusting the "ClockDiv" field by the API HAL_SDIO_ConfigFrequency(). + + (#) Configure the SDIO Card in wide bus mode: 4-bits data by the API HAL_SDIO_SetDataBusWidth(). + + (#) Configure the SDIO Card data block size by the API : HAL_SDIO_SetBlockSize(). + + (#) Configure the SDIO Card speed mode by the API : HAL_SDIO_SetSpeedMode(). + + (#) To custumize the SDIO Init card function for the enumeration card sequence, you can register a user callback + function by calling the HAL_SDIO_RegisterIdentifyCardCallback before the HAL_SDIO_Init() function. + + *** SDIO Card Read operation *** + ============================== + [..] + (+) You can read from SDIO card in polling mode by using function HAL_SDIO_ReadExtended(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + + (+) You can read from SDIO card in DMA mode by using function HAL_SDIO_ReadExtended_DMA(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + After this, you have to ensure that the transfer is done correctly. + You could also check the DMA transfer process through the SDIO Rx interrupt event. + + *** SDIO Card Write operation *** + =============================== + [..] + (+) You can write to SDIO card in polling mode by using function HAL_SDIO_WriteExtended(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + + (+) You can write to SDIO card in DMA mode by using function HAL_SDIO_WriteExtended_DMA(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + You could also check the DMA transfer process through the SDIO Tx interrupt event. + + + *** SDIO card common control register (CCCR) *** + ====================== + [..] + (+) The SDIO CCCR allow for quick host checking and control of an IO card's enable and interrupts on a per card and + per function basis. + To get the Card common control registers field, you can use the API HAL_SDIO_GetCardCommonControlRegister(). + + *** SDIO card Function basic register (FBR) *** + =========================== + [..] + (+) The SDIO card function basic register are used to allow the host to quickly determine the abilities and + requirements of each function. + (+) To get the SDIO function basic register information, you can use the API HAL_SDIO_GetCardFBRRegister(). + + *** SDIO HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SDIO HAL driver. + + (+) __HAL_SDIO_ENABLE_IT: Enable the SDIO device interrupt + (+) __HAL_SDIO_DISABLE_IT: Disable the SDIO device interrupt + (+) __HAL_SDIO_GET_FLAG: Check whether the specified SDIO flag is set or not + (+) __HAL_SDIO_CLEAR_FLAG: Clear the SDIO's pending flags + (+) __HAL_SDIO_GET_IT: Check whether the specified SDIO interrupt has occurred or not + (+) __HAL_SDIO_GET_IT_SOURCE: Checks whether the specified SDIO interrupt is enabled or not + + (@) You can refer to the SDIO HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SDIO_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) MspInitCallback : SDIO MspInit. + (+) MspDeInitCallback : SDIO MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + For specific callbacks TransceiverCallback use dedicated register callbacks: + respectively HAL_SDIO_RegisterTransceiverCallback(). + + Use function HAL_SDIO_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) MspInitCallback : SDIO MspInit. + (+) MspDeInitCallback : SDIO MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + For specific callbacks TransceiverCallback use dedicated unregister callbacks: + respectively HAL_SDIO_UnRegisterTransceiverCallback(). + + By default, after the HAL_SDIO_Init and if the state is HAL_SDIO_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_SDIO_Init + and HAL_SDIO_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDIO_Init and HAL_SDIO_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SDIO_RegisterCallback before calling HAL_SDIO_DeInit + or HAL_SDIO_Init function. + + When The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + *** SDIO peripheral IO interrupt *** + ============================================= + [..] + (+) Below the list of most used SDIO function to check and control the IO card's enable and interrupts on a per + functions basis. + + (+) HAL_SDIO_EnableIOFunctionInterrupt: Enable SDIO IO interrupt. + (+) HAL_SDIO_DisableIOFunctionInterrupt: Disable SDIO IO interrupt. + (+) HAL_SDIO_EnableIOFunction: Enable Function number(0-7) + (+) HAL_SDIO_DisableIOFunction: Disable Function number(0-7) + (+) HAL_SDIO_SelectIOFunction: Select a function number(0-7) + (+) HAL_SDIO_AbortIOFunction: Abort an IO read or write operation and free the SDIO bus. + (+) HAL_SDIO_EnableIOAsynInterrupt: Enable Bit of asynchronous interrupt + (+) HAL_SDIO_DisableIOAsynInterrupt: Disable Bit of asynchronous interrupt + + @endverbatim + ****************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) +#ifdef HAL_SDIO_MODULE_ENABLED + +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** @addtogroup SDIO_Private_Defines + * @{ + */ +#define SDIO_INIT_FREQ 400000U /*!< Initialization phase : 400 kHz max */ +#define SDIO_TIMEOUT 1000U /*!< SDIO timeout millisecond */ + +#define SDIO_FUNCTION_0 0x00U /*!< SDIO_Functions 0 */ +#define SDIO_FUNCTION_1 0x01U /*!< SDIO_Functions 1 */ + +#define SDIO_READ 0x0U /*!< Read flag for cmd52 and cmd53 */ +#define SDIO_WRITE 0x1U /*!< Write flag for cmd52 and cmd53 */ + +#define SDIO_BUS_SPEED_SDR12 0x00U /*!< SDIO bus speed mode SDR12 */ +#define SDIO_BUS_SPEED_SDR25 0x02U /*!< SDIO bus speed mode SDR25 */ +#define SDIO_BUS_SPEED_SDR50 0x04U /*!< SDIO bus speed mode SDR50 */ +#define SDIO_BUS_SPEED_DDR50 0x08U /*!< SDIO bus speed mode DDR50 */ + +#define SDIO_CCCR_REG_NUMBER 0x16U /*!< SDIO card cccr register number */ + +#define SDIO_OCR_VDD_32_33 (1U << 20U) +#define SDIO_OCR_SDIO_S18R (1U << 24U) +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +#define IS_SDIO_RAW_FLAG(ReadAfterWrite) (((ReadAfterWrite) == HAL_SDIO_WRITE_ONLY) || \ + ((ReadAfterWrite) == HAL_SDIO_READ_AFTER_WRITE)) + +#define IS_SDIO_FUNCTION(FN) (((FN) >= HAL_SDIO_FUNCTION_1) && ((FN) <= HAL_SDIO_FUNCTION_7)) + +#define IS_SDIO_SUPPORTED_BLOCK_SIZE(BLOCKSIZE) (((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions SDIO Private Functions + * @{ + */ +static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio); +static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, + uint8_t *pData); +static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, + uint8_t *pData); +static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, + uint8_t *pData, uint16_t Size_byte); +static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size); +static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDIO_Exported_Functions + * @{ + */ +/** @addtogroup SDIO_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the SDIO + device to be ready for use. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the SDIO according to the specified parameters in the + SDIO_HandleTypeDef and create the associated handle. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) +{ + SDIO_InitTypeDef Init; + uint32_t sdmmc_clk; + uint8_t data; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hsdio->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsdio->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hsdio->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsdio->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hsdio->Init.ClockDiv)); + + /* Check the SDIO handle allocation */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_RESET) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_SDIO_STATE_RESET only */ + hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback; + hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback; + hsdio->ErrorCallback = HAL_SDIO_ErrorCallback; +#if (USE_SDIO_TRANSCEIVER != 0U) + if (hsdio->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { + hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback; + } +#endif /* USE_SDIO_TRANSCEIVER */ + + if (hsdio->MspInitCallback == NULL) + { + hsdio->MspInitCallback = HAL_SDIO_MspInit; + } + /* Init the low level hardware */ + hsdio->MspInitCallback(hsdio); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SDIO_MspInit(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + if (sdmmc_clk == 0U) + { + hsdio->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; + } + Init.ClockDiv = sdmmc_clk / (2U * SDIO_INIT_FREQ); + /* Initialize SDMMC peripheral interface with default configuration */ + (void)SDMMC_Init(hsdio->Instance, Init); + + /* Set Power State to ON */ + (void)SDMMC_PowerState_ON(hsdio->Instance); + + /* wait 74 Cycles: required power up waiting time before starting the SDIO initialization sequence */ + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + + if (hsdio->SDIO_IdentifyCard == NULL) + { + hsdio->SDIO_IdentifyCard = SDIO_InitCard; + } + /* SDIO enumeration sequence */ + if (hsdio->SDIO_IdentifyCard(hsdio) != HAL_OK) + { + hsdio->State = HAL_SDIO_STATE_RESET; + return HAL_ERROR; + } + + /* Configure the SDMMC user parameters */ + Init.ClockEdge = hsdio->Init.ClockEdge; + Init.ClockPowerSave = hsdio->Init.ClockPowerSave; + Init.BusWide = hsdio->Init.BusWide; + Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; + Init.ClockDiv = hsdio->Init.ClockDiv; + (void)SDMMC_Init(hsdio->Instance, Init); + + data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->Context = SDIO_CONTEXT_NONE; + hsdio->State = HAL_SDIO_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initializes the SDIO device. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio) +{ + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance)); + + /* Check the SDIO handle allocation */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hsdio->Instance); + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + if (hsdio->MspDeInitCallback == NULL) + { + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + } + + /* DeInit the low level hardware */ + hsdio->MspDeInitCallback(hsdio); +#else + /* De-Initialize the MSP layer */ + HAL_SDIO_MspDeInit(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the SDIO MSP. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize SDIO MSP. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_MspDeInit could be implemented in the user file + */ +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group2 + * @brief + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to re-configure the SDIO peripheral. + +@endverbatim + * @{ + */ +/** + * @brief Enables wide bus operation for the requested card if supported by card. + * @param hsdio: Pointer to SDIO handle + * @param BusWide: Specifies the SDIO card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide) +{ + uint8_t data; + HAL_StatusTypeDef error_state = HAL_OK; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + data = (BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_WIDBUS, + (BusWide == HAL_SDIO_4_WIRES_MODE) ? SDMMC_BUS_WIDE_4B : SDMMC_BUS_WIDE_1B); + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + error_state = HAL_ERROR; + } + } + else + { + error_state = HAL_ERROR; + } + + return error_state; +} + +/** + * @brief Update the SDIO Clock. + * @param hsdio: Pointer to SDIO handle. + * @param ClockSpeed: SDIO Clock speed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed) +{ + uint32_t ClockDiv; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + ClockDiv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)) / (2U * ClockSpeed); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_CLKDIV, ClockDiv); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Set the SDIO block size. + * @param hsdio: Pointer to SDIO handle + * @param function_nbr: Specifies the SDIO function number. + * @param BlockSize: Specifies the SDIO Block size to set. + * This parameter can be one of the following values @ref SDIO_Exported_Constansts_Group7. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize) +{ + HAL_SDIO_ExtendedCmd_TypeDef cmd53; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(function_nbr)); + assert_param(IS_SDIO_SUPPORTED_BLOCK_SIZE(BlockSize)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /* Set SDIO F1 block size */ + cmd53.IOFunctionNbr = SDIO_FUNCTION_0; + cmd53.OpCode = HAL_SDIO_OP_CODE_AUTO_INC; + cmd53.Block_Mode = HAL_SDIO_MODE_BYTE; + cmd53.Reg_Addr = (function_nbr * 0x100UL) + 0x10UL; + if (SDIO_WriteExtended(hsdio, &cmd53, (uint8_t *)(&BlockSize), 2U) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->block_size = BlockSize; + + return HAL_OK; +} + +/** + * @brief Configure the data rate. + * @param hsdio: Pointer to SDIO handle + * @param DataRate: Specifies the SDIO data rate to set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate) +{ + HAL_StatusTypeDef errorstate = HAL_OK; + uint8_t data; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + switch (DataRate) + { + case HAL_SDIOS_DATA_RATE_SDR25: + data = SDIO_BUS_SPEED_SDR25; + errorstate = SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR16_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + break; + + case HAL_SDIOS_DATA_RATE_SDR50: + data = SDIO_BUS_SPEED_SDR50; + errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2U) | (SDIO_FUNCTION_0 << 1U) | (SDIO_FUNCTION_0 << 14U) + | SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED, SDMMC_CLKCR_BUSSPEED); + break; + + case HAL_SDIOS_DATA_RATE_DDR50: + data = SDIO_BUS_SPEED_DDR50; + errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) | + SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED, + SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED); + break; + default: /* SDR12 */ + break; + } + + return (errorstate != HAL_OK) ? HAL_ERROR : HAL_OK; +} + +/** + * @brief Reset SDIO Card + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio) +{ + uint8_t data = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /** To reset the SDIO module by CMD52 with writing to RES in CCCR or send CMD0 the card shall change the speed mode + * default speed mode. + * The reset cmd (cmd0) is only used for memory. In order to reset an I/O card or the I/O portion of a combo card, + * Use CMD52 to write 1 to the RES bit in the CCC(bit3 of register 6). + */ + if (SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) | + SDMMC_SDIO_CCCR4_SD_BYTE2), + HAL_SDIO_WRITE_ONLY, + 0U, + &data) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->State = HAL_SDIO_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Get Card Common Control register (CCCR). + * @param hsdio: Pointer to SDIO handle. + * @param pCccr: Pointer to Cccr register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr) +{ + uint8_t tempBuffer[256] = {0U}; + uint32_t count; + + assert_param(hsdio != NULL); + assert_param(pCccr != NULL); + + if ((hsdio == NULL) || (pCccr == NULL)) + { + return HAL_ERROR; + } + + for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++) + { + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0 + count, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) != + HAL_OK) + { + return HAL_ERROR; + } + } + + pCccr->cccr_revision = tempBuffer[0] & 0x0FU; + pCccr->sdio_revision = (tempBuffer[0] & 0xF0U) >> 4U; + pCccr->sd_spec_revision = tempBuffer[0x01U] & 0x0FU; + pCccr->bus_width_8Bit = ((tempBuffer[0x07U] & 0x04U) != 0U) ? HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED + : HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED; + pCccr->card_capability = (tempBuffer[0x08U] & 0xDFUL); + /* common CIS pointer */ + pCccr->commonCISPointer = tempBuffer[0x09U] | ((uint32_t)tempBuffer[(uint32_t)0x09U + 1U] << 8U) | + ((uint32_t)tempBuffer[(uint32_t)0x09U + 2U] << 16U); + + return HAL_OK; +} + +/** + * @brief Get Card Function Basic register(FBR). + * @param hsdio: Pointer to SDIO handle. + * @param pFbr: Pointer to Fbr register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr) +{ + uint8_t tempBuffer[256] = {0U}; + uint32_t count; + uint8_t func_idx; + + assert_param(hsdio != NULL); + assert_param(pFbr != NULL); + + if ((hsdio == NULL) || (pFbr == NULL)) + { + return HAL_ERROR; + } + + for (func_idx = 2U; func_idx <= SDIO_MAX_IO_NUMBER; func_idx++) + { + for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++) + { + if (SDIO_ReadDirect(hsdio, (((uint32_t)SDMMC_SDIO_F1BR0 * (uint32_t)func_idx) + count), + HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) != HAL_OK) + { + return HAL_ERROR; + } + } + pFbr[(uint32_t)func_idx - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; + pFbr[(uint32_t)func_idx - 1U].ioExtFunctionCode = tempBuffer[1U]; + pFbr[(uint32_t)func_idx - 1U].ioPointerToCIS = tempBuffer[9U] | ((uint32_t)tempBuffer[10U] << 8U) | + ((uint32_t)tempBuffer[11U] << 16U); + pFbr[(uint32_t)func_idx - 1U].ioPointerToCSA = tempBuffer[12U] | ((uint32_t)tempBuffer[13U] << 8U) | + ((uint32_t)tempBuffer[14U] << 16U); + if ((tempBuffer[2U] & 0x01U) != 0U) + { + pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_POWER_SELECTION; + } + if ((tempBuffer[0U] & 0x40U) != 0U) + { + pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_CSA; + } + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group3 + * @brief + * +@verbatim + ============================================================================== + ##### Data management functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data transfer from/to SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief Read data from a specified address using the direct mode through cmd52. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Specifies the SDIO Argument. + * @param pData: pointer to the buffer that will contain the received data. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData) +{ + uint32_t cmd; + uint32_t errorstate; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite)); + + if ((hsdio == NULL) || (Argument == NULL) || (NULL == pData)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + cmd = SDIO_READ << 31U; + cmd |= (((uint32_t)Argument->IOFunctionNbr) << 28U); + cmd |= (((uint32_t)Argument->ReadAfterWrite) << 27U); + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= 0U; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData); + + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + + +/** + * @brief Read data from a specified address using the direct mode through cmd52. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Specifies the SDIO Argument. + * @param Data: pointer to the buffer that will contain the received data. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data) +{ + uint32_t cmd; + uint32_t errorstate; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite)); + + if ((hsdio == NULL) || (Argument == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + cmd = SDIO_WRITE << 31U; + cmd |= ((uint32_t)Argument->IOFunctionNbr) << 28U; + cmd |= ((uint32_t)Argument->ReadAfterWrite) << 27U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= Data; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &Data); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Read data from a specified address using extended mode through cmd53. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: size to read. + * @param Timeout_Ms: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint8_t *tempbuff = pData; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */ + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */ + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC ; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Correspond to the write or read bit of the CMD argument */ + /* Read */ + hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK : + SDIO_CONTEXT_READ_SINGLE_BLOCK; + cmd = SDIO_READ << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (Size_byte & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; + + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + { + /* Read data from SDMMC Rx FIFO */ + for (regCount = 0U; regCount < 8U; regCount++) + { + data = SDMMC_ReadFIFO(hsdio->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + } + dataremaining -= 32U; + } + else if (dataremaining < 32U) + { + while ((dataremaining > 0U) && !(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE))) + { + data = SDMMC_ReadFIFO(hsdio->Instance); + for (byteCount = 0U; byteCount < 4U; byteCount++) + { + if (dataremaining > 0U) + { + *tempbuff = (uint8_t)((data >> (byteCount * 8U)) & 0xFFU); + tempbuff++; + dataremaining--; + } + } + } + } + else + { + /* Nothing to do */ + } + if ((HAL_GetTick() - tickstart) >= Timeout_Ms) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + /* Get error state */ + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_RX_OVERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Write data from a specified address using extended mode through cmd53. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @param Timeout_Ms: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint8_t *u32tempbuff = pData; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Correspond to the write or read bit of the CMD argument */ + hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK; + cmd = SDIO_WRITE << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (Size_byte & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) + { + + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + { + /* Read data from SDMMC Rx FIFO */ + for (regCount = 0U; regCount < 8U; regCount++) + { + hsdio->Instance->FIFO = *u32tempbuff; + u32tempbuff++; + } + dataremaining -= 32U; + } + else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + { + uint8_t *u8buff = (uint8_t *)u32tempbuff; + while (dataremaining > 0U) + { + data = 0U; + for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++) + { + data |= ((uint32_t)(*u8buff) << (byteCount << 3U)); + u8buff++; + dataremaining--; + } + hsdio->Instance->FIFO = data; + } + } + if (((HAL_GetTick() - tickstart) >= Timeout_Ms)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + /* Get error state */ + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Read data from a specified address using extended mode through cmd53 in DMA mode. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint8_t *p_dma_buffer; + uint32_t cmd; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + p_dma_buffer = (uint8_t *)pData; + hsdio->pRxBuffPtr = (uint8_t *)pData; + hsdio->RxXferSize = Size_byte; + hsdio->next_data_addr = (uint32_t)pData; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + if (nbr_of_block != 0U) + { + hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block)); + hsdio->next_reg_addr = (Argument->Reg_Addr) | ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U) + | ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U); + hsdio->next_data_addr += (nbr_of_block * hsdio->block_size); + } + else + { + hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte : + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + if (hsdio->remaining_data != 0U) + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + hsdio->next_reg_addr += (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \ + (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE + 1U) : (Size_byte + 1U); + } + } + + /* DMA configuration (use single buffer) */ + hsdio->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsdio->Instance->IDMABASE0 = (uint32_t)p_dma_buffer; + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC ; + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Read */ + hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK : + SDIO_CONTEXT_READ_SINGLE_BLOCK) | SDIO_CONTEXT_DMA; + + cmd = SDIO_READ << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= ((nbr_of_block == 0U) ? Size_byte : nbr_of_block) & 0x1FFU; + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Enable interrupt */ + __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Write data from a specified address using extended mode through cmd53 in DMA mode. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint8_t *p_dma_buffer; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + p_dma_buffer = (uint8_t *)pData; + hsdio->pTxBuffPtr = (uint8_t *)pData; + hsdio->TxXferSize = Size_byte; + hsdio->next_data_addr = (uint32_t)pData; + + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + if (nbr_of_block != 0U) + { + hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block)); + if (hsdio->block_size <= 128U) + { + hsdio->next_reg_addr = (Argument->Reg_Addr) | + ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U) | + ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U); + } + else + { + hsdio->next_reg_addr = (nbr_of_block * hsdio->block_size) >> 1U; + } + hsdio->next_data_addr += (nbr_of_block * hsdio->block_size); + } + else + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + if (hsdio->remaining_data != 0U) + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + hsdio->next_reg_addr += ((Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \ + (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE >> 1U) : (Size_byte >> 1U)) | + (((hsdio->remaining_data > 0U) ? 0U : 1U)); + } + hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte : + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + } + + /* DMA configuration (use single buffer) */ + hsdio->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsdio->Instance->IDMABASE0 = (uint32_t)p_dma_buffer; + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK + : SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Write */ + hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? + SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK) | SDIO_CONTEXT_DMA; + cmd = SDIO_WRITE << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= ((nbr_of_block == 0U) ? ((Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte) : nbr_of_block) & 0x1FFU; + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Enable interrupt */ + __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group4 + * @brief + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set callback functions allowing to manage the data transfer from/to SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief This function handles SDIO device interrupt request. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio) +{ + HAL_SDIO_ExtendedCmd_TypeDef CMD53_desc; + HAL_StatusTypeDef errorstate; + uint32_t ctx = hsdio->Context; + uint32_t flags; + + flags = READ_REG(((SDMMC_TypeDef *)((uint32_t)(hsdio)->Instance))->STA); + + if (READ_BIT(flags, SDMMC_FLAG_SDIOIT) != 0U) + { + (void)SDIO_IOFunction_IRQHandler(hsdio); + } + + if (READ_BIT(flags, SDMMC_FLAG_DATAEND) != 0U) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_FLAG_DATAEND); + + hsdio->State = HAL_SDIO_STATE_READY; + + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | + SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF); + + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_IDMABTC); + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + if ((ctx & SDIO_CONTEXT_DMA) != 0U) + { + hsdio->Instance->DLEN = 0; + hsdio->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + hsdio->Context = SDIO_CONTEXT_NONE; + hsdio->State = HAL_SDIO_STATE_READY; + } + + if (hsdio->remaining_data != 0U) + { + CMD53_desc.Block_Mode = HAL_SDIO_MODE_BYTE; + CMD53_desc.Reg_Addr = hsdio->next_reg_addr; + CMD53_desc.IOFunctionNbr = 1; + CMD53_desc.OpCode = 1; + if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + hsdio->pRxBuffPtr = (uint8_t *)hsdio->next_data_addr; + errorstate = HAL_SDIO_ReadExtended_DMA(hsdio, &CMD53_desc, hsdio->pRxBuffPtr, hsdio->remaining_data); + } + else + { + hsdio->pTxBuffPtr = (uint8_t *)hsdio->next_data_addr; + errorstate = HAL_SDIO_WriteExtended_DMA(hsdio, &CMD53_desc, hsdio->pTxBuffPtr, hsdio->remaining_data); + } + if (errorstate != HAL_OK) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1) + hsdio->ErrorCallback(hsdio); +#else + HAL_SDIO_ErrorCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + } + else if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + hsdio->RxCpltCallback(hsdio); +#else + HAL_SDIO_RxCpltCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + hsdio->TxCpltCallback(hsdio); +#else + HAL_SDIO_TxCpltCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + } + + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR)) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1) + hsdio->ErrorCallback(hsdio); +#else + HAL_SDIO_ErrorCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hsdio: Pointer SDIO handle + * @retval None + */ +__weak void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief SDIO error callbacks + * @param hsdio: Pointer SDIO handle + * @retval None + */ +__weak void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief SDIO IO Function complete callback + * @param hsdio: Pointer SDIO handle + * @param func: SDIO IO Function + * @retval None + */ +__weak void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + UNUSED(func); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_ErrorCallback can be implemented in the user file + */ +} + +#if (USE_SDIO_TRANSCEIVER != 0U) +/** + * @brief Enable/Disable the SDIO Transceiver 1.8V Mode Callback. + * @param hsdio: Pointer SDIO handle + * @param status: Voltage Switch State + * @retval None + */ +__weak void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + UNUSED(status); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_EnableTransceiver could be implemented in the user file + */ +} +#endif /* USE_SDIO_TRANSCEIVER */ + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SDIO Callback + * To be used instead of the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDIO_TX_CPLT_CB_ID SDIO Tx Complete Callback ID + * @arg @ref HAL_SDIO_RX_CPLT_CB_ID SDIO Rx Complete Callback ID + * @arg @ref HAL_SDIO_ERROR_CB_ID SDIO Error Callback ID + * @arg @ref HAL_SDIO_MSP_INIT_CB_ID SDIO MspInit Callback ID + * @arg @ref HAL_SDIO_MSP_DEINIT_CB_ID SDIO MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID, + pSDIO_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + switch (CallbackID) + { + case HAL_SDIO_TX_CPLT_CB_ID : + hsdio->TxCpltCallback = pCallback; + break; + case HAL_SDIO_RX_CPLT_CB_ID : + hsdio->RxCpltCallback = pCallback; + break; + case HAL_SDIO_ERROR_CB_ID : + hsdio->ErrorCallback = pCallback; + break; + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = pCallback; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdio->State == HAL_SDIO_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = pCallback; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SDIO Callback + * SDIO Callback is redirected to the weak (overridden) predefined callback. + * @note The HAL_SDIO_UnRegisterCallback() may be called before HAL_SDIO_Init() in + * HAL_SDIO_STATE_RESET to register callbacks for HAL_SDIO_MSP_INIT_CB_ID + * and HAL_SDIO_MSP_DEINIT_CB_ID. + * @param hsdio : SDIO handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values @ref SDIO_Exported_Types_Group3. + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + switch (CallbackID) + { + case HAL_SDIO_TX_CPLT_CB_ID : + hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback; + break; + case HAL_SDIO_RX_CPLT_CB_ID : + hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback; + break; + case HAL_SDIO_ERROR_CB_ID : + hsdio->ErrorCallback = HAL_SDIO_ErrorCallback; + break; + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = HAL_SDIO_MspInit; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + break; + default : + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (hsdio->State == HAL_SDIO_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = HAL_SDIO_MspInit; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + break; + default : + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +/** + * @brief Register a User SDIO Transceiver Callback + * To be used instead of the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_TransceiverCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->DriveTransceiver_1_8V_Callback = pCallback; + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SDIO Transceiver Callback + * SDIO Callback is redirected to the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback; + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_SDIO_TRANSCEIVER */ + +/** + * @brief Register a User SDIO Identification Callback + * @param hsdio: Pointer to SDIO handle + * @param pCallback: pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + hsdio->SDIO_IdentifyCard = pCallback; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group5 + * @brief + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the SDIO card operations. + +@endverbatim + * @{ + */ +/** + * @brief return the SDIO state + * @param hsdio: Pointer to SDIO handle + * @retval HAL state + */ +HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio) +{ + return hsdio->State; +} + +/** + * @brief Return the SDIO error code + * @param hsdio : Pointer to a SDIO_HandleTypeDef structure that contains the configuration information. + * @retval SDIO Error Code + */ +uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio) +{ + return hsdio->ErrorCode; +} + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group6 + * @brief + * +@verbatim + ============================================================================== + ##### Peripheral IO interrupt ##### + ============================================================================== + [..] + This subsection provides a set functions allowing to enable/disable IO functions interrupt features + on the SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief Enable SDIO IO interrupt. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t intEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if ((((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U) && ((intEn & 0x01U) != 0U)) + { + return HAL_OK; + } + else + { + intEn |= (1U << (uint32_t)IOFunction) | 0x01U; + hsdio->IOInterruptNbr++; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, + &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + __HAL_SDIO_ENABLE_IT(hsdio, SDMMC_IT_SDIOIT); + + /* Enable host SDIO interrupt operations */ + __SDMMC_OPERATION_ENABLE(hsdio->Instance); + + return HAL_OK; +} + +/** + * @brief Enable SDIO IO interrupt. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t intEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already disable , do not need enable again */ + if (((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U) + { + return HAL_OK; + } + else + { + /* disable the interrupt, don't disable the interrupt master here */ + intEn &= ~(1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + if (hsdio->IOInterruptNbr > 1U) + { + hsdio->IOInterruptNbr--; + } + else + { + hsdio->IOInterruptNbr = 0U; + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_SDIOIT); + } + return HAL_OK; +} + +/** + * @brief Enable SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t ioEn = 0U; + uint8_t ioReady = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need to enable again */ + if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U) + { + return HAL_OK; + } + else + { + ioEn |= (1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioReady) != HAL_OK) + { + return HAL_ERROR; + } + /* check if IO ready */ + if ((ioReady & (1U << (uint32_t)IOFunction)) != 0U) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Disable SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t ioEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U) + { + return HAL_OK; + } + else + { + ioEn &= ~(1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Select SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR12_SD_BYTE1, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + (uint8_t *)&IOFunction) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort IO transfer. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction IO number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + (uint8_t *)&IOFunction) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Enable Assynchrone interrupt. + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) +{ + uint8_t enable_asyn_it = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it) + != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if ((enable_asyn_it & 0x02U) == 0x02U) + { + return HAL_OK; + } + else + { + enable_asyn_it |= 0x02U; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &enable_asyn_it) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable Assynchrone interrupt. + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) +{ + uint8_t enable_asyn_it = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it) + != HAL_OK) + { + return HAL_ERROR; + } + + /* if already disable , do not need disable again */ + if ((enable_asyn_it & 0x02U) == 0x00U) + { + return HAL_OK; + } + else + { + enable_asyn_it &= (uint8_t) ~(0x02U); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &enable_asyn_it) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief sdio set io IRQ handler. + * @param hsdio Pointer to SDIO handle + * @param IOFunction IO function io number. + * @param Callback io IRQ handler. + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, + HAL_SDIO_IOFunction_CallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = pCallback; + hsdio->IOFunctionMask |= (1U << (uint8_t)IOFunction); + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private function --------------------------------------------------------------------------------------------------*/ +/** @addtogroup SDIO_Private_Functions + * @{ + */ +/** + * @brief Initializes the SDIO device. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) +{ + uint32_t errorstate; + uint32_t timeout = 0U; + uint16_t sdio_rca = 1U; + uint32_t Resp4; + uint32_t nbr_of_func; + + /* Identify card operating voltage */ + errorstate = SDMMC_CmdGoIdleState(hsdio->Instance); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + /* Check the power State */ + if (SDMMC_GetPowerState(hsdio->Instance) == 0U) + { + return HAL_ERROR; + } + + /* Send CMD5 */ + errorstate = SDMMC_CmdSendOperationcondition(hsdio->Instance, 0U, &Resp4); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + nbr_of_func = ((Resp4 & 0x70000000U) >> 28U); + /* Check if Nbr of function > 0 and OCR valid */ + if (nbr_of_func > 0U) + { + /* Send CMD5 with arg= S18R, WV*/ + if (SDMMC_CmdSendOperationcondition(hsdio->Instance, (SDIO_OCR_VDD_32_33 | SDIO_OCR_SDIO_S18R), &Resp4) + != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + /* Check if IORDY = 1 and S18A = 1 */ + if ((((Resp4 & 0x80000000U) >> 31U) != 0U) && (((Resp4 & 0x1000000U) >> 24U) != 0U)) + { + /* Send CMD11 to switch 1.8V mode */ + errorstate = SDMMC_CmdVoltageSwitch(hsdio->Instance); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + } + else + { + /* S18A is not supported */ + } + } + + /** Cmd3 is sent while response is SDMMC_ERROR_ILLEGAL_CMD, due to the partial init test done before + * (sending cmd0 after the sequence cmd0/cmd3 is sent is considered illegal). + */ + do + { + errorstate = SDMMC_CmdSetRelAdd(hsdio->Instance, &sdio_rca); + timeout++; + HAL_Delay(1); + } while ((errorstate == SDMMC_ERROR_ILLEGAL_CMD) && (timeout != SDIO_TIMEOUT)); + + if ((timeout == SDIO_TIMEOUT) || (errorstate != HAL_SDIO_ERROR_NONE)) + { + return HAL_ERROR; + } + + /* Select the Card ( Sending CMD7)*/ + errorstate = SDMMC_CmdSelDesel(hsdio->Instance, (uint32_t)(((uint32_t)sdio_rca) << 16U)); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read 1 byte data. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted CMD52 structure + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, + uint32_t function_nbr, uint8_t *pData) +{ + uint32_t errorstate; + uint32_t cmd; + + cmd = SDIO_READ << 31U; + cmd |= function_nbr << 28U; + cmd |= raw << 27U; + cmd |= (addr & 0x1FFFFU) << 9U; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Write 1 byte data. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted CMD52 structure + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, + uint32_t function_nbr, uint8_t *pData) +{ + uint32_t errorstate; + uint32_t cmd; + uint8_t response; + + cmd = SDIO_WRITE << 31U; + cmd |= function_nbr << 28U; + cmd |= raw << 27U; + cmd |= (addr & 0x1FFFFU) << 9U; + cmd |= ((uint32_t) * pData & 0x000000FFU); + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &response); + + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Write multiple data with a single command. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted cmd53 structure + * @param Size_byte: block size if CMD53 defined in HAL_SDIO_MODE_BLOCK + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, + uint8_t *pData, uint16_t Size_byte) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint32_t *u32tempbuff = (uint32_t *)(uint32_t)pData; + SDMMC_TypeDef *SDMMCx; + uint32_t cmd; + uint32_t nbr_of_block; + + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (((uint32_t)Size_byte & ~((uint32_t)hsdio->block_size & 1U))) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = Size_byte; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + hsdio->Context = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK; + cmd = SDIO_WRITE << 31U; + cmd |= cmd_arg->IOFunctionNbr << 28U; + cmd |= cmd_arg->Block_Mode << 27U; + cmd |= cmd_arg->OpCode << 26U; + cmd |= (cmd_arg->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (((uint32_t)Size_byte) & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->ErrorCode |= errorstate; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + + SDMMCx = hsdio->Instance; + dataremaining = config.DataLength; + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) + { + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + { + for (regCount = 8U; regCount > 0U; regCount--) + { + SDMMCx->FIFO = *u32tempbuff; + u32tempbuff++; + } + dataremaining -= 32U; + } + else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + { + uint8_t *u8buff = (uint8_t *)u32tempbuff; + while (dataremaining > 0U) + { + data = 0U; + for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++) + { + data |= ((uint32_t)(*u8buff) << (byteCount << 3U)); + u8buff++; + dataremaining--; + } + SDMMCx->FIFO = data; + } + } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Allows to convert a block size in the according SDMMC value for configuring the SDMMC when doing a CMD53 + * @param hsdio: Pointer to the SDIO handle. + * @param block_size: block size in bytes + * @retval block size as DBLOCKSIZE[3:0] bits format + */ +static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size) +{ + UNUSED(hsdio); + + uint8_t most_bit = (uint8_t)__CLZ(__RBIT(block_size)); + /*(1 << most_bit) - 1) is the mask used for blocksize*/ + if (((uint8_t)block_size & ((1U << most_bit) - 1U)) != 0U) + { + return (uint8_t)SDMMC_DATABLOCK_SIZE_4B; + } + return most_bit << SDMMC_DCTRL_DBLOCKSIZE_Pos; +} + +/*! + * @brief SDIO card io pending interrupt handle function. + * @note This function is used to handle the pending io interrupt. + * To register a IO IRQ handler, Use HAL_SDIO_EnableIOInterrupt and HAL_SDIO_SetIOIRQHandler + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio) +{ + uint8_t count; + uint8_t pendingInt; + + if (hsdio->IOInterruptNbr == 1U) + { + if ((hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U]) != NULL) + { + (hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U])(hsdio, hsdio->IOFunctionMask - 1U); + } + } + else if ((hsdio->IOInterruptNbr > 1U) && (hsdio->IOFunctionMask != 0U)) + { + /* Get pending int firstly */ + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE1, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &pendingInt) != + HAL_OK) + { + return HAL_ERROR; + } + + if ((pendingInt != 0U) && (hsdio->IOFunctionMask != 0U)) + { + for (count = 1; count <= SDIO_MAX_IO_NUMBER; count++) + { + if (((pendingInt & (1U << count)) != 0U) && (((1U << count) & hsdio->IOFunctionMask) != 0U)) + { + if ((hsdio->SDIO_IOFunction_Callback[count - 1U]) != NULL) + { + (hsdio->SDIO_IOFunction_Callback[count - 1U])(hsdio, count); + } + } + } + } + } + else + { + /* Nothing to do */ + } + + return HAL_OK; +} +/** + * @} + */ +#endif /* HAL_SDIO_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c index 8859a08cdd..d376e44631 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c @@ -1214,7 +1214,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) * the configuration information for SDRAM module. * @retval HAL state */ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram) { return hsdram->State; } @@ -1237,6 +1237,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) */ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1259,6 +1260,7 @@ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) */ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1281,6 +1283,7 @@ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) */ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c index 4641fc2c9e..d8742f742b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c @@ -2408,7 +2408,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c index 354966a13e..6149a5f1e3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c @@ -6,6 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions * ****************************************************************************** * @attention diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c index 932eb3fb3d..e0571e0d96 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c @@ -2235,7 +2235,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if (hspi->State != HAL_SPI_STATE_READY) { __HAL_UNLOCK(hspi); @@ -2418,9 +2417,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ - (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)))) + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD) || \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + (((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ + ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))) { /* Restriction the DMA data received is not allowed in this mode */ /* Unlock the process */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c index 7cf5fb343f..fac9ba50d7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c @@ -57,7 +57,6 @@ data transfers. (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_ConfigureUnderrun() diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c index 94d93ca06d..b3ad7f7071 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c @@ -1040,6 +1040,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1062,6 +1063,7 @@ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) */ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1084,6 +1086,7 @@ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) */ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c index 0cf0c1c42f..22fafc585d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c @@ -131,7 +131,7 @@ and a pointer to the user callback function. [..] Use function HAL_SWPMI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_SWPMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: @@ -144,10 +144,10 @@ (+) MspDeInitCallback : SWPMI MspDeInit. [..] By default, after the HAL_SWPMI_Init and if the state is HAL_SWPMI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SWPMI_Init + reset to the legacy weak functions in the HAL_SWPMI_Init and HAL_SWPMI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SWPMI_Init and HAL_SWPMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -162,7 +162,7 @@ [..] When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ @@ -208,7 +208,8 @@ static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, + uint32_t Timeout); /* Exported functions --------------------------------------------------------*/ @@ -276,7 +277,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_SWPMI_MspInit(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } hswpmi->State = HAL_SWPMI_STATE_BUSY; @@ -302,7 +303,8 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /* Enable the SWPMI transceiver */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN); /* Wait on RDYF flag to activate SWPMI */ - if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK) + if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, + SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK) { status = HAL_TIMEOUT; } @@ -365,7 +367,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) hswpmi->MspDeInitCallback(hswpmi); #else HAL_SWPMI_MspDeInit(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; hswpmi->State = HAL_SWPMI_STATE_RESET; @@ -410,7 +412,7 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) /** * @brief Register a user SWPMI callback - * to be used instead of the weak predefined callback. + * To be used to override the weak predefined callback. * @param hswpmi SWPMI handle. * @param CallbackID ID of the callback to be registered. * This parameter can be one of the following values: @@ -503,7 +505,7 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, /** * @brief Unregister a user SWPMI callback. - * SWPMI callback is redirected to the weak predefined callback. + * Callback is redirected to the weak predefined callback. * @param hswpmi SWPMI handle. * @param CallbackID ID of the callback to be unregistered. * This parameter can be one of the following values: @@ -651,12 +653,13 @@ HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpm * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; - uint32_t *ptmp_data; + const uint32_t *ptmp_data; uint32_t tmp_size; if ((pData == NULL) || (Size == 0U)) @@ -713,8 +716,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pDat } } } - } - while (tmp_size != 0U); + } while (tmp_size != 0U); /* Wait on TXBEF flag to be able to start a second transfer */ if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK) @@ -789,7 +791,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; /* Disable any receiver interrupts */ - CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE); + CLEAR_BIT(hswpmi->Instance->IER, + SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE); /* Enable SWPMI peripheral if not */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); @@ -822,8 +825,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData } } } - } - while (tmp_size != 0U); + } while (tmp_size != 0U); if (status == HAL_OK) { @@ -868,7 +870,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; @@ -998,7 +1000,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; @@ -1044,7 +1046,8 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError; /* Enable the SWPMI transmit DMA stream */ - if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, + (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) { hswpmi->State = tmp_state; /* Back to previous state */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; @@ -1130,7 +1133,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError; /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, + (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) { hswpmi->State = tmp_state; /* Back to previous state */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; @@ -1271,8 +1275,8 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) */ /** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks - * @brief SWPMI IRQ handler. - * + * @brief SWPMI IRQ handler. + * @verbatim ============================================================================== ##### SWPMI IRQ handler and callbacks ##### @@ -1363,7 +1367,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1375,7 +1379,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1408,7 +1412,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1420,7 +1424,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } } @@ -1555,19 +1559,19 @@ __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi) * @param hswpmi SWPMI handle * @retval HAL state */ -HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi) +HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(const SWPMI_HandleTypeDef *hswpmi) { /* Return SWPMI handle state */ return hswpmi->State; } /** -* @brief Return the SWPMI error code. -* @param hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains + * @brief Return the SWPMI error code. + * @param hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for the specified SWPMI. -* @retval SWPMI Error Code -*/ -uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi) + * @retval SWPMI Error Code + */ +uint32_t HAL_SWPMI_GetError(const SWPMI_HandleTypeDef *hswpmi) { return hswpmi->ErrorCode; } @@ -1642,7 +1646,7 @@ static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1668,7 +1672,7 @@ static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) hswpmi->RxCpltCallback(hswpmi); #else HAL_SWPMI_RxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1759,7 +1763,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } else { @@ -1778,7 +1782,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } /* DMA Circular mode */ @@ -1788,7 +1792,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } @@ -1805,7 +1809,7 @@ static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) hswpmi->TxHalfCpltCallback(hswpmi); #else HAL_SWPMI_TxHalfCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } @@ -1841,7 +1845,7 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hswpmi->RxCpltCallback(hswpmi); #else HAL_SWPMI_RxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1857,7 +1861,7 @@ static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) hswpmi->RxHalfCpltCallback(hswpmi); #else HAL_SWPMI_RxHalfCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1879,7 +1883,7 @@ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1900,7 +1904,7 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1911,7 +1915,8 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) * @param Timeout timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, + uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c index 1020295267..c0a36edfe7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -6955,8 +6955,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -6969,16 +6967,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c index 3465d29cca..55f1c5835e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c @@ -1078,6 +1078,9 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) reception services: (+) HAL_UARTEx_RxEventCallback() + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is @@ -2425,6 +2428,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3842,7 +3867,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -4513,6 +4537,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4677,6 +4702,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c index 6e5c0b20d7..bb45995e96 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c @@ -576,7 +576,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c index 85ccef27e3..6c77f25fad 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -225,8 +225,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -238,7 +238,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -316,7 +316,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -657,11 +657,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -2910,7 +2909,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c index b1a916da86..8fa72eeaa8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c index 4eed817e5d..676b9c2eb8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c @@ -51,17 +51,17 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values (case of STM32H74x/5x devices): (++) Counter min (T[5;0] = 0x00) @100MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 40.96us + max timeout before reset: approximately 40.96µs (++) Counter max (T[5;0] = 0x3F) @100MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 335.54ms (+) Typical values (case of STM32H7Ax/Bx devices): (++) Counter min (T[5;0] = 0x00) @140MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 29.25us + max timeout before reset: approximately 29.25µs (++) Counter max (T[5;0] = 0x3F) @140MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 239.67ms (+) Typical values (case of STM32H72x/3x devices): (++) Counter min (T[5;0] = 0x00) @125MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 32.76us + max timeout before reset: approximately 32.76µs (++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 268.43ms @@ -131,7 +131,6 @@ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c index 86ef0277a2..2ecaf6ccb6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c @@ -352,7 +352,7 @@ * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c index e79d451964..c1767ab034 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c @@ -136,7 +136,7 @@ * - SUCCESS: DMA2D registers are de-initialized * - ERROR: DMA2D registers are not de-initialized */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx) { ErrorStatus status = SUCCESS; @@ -150,7 +150,6 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) /* Release reset of DMA2D clock */ LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_DMA2D); - } else { @@ -439,7 +438,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -483,7 +482,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -527,7 +526,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -571,7 +570,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c index eab7ae8ca0..fca256ff01 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c @@ -113,8 +113,6 @@ ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) return (status); } - - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c index b9fa468f1a..27aadb10e1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c @@ -61,7 +61,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -188,7 +188,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -322,7 +322,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -338,13 +338,14 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) @@ -370,7 +371,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -515,7 +516,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -548,7 +549,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -562,10 +563,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -579,7 +580,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -593,10 +594,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } @@ -700,7 +701,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -739,7 +740,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui */ - /** @defgroup FMC_LL_SDRAM * @brief SDRAM Controller functions * @@ -786,7 +786,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -849,7 +849,7 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -979,7 +979,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c index 67015f0e60..e37e28dcf2 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c @@ -101,7 +101,7 @@ * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c index 1ee8c0a112..2abc2b1d28 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c @@ -53,7 +53,7 @@ * - SUCCESS: HRTIMx registers are de-initialized * - ERROR: invalid HRTIMx instance */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx) +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx) { ErrorStatus result = SUCCESS; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c index 02981e2c45..192cc90a9c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c @@ -112,7 +112,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c index 38e7697ed6..dd39836dec 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c @@ -162,7 +162,8 @@ * @{ */ -#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) +#if defined (SDMMC1) || defined (SDMMC2) +#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) || defined (HAL_SDIO_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -248,7 +249,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx) { /* Read data from Rx FIFO */ return (SDMMCx->FIFO); @@ -335,7 +336,7 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) * - 0x02: Power UP * - 0x03: Power ON */ -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); } @@ -348,7 +349,7 @@ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) * the configuration information for the SDMMC command * @retval HAL status */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command) { uint32_t tmpreg = 0; @@ -378,7 +379,7 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef * @param SDMMCx: Pointer to SDMMC register base * @retval Command index of the last command response received */ -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx) { return (uint8_t)(SDMMCx->RESPCMD); } @@ -395,7 +396,7 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) * @arg SDMMC_RESP4: Response Register 4 * @retval The Corresponding response register value */ -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response) { uint32_t tmp; @@ -416,7 +417,7 @@ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -451,7 +452,7 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef * @param SDMMCx: Pointer to SDMMC register base * @retval Number of remaining data bytes to be transferred */ -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->DCOUNT); } @@ -461,7 +462,7 @@ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) * @param SDMMCx: Pointer to SDMMC register base * @retval Data received */ -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->FIFO); } @@ -529,6 +530,30 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) return errorstate; } +/** + * @brief Send the Data Block number command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockCount; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCK_COUNT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCK_COUNT, SDMMC_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Read Single Block command and check the response * @param SDMMCx: Pointer to SDMMC register base @@ -1231,6 +1256,78 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) return errorstate; } +/** + * @brief Execute a cmd52 to write single byte data and read single byte data if needed + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @param pData: pointer to read response if needed + * @retval SD Card error state + */ +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_RW_DIRECT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_DIRECT, pResponse); + + return errorstate; +} + +/** + * @brief Execute a cmd53 to write or read multiple data with a single command + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @retval SD Card error state + */ +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_RW_EXTENDED; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_EXTENDED, NULL); + + return errorstate; +} + +/** + * @brief Execute a cmd5 to write or read multiple data with a single command + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @retval SD Card error state + */ +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_SEN_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp4(SDMMCx, pResp); + + return errorstate; +} /** * @} */ @@ -1466,6 +1563,138 @@ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_NONE; } +/** + * @brief Checks for error conditions for R4 response. + * @param SDMMCx: Pointer to SDMMC register base + * @param pResp: pointer to response + * @retval error state + */ +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp) +{ + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + { + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + *pResp = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R5 (cmd52/cmd53) response. + * @param SDMMCx: Pointer to SDMMC register base + * @param SDIO_CMD: The sent command index + * @param pData: pointer to the read/write buffer needed for cmd52 + * @retval SDIO Card error state + */ +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData) +{ + uint32_t response_r5; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Check response received is of desired command */ + if (SDMMC_GetCommandResponse(SDMMCx) != SDIO_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + response_r5 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if ((response_r5 & SDMMC_SDIO_R5_ERRORBITS) == SDMMC_ALLZERO) + { + /* we only want 8 bit read or write data and the 8 bit response flags are masked in the data pointer */ + if (pData != NULL) + { + *pData = (uint8_t)(response_r5 & 0xFFU); + } + + return SDMMC_ERROR_NONE; + } + else if ((response_r5 & SDMMC_SDIO_R5_OUT_OF_RANGE) == SDMMC_SDIO_R5_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if ((response_r5 & SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) == SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + else if ((response_r5 & SDMMC_SDIO_R5_ILLEGAL_CMD) == SDMMC_SDIO_R5_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if ((response_r5 & SDMMC_SDIO_R5_COM_CRC_FAILED) == SDMMC_SDIO_R5_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + /** * @brief Checks for error conditions for R6 (RCA) response. * @param hsd: SD handle @@ -1635,6 +1864,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) */ #endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c index 20c2c5e1a0..50d2377d26 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c @@ -20,11 +20,11 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_ll_swpmi.h" #include "stm32h7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -46,13 +46,13 @@ #define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U)) #define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \ - || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI)) + || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI)) #define IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \ - || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI)) + || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI)) #define IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__) (((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \ - || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B)) + || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B)) /** * @} @@ -76,7 +76,7 @@ * - SUCCESS: SWPMI registers are de-initialized * - ERROR: Not applicable */ -ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) +ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx) { ErrorStatus status = SUCCESS; @@ -108,7 +108,7 @@ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) * - SUCCESS: SWPMI registers are initialized * - ERROR: SWPMI registers are not initialized */ -ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct) +ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c index ed2ca0f04a..54ff752e94 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c @@ -777,17 +777,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } } if (dma == 1U) @@ -1314,8 +1314,8 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host - * 1 : Device + * 1 : Host + * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 8d2e2ead00..a81cc7785e 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -10,7 +10,7 @@ * STM32G0: 1.4.6 * STM32G4: 1.2.5 * STM32H5: 1.4.0 - * STM32H7: 1.11.3 + * STM32H7: 1.11.5 * STM32L0: 1.10.6 * STM32L1: 1.4.5 * STM32L4: 1.13.5 From a3faf96d522a5efceb4cd526d349ead15f11b4a7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 17:09:18 +0100 Subject: [PATCH 019/141] system(H7): update STM32H7xx CMSIS Drivers to v1.10.6 Included in STM32CubeH7 FW v1.12.1 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32H7xx/Include/stm32h723xx.h | 427 +++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h725xx.h | 427 +++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h730xx.h | 427 +++++++++++------ .../ST/STM32H7xx/Include/stm32h730xxq.h | 427 +++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h733xx.h | 429 ++++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h735xx.h | 427 +++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h742xx.h | 292 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h743xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h745xg.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h745xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h747xg.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h747xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h750xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h753xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h755xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h757xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h7a3xx.h | 296 ++++++++---- .../ST/STM32H7xx/Include/stm32h7a3xxq.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h7b0xx.h | 296 ++++++++---- .../ST/STM32H7xx/Include/stm32h7b0xxq.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h7b3xx.h | 296 ++++++++---- .../ST/STM32H7xx/Include/stm32h7b3xxq.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h7xx.h | 7 +- .../ST/STM32H7xx/Include/system_stm32h7xx.h | 1 + .../Device/ST/STM32H7xx/Release_Notes.html | 77 +++- .../gcc/linker/stm32h745xg_flash_CM7.ld | 10 + .../gcc/linker/stm32h745xx_flash_CM7.ld | 10 + .../gcc/linker/stm32h747xg_flash_CM7.ld | 10 + .../gcc/linker/stm32h747xx_flash_CM7.ld | 10 + .../gcc/linker/stm32h755xx_flash_CM7.ld | 10 + .../gcc/linker/stm32h757xx_flash_CM7.ld | 10 + .../Templates/gcc/startup_stm32h723xx.s | 2 + .../Templates/gcc/startup_stm32h725xx.s | 2 + .../Templates/gcc/startup_stm32h730xx.s | 2 + .../Templates/gcc/startup_stm32h730xxq.s | 2 + .../Templates/gcc/startup_stm32h733xx.s | 2 + .../Templates/gcc/startup_stm32h735xx.s | 2 + .../Templates/gcc/startup_stm32h742xx.s | 2 + .../Templates/gcc/startup_stm32h743xx.s | 2 + .../Templates/gcc/startup_stm32h745xg.s | 2 + .../Templates/gcc/startup_stm32h745xx.s | 2 + .../Templates/gcc/startup_stm32h747xg.s | 2 + .../Templates/gcc/startup_stm32h747xx.s | 2 + .../Templates/gcc/startup_stm32h750xx.s | 2 + .../Templates/gcc/startup_stm32h753xx.s | 2 + .../Templates/gcc/startup_stm32h755xx.s | 2 + .../Templates/gcc/startup_stm32h757xx.s | 2 + .../Templates/gcc/startup_stm32h7a3xx.s | 2 + .../Templates/gcc/startup_stm32h7a3xxq.s | 2 + .../Templates/gcc/startup_stm32h7b0xx.s | 2 + .../Templates/gcc/startup_stm32h7b0xxq.s | 2 + .../Templates/gcc/startup_stm32h7b3xx.s | 2 + .../Templates/gcc/startup_stm32h7b3xxq.s | 2 + .../Source/Templates/system_stm32h7xx.c | 120 ++++- .../system_stm32h7xx_dualcore_boot_cm4_cm7.c | 120 ++++- ...stem_stm32h7xx_dualcore_bootcm4_cm7gated.c | 122 ++++- ...stem_stm32h7xx_dualcore_bootcm7_cm4gated.c | 121 ++++- .../Templates/system_stm32h7xx_singlecore.c | 122 ++++- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 59 files changed, 5674 insertions(+), 2418 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h index 4c8a9d0d37..de1ce9482f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h @@ -1321,7 +1321,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -11785,101 +11785,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -16876,7 +16973,104 @@ typedef struct #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -16904,49 +17098,12 @@ typedef struct #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) @@ -21641,7 +21798,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h index 56eb393881..c99cb32ca7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h @@ -1322,7 +1322,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -11786,101 +11786,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -16888,7 +16985,104 @@ typedef struct #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -16916,49 +17110,12 @@ typedef struct #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) @@ -21653,7 +21810,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h index 2b2cea29cf..241f231e7d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h @@ -1324,7 +1324,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -12039,101 +12039,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -17363,7 +17460,104 @@ typedef struct #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17391,49 +17585,12 @@ typedef struct #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) @@ -22128,7 +22285,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h index 01c6a27ff1..bb2b15818a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h @@ -1325,7 +1325,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -12040,101 +12040,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -17375,7 +17472,104 @@ typedef struct #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17403,49 +17597,12 @@ typedef struct #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) @@ -22140,7 +22297,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h index 218232730b..dea34817ca 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h @@ -1324,7 +1324,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -11981,7 +11981,7 @@ typedef struct #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!Release Notes for  STM32H7xx C

                Update History

                - +

                Main Changes

                  +
                • system_stm32h7xx.c template files +
                    +
                  • Fix computed frequencies returned by the HAL_RCC_GetHCLKFreq(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq() APIs.
                    • +
                  • Enable FMC clock to ensure effective write access to FMC Bank1 registers in the SystemInit() API.
                    • +
                  • +
                • STM32H723/H725/H730/H733/H735 devices header files +
                    +
                  • Align the RTC TAMPER register and bitfields naming with the terminology used in the Reference Manual (RM0468).
                    • +
                  • +
                • STM32H742/H743/H745/H747/H750/H753/H755/H757/H7A3/H7B0/H7B3 device header files +
                    +
                  • Define new RTC macros to manage specific supported Tamper features: +
                      +
                    • RTC_TAMPER2_SUPPORT to manage Tamper 2 support
                      • +
                    • RTC_TAMPMASKFLAG_SUPPORT to manage Tamper Event Masking support
                      • +
                    • RTC_TAMPNOERASE_SUPPORT to manage Backup Registers erasure upon Tamper Event support
                      • +
                    • RTC_TAMPxIE_SUPPORT to manage selective TAMPERx interrupt enable support.
                      • +
                    • +
                  • +
                +
                +
                +
                + +
                +

                Main Changes

                +
                  +
                • Update startup files to safely exit from Run* mode. +
                    +
                  • Deploy the recommended “how to exit from Run* mode†configuration sequence available within product documentation.
                    • +
                  • +
                • Update DBGMCU_APB1HFZ1_DBG_TIM24_Pos and FMC_SDCMR_MODE_2 macros with the new values.
                  • +
                • Align GPIO MODER defines with naming used in reference manual. +
                    +
                  • Rename “GPIO_MODER_MODExx†to “GPIO_MODER_MODERxxâ€.
                    • +
                  • +
                • Add alignment statements ALIGN(4) to Flash sections in gcc template linker files.
                  • +
                +
                +
                +
                + +
                +

                Main Changes

                +
                • Update the values of the sensor calibration temperatures for H742, H743, and H753 part numbers.
                • Remove the unsupported MDMA BASE channel.
                • Align CMSIS with IP spec and product reference manual by adding missing bit fields definition.
                  • @@ -47,7 +92,7 @@

                  Main Changes

                  -

                  Main Changes

                  +

                  Main Changes

                  • General updates to fix known defects and implementation enhancements
                  • Update system_stm32h7xx_*.c template files to fix typo in comment: the VTOR offset value is multiple of 0x400.
                    • @@ -58,7 +103,7 @@

                    Main Changes

                    -

                    Main Changes

                    +

                    Main Changes

                    • General updates to fix known defects and implementation enhancements
                    • Add support for ADC LDO output voltage ready bit.
                      • @@ -73,7 +118,7 @@

                      Main Changes

                      -

                      Main Changes

                      +

                      Main Changes

                      • General updates to fix known defects and implementation enhancements
                      • All source files: update disclaimer to add reference to the new license agreement.
                        • @@ -99,7 +144,7 @@

                        Main Changes

                        -

                        Main Changes

                        +

                        Main Changes

                        • Fix minor issues related to English typo in comments of registers and fields description
                        • Update STM32H7 devices header files to add GPV registers definition, base address and instance
                          • @@ -117,7 +162,7 @@

                          Main Changes

                          -

                          Main Changes

                          +

                          Main Changes

                          • Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices:
                              @@ -175,7 +220,7 @@

                              Main Changes

                              -

                              Main Changes

                              +

                              Main Changes

                              • General updates to align Bits and registers definitions with the STM32H7 reference manual
                              • Update “ErrorStatus†enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero
                                • @@ -196,7 +241,7 @@

                                Main Changes

                                -

                                Main Changes

                                +

                                Main Changes

                                • General updates to align Bit and registers definition with the STM32H7 reference manual

                                • Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices: @@ -226,7 +271,7 @@

                                  Main Changes

                                  -

                                  Main Changes

                                  +

                                  Main Changes

                                  • Add definition of “ART_TypeDef†structure: ART accelerator for Cortex-M4 available in Dual Core devices
                                  • Add definition of “ART†instance: pointer to “ART_TypeDef†structure
                                    • @@ -241,7 +286,7 @@

                                    Main Changes

                                    -

                                    Main Changes

                                    +

                                    Main Changes

                                    • General updates to align Bit and registers definition with the STM32H7 reference manual
                                    • Updates to aligned with STM32H7xx rev.V devices
                                      • @@ -305,7 +350,7 @@

                                      Main Changes

                                      -

                                      Main Changes

                                      +

                                      Main Changes

                                      • Patch Release on top of V1.3.0
                                      • Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files: @@ -318,7 +363,7 @@

                                        Main Changes

                                        -

                                        Main Changes

                                        +

                                        Main Changes

                                        • STM32H7xx include files:
                                            @@ -363,7 +408,7 @@

                                            Main Changes

                                            -

                                            Main Changes

                                            +

                                            Main Changes

                                            • Add support for stm32h750xx value line devices:
                                                @@ -376,7 +421,7 @@

                                                Main Changes

                                                -

                                                Main Changes

                                                +

                                                Main Changes

                                                • Update FDCAN bit definition
                                                • Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access
                                                  • @@ -386,7 +431,7 @@

                                                  Main Changes

                                                  -

                                                  Main Changes

                                                  +

                                                  Main Changes

                                                  • Update USB OTG bit definition
                                                  • Adjust PLL fractional computation
                                                    • @@ -396,7 +441,7 @@

                                                    Main Changes

                                                    -

                                                    Main Changes

                                                    +

                                                    Main Changes

                                                    • First official release for STM32H743xx/753xx devices
                                                    diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld index ef62d8e234..f599d60c81 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld @@ -87,34 +87,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld index a6efc45a33..2b251bd2c7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld @@ -87,34 +87,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld index ef62d8e234..f599d60c81 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld @@ -87,34 +87,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld index a6efc45a33..2b251bd2c7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld @@ -87,34 +87,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld index 176419e978..6e88dcf91a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld @@ -86,34 +86,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld index 176419e978..6e88dcf91a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld @@ -86,34 +86,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s index caca6333a8..9c653fb358 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s index 2e13d98887..662c166634 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s index dcbe73896e..85c1de7cf6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s index e21d2a22f7..194d5dde29 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s index 131288012f..55a2c133ca 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s index fe3c52b4b8..5745795c66 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s index e4c4df33b1..e25ddd4877 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s index 26eb214793..2663d53d89 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s index 5ecfcdf7e3..ef1a75d46e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s index 98cd733f50..c04b81cb9f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s index 9729c5c145..5b730883be 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s index 4c55c0598c..9374976871 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s index dc7c0fd066..0290118da9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s index 3dec8aeb21..1c9d6918a3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s index 677907814f..5fce5289f0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s index 7f03e9aa6e..81f80f0b88 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s index e7b5946074..8c9d0c70d5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s index be2331d7df..0f2dc095a8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s index 29d1f09b0a..66fda946e6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s index 7deecf0a1d..9a74c15a8e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s index 5c15c5705b..f41cf1ece1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s index 80a4252091..ebc1743429 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c index 86e678475c..197d15ceac 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c @@ -6,6 +6,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -285,12 +290,21 @@ void SystemInit (void) #endif /* USER_VECT_TAB_ADDRESS */ #else - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -301,7 +315,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -436,6 +450,98 @@ void SystemCoreClockUpdate (void) #endif /* DUAL_CORE && CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} /** * @} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c index 2d0b59ead1..8641d8bcd4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -9,6 +9,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -266,12 +271,21 @@ void SystemInit (void) #endif /* USER_VECT_TAB_ADDRESS */ #elif defined(CORE_CM7) - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -284,7 +298,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -406,6 +420,98 @@ void SystemCoreClockUpdate (void) #endif /* CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} /** * @} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c index dc86d254a9..fe008aba56 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c @@ -12,6 +12,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -258,13 +263,21 @@ void SystemInit (void) /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; } - - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -276,7 +289,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -398,6 +411,99 @@ void SystemCoreClockUpdate (void) #endif /* DUAL_CORE && CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c index f3f3406415..241e937788 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c @@ -12,6 +12,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -264,12 +269,21 @@ void SystemInit (void) #endif /* USER_VECT_TAB_ADDRESS */ #elif defined(CORE_CM7) - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -282,7 +296,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -404,6 +418,99 @@ void SystemCoreClockUpdate (void) #endif /* CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c index 6ab8cc2de9..9823d88300 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c @@ -8,6 +8,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -262,13 +267,21 @@ void SystemInit (void) tmpreg = RCC->AHB2ENR; (void) tmpreg; #endif /* DATA_IN_D2_SRAM */ - - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -277,7 +290,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -401,6 +414,99 @@ void SystemCoreClockUpdate (void) #endif } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 08c80c7f56..e7e12952c8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -10,7 +10,7 @@ * STM32G0: 1.4.4 * STM32G4: 1.2.5 * STM32H5: 1.3.1 - * STM32H7: 1.10.4 + * STM32H7: 1.10.6 * STM32L0: 1.9.3 * STM32L1: 2.3.3 * STM32L4: 1.7.4 From 361fdbab894dc28a7429368a77d44f5107d42bf1 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 17:09:21 +0100 Subject: [PATCH 020/141] core(H7): update wrapped files Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c index 2a9e696c39..c07176b297 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32U5xx +#ifdef STM32H7xx + #include "stm32h7xx_hal_sdio.c" +#elif STM32U5xx #include "stm32u5xx_hal_sdio.c" #endif #pragma GCC diagnostic pop From cc79807898976d8d574116a1a0ccebc292cfd633 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Dec 2024 14:32:08 +0100 Subject: [PATCH 021/141] system(h7): update STM32H7xx hal default config Signed-off-by: Frederic Pillon --- system/STM32H7xx/stm32h7xx_hal_conf_default.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/system/STM32H7xx/stm32h7xx_hal_conf_default.h b/system/STM32H7xx/stm32h7xx_hal_conf_default.h index 0df8a95db6..5dc9afa366 100644 --- a/system/STM32H7xx/stm32h7xx_hal_conf_default.h +++ b/system/STM32H7xx/stm32h7xx_hal_conf_default.h @@ -88,6 +88,7 @@ extern "C" { #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED +#define HAL_SDIO_MODULE_ENABLED #define HAL_SDRAM_MODULE_ENABLED #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED @@ -148,8 +149,8 @@ extern "C" { #if !defined (LSI_VALUE) #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz -The real value may vary depending on the variations -in voltage and temperature.*/ + The real value may vary depending on the variations + in voltage and temperature.*/ /** * @brief External clock source for I2S peripheral @@ -157,7 +158,7 @@ in voltage and temperature.*/ * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE 12288000L /*!< Value of the External clock in Hz*/ +#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -185,7 +186,12 @@ in voltage and temperature.*/ #if !defined (USE_FLASH_ECC) #define USE_FLASH_ECC 0U /*!< use ECC error management in FLASH */ #endif - +#if !defined (USE_SDIO_TRANSCEIVER) +#define USE_SDIO_TRANSCEIVER 0U +#endif +#if !defined (SDIO_MAX_IO_NUMBER) +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ +#endif #if !defined(USE_HAL_ADC_REGISTER_CALLBACKS) #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ @@ -551,6 +557,10 @@ in voltage and temperature.*/ #include "stm32h7xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32h7xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32h7xx_hal_sdram.h" #endif /* HAL_SDRAM_MODULE_ENABLED */ From 6a68ecb5892d918e66970c960f003e21914ff520 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Dec 2024 14:50:40 +0100 Subject: [PATCH 022/141] system(h7): update STM32H7xx system Signed-off-by: Frederic Pillon --- system/STM32H7xx/system_stm32h7xx.c | 119 ++++++++++++++++++++++++++-- 1 file changed, 113 insertions(+), 6 deletions(-) diff --git a/system/STM32H7xx/system_stm32h7xx.c b/system/STM32H7xx/system_stm32h7xx.c index 950ff938a7..dca15c1b7e 100644 --- a/system/STM32H7xx/system_stm32h7xx.c +++ b/system/STM32H7xx/system_stm32h7xx.c @@ -6,6 +6,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -265,12 +270,21 @@ void SystemInit (void) #endif /* DATA_IN_D2_SRAM */ #if !defined(DUAL_CORE) || defined(CORE_CM7) - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; +if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } #endif /* !DUAL_CORE || CORE_CM7 */ /* Configure the Vector Table location add offset address for cortex-M7 or for cortex-M4 ------------------*/ @@ -413,6 +427,99 @@ void SystemCoreClockUpdate (void) } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ From 574f1f6d1bbd646a4d56002102ff26e52b525585 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 16:42:57 +0100 Subject: [PATCH 023/141] system(h7): define system Power Supply Used by exit Run* mode to configure the system Power Supply Signed-off-by: Frederic Pillon --- .../H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h | 2 ++ .../variant_DAISY_PATCH_SM.h | 2 ++ .../variant_DAISY_PETAL_SM.h | 2 ++ .../variant_DAISY_SEED.h | 2 ++ .../variant_DevEBoxH7xx.h | 2 ++ .../variant_WeActMiniH7xx.h | 2 ++ .../variant_STM32H747I_DISCO.h | 1 + .../variant_NUCLEO_H743ZI.h | 2 ++ .../variant_NUCLEO_H753ZI.h | 2 ++ 9 files changed, 17 insertions(+) diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h index 7105d7b416..75bbacbc3d 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h @@ -269,6 +269,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h index 446c9c7fad..fe99fca2fa 100644 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h +++ b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h @@ -257,6 +257,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h index f506c369dc..8408c25f95 100644 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h +++ b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h @@ -145,6 +145,8 @@ #define HAL_DAC_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h index fdfeddaf0a..37ba4323d0 100644 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h +++ b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h @@ -140,6 +140,8 @@ #define HAL_DAC_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.h b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.h index 19efcedec2..10430f322d 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.h +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.h @@ -243,6 +243,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.h b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.h index cdb8fa423d..a74c67cdd7 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.h +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.h @@ -242,6 +242,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h index 43c21a3f4e..da40f465bf 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h @@ -326,6 +326,7 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_DIRECT_SMPS_SUPPLY /*---------------------------------------------------------------------------- * Arduino objects - C++ only diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H743ZI.h b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H743ZI.h index 6813eb16fc..90896259cd 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H743ZI.h +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H743ZI.h @@ -382,6 +382,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h index bb4424b7ec..d6b999ed68 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h @@ -254,6 +254,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ From 27ae59c1a6f152352bbd7b729eb645c4d6a64a8e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 19 Dec 2024 16:54:12 +0100 Subject: [PATCH 024/141] doc(iwatchdog): update with new GitHub alerts formatting Signed-off-by: Frederic Pillon --- libraries/IWatchdog/README.md | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/libraries/IWatchdog/README.md b/libraries/IWatchdog/README.md index 65bd3cf887..c316bc64fe 100644 --- a/libraries/IWatchdog/README.md +++ b/libraries/IWatchdog/README.md @@ -53,14 +53,14 @@ IWatchdogClass IWatchdog = IWatchdogClass(); #### Predefined values - * Minimal timeout in microseconds: `IWDG_TIMEOUT_MIN` - * Maximal timeout in microseconds: `IWDG_TIMEOUT_MAX` + * Minimal timeout in **microseconds**: `IWDG_TIMEOUT_MIN` + * Maximal timeout in **microseconds**: `IWDG_TIMEOUT_MAX` #### `void begin(uint32_t timeout, uint32_t window = IWDG_TIMEOUT_MAX)` The `begin()` function would initialize the IWDG hardware block. -The `timeout` parameter is in microseconds and set the timer reset timeout. +The `timeout` parameter is in **microseconds** and set the timer reset timeout. When the timer reaches zero the hardware block would generate a reset signal for the CPU. @@ -84,22 +84,22 @@ Valid timeout values depends of the LSI clock. Typically, it is 32kH value are b | 8193ms - 16384ms | 4ms | 16385ms - 32768ms | 8ms -The optional `window` parameter is in microseconds and must be less than `timeout`. +The optional `window` parameter is in **microseconds and must be less than `timeout`**. If the window option is enabled, the counter must be refreshed inside the window; otherwise, a system reset is generated. -**Note:** -Window feature is not available for all STM32 series. +> [!NOTE] +> Window feature is not available for all STM32 series. Calling the `begin()` method with value outside of the valid range would return without initializing the watchdog timer. -**WARNING:** -*Once started the IWDG timer can not be stopped. If you are -planning to debug the live system, the watchdog timer may cause the -system to be reset while you are stopped in the debugger. Also consider -the iwatchdog timer implications if you are designing a system which puts -the CPU in sleep mode.* +> [!WARNING] +> Once started the IWDG timer can not be stopped. If you are +> planning to debug the live system, the watchdog timer may cause the +> system to be reset while you are stopped in the debugger. Also consider +> the iwatchdog timer implications if you are designing a system which puts +> the CPU in sleep mode.* #### `void reload()` @@ -119,7 +119,7 @@ The `timeout` and optional `window` parameters are the same than `begin()` metho The `get()` method allows to get the current timeout and window values currently set. -The `timeout` and optional `window` pointers to get values are in microseconds. +The `timeout` and optional `window` pointers to get values are in **microseconds**. #### `bool isEnabled()` From c82f8619f2b1a9d7bd23a0bdc96c48a1a6451a0d Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sat, 20 Jul 2024 16:16:01 +0300 Subject: [PATCH 025/141] variant(g4): register Generic G474CEUx board * UFQFN48 (U) boards were missing from selection, only LQFP48 were available (T) * Copy missing linkerscript from G474CET * Copy missing SystemClock_Config and readjust for HSI16 into PLL150 and HSI48 CRS (for USB FS Device) --- README.md | 12 +- boards.txt | 72 +++++++ .../generic_clock.c | 61 +++++- .../ldscript.ld | 185 ++++++++++++++++++ 4 files changed, 324 insertions(+), 6 deletions(-) create mode 100644 variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/ldscript.ld diff --git a/README.md b/README.md index dbf9d0ed10..f96d5bcae5 100644 --- a/README.md +++ b/README.md @@ -509,25 +509,29 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32G471QC
                                                    STM32G471QE | Generic Board | *2.4.0* | | | :green_heart: | STM32G471RC
                                                    STM32G471RE | Generic Board | *2.4.0* | | | :green_heart: | STM32G471VC
                                                    STM32G471VE | Generic Board | *2.4.0* | | -| :green_heart: | STM32G473CB
                                                    STM32G473CC
                                                    STM32G473CE | Generic Board | *2.4.0* | | +| :green_heart: | STM32G473CBT
                                                    STM32G473CCT
                                                    STM32G473CET | Generic Board | *2.4.0* | | +| :yellow_heart: | STM32G473CBU
                                                    STM32G473CCU
                                                    STM32G473CEU | Generic Board | **2.10.0** | | | :green_heart: | STM32G473MB
                                                    STM32G473MC
                                                    STM32G473ME | Generic Board | *2.4.0* | | | :green_heart: | STM32G473PB
                                                    STM32G473PC
                                                    STM32G473PE | Generic Board | *2.4.0* | | | :green_heart: | STM32G473QB
                                                    STM32G473QC
                                                    STM32G473QE | Generic Board | *2.4.0* | | | :green_heart: | STM32G473RB
                                                    STM32G473RC
                                                    STM32G473RE | Generic Board | *2.0.0* | | | :green_heart: | STM32G473VB
                                                    STM32G473VC
                                                    STM32G473VE | Generic Board | *2.4.0* | | -| :green_heart: | STM32G474CB
                                                    STM32G474CC
                                                    STM32G474CE | Generic Board | *2.4.0* | | +| :green_heart: | STM32G474CBT
                                                    STM32G474CCT
                                                    STM32G474CET | Generic Board | *2.4.0* | | +| :yellow_heart: | STM32G474CBU
                                                    STM32G474CCU
                                                    STM32G474CEU | Generic Board | **2.10.0** | | | :green_heart: | STM32G474MB
                                                    STM32G474MC
                                                    STM32G474ME | Generic Board | *2.4.0* | | | :green_heart: | STM32G474PB
                                                    STM32G474PC
                                                    STM32G474PE | Generic Board | *2.4.0* | | | :green_heart: | STM32G474QB
                                                    STM32G474QC
                                                    STM32G474QE | Generic Board | *2.4.0* | | | :green_heart: | STM32G474RB
                                                    STM32G474RC
                                                    STM32G474RE | Generic Board | *2.0.0* | | | :green_heart: | STM32G474VB
                                                    STM32G474VC
                                                    STM32G474VE | Generic Board | *2.4.0* | | -| :green_heart: | STM32G483CE | Generic Board | *2.4.0* | | +| :green_heart: | STM32G483CET | Generic Board | *2.4.0* | | +| :yellow_heart: | STM32G483CEU | Generic Board | **2.10.0** | | | :green_heart: | STM32G483ME | Generic Board | *2.4.0* | | | :green_heart: | STM32G483PE | Generic Board | *2.4.0* | | | :green_heart: | STM32G483QE | Generic Board | *2.4.0* | | | :green_heart: | STM32G483RE | Generic Board | *2.0.0* | | | :green_heart: | STM32G483VE | Generic Board | *2.4.0* | | -| :green_heart: | STM32G484CE | Generic Board | *2.4.0* | | +| :green_heart: | STM32G484CET | Generic Board | *2.4.0* | | +| :yellow_heart: | STM32G484CEU | Generic Board | **2.10.0** | | | :green_heart: | STM32G484ME | Generic Board | *2.4.0* | | | :green_heart: | STM32G484PE | Generic Board | *2.4.0* | | | :green_heart: | STM32G484QE | Generic Board | *2.4.0* | | diff --git a/boards.txt b/boards.txt index 07fc51e3ad..c1155a00ef 100644 --- a/boards.txt +++ b/boards.txt @@ -7885,6 +7885,15 @@ GenG4.menu.pnum.GENERIC_G473CBTX.build.product_line=STM32G473xx GenG4.menu.pnum.GENERIC_G473CBTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET GenG4.menu.pnum.GENERIC_G473CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd +# Generic G473CBUx +GenG4.menu.pnum.GENERIC_G473CBUX=Generic G473CBUx +GenG4.menu.pnum.GENERIC_G473CBUX.upload.maximum_size=131072 +GenG4.menu.pnum.GENERIC_G473CBUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G473CBUX.build.board=GENERIC_G473CBUX +GenG4.menu.pnum.GENERIC_G473CBUX.build.product_line=STM32G473xx +GenG4.menu.pnum.GENERIC_G473CBUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.GENERIC_G473CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd + # Generic G473CCTx GenG4.menu.pnum.GENERIC_G473CCTX=Generic G473CCTx GenG4.menu.pnum.GENERIC_G473CCTX.upload.maximum_size=262144 @@ -7894,6 +7903,15 @@ GenG4.menu.pnum.GENERIC_G473CCTX.build.product_line=STM32G473xx GenG4.menu.pnum.GENERIC_G473CCTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET GenG4.menu.pnum.GENERIC_G473CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd +# Generic G473CCUx +GenG4.menu.pnum.GENERIC_G473CCUX=Generic G473CCUx +GenG4.menu.pnum.GENERIC_G473CCUX.upload.maximum_size=262144 +GenG4.menu.pnum.GENERIC_G473CCUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G473CCUX.build.board=GENERIC_G473CCUX +GenG4.menu.pnum.GENERIC_G473CCUX.build.product_line=STM32G473xx +GenG4.menu.pnum.GENERIC_G473CCUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.GENERIC_G473CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd + # Generic G473CETx GenG4.menu.pnum.GENERIC_G473CETX=Generic G473CETx GenG4.menu.pnum.GENERIC_G473CETX.upload.maximum_size=524288 @@ -7903,6 +7921,15 @@ GenG4.menu.pnum.GENERIC_G473CETX.build.product_line=STM32G473xx GenG4.menu.pnum.GENERIC_G473CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET GenG4.menu.pnum.GENERIC_G473CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd +# Generic G473CEUx +GenG4.menu.pnum.GENERIC_G473CEUX=Generic G473CEUx +GenG4.menu.pnum.GENERIC_G473CEUX.upload.maximum_size=524288 +GenG4.menu.pnum.GENERIC_G473CEUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G473CEUX.build.board=GENERIC_G473CEUX +GenG4.menu.pnum.GENERIC_G473CEUX.build.product_line=STM32G473xx +GenG4.menu.pnum.GENERIC_G473CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.GENERIC_G473CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd + # Generic G473MBTx GenG4.menu.pnum.GENERIC_G473MBTX=Generic G473MBTx GenG4.menu.pnum.GENERIC_G473MBTX.upload.maximum_size=131072 @@ -8083,6 +8110,15 @@ GenG4.menu.pnum.GENERIC_G474CBTX.build.product_line=STM32G474xx GenG4.menu.pnum.GENERIC_G474CBTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET GenG4.menu.pnum.GENERIC_G474CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd +# Generic G474CBUx +GenG4.menu.pnum.GENERIC_G474CBUX=Generic G474CBUx +GenG4.menu.pnum.GENERIC_G474CBUX.upload.maximum_size=131072 +GenG4.menu.pnum.GENERIC_G474CBUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G474CBUX.build.board=GENERIC_G474CBUX +GenG4.menu.pnum.GENERIC_G474CBUX.build.product_line=STM32G474xx +GenG4.menu.pnum.GENERIC_G474CBUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.GENERIC_G474CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd + # Generic G474CCTx GenG4.menu.pnum.GENERIC_G474CCTX=Generic G474CCTx GenG4.menu.pnum.GENERIC_G474CCTX.upload.maximum_size=262144 @@ -8092,6 +8128,15 @@ GenG4.menu.pnum.GENERIC_G474CCTX.build.product_line=STM32G474xx GenG4.menu.pnum.GENERIC_G474CCTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET GenG4.menu.pnum.GENERIC_G474CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd +# Generic G474CCUx +GenG4.menu.pnum.GENERIC_G474CCUX=Generic G474CCUx +GenG4.menu.pnum.GENERIC_G474CCUX.upload.maximum_size=262144 +GenG4.menu.pnum.GENERIC_G474CCUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G474CCUX.build.board=GENERIC_G474CCUX +GenG4.menu.pnum.GENERIC_G474CCUX.build.product_line=STM32G474xx +GenG4.menu.pnum.GENERIC_G474CCUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.GENERIC_G474CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd + # Generic G474CETx GenG4.menu.pnum.GENERIC_G474CETX=Generic G474CETx GenG4.menu.pnum.GENERIC_G474CETX.upload.maximum_size=524288 @@ -8101,6 +8146,15 @@ GenG4.menu.pnum.GENERIC_G474CETX.build.product_line=STM32G474xx GenG4.menu.pnum.GENERIC_G474CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET GenG4.menu.pnum.GENERIC_G474CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd +# Generic G474CEUx +GenG4.menu.pnum.GENERIC_G474CEUX=Generic G474CEUx +GenG4.menu.pnum.GENERIC_G474CEUX.upload.maximum_size=524288 +GenG4.menu.pnum.GENERIC_G474CEUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G474CEUX.build.board=GENERIC_G474CEUX +GenG4.menu.pnum.GENERIC_G474CEUX.build.product_line=STM32G474xx +GenG4.menu.pnum.GENERIC_G474CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.GENERIC_G474CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd + # Generic G474MBTx GenG4.menu.pnum.GENERIC_G474MBTX=Generic G474MBTx GenG4.menu.pnum.GENERIC_G474MBTX.upload.maximum_size=131072 @@ -8281,6 +8335,15 @@ GenG4.menu.pnum.GENERIC_G483CETX.build.product_line=STM32G483xx GenG4.menu.pnum.GENERIC_G483CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET GenG4.menu.pnum.GENERIC_G483CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G483.svd +# Generic G483CEUx +GenG4.menu.pnum.GENERIC_G483CEUX=Generic G483CEUx +GenG4.menu.pnum.GENERIC_G483CEUX.upload.maximum_size=524288 +GenG4.menu.pnum.GENERIC_G483CEUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G483CEUX.build.board=GENERIC_G483CEUX +GenG4.menu.pnum.GENERIC_G483CEUX.build.product_line=STM32G483xx +GenG4.menu.pnum.GENERIC_G483CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.GENERIC_G483CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G483.svd + # Generic G483METx GenG4.menu.pnum.GENERIC_G483METX=Generic G483METx GenG4.menu.pnum.GENERIC_G483METX.upload.maximum_size=524288 @@ -8344,6 +8407,15 @@ GenG4.menu.pnum.GENERIC_G484CETX.build.product_line=STM32G484xx GenG4.menu.pnum.GENERIC_G484CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET GenG4.menu.pnum.GENERIC_G484CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G484.svd +# Generic G484CEUx +GenG4.menu.pnum.GENERIC_G484CEUX=Generic G484CEUx +GenG4.menu.pnum.GENERIC_G484CEUX.upload.maximum_size=524288 +GenG4.menu.pnum.GENERIC_G484CEUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G484CEUX.build.board=GENERIC_G484CEUX +GenG4.menu.pnum.GENERIC_G484CEUX.build.product_line=STM32G484xx +GenG4.menu.pnum.GENERIC_G484CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.GENERIC_G484CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G484.svd + # Generic G484METx GenG4.menu.pnum.GENERIC_G484METX=Generic G484METx GenG4.menu.pnum.GENERIC_G484METX.upload.maximum_size=524288 diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/generic_clock.c b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/generic_clock.c index fd8ce7402c..b58fe5f220 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/generic_clock.c +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/generic_clock.c @@ -23,8 +23,65 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; +#ifdef USBCON + RCC_CRSInitTypeDef pInit = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; +#endif + + /* Configure the main internal regulator output voltage */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Initializes the RCC Oscillators */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; + RCC_OscInitStruct.PLL.PLLN = 75; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } + +#ifdef USBCON + /* Enable the SYSCFG APB clock */ + __HAL_RCC_CRS_CLK_ENABLE(); + + /* Configures CRS */ + pInit.Prescaler = RCC_CRS_SYNC_DIV1; + pInit.Source = RCC_CRS_SYNC_SOURCE_USB; + pInit.Polarity = RCC_CRS_SYNC_POLARITY_RISING; + pInit.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); + pInit.ErrorLimitValue = 34; + pInit.HSI48CalibrationValue = 32; + + HAL_RCCEx_CRSConfig(&pInit); + + /* Initializes the peripherals clocks */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } +#endif } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/ldscript.ld b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/ldscript.ld new file mode 100644 index 0000000000..9ec558bba2 --- /dev/null +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/ldscript.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32G473CBUx Device from STM32G4 series +** 128Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From f34894a1fe7008812c6ea296782c33fc1af4b420 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Wed, 25 Dec 2024 19:29:39 +0300 Subject: [PATCH 026/141] variant(g4): add WeAct G474CEU support --- README.md | 1 + boards.txt | 10 + .../variant_WEACT_G474CE.cpp | 149 ++++++++++++ .../variant_WEACT_G474CE.h | 213 ++++++++++++++++++ 4 files changed, 373 insertions(+) create mode 100644 variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp create mode 100644 variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h diff --git a/README.md b/README.md index f96d5bcae5..85af2dd6a6 100644 --- a/README.md +++ b/README.md @@ -492,6 +492,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | +| :yellow_heart: | STM32G474CEU | WeAct G474CE | **2.10.0** | [More info](https://github.com/WeActStudio/WeActStudio.STM32G474CoreBoard) | | :green_heart: | STM32G431C6
                                                    STM32G431C8
                                                    STM32G431CB | Generic Board | *2.4.0* | | | :green_heart: | STM32G431C6U
                                                    STM32G431C8U
                                                    STM32G431CBU | Generic Board | *2.0.0* | | | :green_heart: | STM32G431M6
                                                    STM32G431M8
                                                    STM32G431MB | Generic Board | *2.4.0* | | diff --git a/boards.txt b/boards.txt index c1155a00ef..08b4d3fa7e 100644 --- a/boards.txt +++ b/boards.txt @@ -7453,6 +7453,16 @@ GenG4.openocd.target=stm32g4x GenG4.vid.0=0x0483 GenG4.pid.0=0x5740 +# WEACT_G474CE board +GenG4.menu.pnum.WEACT_G474CE=WeAct G474CE +GenG4.menu.pnum.WEACT_G474CE.upload.maximum_size=524288 +GenG4.menu.pnum.WEACT_G474CE.upload.maximum_data_size=131072 +GenG4.menu.pnum.WEACT_G474CE.build.board=WEACT_G474CE +GenG4.menu.pnum.WEACT_G474CE.build.product_line=STM32G474xx +GenG4.menu.pnum.WEACT_G474CE.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU +GenG4.menu.pnum.WEACT_G474CE.build.variant_h=variant_{build.board}.h +GenG4.menu.pnum.WEACT_G474CE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd + # Generic G431C6Tx GenG4.menu.pnum.GENERIC_G431C6TX=Generic G431C6Tx GenG4.menu.pnum.GENERIC_G431C6TX.upload.maximum_size=32768 diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp new file mode 100644 index 0000000000..7f77b7eee5 --- /dev/null +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp @@ -0,0 +1,149 @@ +/* + ******************************************************************************* + * Copyright (c) 2024, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_WEACT_G474CE) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9/A9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13/SWDIO + PA_14, // D14/SWCLK + PA_15, // D15 + PB_0, // D16/A10 + PB_1, // D17/A11 + PB_2, // D18/A12 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27/A13 + PB_12, // D28/A14 + PB_13, // D29/A15 + PB_14, // D30/A16 + PB_15, // D31/A17 + PC_4, // D32/A18 + PC_6, // D33/LED + PC_10, // D34 + PC_11, // D35 + PC_13, // D36/BTN + PC_14, // D37 + PC_15, // D38 + PF_0, // D39/A19 + PF_1, // D40/A20 + PG_10 // D41 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 9, // A9, PA9 + 16, // A10, PB0 + 17, // A11, PB1 + 18, // A12, PB2 + 27, // A13, PB11 + 28, // A14, PB12 + 29, // A15, PB13 + 30, // A16, PB14 + 31, // A17, PB15 + 32, // A18, PC4 + 39, // A19, PF0 + 40 // A20, PF1 +}; + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** + * @brief System Clock Configuration + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; +#ifdef USBCON + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; +#endif + + /* Configure the main internal regulator output voltage */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLN = 85; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV6; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } + +#ifdef USBCON + /* Initializes the peripherals clocks */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } +#endif +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* ARDUINO_NUCLEO_G431RB */ diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h new file mode 100644 index 0000000000..2d66c2ab32 --- /dev/null +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h @@ -0,0 +1,213 @@ +/* + ******************************************************************************* + * Copyright (c) 2024, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 PIN_A9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A10 +#define PB1 PIN_A11 +#define PB2 PIN_A12 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 PIN_A13 +#define PB12 PIN_A14 +#define PB13 PIN_A15 +#define PB14 PIN_A16 +#define PB15 PIN_A17 +#define PC4 PIN_A18 +#define PC6 33 // LED +#define PC10 34 +#define PC11 35 +#define PC13 36 // BTN +#define PC14 37 +#define PC15 38 +#define PF0 PIN_A19 +#define PF1 PIN_A20 +#define PG10 41 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA11_ALT2 (PA11 | ALT2) +#define PA12_ALT1 (PA12 | ALT1) +#define PA12_ALT2 (PA12 | ALT2) +#define PA13_ALT1 (PA13 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB8_ALT2 (PB8 | ALT2) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB9_ALT3 (PB9 | ALT3) +#define PB11_ALT1 (PB11 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC13_ALT1 (PC13 | ALT1) + +#define NUM_DIGITAL_PINS 42 +#define NUM_ANALOG_INPUTS 21 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PC6 +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA8 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 2 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_QSPI_MODULE_DISABLED) + #define HAL_QSPI_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial2 + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial2 + #endif +#endif From 59ed28d246e6299e906d43f6ebe7170000227ed0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jan 2025 17:27:29 +0100 Subject: [PATCH 027/141] chore(cmake): update with new G4 boards Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 738 ++++++++++++++++++ .../CMakeLists.txt | 1 + 2 files changed, 739 insertions(+) diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 5a7465fbc5..06cfe9a4a8 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -66880,6 +66880,88 @@ target_compile_options(GENERIC_G473CBTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G473CBUX +# ----------------------------------------------------------------------------- + +set(GENERIC_G473CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(GENERIC_G473CBUX_MAXSIZE 131072) +set(GENERIC_G473CBUX_MAXDATASIZE 131072) +set(GENERIC_G473CBUX_MCU cortex-m4) +set(GENERIC_G473CBUX_FPCONF "-") +add_library(GENERIC_G473CBUX INTERFACE) +target_compile_options(GENERIC_G473CBUX INTERFACE + "SHELL:-DSTM32G473xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473CBUX_MCU} +) +target_compile_definitions(GENERIC_G473CBUX INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G473CBUX" + "BOARD_NAME=\"GENERIC_G473CBUX\"" + "BOARD_ID=GENERIC_G473CBUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G473CBUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G473CBUX_VARIANT_PATH} +) + +target_link_options(GENERIC_G473CBUX INTERFACE + "LINKER:--default-script=${GENERIC_G473CBUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473CBUX_MCU} +) + +add_library(GENERIC_G473CBUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_G473CBUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CBUX_serial_generic INTERFACE) +target_compile_options(GENERIC_G473CBUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G473CBUX_serial_none INTERFACE) +target_compile_options(GENERIC_G473CBUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G473CBUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_G473CBUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G473CBUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G473CBUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G473CBUX_usb_HID INTERFACE) +target_compile_options(GENERIC_G473CBUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G473CBUX_usb_none INTERFACE) +target_compile_options(GENERIC_G473CBUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CBUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_G473CBUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CBUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_G473CBUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G473CBUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G473CBUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G473CCTX # ----------------------------------------------------------------------------- @@ -66962,6 +67044,88 @@ target_compile_options(GENERIC_G473CCTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G473CCUX +# ----------------------------------------------------------------------------- + +set(GENERIC_G473CCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(GENERIC_G473CCUX_MAXSIZE 262144) +set(GENERIC_G473CCUX_MAXDATASIZE 131072) +set(GENERIC_G473CCUX_MCU cortex-m4) +set(GENERIC_G473CCUX_FPCONF "-") +add_library(GENERIC_G473CCUX INTERFACE) +target_compile_options(GENERIC_G473CCUX INTERFACE + "SHELL:-DSTM32G473xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473CCUX_MCU} +) +target_compile_definitions(GENERIC_G473CCUX INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G473CCUX" + "BOARD_NAME=\"GENERIC_G473CCUX\"" + "BOARD_ID=GENERIC_G473CCUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G473CCUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G473CCUX_VARIANT_PATH} +) + +target_link_options(GENERIC_G473CCUX INTERFACE + "LINKER:--default-script=${GENERIC_G473CCUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473CCUX_MCU} +) + +add_library(GENERIC_G473CCUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_G473CCUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CCUX_serial_generic INTERFACE) +target_compile_options(GENERIC_G473CCUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G473CCUX_serial_none INTERFACE) +target_compile_options(GENERIC_G473CCUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G473CCUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_G473CCUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G473CCUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G473CCUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G473CCUX_usb_HID INTERFACE) +target_compile_options(GENERIC_G473CCUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G473CCUX_usb_none INTERFACE) +target_compile_options(GENERIC_G473CCUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CCUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_G473CCUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CCUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_G473CCUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G473CCUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G473CCUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G473CETX # ----------------------------------------------------------------------------- @@ -67044,6 +67208,88 @@ target_compile_options(GENERIC_G473CETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G473CEUX +# ----------------------------------------------------------------------------- + +set(GENERIC_G473CEUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(GENERIC_G473CEUX_MAXSIZE 524288) +set(GENERIC_G473CEUX_MAXDATASIZE 131072) +set(GENERIC_G473CEUX_MCU cortex-m4) +set(GENERIC_G473CEUX_FPCONF "-") +add_library(GENERIC_G473CEUX INTERFACE) +target_compile_options(GENERIC_G473CEUX INTERFACE + "SHELL:-DSTM32G473xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473CEUX_MCU} +) +target_compile_definitions(GENERIC_G473CEUX INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G473CEUX" + "BOARD_NAME=\"GENERIC_G473CEUX\"" + "BOARD_ID=GENERIC_G473CEUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G473CEUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G473CEUX_VARIANT_PATH} +) + +target_link_options(GENERIC_G473CEUX INTERFACE + "LINKER:--default-script=${GENERIC_G473CEUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473CEUX_MCU} +) + +add_library(GENERIC_G473CEUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_G473CEUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CEUX_serial_generic INTERFACE) +target_compile_options(GENERIC_G473CEUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G473CEUX_serial_none INTERFACE) +target_compile_options(GENERIC_G473CEUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G473CEUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_G473CEUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G473CEUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G473CEUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G473CEUX_usb_HID INTERFACE) +target_compile_options(GENERIC_G473CEUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G473CEUX_usb_none INTERFACE) +target_compile_options(GENERIC_G473CEUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CEUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_G473CEUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G473CEUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_G473CEUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G473CEUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G473CEUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G473MBTX # ----------------------------------------------------------------------------- @@ -68766,6 +69012,88 @@ target_compile_options(GENERIC_G474CBTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G474CBUX +# ----------------------------------------------------------------------------- + +set(GENERIC_G474CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(GENERIC_G474CBUX_MAXSIZE 131072) +set(GENERIC_G474CBUX_MAXDATASIZE 131072) +set(GENERIC_G474CBUX_MCU cortex-m4) +set(GENERIC_G474CBUX_FPCONF "-") +add_library(GENERIC_G474CBUX INTERFACE) +target_compile_options(GENERIC_G474CBUX INTERFACE + "SHELL:-DSTM32G474xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G474CBUX_MCU} +) +target_compile_definitions(GENERIC_G474CBUX INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G474CBUX" + "BOARD_NAME=\"GENERIC_G474CBUX\"" + "BOARD_ID=GENERIC_G474CBUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G474CBUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G474CBUX_VARIANT_PATH} +) + +target_link_options(GENERIC_G474CBUX INTERFACE + "LINKER:--default-script=${GENERIC_G474CBUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G474CBUX_MCU} +) + +add_library(GENERIC_G474CBUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_G474CBUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CBUX_serial_generic INTERFACE) +target_compile_options(GENERIC_G474CBUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G474CBUX_serial_none INTERFACE) +target_compile_options(GENERIC_G474CBUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G474CBUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_G474CBUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G474CBUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G474CBUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G474CBUX_usb_HID INTERFACE) +target_compile_options(GENERIC_G474CBUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G474CBUX_usb_none INTERFACE) +target_compile_options(GENERIC_G474CBUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CBUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_G474CBUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CBUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_G474CBUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G474CBUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G474CBUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G474CCTX # ----------------------------------------------------------------------------- @@ -68848,6 +69176,88 @@ target_compile_options(GENERIC_G474CCTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G474CCUX +# ----------------------------------------------------------------------------- + +set(GENERIC_G474CCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(GENERIC_G474CCUX_MAXSIZE 262144) +set(GENERIC_G474CCUX_MAXDATASIZE 131072) +set(GENERIC_G474CCUX_MCU cortex-m4) +set(GENERIC_G474CCUX_FPCONF "-") +add_library(GENERIC_G474CCUX INTERFACE) +target_compile_options(GENERIC_G474CCUX INTERFACE + "SHELL:-DSTM32G474xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G474CCUX_MCU} +) +target_compile_definitions(GENERIC_G474CCUX INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G474CCUX" + "BOARD_NAME=\"GENERIC_G474CCUX\"" + "BOARD_ID=GENERIC_G474CCUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G474CCUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G474CCUX_VARIANT_PATH} +) + +target_link_options(GENERIC_G474CCUX INTERFACE + "LINKER:--default-script=${GENERIC_G474CCUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G474CCUX_MCU} +) + +add_library(GENERIC_G474CCUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_G474CCUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CCUX_serial_generic INTERFACE) +target_compile_options(GENERIC_G474CCUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G474CCUX_serial_none INTERFACE) +target_compile_options(GENERIC_G474CCUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G474CCUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_G474CCUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G474CCUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G474CCUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G474CCUX_usb_HID INTERFACE) +target_compile_options(GENERIC_G474CCUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G474CCUX_usb_none INTERFACE) +target_compile_options(GENERIC_G474CCUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CCUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_G474CCUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CCUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_G474CCUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G474CCUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G474CCUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G474CETX # ----------------------------------------------------------------------------- @@ -68930,6 +69340,88 @@ target_compile_options(GENERIC_G474CETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G474CEUX +# ----------------------------------------------------------------------------- + +set(GENERIC_G474CEUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(GENERIC_G474CEUX_MAXSIZE 524288) +set(GENERIC_G474CEUX_MAXDATASIZE 131072) +set(GENERIC_G474CEUX_MCU cortex-m4) +set(GENERIC_G474CEUX_FPCONF "-") +add_library(GENERIC_G474CEUX INTERFACE) +target_compile_options(GENERIC_G474CEUX INTERFACE + "SHELL:-DSTM32G474xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G474CEUX_MCU} +) +target_compile_definitions(GENERIC_G474CEUX INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G474CEUX" + "BOARD_NAME=\"GENERIC_G474CEUX\"" + "BOARD_ID=GENERIC_G474CEUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G474CEUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G474CEUX_VARIANT_PATH} +) + +target_link_options(GENERIC_G474CEUX INTERFACE + "LINKER:--default-script=${GENERIC_G474CEUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G474CEUX_MCU} +) + +add_library(GENERIC_G474CEUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_G474CEUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CEUX_serial_generic INTERFACE) +target_compile_options(GENERIC_G474CEUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G474CEUX_serial_none INTERFACE) +target_compile_options(GENERIC_G474CEUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G474CEUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_G474CEUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G474CEUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G474CEUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G474CEUX_usb_HID INTERFACE) +target_compile_options(GENERIC_G474CEUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G474CEUX_usb_none INTERFACE) +target_compile_options(GENERIC_G474CEUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CEUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_G474CEUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G474CEUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_G474CEUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G474CEUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G474CEUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G474MBTX # ----------------------------------------------------------------------------- @@ -70488,6 +70980,88 @@ target_compile_options(GENERIC_G483CETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G483CEUX +# ----------------------------------------------------------------------------- + +set(GENERIC_G483CEUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(GENERIC_G483CEUX_MAXSIZE 524288) +set(GENERIC_G483CEUX_MAXDATASIZE 131072) +set(GENERIC_G483CEUX_MCU cortex-m4) +set(GENERIC_G483CEUX_FPCONF "-") +add_library(GENERIC_G483CEUX INTERFACE) +target_compile_options(GENERIC_G483CEUX INTERFACE + "SHELL:-DSTM32G483xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G483CEUX_MCU} +) +target_compile_definitions(GENERIC_G483CEUX INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G483CEUX" + "BOARD_NAME=\"GENERIC_G483CEUX\"" + "BOARD_ID=GENERIC_G483CEUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G483CEUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G483CEUX_VARIANT_PATH} +) + +target_link_options(GENERIC_G483CEUX INTERFACE + "LINKER:--default-script=${GENERIC_G483CEUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G483CEUX_MCU} +) + +add_library(GENERIC_G483CEUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_G483CEUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G483CEUX_serial_generic INTERFACE) +target_compile_options(GENERIC_G483CEUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G483CEUX_serial_none INTERFACE) +target_compile_options(GENERIC_G483CEUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G483CEUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_G483CEUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G483CEUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G483CEUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G483CEUX_usb_HID INTERFACE) +target_compile_options(GENERIC_G483CEUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G483CEUX_usb_none INTERFACE) +target_compile_options(GENERIC_G483CEUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G483CEUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_G483CEUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G483CEUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_G483CEUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G483CEUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G483CEUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G483METX # ----------------------------------------------------------------------------- @@ -71062,6 +71636,88 @@ target_compile_options(GENERIC_G484CETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G484CEUX +# ----------------------------------------------------------------------------- + +set(GENERIC_G484CEUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(GENERIC_G484CEUX_MAXSIZE 524288) +set(GENERIC_G484CEUX_MAXDATASIZE 131072) +set(GENERIC_G484CEUX_MCU cortex-m4) +set(GENERIC_G484CEUX_FPCONF "-") +add_library(GENERIC_G484CEUX INTERFACE) +target_compile_options(GENERIC_G484CEUX INTERFACE + "SHELL:-DSTM32G484xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G484CEUX_MCU} +) +target_compile_definitions(GENERIC_G484CEUX INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G484CEUX" + "BOARD_NAME=\"GENERIC_G484CEUX\"" + "BOARD_ID=GENERIC_G484CEUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G484CEUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G484CEUX_VARIANT_PATH} +) + +target_link_options(GENERIC_G484CEUX INTERFACE + "LINKER:--default-script=${GENERIC_G484CEUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G484CEUX_MCU} +) + +add_library(GENERIC_G484CEUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_G484CEUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G484CEUX_serial_generic INTERFACE) +target_compile_options(GENERIC_G484CEUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G484CEUX_serial_none INTERFACE) +target_compile_options(GENERIC_G484CEUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G484CEUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_G484CEUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G484CEUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G484CEUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G484CEUX_usb_HID INTERFACE) +target_compile_options(GENERIC_G484CEUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G484CEUX_usb_none INTERFACE) +target_compile_options(GENERIC_G484CEUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G484CEUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_G484CEUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G484CEUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_G484CEUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G484CEUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G484CEUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G484METX # ----------------------------------------------------------------------------- @@ -110448,6 +111104,88 @@ target_link_options(VCCGND_F407ZG_MINI_hid INTERFACE ) +# WEACT_G474CE +# ----------------------------------------------------------------------------- + +set(WEACT_G474CE_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU") +set(WEACT_G474CE_MAXSIZE 524288) +set(WEACT_G474CE_MAXDATASIZE 131072) +set(WEACT_G474CE_MCU cortex-m4) +set(WEACT_G474CE_FPCONF "-") +add_library(WEACT_G474CE INTERFACE) +target_compile_options(WEACT_G474CE INTERFACE + "SHELL:-DSTM32G474xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${WEACT_G474CE_MCU} +) +target_compile_definitions(WEACT_G474CE INTERFACE + "STM32G4xx" + "ARDUINO_WEACT_G474CE" + "BOARD_NAME=\"WEACT_G474CE\"" + "BOARD_ID=WEACT_G474CE" + "VARIANT_H=\"variant_WEACT_G474CE.h\"" +) +target_include_directories(WEACT_G474CE INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${WEACT_G474CE_VARIANT_PATH} +) + +target_link_options(WEACT_G474CE INTERFACE + "LINKER:--default-script=${WEACT_G474CE_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${WEACT_G474CE_MCU} +) + +add_library(WEACT_G474CE_serial_disabled INTERFACE) +target_compile_options(WEACT_G474CE_serial_disabled INTERFACE + "SHELL:" +) +add_library(WEACT_G474CE_serial_generic INTERFACE) +target_compile_options(WEACT_G474CE_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(WEACT_G474CE_serial_none INTERFACE) +target_compile_options(WEACT_G474CE_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(WEACT_G474CE_usb_CDC INTERFACE) +target_compile_options(WEACT_G474CE_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(WEACT_G474CE_usb_CDCgen INTERFACE) +target_compile_options(WEACT_G474CE_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(WEACT_G474CE_usb_HID INTERFACE) +target_compile_options(WEACT_G474CE_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(WEACT_G474CE_usb_none INTERFACE) +target_compile_options(WEACT_G474CE_usb_none INTERFACE + "SHELL:" +) +add_library(WEACT_G474CE_xusb_FS INTERFACE) +target_compile_options(WEACT_G474CE_xusb_FS INTERFACE + "SHELL:" +) +add_library(WEACT_G474CE_xusb_HS INTERFACE) +target_compile_options(WEACT_G474CE_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(WEACT_G474CE_xusb_HSFS INTERFACE) +target_compile_options(WEACT_G474CE_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # WEACT_H562RG # ----------------------------------------------------------------------------- diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/CMakeLists.txt b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/CMakeLists.txt index 2a4d55b6b1..bb65361bdb 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/CMakeLists.txt +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_WEACT_G474CE.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) From d4a0b3cbafeb14869d7507e95e39d4ffacfb60cc Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Mon, 6 Jan 2025 05:32:32 +0300 Subject: [PATCH 028/141] variant(g4): correct the clock config for HSE8 on WeAct G474CEU * Override HSE value to 8 MHz not 24 * Keep PLL input above 2.66 MHz spec * Set VCO to a multiple of USB48 and feed that from PLL, sysclk becomes 144 --- .../variant_WEACT_G474CE.cpp | 8 ++++---- .../variant_WEACT_G474CE.h | 4 ++++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp index 7f77b7eee5..209da49ce5 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp @@ -111,9 +111,9 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLN = 85; + RCC_OscInitStruct.PLL.PLLN = 72; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV6; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; @@ -135,7 +135,7 @@ WEAK void SystemClock_Config(void) #ifdef USBCON /* Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } @@ -146,4 +146,4 @@ WEAK void SystemClock_Config(void) } // extern "C" #endif -#endif /* ARDUINO_NUCLEO_G431RB */ +#endif /* ARDUINO_WEACT_G474CE */ diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h index 2d66c2ab32..785cc5eaf1 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h @@ -184,6 +184,10 @@ #define HAL_QSPI_MODULE_ENABLED #endif +#ifndef HSE_VALUE + #define HSE_VALUE 8000000U +#endif + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ From b94080997a8b04cde7dcdd777cdbfe917e76eab1 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Mon, 6 Jan 2025 05:35:46 +0300 Subject: [PATCH 029/141] variant(g4): enhance WeAct G474CE clock config for USB * Enable CRS and switch USB to HSI48, decoupling it from PLL * Increase VCO multiplier to reach 170 MHz max spec --- .../variant_WEACT_G474CE.cpp | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp index 209da49ce5..d48e8a9fb1 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp @@ -98,6 +98,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; #ifdef USBCON + RCC_CRSInitTypeDef RCC_CRSInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; #endif @@ -113,7 +114,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLN = 72; + RCC_OscInitStruct.PLL.PLLN = 85; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV6; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; @@ -133,9 +134,22 @@ WEAK void SystemClock_Config(void) } #ifdef USBCON + /* Enable the SYSCFG APB clock */ + __HAL_RCC_CRS_CLK_ENABLE(); + + /* Configures CRS */ + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; + RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; + RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); + RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT; + RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT; + + HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); + /* Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } From d80a6724ad637d7b30c74655136e7f02fced0193 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 7 Jan 2025 11:28:05 +0100 Subject: [PATCH 030/141] ci(common): harden functions Signed-off-by: Frederic Pillon --- CI/utils/common_ext.py | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/CI/utils/common_ext.py b/CI/utils/common_ext.py index cf3f2048e3..7a7d8163ec 100644 --- a/CI/utils/common_ext.py +++ b/CI/utils/common_ext.py @@ -3,10 +3,11 @@ import subprocess import shutil import sys +from pathlib import Path # Add default key/value pair to config file -def defaultConfig(config_file_path, data): +def defaultConfig(config_file_path: Path, data: dict): print(f"Please check the default configuration '{config_file_path}'.") config_file = open(config_file_path, "w") config_file.write(json.dumps(data, indent=2)) @@ -15,7 +16,7 @@ def defaultConfig(config_file_path, data): # Create a folder if not exists -def createFolder(path): +def createFolder(path: Path): try: path.mkdir(parents=True, exist_ok=True) except OSError: @@ -23,7 +24,7 @@ def createFolder(path): # Delete targeted folder recursively -def deleteFolder(path): +def deleteFolder(path: Path): if path.is_dir(): shutil.rmtree(path, ignore_errors=True) @@ -38,7 +39,7 @@ def copyFolder(src, dest, ign_patt=set()): # copy one file to dest -def copyFile(src, dest): +def copyFile(src: Path, dest: Path): try: if src.is_file(): shutil.copy(str(src), str(dest)) @@ -46,7 +47,8 @@ def copyFile(src, dest): print(f"Error: File {src} not copied. {e}") -def genSTM32List(path, pattern): +# get list of STM32 series from HAL driver directory +def genSTM32List(path: Path, pattern: str = None): stm32_list = [] # series dir_pattern = re.compile(r"^STM32(.*)xx_HAL_Driver$", re.IGNORECASE) @@ -63,7 +65,7 @@ def genSTM32List(path, pattern): return stm32_list -def execute_cmd(cmd, stderror): +def execute_cmd(cmd: list, stderror: int): try: output = subprocess.check_output(cmd, stderr=stderror).decode("utf-8").strip() except subprocess.CalledProcessError as e: @@ -72,7 +74,7 @@ def execute_cmd(cmd, stderror): return output -def getRepoBranchName(repo_path): +def getRepoBranchName(repo_path: Path): bname = "" rname = "" cmd = ["git", "-C", repo_path, "branch", "-r"] From 7b30c6acfc5c80c269653969e6de3231f759d256 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 6 Jan 2025 14:28:06 +0100 Subject: [PATCH 031/141] ci(stm32svd): sort by supported cube series Signed-off-by: Frederic Pillon --- CI/update/stm32svd.py | 83 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 76 insertions(+), 7 deletions(-) diff --git a/CI/update/stm32svd.py b/CI/update/stm32svd.py index 87a0eceb0b..199c8baab1 100644 --- a/CI/update/stm32svd.py +++ b/CI/update/stm32svd.py @@ -1,6 +1,7 @@ import json import sys from pathlib import Path +from xml.dom.minidom import parse script_path = Path(__file__).parent.resolve() sys.path.append(str(script_path.parent)) @@ -8,9 +9,11 @@ from utils import defaultConfig, genSTM32List stm32_list = [] # series +svd_dict = {} # 'svd file': 'name' root_path = script_path.parent.parent.resolve() hal_path = root_path / "system" / "Drivers" cubeclt_path = Path("") +cubeclt_mcu_path = Path() cubeclt_svd_path = Path("") stm32_svd_repo = Path("") stm32_svd_dir = Path("") @@ -18,6 +21,7 @@ def checkConfig(): global cubeclt_path + global cubeclt_mcu_path global cubeclt_svd_path global stm32_svd_repo global stm32_svd_dir @@ -43,6 +47,10 @@ def checkConfig(): if not cubeclt_svd_path.is_dir(): print(f"{cubeclt_svd_path} does not exist!") exit(1) + cubeclt_mcu_path = cubeclt_path / "STM32target-mcu" + if not cubeclt_mcu_path.is_dir(): + print(f"{cubeclt_mcu_path} does not exist!") + exit(1) if "STM32_SVD_PATH" not in path_config: path_config["STM32_SVD_PATH"] = str("Path to stm32_svd repository") defaultConfig(config_file_path, path_config) @@ -62,11 +70,56 @@ def checkConfig(): ) +def parse_stm32targets(stm32targets_file: Path): + global stm32_list + global svd_dict + + xml_stm32targets = parse(str(stm32targets_file)) + mcu_nodes = xml_stm32targets.getElementsByTagName("mcu") + for mcu_node in mcu_nodes: + parent_node_name = mcu_node.getElementsByTagName("parent")[0].firstChild.data + mcu_node_name = mcu_node.getElementsByTagName("name")[0].firstChild.data + cpus_node_name = mcu_node.getElementsByTagName("cpus") + cpu_node_name = cpus_node_name[0].getElementsByTagName("cpu") + svd_node = cpu_node_name[0].getElementsByTagName("svd") + svd_file = svd_node[0].getElementsByTagName("name")[0].firstChild.data + serie = ( + parent_node_name.upper() + .removeprefix("STM32") + .removesuffix("SINGLE") + .removesuffix("DUAL") + ) + if serie == "L4PLUS": + serie = "L4" + else: + if mcu_node_name.startswith("STM32H7R") or mcu_node_name.startswith( + "STM32H7S" + ): + serie = "H7RS" + svd_dict[svd_file] = serie + # Check if a second cpu is defined + if cpu_node_name.length > 1: + svd_node = cpu_node_name[1].getElementsByTagName("svd") + svd_file = svd_node[0].getElementsByTagName("name")[0].firstChild.data + serie = parent_node_name.upper().removeprefix("STM32").removesuffix("DUAL") + svd_dict[svd_file] = serie + xml_stm32targets.unlink() + + def main(): global stm32_list - # check config have to be done first + # Check config have to be done first checkConfig() + # Get list of STM32 series from HAL driver directory stm32_list = genSTM32List(hal_path, None) + # Parse STM32Targets.xml to get list of STM32 series and svd file + # one per Cube reference + stm32targets_file = cubeclt_mcu_path / "stm32targets.xml" + if stm32targets_file.is_file(): + parse_stm32targets(stm32targets_file) + else: + print(f"{stm32targets_file} does not exits!") + exit(1) # Reverse order to get WBA before WB to ease svd sorting stm32_list.sort(reverse=True) # Clean up core svd folder @@ -81,17 +134,33 @@ def main(): # Create all directories for serie in stm32_list: createFolder(stm32_svd_dir / f"STM32{serie}xx") - # Get all xml files + # Get all svd files svd_list = sorted(cubeclt_svd_path.glob("STM32*.svd")) - # Copy all svd files per series + # Copy all svd files per supported series for svd_file in svd_list: svd_name = svd_file.name - for serie in stm32_list: - if svd_name.find(f"STM32{serie}") != -1: - copyFile(svd_file, stm32_svd_dir / f"STM32{serie}xx") - break + if svd_name in svd_dict: + if svd_dict[svd_name] in stm32_list: + copyFile(svd_file, stm32_svd_dir / f"STM32{svd_dict[svd_name]}xx") + else: + # File not copied as not referenced in stm32targets.xml + if svd_name.startswith("STM32GBK"): + copyFile(svd_file, stm32_svd_dir / "STM32G4xx") + else: + for serie in stm32_list: + if svd_name.startswith(f"STM32{serie}"): + copyFile(svd_file, stm32_svd_dir / f"STM32{serie}xx") + break + else: + print(f"File {svd_name} not copied.") + # Check if created folder is empty and delete it + for serie in stm32_list: + serie_dir = stm32_svd_dir / f"STM32{serie}xx" + if not any(serie_dir.glob("*")): + print (f"Folder {serie_dir} is empty.") + serie_dir.rmdir() if __name__ == "__main__": main() From 575baf5c080353849a6e3b901504da8dd9edb964 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 6 Jan 2025 11:09:47 +0100 Subject: [PATCH 032/141] ci(stm32variant): dynamically manage syswkup list Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index 5d53d01164..fb6b1cc8ef 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -1205,12 +1205,16 @@ def print_peripheral(): # PinNamesVar.h generation def manage_syswkup(): - syswkup_pins_list = [[] for _ in range(8)] if len(syswkup_list) != 0: - # H7xx and F446 start from 0 + # Find the max range of SYS_WKUP + max_range = syswkup_list[-1][2].replace("SYS_WKUP", "") + max_range = int(max_range) if max_range else 1 + # F446 start from 0 base_index = 1 if syswkup_list[0][2].replace("SYS_WKUP", "") == "0": base_index = 0 + max_range += 1 + syswkup_pins_list = [[] for _ in range(max_range)] for p in syswkup_list: num = p[2].replace("SYS_WKUP", "") num = int(num) if num else 1 @@ -1220,6 +1224,8 @@ def manage_syswkup(): else: cmt = f" /* {p[2]} */" syswkup_pins_list[num].append([p[0], cmt]) + else: + syswkup_pins_list = [] return syswkup_pins_list From b19931a03af01b9212211686e3ccc2d3b1129dd3 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 6 Jan 2025 11:09:12 +0100 Subject: [PATCH 033/141] ci(stm32variant): delete folder with no ldscript Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index fb6b1cc8ef..ffa979fa1d 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -2381,14 +2381,20 @@ def aggregate_dir(): dir_str = "Directories" if nb_old > 1 else "Directory" print(f"\n{dir_str} not updated for {mcu_family.name}:\n") for d in old_dirs: - print(f" - {d.name}") + # Check if ldsript.ld file exists in the folder + if not (d / "ldscript.ld").exists(): + deleteFolder(d) + print(f" - {d.name} (deleted)") + else: + print(f" - {d.name}") print( """ - --> Please, check if it is due to directory name update (renamed), if true then: + --> For each directory not deleted, it requires manual update as it was renamed: + - Find new directory name. - Move custom boards definition files, if any. - - Move linker script(s), if any. + - Move linker script(s). - Copy 'SystemClock_Config(void)' function to the new generic clock config file. - --> Then remove it, update old path in boards.txt + --> Then remove it and update old path in boards.txt (for custom board(s) as well as generic ones). """ ) From 0c687c9701893d05c9c977b1bbd347456be9d5ec Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Tue, 7 Jan 2025 15:09:18 +0300 Subject: [PATCH 034/141] feat(platform): add BMP upload method to 3rd party boards --- boards.txt | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/boards.txt b/boards.txt index 08b4d3fa7e..494bbfd73a 100644 --- a/boards.txt +++ b/boards.txt @@ -12930,6 +12930,10 @@ GenWL.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload 3dprinter.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} 3dprinter.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +3dprinter.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +3dprinter.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +3dprinter.menu.upload_method.bmpMethod.upload.tool=bmp_upload + 3dprinter.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) 3dprinter.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink 3dprinter.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -13006,6 +13010,10 @@ Blues.menu.upload_method.dfuMethod.upload.protocol=dfu Blues.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Blues.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Blues.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +Blues.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +Blues.menu.upload_method.bmpMethod.upload.tool=bmp_upload + Blues.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) Blues.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink Blues.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -13060,6 +13068,10 @@ Elecgator.menu.upload_method.dfuMethod.upload.protocol=dfu Elecgator.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Elecgator.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Elecgator.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +Elecgator.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +Elecgator.menu.upload_method.bmpMethod.upload.tool=bmp_upload + Elecgator.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) Elecgator.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink Elecgator.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -13130,6 +13142,10 @@ ESC_board.menu.upload_method.dfuMethod.upload.protocol=dfu ESC_board.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} ESC_board.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +ESC_board.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +ESC_board.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +ESC_board.menu.upload_method.bmpMethod.upload.tool=bmp_upload + ESC_board.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) ESC_board.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink ESC_board.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -13378,6 +13394,10 @@ IotContinuum.menu.upload_method.dfuMethod.upload.protocol=dfu IotContinuum.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} IotContinuum.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +IotContinuum.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +IotContinuum.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +IotContinuum.menu.upload_method.bmpMethod.upload.tool=bmp_upload + IotContinuum.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) IotContinuum.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink IotContinuum.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -13558,6 +13578,10 @@ LoRa.menu.upload_method.dfuMethod.upload.protocol=dfu LoRa.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} LoRa.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +LoRa.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +LoRa.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +LoRa.menu.upload_method.bmpMethod.upload.tool=bmp_upload + LoRa.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) LoRa.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink LoRa.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -13621,6 +13645,10 @@ Midatronics.menu.upload_method.dfuMethod.upload.protocol=dfu Midatronics.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Midatronics.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Midatronics.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +Midatronics.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +Midatronics.menu.upload_method.bmpMethod.upload.tool=bmp_upload + Midatronics.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) Midatronics.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink Midatronics.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -13700,6 +13728,10 @@ SparkFun.menu.upload_method.dfuMethod.upload.protocol=dfu SparkFun.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} SparkFun.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +SparkFun.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +SparkFun.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +SparkFun.menu.upload_method.bmpMethod.upload.tool=bmp_upload + SparkFun.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) SparkFun.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink SparkFun.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload From eb82540e271974274424e2f1b0058e7fb651dce1 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Tue, 7 Jan 2025 18:56:38 +0300 Subject: [PATCH 035/141] feat(platform): add BMP upload support to ST Nucleo/Disco/Eval boards --- boards.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/boards.txt b/boards.txt index 494bbfd73a..a311f0416d 100644 --- a/boards.txt +++ b/boards.txt @@ -389,6 +389,10 @@ Nucleo_144.menu.upload_method.dfuMethod.upload.protocol=dfu Nucleo_144.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Nucleo_144.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Nucleo_144.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +Nucleo_144.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +Nucleo_144.menu.upload_method.bmpMethod.upload.tool=bmp_upload + Nucleo_144.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) Nucleo_144.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink Nucleo_144.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -910,6 +914,10 @@ Nucleo_64.menu.upload_method.dfuMethod.upload.protocol=dfu Nucleo_64.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Nucleo_64.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Nucleo_64.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +Nucleo_64.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +Nucleo_64.menu.upload_method.bmpMethod.upload.tool=bmp_upload + Nucleo_64.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) Nucleo_64.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink Nucleo_64.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -1086,6 +1094,10 @@ Nucleo_32.menu.upload_method.dfuMethod.upload.protocol=dfu Nucleo_32.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Nucleo_32.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Nucleo_32.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +Nucleo_32.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +Nucleo_32.menu.upload_method.bmpMethod.upload.tool=bmp_upload + Nucleo_32.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) Nucleo_32.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink Nucleo_32.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -1420,6 +1432,10 @@ Disco.menu.upload_method.dfuMethod.upload.protocol=dfu Disco.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Disco.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Disco.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +Disco.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +Disco.menu.upload_method.bmpMethod.upload.tool=bmp_upload + Disco.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) Disco.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink Disco.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -1504,6 +1520,10 @@ Eval.menu.upload_method.dfuMethod.upload.protocol=dfu Eval.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Eval.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Eval.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +Eval.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +Eval.menu.upload_method.bmpMethod.upload.tool=bmp_upload + Eval.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) Eval.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink Eval.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload From c6b57c0e7c27981e8bd0516465c025c040d9f16d Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Tue, 7 Jan 2025 14:52:51 +0300 Subject: [PATCH 036/141] feat(platform): add BMP upload support to Generic boards * Only GenF1, GenF3, GenF4, GenL0 and GenFlight allowed this by now, so extend support to the rest of chip families supported by BMP v2.0 * GenU0 and GenWBA are not supported. --- boards.txt | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/boards.txt b/boards.txt index a311f0416d..714227fc8e 100644 --- a/boards.txt +++ b/boards.txt @@ -1738,6 +1738,10 @@ GenC0.menu.upload_method.serialMethod.upload.protocol=serial GenC0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} GenC0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg +GenC0.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenC0.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenC0.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenC0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenC0.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenC0.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -2659,6 +2663,10 @@ GenF0.menu.upload_method.dfuMethod.upload.protocol=dfu GenF0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenF0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenF0.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenF0.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenF0.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenF0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenF0.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenF0.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -3984,6 +3992,10 @@ GenF2.menu.upload_method.dfuMethod.upload.protocol=dfu GenF2.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenF2.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenF2.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenF2.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenF2.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenF2.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenF2.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenF2.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -6023,6 +6035,10 @@ GenF7.menu.upload_method.dfuMethod.upload.protocol=dfu GenF7.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenF7.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenF7.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenF7.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenF7.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenF7.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenF7.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenF7.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -7447,6 +7463,10 @@ GenG0.menu.upload_method.dfuMethod.upload.protocol=dfu GenG0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenG0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenG0.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenG0.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenG0.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenG0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenG0.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenG0.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -8736,6 +8756,10 @@ GenG4.menu.upload_method.dfuMethod.upload.protocol=dfu GenG4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenG4.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenG4.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenG4.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenG4.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenG4.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenG4.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenG4.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -8921,6 +8945,10 @@ GenH5.menu.upload_method.dfuMethod.upload.protocol=dfu GenH5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenH5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenH5.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenH5.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenH5.menu.upload_method.bmpMethod.upload.tool=bmp_upload + #GenH5.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) #GenH5.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink #GenH5.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -9570,6 +9598,10 @@ GenH7.menu.upload_method.dfuMethod.upload.protocol=dfu GenH7.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenH7.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenH7.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenH7.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenH7.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenH7.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenH7.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenH7.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -11198,6 +11230,10 @@ GenL1.menu.upload_method.dfuMethod.upload.protocol=dfu GenL1.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenL1.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenL1.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenL1.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenL1.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenL1.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenL1.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenL1.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -12011,6 +12047,10 @@ GenL4.menu.upload_method.dfuMethod.upload.protocol=dfu GenL4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenL4.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenL4.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenL4.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenL4.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenL4.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenL4.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenL4.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -12085,6 +12125,10 @@ GenL5.menu.upload_method.dfuMethod.upload.protocol=dfu GenL5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenL5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenL5.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenL5.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenL5.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenL5.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenL5.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenL5.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -12340,6 +12384,10 @@ GenU5.menu.upload_method.dfuMethod.upload.protocol=dfu GenU5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenU5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenU5.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenU5.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenU5.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenU5.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenU5.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenU5.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -12459,6 +12507,10 @@ GenWB.menu.upload_method.dfuMethod.upload.protocol=dfu GenWB.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenWB.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenWB.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenWB.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenWB.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenWB.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenWB.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenWB.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload @@ -12706,6 +12758,10 @@ GenWL.menu.upload_method.dfuMethod.upload.protocol=dfu GenWL.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenWL.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenWL.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenWL.menu.upload_method.bmpMethod.upload.tool=bmp_upload + GenWL.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) GenWL.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink GenWL.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload From 2ccfc78fd1bbbf851610db9bd153b5a797e63069 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 7 Jan 2025 14:35:54 +0100 Subject: [PATCH 037/141] ci(stm32variant): enhance series managements - dynamically manage ignores series (i.e. the one not supported by the core) - allow to update one or several series based on a pattern. Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 89 ++++++++++++++++++++++----------------- 1 file changed, 50 insertions(+), 39 deletions(-) diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index ffa979fa1d..34936c8afd 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -14,8 +14,17 @@ script_path = Path(__file__).parent.resolve() sys.path.append(str(script_path.parent)) -from utils import defaultConfig, deleteFolder, execute_cmd, getRepoBranchName +from utils import ( + defaultConfig, + deleteFolder, + execute_cmd, + getRepoBranchName, + genSTM32List, +) +stm32_list = [] # series +ignored_stm32_list = [] # series +aggregate_serie_list = [] # series mcu_list = [] # 'name' io_list = [] # 'PIN','name' alt_list = [] # 'PIN','name' @@ -158,6 +167,12 @@ def parse_mcu_file(): mcu_node = xml_mcu.getElementsByTagName("Mcu")[0] mcu_family = mcu_node.attributes["Family"].value + # Check if FwLibrary is present in the attributes + if "FwLibrary" in mcu_node.attributes: + mcu_family = mcu_node.attributes["FwLibrary"].value + # split using '_' and kept the lasy part + mcu_family = f"STM32{mcu_family.split('_')[-1]}" + if mcu_family.endswith("+"): mcu_family = mcu_family[:-1] mcu_refname = mcu_node.attributes["RefName"].value @@ -2271,17 +2286,14 @@ def merge_dir(out_temp_path, group_mcu_dir, mcu_family, periph_xml, variant_exp) def aggregate_dir(): # Get mcu_family directories out_temp_path = tmp_dir - mcu_families = sorted(out_temp_path.glob("STM32*/")) group_mcu_dir = [] mcu_dir1_files_list = [] mcu_dir2_files_list = [] # Compare per family - for mcu_family in mcu_families: - # Generate only for one family - if filtered_family and filtered_family not in mcu_family.name: - continue + for mcu_family_name in aggregate_serie_list: + mcu_family = out_temp_path / f"{mcu_family_name}xx" out_family_path = root_dir / "variants" / mcu_family.name # Get all mcu_dir mcu_dirs = sorted(mcu_family.glob("*/")) @@ -2525,14 +2537,7 @@ def manage_repo(): system_path = root_dir / "system" templates_dir = script_path / "templates" mcu_family_dir = "" -filtered_family = "" -refname_filter = [ - "STM32H7R", - "STM32H7S", - "STM32MP13", - "STM32MP2", - "STM32WB0", -] +filtered_serie = "" periph_c_filename = "PeripheralPins.c" pinvar_h_filename = "PinNamesVar.h" config_filename = script_path / "update_config.json" @@ -2582,15 +2587,15 @@ def manage_repo(): group.add_argument( "-l", "--list", - help="list available xml files description in database", + help="list available xml files description in database.", action="store_true", ) group.add_argument( - "-f", - "--family", - metavar="name", - help="Generate all files for specified mcu family.", + "-s", + "--serie", + metavar="pattern", + help="Generate all files for specified STM32 serie(s) pattern.", ) parser.add_argument( @@ -2604,7 +2609,6 @@ def manage_repo(): action="store_true", ) parser.add_argument( - "-s", "--skip", help=f"Skip {repo_name} clone/fetch", action="store_true", @@ -2656,13 +2660,9 @@ def manage_repo(): print(f"{stm32targets_file} does not exits!") exit(1) -if args.family: - filtered_family = args.family.upper() - filtered_family = filtered_family.removeprefix("STM32") - while filtered_family.endswith("X"): - filtered_family = filtered_family.rstrip("X") - filtered_family = f"STM32{filtered_family}" - +if args.serie: + serie = args.serie.upper() + serie_pattern = re.compile(rf"STM32({serie})$", re.IGNORECASE) # Get all xml files mcu_list = sorted(dirMCU.glob("STM32*.xml")) @@ -2672,6 +2672,11 @@ def manage_repo(): print(f.name) quit() +stm32_list = [f"STM32{stm32}" for stm32 in genSTM32List(system_path / "Drivers")] +if not stm32_list: + print(f"No STM32 series found in {system_path}/Drivers") + quit() + # Create the jinja2 environment. j2_env = Environment( loader=FileSystemLoader(str(templates_dir)), trim_blocks=True, lstrip_blocks=True @@ -2687,23 +2692,22 @@ def manage_repo(): # Open input file xml_mcu = parse(str(mcu_file)) parse_mcu_file() - - # Generate only for one family or supported reference + # Generate only for specified pattern series or supported one + # Check if mcu_family is supported by the core if ( - filtered_family - and filtered_family not in mcu_family - or any(skp in mcu_refname for skp in refname_filter) + mcu_family not in stm32_list + or args.serie + and serie_pattern.search(mcu_family) is None ): - # Add a warning if filtered family is requested - if filtered_family and filtered_family not in refname_filter: - for skp in refname_filter: - if skp == filtered_family: - print(f"Requested family {filtered_family} is filtered!") - print("Please update the refname_filter list.") - quit() + if mcu_family not in ignored_stm32_list and mcu_family not in stm32_list: + ignored_stm32_list.append(mcu_family) xml_mcu.unlink() continue + # Add mcu family to the list of directory to aggregate + if mcu_family not in aggregate_serie_list: + aggregate_serie_list.append(mcu_family) + print(f"Generating files for '{mcu_file.name}'...") if not gpiofile: print("Could not find GPIO file") @@ -2771,3 +2775,10 @@ def manage_repo(): # Clean temporary dir deleteFolder(tmp_dir) + +# Display ignored families +if ignored_stm32_list: + print("\nIgnored families:") + for family in ignored_stm32_list: + print(f" - {family}") + print("To be supported, series must first be supported by the core.") From 9698938bd82be49a8ebed069c0c4a53da84bf501 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:24:01 +0100 Subject: [PATCH 038/141] chore(c0): update variant after script update Signed-off-by: Frederic Pillon --- .../PinNamesVar.h | 12 ------------ variants/STM32C0xx/C011J(4-6)M/PinNamesVar.h | 12 ------------ variants/STM32C0xx/C031C(4-6)(T-U)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C031G(4-6)U/PinNamesVar.h | 6 ------ variants/STM32C0xx/C031K(4-6)(T-U)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h | 6 ------ variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h | 6 ------ variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071C(8-B)(T-U)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071C(8-B)(T-U)xN/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071F(8-B)PxN/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071F8P_C071FB(P-Y)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071G(8-B)U/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071G(8-B)UxN/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071K(8-B)(T-U)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071K(8-B)(T-U)xN/PinNamesVar.h | 6 ------ variants/STM32C0xx/C071R(8-B)T/PinNamesVar.h | 6 ------ .../STM32C0xx/C071R8TxN_C071RB(I-T)xN/PinNamesVar.h | 6 ------ variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h | 6 ------ variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h | 6 ------ variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h | 6 ------ .../C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h | 6 ------ variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h | 6 ------ variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h | 6 ------ variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h | 6 ------ 29 files changed, 186 deletions(-) diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PinNamesVar.h b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PinNamesVar.h index 279477859b..b720b51afe 100644 --- a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PinNamesVar.h +++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PinNamesVar.h @@ -43,17 +43,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C011J(4-6)M/PinNamesVar.h b/variants/STM32C0xx/C011J(4-6)M/PinNamesVar.h index 1bc0a76082..15d0ed6f75 100644 --- a/variants/STM32C0xx/C011J(4-6)M/PinNamesVar.h +++ b/variants/STM32C0xx/C011J(4-6)M/PinNamesVar.h @@ -35,17 +35,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C031C(4-6)(T-U)/PinNamesVar.h index 4d5bf931ac..7c5298417e 100644 --- a/variants/STM32C0xx/C031C(4-6)(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C031C(4-6)(T-U)/PinNamesVar.h @@ -53,11 +53,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C031G(4-6)U/PinNamesVar.h b/variants/STM32C0xx/C031G(4-6)U/PinNamesVar.h index 8e8c40e176..2a6904605f 100644 --- a/variants/STM32C0xx/C031G(4-6)U/PinNamesVar.h +++ b/variants/STM32C0xx/C031G(4-6)U/PinNamesVar.h @@ -52,11 +52,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C031K(4-6)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C031K(4-6)(T-U)/PinNamesVar.h index 2f8b68228a..dbacdacf5e 100644 --- a/variants/STM32C0xx/C031K(4-6)(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C031K(4-6)(T-U)/PinNamesVar.h @@ -53,11 +53,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h index 250cef0aa0..8576cb7fff 100644 --- a/variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/PinNamesVar.h @@ -66,11 +66,5 @@ PC_15_ALT1 = PC_15 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h index 1ccc645780..aea41c7668 100644 --- a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PinNamesVar.h @@ -57,11 +57,5 @@ PC_15_ALT1 = PC_15 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h b/variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h index 6edccbfebb..ba53b48580 100644 --- a/variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h +++ b/variants/STM32C0xx/C051G(6-8)U/PinNamesVar.h @@ -62,11 +62,5 @@ PC_15_ALT1 = PC_15 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h index f70f83fb2d..c8885d517b 100644 --- a/variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PinNamesVar.h @@ -65,11 +65,5 @@ PC_15_ALT1 = PC_15 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C071C(8-B)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C071C(8-B)(T-U)/PinNamesVar.h index d0dfc8889f..8b8ba7bde7 100644 --- a/variants/STM32C0xx/C071C(8-B)(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C071C(8-B)(T-U)/PinNamesVar.h @@ -64,12 +64,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071C(8-B)(T-U)xN/PinNamesVar.h b/variants/STM32C0xx/C071C(8-B)(T-U)xN/PinNamesVar.h index a87e2531fa..c5e85ee2ed 100644 --- a/variants/STM32C0xx/C071C(8-B)(T-U)xN/PinNamesVar.h +++ b/variants/STM32C0xx/C071C(8-B)(T-U)xN/PinNamesVar.h @@ -62,12 +62,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071F(8-B)PxN/PinNamesVar.h b/variants/STM32C0xx/C071F(8-B)PxN/PinNamesVar.h index 2345c11cd7..dc152a95e6 100644 --- a/variants/STM32C0xx/C071F(8-B)PxN/PinNamesVar.h +++ b/variants/STM32C0xx/C071F(8-B)PxN/PinNamesVar.h @@ -52,12 +52,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PinNamesVar.h b/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PinNamesVar.h index 0e6733b708..68d727ee20 100644 --- a/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PinNamesVar.h +++ b/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PinNamesVar.h @@ -55,12 +55,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071G(8-B)U/PinNamesVar.h b/variants/STM32C0xx/C071G(8-B)U/PinNamesVar.h index 4a8ec8c220..aef5258d08 100644 --- a/variants/STM32C0xx/C071G(8-B)U/PinNamesVar.h +++ b/variants/STM32C0xx/C071G(8-B)U/PinNamesVar.h @@ -60,12 +60,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071G(8-B)UxN/PinNamesVar.h b/variants/STM32C0xx/C071G(8-B)UxN/PinNamesVar.h index e6e883c2d1..a512ce3a98 100644 --- a/variants/STM32C0xx/C071G(8-B)UxN/PinNamesVar.h +++ b/variants/STM32C0xx/C071G(8-B)UxN/PinNamesVar.h @@ -59,12 +59,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071K(8-B)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C071K(8-B)(T-U)/PinNamesVar.h index 248b4d9dfc..5f678bfc4d 100644 --- a/variants/STM32C0xx/C071K(8-B)(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C071K(8-B)(T-U)/PinNamesVar.h @@ -63,12 +63,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071K(8-B)(T-U)xN/PinNamesVar.h b/variants/STM32C0xx/C071K(8-B)(T-U)xN/PinNamesVar.h index 316454b384..fa0b635d91 100644 --- a/variants/STM32C0xx/C071K(8-B)(T-U)xN/PinNamesVar.h +++ b/variants/STM32C0xx/C071K(8-B)(T-U)xN/PinNamesVar.h @@ -62,12 +62,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071R(8-B)T/PinNamesVar.h b/variants/STM32C0xx/C071R(8-B)T/PinNamesVar.h index c6552ed567..bf08f058c5 100644 --- a/variants/STM32C0xx/C071R(8-B)T/PinNamesVar.h +++ b/variants/STM32C0xx/C071R(8-B)T/PinNamesVar.h @@ -66,12 +66,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PinNamesVar.h b/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PinNamesVar.h index c6552ed567..bf08f058c5 100644 --- a/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PinNamesVar.h +++ b/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PinNamesVar.h @@ -66,12 +66,6 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h index ccdbd909c2..5c784ed322 100644 --- a/variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/PinNamesVar.h @@ -72,11 +72,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h index 6f63f893c7..09e0f7fcbf 100644 --- a/variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PinNamesVar.h @@ -63,11 +63,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h b/variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h index c9586ee36a..3e129cee5f 100644 --- a/variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h +++ b/variants/STM32C0xx/C091G(B-C)U/PinNamesVar.h @@ -64,11 +64,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h index c393d2c004..7bd09bc25a 100644 --- a/variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/PinNamesVar.h @@ -67,11 +67,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h index 38f8b30764..e2f2a71979 100644 --- a/variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PinNamesVar.h @@ -78,11 +78,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h index 38f8b30764..e2f2a71979 100644 --- a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h +++ b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h @@ -78,11 +78,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h b/variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h index ccdbd909c2..5c784ed322 100644 --- a/variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h @@ -72,11 +72,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h index 6f63f893c7..09e0f7fcbf 100644 --- a/variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PinNamesVar.h @@ -63,11 +63,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h b/variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h index c9586ee36a..3e129cee5f 100644 --- a/variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h +++ b/variants/STM32C0xx/C092G(B-C)U/PinNamesVar.h @@ -64,11 +64,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h index c393d2c004..7bd09bc25a 100644 --- a/variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/PinNamesVar.h @@ -67,11 +67,5 @@ PC_14_ALT1 = PC_14 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ From c93dc10cc628a02a163cd1e0df75fb41ce53a482 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:25:14 +0100 Subject: [PATCH 039/141] chore(f0): update variant after script update Signed-off-by: Frederic Pillon --- variants/STM32F0xx/F030C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030C6T/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F030C8T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030C8T/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F030CCT/PeripheralPins.c | 2 +- variants/STM32F0xx/F030CCT/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F030F4P/PeripheralPins.c | 2 +- variants/STM32F0xx/F030F4P/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F030K6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030K6T/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F030R8T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030R8T/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F030RCT/PeripheralPins.c | 2 +- variants/STM32F0xx/F030RCT/PinNamesVar.h | 18 ---------------- .../STM32F0xx/F031C(4-6)T/PeripheralPins.c | 2 +- variants/STM32F0xx/F031C(4-6)T/PinNamesVar.h | 18 ---------------- .../F031E6Y_F038E6Y/PeripheralPins.c | 2 +- .../STM32F0xx/F031E6Y_F038E6Y/PinNamesVar.h | 21 ------------------- .../STM32F0xx/F031F(4-6)P/PeripheralPins.c | 2 +- variants/STM32F0xx/F031F(4-6)P/PinNamesVar.h | 21 ------------------- .../STM32F0xx/F031G(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F031G(4-6)U/PinNamesVar.h | 21 ------------------- .../STM32F0xx/F031K(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F031K(4-6)U/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F031K6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F031K6T/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F038C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F038C6T/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F038F6P/PeripheralPins.c | 2 +- variants/STM32F0xx/F038F6P/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F038G6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F038G6U/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F038K6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F038K6U/PinNamesVar.h | 21 ------------------- .../F042C(4-6)(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F042C(4-6)(T-U)/PinNamesVar.h | 3 --- .../STM32F0xx/F042F(4-6)P/PeripheralPins.c | 2 +- variants/STM32F0xx/F042F(4-6)P/PinNamesVar.h | 12 ----------- .../STM32F0xx/F042G(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F042G(4-6)U/PinNamesVar.h | 6 ------ .../STM32F0xx/F042K(4-6)T/PeripheralPins.c | 2 +- variants/STM32F0xx/F042K(4-6)T/PinNamesVar.h | 6 ------ .../STM32F0xx/F042K(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F042K(4-6)U/PinNamesVar.h | 6 ------ variants/STM32F0xx/F042T6Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F042T6Y/PinNamesVar.h | 6 ------ variants/STM32F0xx/F048C6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F048C6U/PinNamesVar.h | 3 --- variants/STM32F0xx/F048G6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F048G6U/PinNamesVar.h | 6 ------ variants/STM32F0xx/F048T6Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F048T6Y/PinNamesVar.h | 6 ------ .../STM32F0xx/F051C4(T-U)/PeripheralPins.c | 2 +- variants/STM32F0xx/F051C4(T-U)/PinNamesVar.h | 18 ---------------- .../STM32F0xx/F051C6(T-U)/PeripheralPins.c | 2 +- variants/STM32F0xx/F051C6(T-U)/PinNamesVar.h | 18 ---------------- .../STM32F0xx/F051C8(T-U)/PeripheralPins.c | 2 +- variants/STM32F0xx/F051C8(T-U)/PinNamesVar.h | 18 ---------------- .../STM32F0xx/F051K(6-8)T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K(6-8)T/PinNamesVar.h | 21 ------------------- .../STM32F0xx/F051K(6-8)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K(6-8)U/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F051K4T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K4T/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F051K4U/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K4U/PinNamesVar.h | 21 ------------------- variants/STM32F0xx/F051R4T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R4T/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F051R6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R6T/PinNamesVar.h | 18 ---------------- .../STM32F0xx/F051R8(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R8(H-T)/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F051T8Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F051T8Y/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F058C8U/PeripheralPins.c | 2 +- variants/STM32F0xx/F058C8U/PinNamesVar.h | 18 ---------------- .../STM32F0xx/F058R8(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F058R8(H-T)/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F058T8Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F058T8Y/PinNamesVar.h | 18 ---------------- variants/STM32F0xx/F070C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F070C6T/PinNamesVar.h | 3 --- variants/STM32F0xx/F070CBT/PeripheralPins.c | 2 +- variants/STM32F0xx/F070CBT/PinNamesVar.h | 3 --- variants/STM32F0xx/F070F6P/PeripheralPins.c | 2 +- variants/STM32F0xx/F070F6P/PinNamesVar.h | 12 ----------- variants/STM32F0xx/F070RBT/PeripheralPins.c | 2 +- variants/STM32F0xx/F070RBT/PinNamesVar.h | 3 --- .../PeripheralPins.c | 2 +- .../F071C8(T-U)_F071CB(T-U-Y)/PinNamesVar.h | 3 --- variants/STM32F0xx/F071RBT/PeripheralPins.c | 2 +- variants/STM32F0xx/F071RBT/PinNamesVar.h | 3 --- .../F071V(8-B)(H-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F072C8(T-U)_F072CB(T-U-Y)/PinNamesVar.h | 3 --- .../F072R8T_F072RB(H-I-T)/PeripheralPins.c | 2 +- .../F072R8T_F072RB(H-I-T)/PinNamesVar.h | 3 --- .../F072V(8-B)(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c | 2 +- .../STM32F0xx/F078CB(T-U-Y)/PinNamesVar.h | 3 --- .../STM32F0xx/F078RB(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F078RB(H-T)/PinNamesVar.h | 3 --- .../STM32F0xx/F078VB(H-T)/PeripheralPins.c | 2 +- .../F091C(B-C)(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F091C(B-C)(T-U)/PinNamesVar.h | 3 --- .../F091RBT_F091RC(H-T-Y)/PeripheralPins.c | 2 +- .../F091RBT_F091RC(H-T-Y)/PinNamesVar.h | 3 --- .../F091VBT_F091VC(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F098CC(T-U)/PeripheralPins.c | 2 +- variants/STM32F0xx/F098CC(T-U)/PinNamesVar.h | 3 --- .../STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c | 2 +- .../STM32F0xx/F098RC(H-T-Y)/PinNamesVar.h | 3 --- .../STM32F0xx/F098VC(H-T)/PeripheralPins.c | 2 +- 113 files changed, 59 insertions(+), 764 deletions(-) diff --git a/variants/STM32F0xx/F030C6T/PeripheralPins.c b/variants/STM32F0xx/F030C6T/PeripheralPins.c index b5bee0a5fa..68cb3a1a3a 100644 --- a/variants/STM32F0xx/F030C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F030C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030C6Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030C6T/PinNamesVar.h b/variants/STM32F0xx/F030C6T/PinNamesVar.h index a13e41d07b..a1b4626ee4 100644 --- a/variants/STM32F0xx/F030C6T/PinNamesVar.h +++ b/variants/STM32F0xx/F030C6T/PinNamesVar.h @@ -14,23 +14,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F030C8T/PeripheralPins.c b/variants/STM32F0xx/F030C8T/PeripheralPins.c index 673300e74d..b53113dbaa 100644 --- a/variants/STM32F0xx/F030C8T/PeripheralPins.c +++ b/variants/STM32F0xx/F030C8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030C8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030C8T/PinNamesVar.h b/variants/STM32F0xx/F030C8T/PinNamesVar.h index ef45533918..ae05c17705 100644 --- a/variants/STM32F0xx/F030C8T/PinNamesVar.h +++ b/variants/STM32F0xx/F030C8T/PinNamesVar.h @@ -17,23 +17,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F030CCT/PeripheralPins.c b/variants/STM32F0xx/F030CCT/PeripheralPins.c index e7d35c75cf..21a30ddcde 100644 --- a/variants/STM32F0xx/F030CCT/PeripheralPins.c +++ b/variants/STM32F0xx/F030CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030CCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030CCT/PinNamesVar.h b/variants/STM32F0xx/F030CCT/PinNamesVar.h index ef45533918..ae05c17705 100644 --- a/variants/STM32F0xx/F030CCT/PinNamesVar.h +++ b/variants/STM32F0xx/F030CCT/PinNamesVar.h @@ -17,23 +17,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F030F4P/PeripheralPins.c b/variants/STM32F0xx/F030F4P/PeripheralPins.c index a0893cf235..95eed600cc 100644 --- a/variants/STM32F0xx/F030F4P/PeripheralPins.c +++ b/variants/STM32F0xx/F030F4P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030F4Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030F4P/PinNamesVar.h b/variants/STM32F0xx/F030F4P/PinNamesVar.h index dd27a1ffa5..62661c4e7d 100644 --- a/variants/STM32F0xx/F030F4P/PinNamesVar.h +++ b/variants/STM32F0xx/F030F4P/PinNamesVar.h @@ -10,26 +10,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F030K6T/PeripheralPins.c b/variants/STM32F0xx/F030K6T/PeripheralPins.c index e3a2157a07..d2bbfe29b0 100644 --- a/variants/STM32F0xx/F030K6T/PeripheralPins.c +++ b/variants/STM32F0xx/F030K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030K6Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030K6T/PinNamesVar.h b/variants/STM32F0xx/F030K6T/PinNamesVar.h index 6de379b4e0..e95d1e8c82 100644 --- a/variants/STM32F0xx/F030K6T/PinNamesVar.h +++ b/variants/STM32F0xx/F030K6T/PinNamesVar.h @@ -11,26 +11,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F030R8T/PeripheralPins.c b/variants/STM32F0xx/F030R8T/PeripheralPins.c index fed5417628..1b0f07f045 100644 --- a/variants/STM32F0xx/F030R8T/PeripheralPins.c +++ b/variants/STM32F0xx/F030R8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030R8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030R8T/PinNamesVar.h b/variants/STM32F0xx/F030R8T/PinNamesVar.h index ef45533918..ae05c17705 100644 --- a/variants/STM32F0xx/F030R8T/PinNamesVar.h +++ b/variants/STM32F0xx/F030R8T/PinNamesVar.h @@ -17,23 +17,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F030RCT/PeripheralPins.c b/variants/STM32F0xx/F030RCT/PeripheralPins.c index 91dbb62296..f18598af2c 100644 --- a/variants/STM32F0xx/F030RCT/PeripheralPins.c +++ b/variants/STM32F0xx/F030RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030RCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030RCT/PinNamesVar.h b/variants/STM32F0xx/F030RCT/PinNamesVar.h index 461ba5d5de..56765edfde 100644 --- a/variants/STM32F0xx/F030RCT/PinNamesVar.h +++ b/variants/STM32F0xx/F030RCT/PinNamesVar.h @@ -19,23 +19,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c b/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c index 8c76e43b62..ebcda8d92d 100644 --- a/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c +++ b/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031C(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031C(4-6)T/PinNamesVar.h b/variants/STM32F0xx/F031C(4-6)T/PinNamesVar.h index a13e41d07b..a1b4626ee4 100644 --- a/variants/STM32F0xx/F031C(4-6)T/PinNamesVar.h +++ b/variants/STM32F0xx/F031C(4-6)T/PinNamesVar.h @@ -14,23 +14,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c b/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c index ab4f1861f8..41f440721c 100644 --- a/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031E6Yx.xml, STM32F038E6Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031E6Y_F038E6Y/PinNamesVar.h b/variants/STM32F0xx/F031E6Y_F038E6Y/PinNamesVar.h index 6de379b4e0..e95d1e8c82 100644 --- a/variants/STM32F0xx/F031E6Y_F038E6Y/PinNamesVar.h +++ b/variants/STM32F0xx/F031E6Y_F038E6Y/PinNamesVar.h @@ -11,26 +11,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c b/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c index 617c4c9fc1..6838ec8f62 100644 --- a/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c +++ b/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031F(4-6)Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031F(4-6)P/PinNamesVar.h b/variants/STM32F0xx/F031F(4-6)P/PinNamesVar.h index dd27a1ffa5..62661c4e7d 100644 --- a/variants/STM32F0xx/F031F(4-6)P/PinNamesVar.h +++ b/variants/STM32F0xx/F031F(4-6)P/PinNamesVar.h @@ -10,26 +10,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c index f94613802b..46e1eabc2f 100644 --- a/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031G(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031G(4-6)U/PinNamesVar.h b/variants/STM32F0xx/F031G(4-6)U/PinNamesVar.h index 6de379b4e0..e95d1e8c82 100644 --- a/variants/STM32F0xx/F031G(4-6)U/PinNamesVar.h +++ b/variants/STM32F0xx/F031G(4-6)U/PinNamesVar.h @@ -11,26 +11,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c index 6219ef3e32..e24e13b124 100644 --- a/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031K(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031K(4-6)U/PinNamesVar.h b/variants/STM32F0xx/F031K(4-6)U/PinNamesVar.h index 6de379b4e0..e95d1e8c82 100644 --- a/variants/STM32F0xx/F031K(4-6)U/PinNamesVar.h +++ b/variants/STM32F0xx/F031K(4-6)U/PinNamesVar.h @@ -11,26 +11,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F031K6T/PeripheralPins.c b/variants/STM32F0xx/F031K6T/PeripheralPins.c index 7c57167bef..e73db9759c 100644 --- a/variants/STM32F0xx/F031K6T/PeripheralPins.c +++ b/variants/STM32F0xx/F031K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031K6Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031K6T/PinNamesVar.h b/variants/STM32F0xx/F031K6T/PinNamesVar.h index 6de379b4e0..e95d1e8c82 100644 --- a/variants/STM32F0xx/F031K6T/PinNamesVar.h +++ b/variants/STM32F0xx/F031K6T/PinNamesVar.h @@ -11,26 +11,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F038C6T/PeripheralPins.c b/variants/STM32F0xx/F038C6T/PeripheralPins.c index 327f4af3d3..be449e0b64 100644 --- a/variants/STM32F0xx/F038C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F038C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038C6Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038C6T/PinNamesVar.h b/variants/STM32F0xx/F038C6T/PinNamesVar.h index a13e41d07b..a1b4626ee4 100644 --- a/variants/STM32F0xx/F038C6T/PinNamesVar.h +++ b/variants/STM32F0xx/F038C6T/PinNamesVar.h @@ -14,23 +14,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F038F6P/PeripheralPins.c b/variants/STM32F0xx/F038F6P/PeripheralPins.c index dfc044980a..2f31b2580b 100644 --- a/variants/STM32F0xx/F038F6P/PeripheralPins.c +++ b/variants/STM32F0xx/F038F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038F6Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038F6P/PinNamesVar.h b/variants/STM32F0xx/F038F6P/PinNamesVar.h index ea959a0877..bb1cb2a673 100644 --- a/variants/STM32F0xx/F038F6P/PinNamesVar.h +++ b/variants/STM32F0xx/F038F6P/PinNamesVar.h @@ -8,26 +8,5 @@ PA_7_ALT3 = PA_7 | ALT3, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F038G6U/PeripheralPins.c b/variants/STM32F0xx/F038G6U/PeripheralPins.c index 8fa00d757f..d1cb0b83de 100644 --- a/variants/STM32F0xx/F038G6U/PeripheralPins.c +++ b/variants/STM32F0xx/F038G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038G6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038G6U/PinNamesVar.h b/variants/STM32F0xx/F038G6U/PinNamesVar.h index 8899b9f2b4..cab1290980 100644 --- a/variants/STM32F0xx/F038G6U/PinNamesVar.h +++ b/variants/STM32F0xx/F038G6U/PinNamesVar.h @@ -9,26 +9,5 @@ PB_0_ALT1 = PB_0 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F038K6U/PeripheralPins.c b/variants/STM32F0xx/F038K6U/PeripheralPins.c index a4961e594e..5d3c5cb947 100644 --- a/variants/STM32F0xx/F038K6U/PeripheralPins.c +++ b/variants/STM32F0xx/F038K6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038K6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038K6U/PinNamesVar.h b/variants/STM32F0xx/F038K6U/PinNamesVar.h index 6de379b4e0..e95d1e8c82 100644 --- a/variants/STM32F0xx/F038K6U/PinNamesVar.h +++ b/variants/STM32F0xx/F038K6U/PinNamesVar.h @@ -11,26 +11,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c b/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c index 3937aa0bf5..6e082c9957 100644 --- a/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042C(4-6)Tx.xml, STM32F042C(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042C(4-6)(T-U)/PinNamesVar.h b/variants/STM32F0xx/F042C(4-6)(T-U)/PinNamesVar.h index 4f234fd328..d32f50d972 100644 --- a/variants/STM32F0xx/F042C(4-6)(T-U)/PinNamesVar.h +++ b/variants/STM32F0xx/F042C(4-6)(T-U)/PinNamesVar.h @@ -29,9 +29,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c b/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c index 7f355ded49..c800641241 100644 --- a/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c +++ b/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042F4Px.xml, STM32F042F6Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042F(4-6)P/PinNamesVar.h b/variants/STM32F0xx/F042F(4-6)P/PinNamesVar.h index 8b4168f3d7..639fbcea47 100644 --- a/variants/STM32F0xx/F042F(4-6)P/PinNamesVar.h +++ b/variants/STM32F0xx/F042F(4-6)P/PinNamesVar.h @@ -23,18 +23,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c index bc5fbb5af4..45a8cabb15 100644 --- a/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042G(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042G(4-6)U/PinNamesVar.h b/variants/STM32F0xx/F042G(4-6)U/PinNamesVar.h index 2bebd84fdf..24388f020b 100644 --- a/variants/STM32F0xx/F042G(4-6)U/PinNamesVar.h +++ b/variants/STM32F0xx/F042G(4-6)U/PinNamesVar.h @@ -30,12 +30,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c b/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c index 3f23075b65..dcf21bcfc2 100644 --- a/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c +++ b/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042K(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042K(4-6)T/PinNamesVar.h b/variants/STM32F0xx/F042K(4-6)T/PinNamesVar.h index 35eeff6eac..6c940c38b2 100644 --- a/variants/STM32F0xx/F042K(4-6)T/PinNamesVar.h +++ b/variants/STM32F0xx/F042K(4-6)T/PinNamesVar.h @@ -26,12 +26,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c index 9753539ba0..bdc0791665 100644 --- a/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042K(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042K(4-6)U/PinNamesVar.h b/variants/STM32F0xx/F042K(4-6)U/PinNamesVar.h index 35eeff6eac..6c940c38b2 100644 --- a/variants/STM32F0xx/F042K(4-6)U/PinNamesVar.h +++ b/variants/STM32F0xx/F042K(4-6)U/PinNamesVar.h @@ -26,12 +26,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F042T6Y/PeripheralPins.c b/variants/STM32F0xx/F042T6Y/PeripheralPins.c index 2dd74bc2c6..194966adc0 100644 --- a/variants/STM32F0xx/F042T6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F042T6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042T6Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042T6Y/PinNamesVar.h b/variants/STM32F0xx/F042T6Y/PinNamesVar.h index 65c322e641..47155e20dd 100644 --- a/variants/STM32F0xx/F042T6Y/PinNamesVar.h +++ b/variants/STM32F0xx/F042T6Y/PinNamesVar.h @@ -26,12 +26,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F048C6U/PeripheralPins.c b/variants/STM32F0xx/F048C6U/PeripheralPins.c index 261a738c51..24d82e7e38 100644 --- a/variants/STM32F0xx/F048C6U/PeripheralPins.c +++ b/variants/STM32F0xx/F048C6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048C6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048C6U/PinNamesVar.h b/variants/STM32F0xx/F048C6U/PinNamesVar.h index 4f234fd328..d32f50d972 100644 --- a/variants/STM32F0xx/F048C6U/PinNamesVar.h +++ b/variants/STM32F0xx/F048C6U/PinNamesVar.h @@ -29,9 +29,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F048G6U/PeripheralPins.c b/variants/STM32F0xx/F048G6U/PeripheralPins.c index f020fc2194..bbcac2dfdf 100644 --- a/variants/STM32F0xx/F048G6U/PeripheralPins.c +++ b/variants/STM32F0xx/F048G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048G6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048G6U/PinNamesVar.h b/variants/STM32F0xx/F048G6U/PinNamesVar.h index 3effd3953f..a51b4156e8 100644 --- a/variants/STM32F0xx/F048G6U/PinNamesVar.h +++ b/variants/STM32F0xx/F048G6U/PinNamesVar.h @@ -28,12 +28,6 @@ PB_0_ALT1 = PB_0 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F048T6Y/PeripheralPins.c b/variants/STM32F0xx/F048T6Y/PeripheralPins.c index d013579daa..7fb5976b5c 100644 --- a/variants/STM32F0xx/F048T6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F048T6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048T6Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048T6Y/PinNamesVar.h b/variants/STM32F0xx/F048T6Y/PinNamesVar.h index 65c322e641..47155e20dd 100644 --- a/variants/STM32F0xx/F048T6Y/PinNamesVar.h +++ b/variants/STM32F0xx/F048T6Y/PinNamesVar.h @@ -26,12 +26,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c index 2e320e966d..b35540c657 100644 --- a/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C4Tx.xml, STM32F051C4Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C4(T-U)/PinNamesVar.h b/variants/STM32F0xx/F051C4(T-U)/PinNamesVar.h index 95eb40c635..2068378618 100644 --- a/variants/STM32F0xx/F051C4(T-U)/PinNamesVar.h +++ b/variants/STM32F0xx/F051C4(T-U)/PinNamesVar.h @@ -19,23 +19,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c index b59c9005fb..7d9b0c5bfb 100644 --- a/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C6Tx.xml, STM32F051C6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C6(T-U)/PinNamesVar.h b/variants/STM32F0xx/F051C6(T-U)/PinNamesVar.h index 95eb40c635..2068378618 100644 --- a/variants/STM32F0xx/F051C6(T-U)/PinNamesVar.h +++ b/variants/STM32F0xx/F051C6(T-U)/PinNamesVar.h @@ -19,23 +19,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c index e5bb6cb596..7aadb13a7a 100644 --- a/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C8Tx.xml, STM32F051C8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C8(T-U)/PinNamesVar.h b/variants/STM32F0xx/F051C8(T-U)/PinNamesVar.h index 95eb40c635..2068378618 100644 --- a/variants/STM32F0xx/F051C8(T-U)/PinNamesVar.h +++ b/variants/STM32F0xx/F051C8(T-U)/PinNamesVar.h @@ -19,23 +19,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c b/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c index bcc4a666de..c469e83a44 100644 --- a/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c +++ b/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K6Tx.xml, STM32F051K8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K(6-8)T/PinNamesVar.h b/variants/STM32F0xx/F051K(6-8)T/PinNamesVar.h index d7fcb43321..8c47a96e68 100644 --- a/variants/STM32F0xx/F051K(6-8)T/PinNamesVar.h +++ b/variants/STM32F0xx/F051K(6-8)T/PinNamesVar.h @@ -13,26 +13,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c b/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c index 9a1daf72e2..f77e06a235 100644 --- a/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c +++ b/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K6Ux.xml, STM32F051K8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K(6-8)U/PinNamesVar.h b/variants/STM32F0xx/F051K(6-8)U/PinNamesVar.h index d7fcb43321..8c47a96e68 100644 --- a/variants/STM32F0xx/F051K(6-8)U/PinNamesVar.h +++ b/variants/STM32F0xx/F051K(6-8)U/PinNamesVar.h @@ -13,26 +13,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051K4T/PeripheralPins.c b/variants/STM32F0xx/F051K4T/PeripheralPins.c index 7cd36d3085..c4c98ab4ca 100644 --- a/variants/STM32F0xx/F051K4T/PeripheralPins.c +++ b/variants/STM32F0xx/F051K4T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K4Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K4T/PinNamesVar.h b/variants/STM32F0xx/F051K4T/PinNamesVar.h index d7fcb43321..8c47a96e68 100644 --- a/variants/STM32F0xx/F051K4T/PinNamesVar.h +++ b/variants/STM32F0xx/F051K4T/PinNamesVar.h @@ -13,26 +13,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051K4U/PeripheralPins.c b/variants/STM32F0xx/F051K4U/PeripheralPins.c index afa0a97bf4..5dc8fe18e3 100644 --- a/variants/STM32F0xx/F051K4U/PeripheralPins.c +++ b/variants/STM32F0xx/F051K4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K4Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K4U/PinNamesVar.h b/variants/STM32F0xx/F051K4U/PinNamesVar.h index d7fcb43321..8c47a96e68 100644 --- a/variants/STM32F0xx/F051K4U/PinNamesVar.h +++ b/variants/STM32F0xx/F051K4U/PinNamesVar.h @@ -13,26 +13,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051R4T/PeripheralPins.c b/variants/STM32F0xx/F051R4T/PeripheralPins.c index 46c931a678..0d0b425199 100644 --- a/variants/STM32F0xx/F051R4T/PeripheralPins.c +++ b/variants/STM32F0xx/F051R4T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R4Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R4T/PinNamesVar.h b/variants/STM32F0xx/F051R4T/PinNamesVar.h index 95eb40c635..2068378618 100644 --- a/variants/STM32F0xx/F051R4T/PinNamesVar.h +++ b/variants/STM32F0xx/F051R4T/PinNamesVar.h @@ -19,23 +19,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051R6T/PeripheralPins.c b/variants/STM32F0xx/F051R6T/PeripheralPins.c index b6edabef0a..1906e1a9a8 100644 --- a/variants/STM32F0xx/F051R6T/PeripheralPins.c +++ b/variants/STM32F0xx/F051R6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R6Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R6T/PinNamesVar.h b/variants/STM32F0xx/F051R6T/PinNamesVar.h index 95eb40c635..2068378618 100644 --- a/variants/STM32F0xx/F051R6T/PinNamesVar.h +++ b/variants/STM32F0xx/F051R6T/PinNamesVar.h @@ -19,23 +19,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c b/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c index fc39c88960..2b4a05213e 100644 --- a/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R8Hx.xml, STM32F051R8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R8(H-T)/PinNamesVar.h b/variants/STM32F0xx/F051R8(H-T)/PinNamesVar.h index 95eb40c635..2068378618 100644 --- a/variants/STM32F0xx/F051R8(H-T)/PinNamesVar.h +++ b/variants/STM32F0xx/F051R8(H-T)/PinNamesVar.h @@ -19,23 +19,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F051T8Y/PeripheralPins.c b/variants/STM32F0xx/F051T8Y/PeripheralPins.c index 5fbd352ff9..efb84515a0 100644 --- a/variants/STM32F0xx/F051T8Y/PeripheralPins.c +++ b/variants/STM32F0xx/F051T8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051T8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051T8Y/PinNamesVar.h b/variants/STM32F0xx/F051T8Y/PinNamesVar.h index d1aba32d3c..618b9ebeed 100644 --- a/variants/STM32F0xx/F051T8Y/PinNamesVar.h +++ b/variants/STM32F0xx/F051T8Y/PinNamesVar.h @@ -16,23 +16,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F058C8U/PeripheralPins.c b/variants/STM32F0xx/F058C8U/PeripheralPins.c index 220d9ec6ee..523093e3aa 100644 --- a/variants/STM32F0xx/F058C8U/PeripheralPins.c +++ b/variants/STM32F0xx/F058C8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058C8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058C8U/PinNamesVar.h b/variants/STM32F0xx/F058C8U/PinNamesVar.h index 95eb40c635..2068378618 100644 --- a/variants/STM32F0xx/F058C8U/PinNamesVar.h +++ b/variants/STM32F0xx/F058C8U/PinNamesVar.h @@ -19,23 +19,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c b/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c index 88392c5405..a2640c88e6 100644 --- a/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058R8Hx.xml, STM32F058R8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058R8(H-T)/PinNamesVar.h b/variants/STM32F0xx/F058R8(H-T)/PinNamesVar.h index 95eb40c635..2068378618 100644 --- a/variants/STM32F0xx/F058R8(H-T)/PinNamesVar.h +++ b/variants/STM32F0xx/F058R8(H-T)/PinNamesVar.h @@ -19,23 +19,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F058T8Y/PeripheralPins.c b/variants/STM32F0xx/F058T8Y/PeripheralPins.c index 71f857c1f8..0d17079bd9 100644 --- a/variants/STM32F0xx/F058T8Y/PeripheralPins.c +++ b/variants/STM32F0xx/F058T8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058T8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058T8Y/PinNamesVar.h b/variants/STM32F0xx/F058T8Y/PinNamesVar.h index d1aba32d3c..618b9ebeed 100644 --- a/variants/STM32F0xx/F058T8Y/PinNamesVar.h +++ b/variants/STM32F0xx/F058T8Y/PinNamesVar.h @@ -16,23 +16,5 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F070C6T/PeripheralPins.c b/variants/STM32F0xx/F070C6T/PeripheralPins.c index a4b608f1a9..056ffb08ea 100644 --- a/variants/STM32F0xx/F070C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F070C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070C6Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070C6T/PinNamesVar.h b/variants/STM32F0xx/F070C6T/PinNamesVar.h index c97baae45e..9506478e21 100644 --- a/variants/STM32F0xx/F070C6T/PinNamesVar.h +++ b/variants/STM32F0xx/F070C6T/PinNamesVar.h @@ -29,9 +29,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F070CBT/PeripheralPins.c b/variants/STM32F0xx/F070CBT/PeripheralPins.c index 19c138ed95..d28c74be73 100644 --- a/variants/STM32F0xx/F070CBT/PeripheralPins.c +++ b/variants/STM32F0xx/F070CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070CBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070CBT/PinNamesVar.h b/variants/STM32F0xx/F070CBT/PinNamesVar.h index fb768daa09..6803349115 100644 --- a/variants/STM32F0xx/F070CBT/PinNamesVar.h +++ b/variants/STM32F0xx/F070CBT/PinNamesVar.h @@ -32,9 +32,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F070F6P/PeripheralPins.c b/variants/STM32F0xx/F070F6P/PeripheralPins.c index f8f95efd77..d3e181b96a 100644 --- a/variants/STM32F0xx/F070F6P/PeripheralPins.c +++ b/variants/STM32F0xx/F070F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070F6Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070F6P/PinNamesVar.h b/variants/STM32F0xx/F070F6P/PinNamesVar.h index 8b4168f3d7..639fbcea47 100644 --- a/variants/STM32F0xx/F070F6P/PinNamesVar.h +++ b/variants/STM32F0xx/F070F6P/PinNamesVar.h @@ -23,18 +23,6 @@ PB_1_ALT2 = PB_1 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F070RBT/PeripheralPins.c b/variants/STM32F0xx/F070RBT/PeripheralPins.c index 75db6de3b6..7d547466fc 100644 --- a/variants/STM32F0xx/F070RBT/PeripheralPins.c +++ b/variants/STM32F0xx/F070RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070RBT/PinNamesVar.h b/variants/STM32F0xx/F070RBT/PinNamesVar.h index 72c216674f..4846471eff 100644 --- a/variants/STM32F0xx/F070RBT/PinNamesVar.h +++ b/variants/STM32F0xx/F070RBT/PinNamesVar.h @@ -34,9 +34,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c index 5f45f39be1..85362a1829 100644 --- a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F071C(8-B)Tx.xml, STM32F071C(8-B)Ux.xml * STM32F071CBYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PinNamesVar.h b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PinNamesVar.h index 75da9cbaac..c2dd56a071 100644 --- a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PinNamesVar.h +++ b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PinNamesVar.h @@ -35,8 +35,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F071RBT/PeripheralPins.c b/variants/STM32F0xx/F071RBT/PeripheralPins.c index b4e758ba02..d926a3117f 100644 --- a/variants/STM32F0xx/F071RBT/PeripheralPins.c +++ b/variants/STM32F0xx/F071RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F071RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071RBT/PinNamesVar.h b/variants/STM32F0xx/F071RBT/PinNamesVar.h index bb683d043a..76979a9954 100644 --- a/variants/STM32F0xx/F071RBT/PinNamesVar.h +++ b/variants/STM32F0xx/F071RBT/PinNamesVar.h @@ -37,8 +37,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c b/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c index c8c49e81b4..1b263ace9b 100644 --- a/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F071V(8-B)Hx.xml, STM32F071V(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c index c9714e5691..b625c583b0 100644 --- a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F072C(8-B)Tx.xml, STM32F072C(8-B)Ux.xml * STM32F072CBYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PinNamesVar.h b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PinNamesVar.h index ac4ec654be..832956e0d9 100644 --- a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PinNamesVar.h +++ b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PinNamesVar.h @@ -35,9 +35,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c index 3b6552bd5b..976935eafe 100644 --- a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F072R(8-B)Tx.xml, STM32F072RBHx.xml * STM32F072RBIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PinNamesVar.h b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PinNamesVar.h index 4e012676ee..058398ce50 100644 --- a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PinNamesVar.h +++ b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PinNamesVar.h @@ -37,9 +37,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c b/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c index 0ccd9fe108..95cdf41b9c 100644 --- a/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F072V(8-B)Hx.xml, STM32F072V(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c index 2b1424ccaf..707c1e93ea 100644 --- a/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F078CBTx.xml, STM32F078CBUx.xml * STM32F078CBYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078CB(T-U-Y)/PinNamesVar.h b/variants/STM32F0xx/F078CB(T-U-Y)/PinNamesVar.h index ac4ec654be..832956e0d9 100644 --- a/variants/STM32F0xx/F078CB(T-U-Y)/PinNamesVar.h +++ b/variants/STM32F0xx/F078CB(T-U-Y)/PinNamesVar.h @@ -35,9 +35,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c b/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c index 570901ff62..a662b2ee1a 100644 --- a/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F078RBHx.xml, STM32F078RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078RB(H-T)/PinNamesVar.h b/variants/STM32F0xx/F078RB(H-T)/PinNamesVar.h index 4e012676ee..058398ce50 100644 --- a/variants/STM32F0xx/F078RB(H-T)/PinNamesVar.h +++ b/variants/STM32F0xx/F078RB(H-T)/PinNamesVar.h @@ -37,9 +37,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c b/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c index 63d1f5eeb8..7bbba5203f 100644 --- a/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F078VBHx.xml, STM32F078VBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c b/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c index d065dfa81f..f5b8009f25 100644 --- a/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F091C(B-C)Tx.xml, STM32F091C(B-C)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091C(B-C)(T-U)/PinNamesVar.h b/variants/STM32F0xx/F091C(B-C)(T-U)/PinNamesVar.h index 75da9cbaac..c2dd56a071 100644 --- a/variants/STM32F0xx/F091C(B-C)(T-U)/PinNamesVar.h +++ b/variants/STM32F0xx/F091C(B-C)(T-U)/PinNamesVar.h @@ -35,8 +35,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c index d664b2f7f6..cdb87bbfdb 100644 --- a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F091R(B-C)Tx.xml, STM32F091RCHx.xml * STM32F091RCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PinNamesVar.h b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PinNamesVar.h index 0309f13ac1..24dabc2ec2 100644 --- a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PinNamesVar.h +++ b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PinNamesVar.h @@ -39,8 +39,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c b/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c index b171637515..13290f0c08 100644 --- a/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F091V(B-C)Tx.xml, STM32F091VCHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c b/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c index a7abdcb15f..ba41226ec2 100644 --- a/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F098CCTx.xml, STM32F098CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098CC(T-U)/PinNamesVar.h b/variants/STM32F0xx/F098CC(T-U)/PinNamesVar.h index 75da9cbaac..c2dd56a071 100644 --- a/variants/STM32F0xx/F098CC(T-U)/PinNamesVar.h +++ b/variants/STM32F0xx/F098CC(T-U)/PinNamesVar.h @@ -35,8 +35,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c b/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c index f865f452bd..996353cbae 100644 --- a/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F098RCHx.xml, STM32F098RCTx.xml * STM32F098RCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098RC(H-T-Y)/PinNamesVar.h b/variants/STM32F0xx/F098RC(H-T-Y)/PinNamesVar.h index 0309f13ac1..24dabc2ec2 100644 --- a/variants/STM32F0xx/F098RC(H-T-Y)/PinNamesVar.h +++ b/variants/STM32F0xx/F098RC(H-T-Y)/PinNamesVar.h @@ -39,8 +39,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c b/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c index 7ebf07931f..7202a65c11 100644 --- a/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F098VCHx.xml, STM32F098VCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" From 89880911ee403060877111e4c37a4c8052c1b52f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:25:59 +0100 Subject: [PATCH 040/141] chore(f1): update variant after script update Signed-off-by: Frederic Pillon --- .../STM32F1xx/F100C(4-6)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F100C(4-6)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100C(8-B)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F100C(8-B)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100R(4-6)H/PeripheralPins.c | 2 +- variants/STM32F1xx/F100R(4-6)H/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100R(4-6)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F100R(4-6)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100R(8-B)H/PeripheralPins.c | 2 +- variants/STM32F1xx/F100R(8-B)H/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100R(8-B)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F100R(8-B)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(C-D-E)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100V(8-B)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F100V(8-B)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100V(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100V(C-D-E)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100Z(C-D-E)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101C(4-6)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101C(4-6)T/PinNamesVar.h | 21 ------------------- .../F101C(8-B)(T-U)/PeripheralPins.c | 2 +- .../STM32F1xx/F101C(8-B)(T-U)/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101R(4-6)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101R(4-6)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101R(8-B)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101R(8-B)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(C-D-E)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101R(F-G)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101R(F-G)T/PinNamesVar.h | 21 ------------------- variants/STM32F1xx/F101RBH/PeripheralPins.c | 2 +- variants/STM32F1xx/F101RBH/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101T(4-6)U/PeripheralPins.c | 2 +- variants/STM32F1xx/F101T(4-6)U/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101T(8-B)U/PeripheralPins.c | 2 +- variants/STM32F1xx/F101T(8-B)U/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101V(8-B)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101V(8-B)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101V(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(C-D-E)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101V(F-G)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101V(F-G)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101Z(C-D-E)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F101Z(F-G)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101Z(F-G)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F102C(4-6)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F102C(4-6)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F102C(8-B)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F102C(8-B)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F102R(4-6)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F102R(4-6)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F102R(8-B)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F102R(8-B)T/PinNamesVar.h | 21 ------------------- .../F103C4T_F103C6(T-U)/PeripheralPins.c | 2 +- .../F103C4T_F103C6(T-U)/PinNamesVar.h | 21 ------------------- .../F103C8T_F103CB(T-U)/PeripheralPins.c | 2 +- .../F103C8T_F103CB(T-U)/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103R(4-6)H/PeripheralPins.c | 2 +- variants/STM32F1xx/F103R(4-6)H/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103R(4-6)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F103R(4-6)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103R(8-B)H/PeripheralPins.c | 2 +- variants/STM32F1xx/F103R(8-B)H/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103R(8-B)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F103R(8-B)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(C-D-E)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(C-D-E)Y/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103R(F-G)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F103R(F-G)T/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103T(4-6)U/PeripheralPins.c | 2 +- variants/STM32F1xx/F103T(4-6)U/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103T(8-B)U/PeripheralPins.c | 2 +- variants/STM32F1xx/F103T(8-B)U/PinNamesVar.h | 21 ------------------- .../F103V(C-D-E)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F103V(C-D-E)(H-T)/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F103V(F-G)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F103V(F-G)T/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../F103V8(H-T)_F103VB(H-I-T)/PinNamesVar.h | 21 ------------------- .../F103Z(C-D-E)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F103Z(C-D-E)(H-T)/PinNamesVar.h | 21 ------------------- .../F103Z(F-G)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F103Z(F-G)(H-T)/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F105R(8-B-C)T/PeripheralPins.c | 2 +- .../STM32F1xx/F105R(8-B-C)T/PinNamesVar.h | 21 ------------------- .../F105V(8-B)(H-T)_F105VCT/PeripheralPins.c | 2 +- .../F105V(8-B)(H-T)_F105VCT/PinNamesVar.h | 21 ------------------- .../STM32F1xx/F107R(B-C)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F107R(B-C)T/PinNamesVar.h | 21 ------------------- .../F107VBT_F107VC(H-T)/PeripheralPins.c | 2 +- .../F107VBT_F107VC(H-T)/PinNamesVar.h | 21 ------------------- 96 files changed, 48 insertions(+), 1056 deletions(-) diff --git a/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c index 963e7b0d2b..550507b39f 100644 --- a/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100C(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100C(4-6)T/PinNamesVar.h b/variants/STM32F1xx/F100C(4-6)T/PinNamesVar.h index 18654e18ab..24cada215f 100644 --- a/variants/STM32F1xx/F100C(4-6)T/PinNamesVar.h +++ b/variants/STM32F1xx/F100C(4-6)T/PinNamesVar.h @@ -28,26 +28,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c index a131a747ae..486ba8cfe9 100644 --- a/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100C(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100C(8-B)T/PinNamesVar.h b/variants/STM32F1xx/F100C(8-B)T/PinNamesVar.h index 2267d566cc..0456718958 100644 --- a/variants/STM32F1xx/F100C(8-B)T/PinNamesVar.h +++ b/variants/STM32F1xx/F100C(8-B)T/PinNamesVar.h @@ -33,26 +33,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c b/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c index 021342f660..ad75ed6248 100644 --- a/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(4-6)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(4-6)H/PinNamesVar.h b/variants/STM32F1xx/F100R(4-6)H/PinNamesVar.h index 18654e18ab..24cada215f 100644 --- a/variants/STM32F1xx/F100R(4-6)H/PinNamesVar.h +++ b/variants/STM32F1xx/F100R(4-6)H/PinNamesVar.h @@ -28,26 +28,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c index 5245757ae6..24cb652f93 100644 --- a/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(4-6)T/PinNamesVar.h b/variants/STM32F1xx/F100R(4-6)T/PinNamesVar.h index 18654e18ab..24cada215f 100644 --- a/variants/STM32F1xx/F100R(4-6)T/PinNamesVar.h +++ b/variants/STM32F1xx/F100R(4-6)T/PinNamesVar.h @@ -28,26 +28,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c b/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c index 55fb39bb96..b3f7802f58 100644 --- a/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(8-B)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(8-B)H/PinNamesVar.h b/variants/STM32F1xx/F100R(8-B)H/PinNamesVar.h index 2267d566cc..0456718958 100644 --- a/variants/STM32F1xx/F100R(8-B)H/PinNamesVar.h +++ b/variants/STM32F1xx/F100R(8-B)H/PinNamesVar.h @@ -33,26 +33,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c index 80469ff3ce..b0e3a0e8fa 100644 --- a/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(8-B)T/PinNamesVar.h b/variants/STM32F1xx/F100R(8-B)T/PinNamesVar.h index 2267d566cc..0456718958 100644 --- a/variants/STM32F1xx/F100R(8-B)T/PinNamesVar.h +++ b/variants/STM32F1xx/F100R(8-B)T/PinNamesVar.h @@ -33,26 +33,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c index e244636d97..6b0ddc7270 100644 --- a/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(C-D-E)T/PinNamesVar.h b/variants/STM32F1xx/F100R(C-D-E)T/PinNamesVar.h index 71a4df6823..baadb2ac01 100644 --- a/variants/STM32F1xx/F100R(C-D-E)T/PinNamesVar.h +++ b/variants/STM32F1xx/F100R(C-D-E)T/PinNamesVar.h @@ -45,26 +45,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c index 1dfc8fe064..174fa0db5c 100644 --- a/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100V(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100V(8-B)T/PinNamesVar.h b/variants/STM32F1xx/F100V(8-B)T/PinNamesVar.h index 2267d566cc..0456718958 100644 --- a/variants/STM32F1xx/F100V(8-B)T/PinNamesVar.h +++ b/variants/STM32F1xx/F100V(8-B)T/PinNamesVar.h @@ -33,26 +33,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c index b51cafb646..aac0e57b40 100644 --- a/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100V(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100V(C-D-E)T/PinNamesVar.h b/variants/STM32F1xx/F100V(C-D-E)T/PinNamesVar.h index 71a4df6823..baadb2ac01 100644 --- a/variants/STM32F1xx/F100V(C-D-E)T/PinNamesVar.h +++ b/variants/STM32F1xx/F100V(C-D-E)T/PinNamesVar.h @@ -45,26 +45,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c index 355bccadab..6564972d93 100644 --- a/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100Z(C-D-E)T/PinNamesVar.h b/variants/STM32F1xx/F100Z(C-D-E)T/PinNamesVar.h index 71a4df6823..baadb2ac01 100644 --- a/variants/STM32F1xx/F100Z(C-D-E)T/PinNamesVar.h +++ b/variants/STM32F1xx/F100Z(C-D-E)T/PinNamesVar.h @@ -45,26 +45,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c index fa26bca895..c0e9dd3c31 100644 --- a/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101C(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101C(4-6)T/PinNamesVar.h b/variants/STM32F1xx/F101C(4-6)T/PinNamesVar.h index d4261fa71f..86d8502f23 100644 --- a/variants/STM32F1xx/F101C(4-6)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101C(4-6)T/PinNamesVar.h @@ -14,26 +14,5 @@ PB_11_ALT1 = PB_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c b/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c index f96c01bd82..1a141c3b61 100644 --- a/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101C(8-B)Tx.xml, STM32F101C(8-B)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101C(8-B)(T-U)/PinNamesVar.h b/variants/STM32F1xx/F101C(8-B)(T-U)/PinNamesVar.h index 2a114fbc77..9dd42eec9c 100644 --- a/variants/STM32F1xx/F101C(8-B)(T-U)/PinNamesVar.h +++ b/variants/STM32F1xx/F101C(8-B)(T-U)/PinNamesVar.h @@ -16,26 +16,5 @@ PB_14_ALT1 = PB_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c index 88c2139dbb..5ca35ec4d0 100644 --- a/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(4-6)T/PinNamesVar.h b/variants/STM32F1xx/F101R(4-6)T/PinNamesVar.h index d4261fa71f..86d8502f23 100644 --- a/variants/STM32F1xx/F101R(4-6)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101R(4-6)T/PinNamesVar.h @@ -14,26 +14,5 @@ PB_11_ALT1 = PB_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c index a05471c98c..a7e4cfae75 100644 --- a/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(8-B)T/PinNamesVar.h b/variants/STM32F1xx/F101R(8-B)T/PinNamesVar.h index 2a114fbc77..9dd42eec9c 100644 --- a/variants/STM32F1xx/F101R(8-B)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101R(8-B)T/PinNamesVar.h @@ -16,26 +16,5 @@ PB_14_ALT1 = PB_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c index dad18db32f..e4b0d01483 100644 --- a/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(C-D-E)T/PinNamesVar.h b/variants/STM32F1xx/F101R(C-D-E)T/PinNamesVar.h index 3eedc0c99b..c4736d590c 100644 --- a/variants/STM32F1xx/F101R(C-D-E)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101R(C-D-E)T/PinNamesVar.h @@ -24,26 +24,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c index 3a56b528d4..0b6ca554d7 100644 --- a/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(F-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(F-G)T/PinNamesVar.h b/variants/STM32F1xx/F101R(F-G)T/PinNamesVar.h index f8fbbe45f0..32a3dd01d5 100644 --- a/variants/STM32F1xx/F101R(F-G)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101R(F-G)T/PinNamesVar.h @@ -30,26 +30,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101RBH/PeripheralPins.c b/variants/STM32F1xx/F101RBH/PeripheralPins.c index 25648e4b17..afb2197a11 100644 --- a/variants/STM32F1xx/F101RBH/PeripheralPins.c +++ b/variants/STM32F1xx/F101RBH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101RBHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101RBH/PinNamesVar.h b/variants/STM32F1xx/F101RBH/PinNamesVar.h index 2a114fbc77..9dd42eec9c 100644 --- a/variants/STM32F1xx/F101RBH/PinNamesVar.h +++ b/variants/STM32F1xx/F101RBH/PinNamesVar.h @@ -16,26 +16,5 @@ PB_14_ALT1 = PB_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c b/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c index 1d5374e0fb..adc3abf6e3 100644 --- a/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c +++ b/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101T(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101T(4-6)U/PinNamesVar.h b/variants/STM32F1xx/F101T(4-6)U/PinNamesVar.h index 9692bea84b..692446e400 100644 --- a/variants/STM32F1xx/F101T(4-6)U/PinNamesVar.h +++ b/variants/STM32F1xx/F101T(4-6)U/PinNamesVar.h @@ -12,26 +12,5 @@ PB_3_ALT1 = PB_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c b/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c index bc55aeb96e..3c46f12b40 100644 --- a/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c +++ b/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101T(8-B)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101T(8-B)U/PinNamesVar.h b/variants/STM32F1xx/F101T(8-B)U/PinNamesVar.h index 9692bea84b..692446e400 100644 --- a/variants/STM32F1xx/F101T(8-B)U/PinNamesVar.h +++ b/variants/STM32F1xx/F101T(8-B)U/PinNamesVar.h @@ -12,26 +12,5 @@ PB_3_ALT1 = PB_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c index 61d7fc8cb2..5db34833bc 100644 --- a/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(8-B)T/PinNamesVar.h b/variants/STM32F1xx/F101V(8-B)T/PinNamesVar.h index 2a114fbc77..9dd42eec9c 100644 --- a/variants/STM32F1xx/F101V(8-B)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101V(8-B)T/PinNamesVar.h @@ -16,26 +16,5 @@ PB_14_ALT1 = PB_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c index 5bebe70a3a..0dd2b71fb0 100644 --- a/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(C-D-E)T/PinNamesVar.h b/variants/STM32F1xx/F101V(C-D-E)T/PinNamesVar.h index 3eedc0c99b..c4736d590c 100644 --- a/variants/STM32F1xx/F101V(C-D-E)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101V(C-D-E)T/PinNamesVar.h @@ -24,26 +24,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c index a783c1d3bc..25ade74400 100644 --- a/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(F-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(F-G)T/PinNamesVar.h b/variants/STM32F1xx/F101V(F-G)T/PinNamesVar.h index f8fbbe45f0..32a3dd01d5 100644 --- a/variants/STM32F1xx/F101V(F-G)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101V(F-G)T/PinNamesVar.h @@ -30,26 +30,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c index 222f5f84b0..f72963ba09 100644 --- a/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101Z(C-D-E)T/PinNamesVar.h b/variants/STM32F1xx/F101Z(C-D-E)T/PinNamesVar.h index 3eedc0c99b..c4736d590c 100644 --- a/variants/STM32F1xx/F101Z(C-D-E)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101Z(C-D-E)T/PinNamesVar.h @@ -24,26 +24,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c index 800b403462..28871266f7 100644 --- a/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101Z(F-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101Z(F-G)T/PinNamesVar.h b/variants/STM32F1xx/F101Z(F-G)T/PinNamesVar.h index f8fbbe45f0..32a3dd01d5 100644 --- a/variants/STM32F1xx/F101Z(F-G)T/PinNamesVar.h +++ b/variants/STM32F1xx/F101Z(F-G)T/PinNamesVar.h @@ -30,26 +30,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c index 1c229efc08..0732743d7a 100644 --- a/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102C(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102C(4-6)T/PinNamesVar.h b/variants/STM32F1xx/F102C(4-6)T/PinNamesVar.h index b891ee810d..1ebf298b7c 100644 --- a/variants/STM32F1xx/F102C(4-6)T/PinNamesVar.h +++ b/variants/STM32F1xx/F102C(4-6)T/PinNamesVar.h @@ -14,27 +14,6 @@ PB_11_ALT1 = PB_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c index b7c5690c85..e1a2bfc9a1 100644 --- a/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102C(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102C(8-B)T/PinNamesVar.h b/variants/STM32F1xx/F102C(8-B)T/PinNamesVar.h index 8e4429ae74..2cda59909d 100644 --- a/variants/STM32F1xx/F102C(8-B)T/PinNamesVar.h +++ b/variants/STM32F1xx/F102C(8-B)T/PinNamesVar.h @@ -16,27 +16,6 @@ PB_14_ALT1 = PB_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c index d4b1fc6e24..6e39b88150 100644 --- a/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102R(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102R(4-6)T/PinNamesVar.h b/variants/STM32F1xx/F102R(4-6)T/PinNamesVar.h index b891ee810d..1ebf298b7c 100644 --- a/variants/STM32F1xx/F102R(4-6)T/PinNamesVar.h +++ b/variants/STM32F1xx/F102R(4-6)T/PinNamesVar.h @@ -14,27 +14,6 @@ PB_11_ALT1 = PB_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c index cb707c15f0..a9ea3b4869 100644 --- a/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102R(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102R(8-B)T/PinNamesVar.h b/variants/STM32F1xx/F102R(8-B)T/PinNamesVar.h index 8e4429ae74..2cda59909d 100644 --- a/variants/STM32F1xx/F102R(8-B)T/PinNamesVar.h +++ b/variants/STM32F1xx/F102R(8-B)T/PinNamesVar.h @@ -16,27 +16,6 @@ PB_14_ALT1 = PB_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c index eed952644f..a9b4caaf53 100644 --- a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103C(4-6)Tx.xml, STM32F103C6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PinNamesVar.h b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PinNamesVar.h index 2b0fb9d890..0706c6faae 100644 --- a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PinNamesVar.h +++ b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PinNamesVar.h @@ -24,27 +24,6 @@ PB_11_ALT1 = PB_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c index bed7726161..ab73cd16ba 100644 --- a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103C(8-B)Tx.xml, STM32F103CBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PinNamesVar.h b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PinNamesVar.h index 7d7ca6fdf0..0538f48ece 100644 --- a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PinNamesVar.h +++ b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PinNamesVar.h @@ -26,27 +26,6 @@ PB_14_ALT1 = PB_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c b/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c index 2c1226a739..5dacd89ef6 100644 --- a/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(4-6)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(4-6)H/PinNamesVar.h b/variants/STM32F1xx/F103R(4-6)H/PinNamesVar.h index 712487fafc..fcdc3896a2 100644 --- a/variants/STM32F1xx/F103R(4-6)H/PinNamesVar.h +++ b/variants/STM32F1xx/F103R(4-6)H/PinNamesVar.h @@ -29,27 +29,6 @@ PC_5_ALT1 = PC_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c index c739dda78c..1964497784 100644 --- a/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(4-6)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(4-6)T/PinNamesVar.h b/variants/STM32F1xx/F103R(4-6)T/PinNamesVar.h index 1867591d47..e71580cfc4 100644 --- a/variants/STM32F1xx/F103R(4-6)T/PinNamesVar.h +++ b/variants/STM32F1xx/F103R(4-6)T/PinNamesVar.h @@ -30,27 +30,6 @@ PC_5_ALT1 = PC_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c b/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c index 80a7ce494a..20505da4f1 100644 --- a/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(8-B)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(8-B)H/PinNamesVar.h b/variants/STM32F1xx/F103R(8-B)H/PinNamesVar.h index a36a02161b..a3f885829b 100644 --- a/variants/STM32F1xx/F103R(8-B)H/PinNamesVar.h +++ b/variants/STM32F1xx/F103R(8-B)H/PinNamesVar.h @@ -31,27 +31,6 @@ PC_5_ALT1 = PC_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c index 80c8857cfa..7c944c576a 100644 --- a/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(8-B)T/PinNamesVar.h b/variants/STM32F1xx/F103R(8-B)T/PinNamesVar.h index 699fd8dd75..8187c5b27e 100644 --- a/variants/STM32F1xx/F103R(8-B)T/PinNamesVar.h +++ b/variants/STM32F1xx/F103R(8-B)T/PinNamesVar.h @@ -32,27 +32,6 @@ PC_5_ALT1 = PC_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c index 6a45030e69..5b40f2dbbb 100644 --- a/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(C-D-E)T/PinNamesVar.h b/variants/STM32F1xx/F103R(C-D-E)T/PinNamesVar.h index 42669478f8..6a110b84f3 100644 --- a/variants/STM32F1xx/F103R(C-D-E)T/PinNamesVar.h +++ b/variants/STM32F1xx/F103R(C-D-E)T/PinNamesVar.h @@ -51,27 +51,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c b/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c index f078b3d1c0..b4751cecc7 100644 --- a/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(C-D-E)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(C-D-E)Y/PinNamesVar.h b/variants/STM32F1xx/F103R(C-D-E)Y/PinNamesVar.h index 1c9c3618b5..ad9a348ff4 100644 --- a/variants/STM32F1xx/F103R(C-D-E)Y/PinNamesVar.h +++ b/variants/STM32F1xx/F103R(C-D-E)Y/PinNamesVar.h @@ -49,27 +49,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c index 4e9b4c2cc2..30491b9236 100644 --- a/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(F-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(F-G)T/PinNamesVar.h b/variants/STM32F1xx/F103R(F-G)T/PinNamesVar.h index d9faacf359..1a9c7e1599 100644 --- a/variants/STM32F1xx/F103R(F-G)T/PinNamesVar.h +++ b/variants/STM32F1xx/F103R(F-G)T/PinNamesVar.h @@ -57,27 +57,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c b/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c index 677a324de6..9e4b455cd5 100644 --- a/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c +++ b/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103T(4-6)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103T(4-6)U/PinNamesVar.h b/variants/STM32F1xx/F103T(4-6)U/PinNamesVar.h index 86cd34b22c..d323cc7f40 100644 --- a/variants/STM32F1xx/F103T(4-6)U/PinNamesVar.h +++ b/variants/STM32F1xx/F103T(4-6)U/PinNamesVar.h @@ -22,27 +22,6 @@ PB_3_ALT1 = PB_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c b/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c index 903c783d3e..f57b5a2809 100644 --- a/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c +++ b/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103T(8-B)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103T(8-B)U/PinNamesVar.h b/variants/STM32F1xx/F103T(8-B)U/PinNamesVar.h index 86cd34b22c..d323cc7f40 100644 --- a/variants/STM32F1xx/F103T(8-B)U/PinNamesVar.h +++ b/variants/STM32F1xx/F103T(8-B)U/PinNamesVar.h @@ -22,27 +22,6 @@ PB_3_ALT1 = PB_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c index b7005e05ef..f2028cd4d1 100644 --- a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103V(C-D-E)Hx.xml, STM32F103V(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PinNamesVar.h b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PinNamesVar.h index 42669478f8..6a110b84f3 100644 --- a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PinNamesVar.h +++ b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PinNamesVar.h @@ -51,27 +51,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c index 78483ab944..55b866c4f0 100644 --- a/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103V(F-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V(F-G)T/PinNamesVar.h b/variants/STM32F1xx/F103V(F-G)T/PinNamesVar.h index d9faacf359..1a9c7e1599 100644 --- a/variants/STM32F1xx/F103V(F-G)T/PinNamesVar.h +++ b/variants/STM32F1xx/F103V(F-G)T/PinNamesVar.h @@ -57,27 +57,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c index f83143bf68..1eae0351de 100644 --- a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F103V(8-B)Hx.xml, STM32F103V(8-B)Tx.xml * STM32F103VBIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PinNamesVar.h b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PinNamesVar.h index 699fd8dd75..8187c5b27e 100644 --- a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PinNamesVar.h +++ b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PinNamesVar.h @@ -32,27 +32,6 @@ PC_5_ALT1 = PC_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c index ae366659e1..b83ad39972 100644 --- a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103Z(C-D-E)Hx.xml, STM32F103Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PinNamesVar.h b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PinNamesVar.h index 42669478f8..6a110b84f3 100644 --- a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PinNamesVar.h +++ b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PinNamesVar.h @@ -51,27 +51,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c index 0b3807bc91..95f52f6736 100644 --- a/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103Z(F-G)Hx.xml, STM32F103Z(F-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103Z(F-G)(H-T)/PinNamesVar.h b/variants/STM32F1xx/F103Z(F-G)(H-T)/PinNamesVar.h index d9faacf359..1a9c7e1599 100644 --- a/variants/STM32F1xx/F103Z(F-G)(H-T)/PinNamesVar.h +++ b/variants/STM32F1xx/F103Z(F-G)(H-T)/PinNamesVar.h @@ -57,27 +57,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c b/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c index 4d3134555d..ddea8c61e3 100644 --- a/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F105R(8-B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F105R(8-B-C)T/PinNamesVar.h b/variants/STM32F1xx/F105R(8-B-C)T/PinNamesVar.h index ec8f80cab8..efd1825c12 100644 --- a/variants/STM32F1xx/F105R(8-B-C)T/PinNamesVar.h +++ b/variants/STM32F1xx/F105R(8-B-C)T/PinNamesVar.h @@ -40,27 +40,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c index b6506f1114..e3d89ee190 100644 --- a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c +++ b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F105V(8-B)Hx.xml, STM32F105V(8-B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PinNamesVar.h b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PinNamesVar.h index ec8f80cab8..efd1825c12 100644 --- a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PinNamesVar.h +++ b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PinNamesVar.h @@ -40,27 +40,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c b/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c index 838c172665..6b5c4cf69e 100644 --- a/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c +++ b/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F107R(B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F107R(B-C)T/PinNamesVar.h b/variants/STM32F1xx/F107R(B-C)T/PinNamesVar.h index ec8f80cab8..efd1825c12 100644 --- a/variants/STM32F1xx/F107R(B-C)T/PinNamesVar.h +++ b/variants/STM32F1xx/F107R(B-C)T/PinNamesVar.h @@ -40,27 +40,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c index 0c21819cd9..01a62cc46a 100644 --- a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F107V(B-C)Tx.xml, STM32F107VCHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PinNamesVar.h b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PinNamesVar.h index aea05f6ebb..ff8dd675d7 100644 --- a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PinNamesVar.h +++ b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PinNamesVar.h @@ -41,27 +41,6 @@ PD_8_ALT1 = PD_8 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 218c6a81b730bb539a26ae5dc3f457dbccf73ac1 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:26:28 +0100 Subject: [PATCH 041/141] chore(f2): update variant after script update Signed-off-by: Frederic Pillon --- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../F205Z(C-E-F-G)T_F215Z(E-G)T/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../F207V(C-E-F-G)T_F217V(E-G)T/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../F207Z(C-E-F-G)T_F217Z(E-G)T/PinNamesVar.h | 21 ------------------- 12 files changed, 6 insertions(+), 132 deletions(-) diff --git a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c index e9f48a32d8..747457b711 100644 --- a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F205R(B-C-E-F-G)Tx.xml, STM32F205R(E-G)Yx.xml * STM32F205RGEx.xml, STM32F215R(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PinNamesVar.h b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PinNamesVar.h +++ b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c index 0c096d9448..48d2783735 100644 --- a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F205V(B-C-E-F-G)Tx.xml, STM32F215V(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PinNamesVar.h b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PinNamesVar.h +++ b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c index 123000be46..5b211ed8dd 100644 --- a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F205Z(C-E-F-G)Tx.xml, STM32F215Z(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PinNamesVar.h b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PinNamesVar.h +++ b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c index 65b456bf6a..8e5908aa49 100644 --- a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F207I(C-E-F-G)Hx.xml, STM32F207I(C-E-F-G)Tx.xml * STM32F217I(E-G)Hx.xml, STM32F217I(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PinNamesVar.h b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PinNamesVar.h index e287b8d21e..9665bfddb0 100644 --- a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PinNamesVar.h +++ b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c index ab36f6c801..d5d00e48a2 100644 --- a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F207V(C-E-F-G)Tx.xml, STM32F217V(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PinNamesVar.h b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PinNamesVar.h +++ b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c index 96221815a3..ce7893007d 100644 --- a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F207Z(C-E-F-G)Tx.xml, STM32F217Z(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PinNamesVar.h b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PinNamesVar.h +++ b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 1aaf0d06e39101c9b8d8b6fdf63f785af517aa13 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:27:05 +0100 Subject: [PATCH 042/141] chore(f3): update variant after script update Signed-off-by: Frederic Pillon --- .../F301C6T_F301C8(T-Y)/PeripheralPins.c | 2 +- .../F301C6T_F301C8(T-Y)/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F301K(6-8)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F301K(6-8)T/PinNamesVar.h | 21 ------------------- .../STM32F3xx/F301K(6-8)U/PeripheralPins.c | 2 +- variants/STM32F3xx/F301K(6-8)U/PinNamesVar.h | 21 ------------------- .../STM32F3xx/F301R(6-8)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F301R(6-8)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F302C(B-C)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F302C(B-C)T/PinNamesVar.h | 18 ---------------- .../F302C6T_F302C8(T-Y)/PeripheralPins.c | 2 +- .../F302C6T_F302C8(T-Y)/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F302K(6-8)U/PeripheralPins.c | 2 +- variants/STM32F3xx/F302K(6-8)U/PinNamesVar.h | 21 ------------------- .../STM32F3xx/F302R(6-8)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F302R(6-8)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F302R(B-C)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F302R(B-C)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F302R(D-E)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F302R(D-E)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F302V(B-C)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F302V(B-C)T/PinNamesVar.h | 15 ------------- .../F302V(D-E)(H-T)/PeripheralPins.c | 2 +- .../STM32F3xx/F302V(D-E)(H-T)/PinNamesVar.h | 15 ------------- variants/STM32F3xx/F302VCY/PeripheralPins.c | 2 +- variants/STM32F3xx/F302VCY/PinNamesVar.h | 15 ------------- .../STM32F3xx/F302Z(D-E)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F302Z(D-E)T/PinNamesVar.h | 15 ------------- .../PeripheralPins.c | 2 +- .../F303C(6-8)T_F334C(4-6-8)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F303C(B-C)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F303C(B-C)T/PinNamesVar.h | 18 ---------------- .../F303C8Y_F334C8Y/PeripheralPins.c | 2 +- .../STM32F3xx/F303C8Y_F334C8Y/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../F303K(6-8)T_F334K(4-6-8)T/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../F303K(6-8)U_F334K(4-6-8)U/PinNamesVar.h | 21 ------------------- .../F303R(6-8)T_F334R(6-8)T/PeripheralPins.c | 2 +- .../F303R(6-8)T_F334R(6-8)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F303R(B-C)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F303R(B-C)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F303R(D-E)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F303R(D-E)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F303V(B-C)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F303V(B-C)T/PinNamesVar.h | 15 ------------- .../F303V(D-E)(H-T)/PeripheralPins.c | 2 +- .../STM32F3xx/F303V(D-E)(H-T)/PinNamesVar.h | 15 ------------- variants/STM32F3xx/F303VCY/PeripheralPins.c | 2 +- variants/STM32F3xx/F303VCY/PinNamesVar.h | 15 ------------- variants/STM32F3xx/F303VEY/PeripheralPins.c | 2 +- variants/STM32F3xx/F303VEY/PinNamesVar.h | 15 ------------- .../STM32F3xx/F303Z(D-E)T/PeripheralPins.c | 2 +- variants/STM32F3xx/F303Z(D-E)T/PinNamesVar.h | 15 ------------- .../STM32F3xx/F318C8(T-Y)/PeripheralPins.c | 2 +- variants/STM32F3xx/F318C8(T-Y)/PinNamesVar.h | 18 ---------------- variants/STM32F3xx/F318K8U/PeripheralPins.c | 2 +- variants/STM32F3xx/F318K8U/PinNamesVar.h | 21 ------------------- variants/STM32F3xx/F328C8T/PeripheralPins.c | 2 +- variants/STM32F3xx/F328C8T/PinNamesVar.h | 18 ---------------- variants/STM32F3xx/F358CCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358CCT/PinNamesVar.h | 18 ---------------- variants/STM32F3xx/F358RCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358RCT/PinNamesVar.h | 18 ---------------- variants/STM32F3xx/F358VCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358VCT/PinNamesVar.h | 15 ------------- .../STM32F3xx/F373C(8-B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F373C(8-B-C)T/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F373R(8-B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F373R(8-B-C)T/PinNamesVar.h | 18 ---------------- .../F373V(8-B-C)(H-T)/PeripheralPins.c | 2 +- .../STM32F3xx/F373V(8-B-C)(H-T)/PinNamesVar.h | 15 ------------- variants/STM32F3xx/F378CCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F378CCT/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F378RC(T-Y)/PeripheralPins.c | 2 +- variants/STM32F3xx/F378RC(T-Y)/PinNamesVar.h | 18 ---------------- .../STM32F3xx/F378VC(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F378VC(H-T)/PinNamesVar.h | 15 ------------- variants/STM32F3xx/F398VET/PeripheralPins.c | 2 +- variants/STM32F3xx/F398VET/PinNamesVar.h | 15 ------------- 80 files changed, 40 insertions(+), 742 deletions(-) diff --git a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c index 260b00f8fe..48b0b09b96 100644 --- a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301C(6-8)Tx.xml, STM32F301C8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PinNamesVar.h b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PinNamesVar.h index 469be9db79..e22c74eb2f 100644 --- a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PinNamesVar.h +++ b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PinNamesVar.h @@ -18,23 +18,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c index 276df53aea..265f6702b8 100644 --- a/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301K(6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301K(6-8)T/PinNamesVar.h b/variants/STM32F3xx/F301K(6-8)T/PinNamesVar.h index 183edc3cc0..c58987be2a 100644 --- a/variants/STM32F3xx/F301K(6-8)T/PinNamesVar.h +++ b/variants/STM32F3xx/F301K(6-8)T/PinNamesVar.h @@ -12,26 +12,5 @@ PA_12_ALT1 = PA_12 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c b/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c index 0da43d45c5..a5bfa0800d 100644 --- a/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301K(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301K(6-8)U/PinNamesVar.h b/variants/STM32F3xx/F301K(6-8)U/PinNamesVar.h index 183edc3cc0..c58987be2a 100644 --- a/variants/STM32F3xx/F301K(6-8)U/PinNamesVar.h +++ b/variants/STM32F3xx/F301K(6-8)U/PinNamesVar.h @@ -12,26 +12,5 @@ PA_12_ALT1 = PA_12 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c index 9e42349c0e..721a296ae4 100644 --- a/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301R(6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301R(6-8)T/PinNamesVar.h b/variants/STM32F3xx/F301R(6-8)T/PinNamesVar.h index 469be9db79..e22c74eb2f 100644 --- a/variants/STM32F3xx/F301R(6-8)T/PinNamesVar.h +++ b/variants/STM32F3xx/F301R(6-8)T/PinNamesVar.h @@ -18,23 +18,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c index fc63d8625c..c40b5e87ed 100644 --- a/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302C(B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302C(B-C)T/PinNamesVar.h b/variants/STM32F3xx/F302C(B-C)T/PinNamesVar.h index 56436c5c14..7d359260ef 100644 --- a/variants/STM32F3xx/F302C(B-C)T/PinNamesVar.h +++ b/variants/STM32F3xx/F302C(B-C)T/PinNamesVar.h @@ -35,24 +35,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c index 7e5844e996..fe6a032a04 100644 --- a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302C(6-8)Tx.xml, STM32F302C8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PinNamesVar.h b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PinNamesVar.h index 3b9fd7b0f3..c5e547c152 100644 --- a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PinNamesVar.h +++ b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PinNamesVar.h @@ -18,24 +18,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c b/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c index be5c819794..7db36f7bf3 100644 --- a/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302K(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302K(6-8)U/PinNamesVar.h b/variants/STM32F3xx/F302K(6-8)U/PinNamesVar.h index 015ec7a67f..6453c835dd 100644 --- a/variants/STM32F3xx/F302K(6-8)U/PinNamesVar.h +++ b/variants/STM32F3xx/F302K(6-8)U/PinNamesVar.h @@ -12,27 +12,6 @@ PA_12_ALT1 = PA_12 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c index b729d41ac6..54b27285d4 100644 --- a/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(6-8)T/PinNamesVar.h b/variants/STM32F3xx/F302R(6-8)T/PinNamesVar.h index 3b9fd7b0f3..c5e547c152 100644 --- a/variants/STM32F3xx/F302R(6-8)T/PinNamesVar.h +++ b/variants/STM32F3xx/F302R(6-8)T/PinNamesVar.h @@ -18,24 +18,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c index 4515b18ba2..099ce1d2e4 100644 --- a/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(B-C)T/PinNamesVar.h b/variants/STM32F3xx/F302R(B-C)T/PinNamesVar.h index cc0482e10f..b0297c2885 100644 --- a/variants/STM32F3xx/F302R(B-C)T/PinNamesVar.h +++ b/variants/STM32F3xx/F302R(B-C)T/PinNamesVar.h @@ -41,24 +41,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c index be5c418ca6..6ae7147ffd 100644 --- a/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(D-E)T/PinNamesVar.h b/variants/STM32F3xx/F302R(D-E)T/PinNamesVar.h index dcfd3ff3f2..e39f6f931c 100644 --- a/variants/STM32F3xx/F302R(D-E)T/PinNamesVar.h +++ b/variants/STM32F3xx/F302R(D-E)T/PinNamesVar.h @@ -42,24 +42,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c index 96912f9730..cb556cd7a1 100644 --- a/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302V(B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302V(B-C)T/PinNamesVar.h b/variants/STM32F3xx/F302V(B-C)T/PinNamesVar.h index 22154bbdac..263f3c72c7 100644 --- a/variants/STM32F3xx/F302V(B-C)T/PinNamesVar.h +++ b/variants/STM32F3xx/F302V(B-C)T/PinNamesVar.h @@ -45,21 +45,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c index 8f80923903..f0584427bd 100644 --- a/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302V(D-E)Hx.xml, STM32F302V(D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302V(D-E)(H-T)/PinNamesVar.h b/variants/STM32F3xx/F302V(D-E)(H-T)/PinNamesVar.h index 06bd143ec4..ab555ba677 100644 --- a/variants/STM32F3xx/F302V(D-E)(H-T)/PinNamesVar.h +++ b/variants/STM32F3xx/F302V(D-E)(H-T)/PinNamesVar.h @@ -46,21 +46,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302VCY/PeripheralPins.c b/variants/STM32F3xx/F302VCY/PeripheralPins.c index 445a108e5a..79f4396eec 100644 --- a/variants/STM32F3xx/F302VCY/PeripheralPins.c +++ b/variants/STM32F3xx/F302VCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302VCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302VCY/PinNamesVar.h b/variants/STM32F3xx/F302VCY/PinNamesVar.h index 22154bbdac..263f3c72c7 100644 --- a/variants/STM32F3xx/F302VCY/PinNamesVar.h +++ b/variants/STM32F3xx/F302VCY/PinNamesVar.h @@ -45,21 +45,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c index 5cb314dab0..ccef2a5999 100644 --- a/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302Z(D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302Z(D-E)T/PinNamesVar.h b/variants/STM32F3xx/F302Z(D-E)T/PinNamesVar.h index 06bd143ec4..ab555ba677 100644 --- a/variants/STM32F3xx/F302Z(D-E)T/PinNamesVar.h +++ b/variants/STM32F3xx/F302Z(D-E)T/PinNamesVar.h @@ -46,21 +46,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c index 6d25547707..bdf56d7bd0 100644 --- a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C(6-8)Tx.xml, STM32F334C(4-6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PinNamesVar.h b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PinNamesVar.h index 14708d0383..c6b8d7ad7e 100644 --- a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PinNamesVar.h +++ b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PinNamesVar.h @@ -25,23 +25,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c index 1ef3997385..0568433f08 100644 --- a/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C(B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C(B-C)T/PinNamesVar.h b/variants/STM32F3xx/F303C(B-C)T/PinNamesVar.h index d356ef3ef1..57d465b493 100644 --- a/variants/STM32F3xx/F303C(B-C)T/PinNamesVar.h +++ b/variants/STM32F3xx/F303C(B-C)T/PinNamesVar.h @@ -43,24 +43,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c b/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c index 7bbd4efc66..1b2f6c832c 100644 --- a/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c +++ b/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C8Yx.xml, STM32F334C8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C8Y_F334C8Y/PinNamesVar.h b/variants/STM32F3xx/F303C8Y_F334C8Y/PinNamesVar.h index a3bd39d767..518987a4bb 100644 --- a/variants/STM32F3xx/F303C8Y_F334C8Y/PinNamesVar.h +++ b/variants/STM32F3xx/F303C8Y_F334C8Y/PinNamesVar.h @@ -23,26 +23,5 @@ PC_3_ALT1 = PC_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c index 3040f0aef9..ebfca6c6d1 100644 --- a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303K(6-8)Tx.xml, STM32F334K(4-6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PinNamesVar.h b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PinNamesVar.h index 530dde86e5..176c323fed 100644 --- a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PinNamesVar.h +++ b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PinNamesVar.h @@ -19,26 +19,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c index 245c02a9d0..bda35206a7 100644 --- a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303K(6-8)Ux.xml, STM32F334K(4-6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PinNamesVar.h b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PinNamesVar.h index b8d39d0916..704e053ebe 100644 --- a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PinNamesVar.h +++ b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PinNamesVar.h @@ -18,26 +18,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c index 2e8c8a92c0..10db6ea9ba 100644 --- a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(6-8)Tx.xml, STM32F334R(6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PinNamesVar.h b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PinNamesVar.h index e9101418e2..0a5e289dde 100644 --- a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PinNamesVar.h +++ b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PinNamesVar.h @@ -29,23 +29,5 @@ PC_3_ALT1 = PC_3 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c index 15dfa9ce18..20302922db 100644 --- a/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(B-C)T/PinNamesVar.h b/variants/STM32F3xx/F303R(B-C)T/PinNamesVar.h index 45ca635a58..890139c8db 100644 --- a/variants/STM32F3xx/F303R(B-C)T/PinNamesVar.h +++ b/variants/STM32F3xx/F303R(B-C)T/PinNamesVar.h @@ -53,24 +53,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c index 7e4d9db009..1e1952694e 100644 --- a/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(D-E)T/PinNamesVar.h b/variants/STM32F3xx/F303R(D-E)T/PinNamesVar.h index b832ac436a..b3de8c7c20 100644 --- a/variants/STM32F3xx/F303R(D-E)T/PinNamesVar.h +++ b/variants/STM32F3xx/F303R(D-E)T/PinNamesVar.h @@ -54,24 +54,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c index b22b67886d..023e90be47 100644 --- a/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303V(B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303V(B-C)T/PinNamesVar.h b/variants/STM32F3xx/F303V(B-C)T/PinNamesVar.h index b4c25f7afa..ab188888e8 100644 --- a/variants/STM32F3xx/F303V(B-C)T/PinNamesVar.h +++ b/variants/STM32F3xx/F303V(B-C)T/PinNamesVar.h @@ -63,21 +63,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c index d074ca60db..af8e59bd48 100644 --- a/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303V(D-E)Hx.xml, STM32F303V(D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303V(D-E)(H-T)/PinNamesVar.h b/variants/STM32F3xx/F303V(D-E)(H-T)/PinNamesVar.h index bd3334cbd0..651a70698c 100644 --- a/variants/STM32F3xx/F303V(D-E)(H-T)/PinNamesVar.h +++ b/variants/STM32F3xx/F303V(D-E)(H-T)/PinNamesVar.h @@ -69,21 +69,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F303VCY/PeripheralPins.c b/variants/STM32F3xx/F303VCY/PeripheralPins.c index bd83ce91b3..fc0a5b10ed 100644 --- a/variants/STM32F3xx/F303VCY/PeripheralPins.c +++ b/variants/STM32F3xx/F303VCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303VCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303VCY/PinNamesVar.h b/variants/STM32F3xx/F303VCY/PinNamesVar.h index b4c25f7afa..ab188888e8 100644 --- a/variants/STM32F3xx/F303VCY/PinNamesVar.h +++ b/variants/STM32F3xx/F303VCY/PinNamesVar.h @@ -63,21 +63,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F303VEY/PeripheralPins.c b/variants/STM32F3xx/F303VEY/PeripheralPins.c index 98947d07b4..9dd5320a8d 100644 --- a/variants/STM32F3xx/F303VEY/PeripheralPins.c +++ b/variants/STM32F3xx/F303VEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303VEYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303VEY/PinNamesVar.h b/variants/STM32F3xx/F303VEY/PinNamesVar.h index bd3334cbd0..651a70698c 100644 --- a/variants/STM32F3xx/F303VEY/PinNamesVar.h +++ b/variants/STM32F3xx/F303VEY/PinNamesVar.h @@ -69,21 +69,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c index 6986b8fe06..f1ca4aef83 100644 --- a/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303Z(D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303Z(D-E)T/PinNamesVar.h b/variants/STM32F3xx/F303Z(D-E)T/PinNamesVar.h index bd3334cbd0..651a70698c 100644 --- a/variants/STM32F3xx/F303Z(D-E)T/PinNamesVar.h +++ b/variants/STM32F3xx/F303Z(D-E)T/PinNamesVar.h @@ -69,21 +69,6 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c index 70473e891a..abbf5a9fe8 100644 --- a/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F318C8Tx.xml, STM32F318C8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F318C8(T-Y)/PinNamesVar.h b/variants/STM32F3xx/F318C8(T-Y)/PinNamesVar.h index 469be9db79..e22c74eb2f 100644 --- a/variants/STM32F3xx/F318C8(T-Y)/PinNamesVar.h +++ b/variants/STM32F3xx/F318C8(T-Y)/PinNamesVar.h @@ -18,23 +18,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F318K8U/PeripheralPins.c b/variants/STM32F3xx/F318K8U/PeripheralPins.c index 0e1f68eee3..b0a9b40837 100644 --- a/variants/STM32F3xx/F318K8U/PeripheralPins.c +++ b/variants/STM32F3xx/F318K8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F318K8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F318K8U/PinNamesVar.h b/variants/STM32F3xx/F318K8U/PinNamesVar.h index 183edc3cc0..c58987be2a 100644 --- a/variants/STM32F3xx/F318K8U/PinNamesVar.h +++ b/variants/STM32F3xx/F318K8U/PinNamesVar.h @@ -12,26 +12,5 @@ PA_12_ALT1 = PA_12 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F328C8T/PeripheralPins.c b/variants/STM32F3xx/F328C8T/PeripheralPins.c index 6d043db47c..e3bceaa8a3 100644 --- a/variants/STM32F3xx/F328C8T/PeripheralPins.c +++ b/variants/STM32F3xx/F328C8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F328C8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F328C8T/PinNamesVar.h b/variants/STM32F3xx/F328C8T/PinNamesVar.h index 14708d0383..c6b8d7ad7e 100644 --- a/variants/STM32F3xx/F328C8T/PinNamesVar.h +++ b/variants/STM32F3xx/F328C8T/PinNamesVar.h @@ -25,23 +25,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F358CCT/PeripheralPins.c b/variants/STM32F3xx/F358CCT/PeripheralPins.c index c5fe223131..0af0783603 100644 --- a/variants/STM32F3xx/F358CCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358CCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358CCT/PinNamesVar.h b/variants/STM32F3xx/F358CCT/PinNamesVar.h index f522d9fff7..5a72d39011 100644 --- a/variants/STM32F3xx/F358CCT/PinNamesVar.h +++ b/variants/STM32F3xx/F358CCT/PinNamesVar.h @@ -43,23 +43,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F358RCT/PeripheralPins.c b/variants/STM32F3xx/F358RCT/PeripheralPins.c index 654c8f8f77..c43b892b8c 100644 --- a/variants/STM32F3xx/F358RCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358RCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358RCT/PinNamesVar.h b/variants/STM32F3xx/F358RCT/PinNamesVar.h index 69ae934f7d..3a47482dde 100644 --- a/variants/STM32F3xx/F358RCT/PinNamesVar.h +++ b/variants/STM32F3xx/F358RCT/PinNamesVar.h @@ -53,23 +53,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F358VCT/PeripheralPins.c b/variants/STM32F3xx/F358VCT/PeripheralPins.c index bcb1d87df7..ef223f7166 100644 --- a/variants/STM32F3xx/F358VCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358VCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358VCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358VCT/PinNamesVar.h b/variants/STM32F3xx/F358VCT/PinNamesVar.h index 811cb88b62..5d1610b119 100644 --- a/variants/STM32F3xx/F358VCT/PinNamesVar.h +++ b/variants/STM32F3xx/F358VCT/PinNamesVar.h @@ -63,20 +63,5 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c b/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c index 892a8c115b..70a7c4913a 100644 --- a/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373C(8-B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373C(8-B-C)T/PinNamesVar.h b/variants/STM32F3xx/F373C(8-B-C)T/PinNamesVar.h index cfacc01f96..017a35d5c9 100644 --- a/variants/STM32F3xx/F373C(8-B-C)T/PinNamesVar.h +++ b/variants/STM32F3xx/F373C(8-B-C)T/PinNamesVar.h @@ -51,24 +51,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c b/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c index 16263a46e1..d78fd23dc8 100644 --- a/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373R(8-B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373R(8-B-C)T/PinNamesVar.h b/variants/STM32F3xx/F373R(8-B-C)T/PinNamesVar.h index 63dca64939..373fe6c680 100644 --- a/variants/STM32F3xx/F373R(8-B-C)T/PinNamesVar.h +++ b/variants/STM32F3xx/F373R(8-B-C)T/PinNamesVar.h @@ -53,24 +53,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c index 358fa1d442..55da69d1d2 100644 --- a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373V(8-B-C)Hx.xml, STM32F373V(8-B-C)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PinNamesVar.h b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PinNamesVar.h index 7726786367..633e0696b9 100644 --- a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PinNamesVar.h +++ b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PinNamesVar.h @@ -56,21 +56,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F3xx/F378CCT/PeripheralPins.c b/variants/STM32F3xx/F378CCT/PeripheralPins.c index ae4b837025..42bc8e0194 100644 --- a/variants/STM32F3xx/F378CCT/PeripheralPins.c +++ b/variants/STM32F3xx/F378CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378CCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378CCT/PinNamesVar.h b/variants/STM32F3xx/F378CCT/PinNamesVar.h index a201392ea1..9b1d667bfc 100644 --- a/variants/STM32F3xx/F378CCT/PinNamesVar.h +++ b/variants/STM32F3xx/F378CCT/PinNamesVar.h @@ -51,23 +51,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c index 5095339377..98d809e95a 100644 --- a/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378RCTx.xml, STM32F378RCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378RC(T-Y)/PinNamesVar.h b/variants/STM32F3xx/F378RC(T-Y)/PinNamesVar.h index 45ccd18e6b..470c15bc03 100644 --- a/variants/STM32F3xx/F378RC(T-Y)/PinNamesVar.h +++ b/variants/STM32F3xx/F378RC(T-Y)/PinNamesVar.h @@ -53,23 +53,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c b/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c index 180b81fb17..665eb0f0e7 100644 --- a/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378VCHx.xml, STM32F378VCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378VC(H-T)/PinNamesVar.h b/variants/STM32F3xx/F378VC(H-T)/PinNamesVar.h index 7ae269c477..933098794c 100644 --- a/variants/STM32F3xx/F378VC(H-T)/PinNamesVar.h +++ b/variants/STM32F3xx/F378VC(H-T)/PinNamesVar.h @@ -56,20 +56,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F3xx/F398VET/PeripheralPins.c b/variants/STM32F3xx/F398VET/PeripheralPins.c index 03d8912945..3f768eb6ab 100644 --- a/variants/STM32F3xx/F398VET/PeripheralPins.c +++ b/variants/STM32F3xx/F398VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F398VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F398VET/PinNamesVar.h b/variants/STM32F3xx/F398VET/PinNamesVar.h index 3e89985bb2..e7326a05ec 100644 --- a/variants/STM32F3xx/F398VET/PinNamesVar.h +++ b/variants/STM32F3xx/F398VET/PinNamesVar.h @@ -69,20 +69,5 @@ PF_2_ALT1 = PF_2 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ From 3582721e5e050d507b2dec4d0cd6a84f310d150f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:27:39 +0100 Subject: [PATCH 043/141] chore(f4): update variant after script update Signed-off-by: Frederic Pillon --- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../F401R(B-C-D-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F401R(B-C-D-E)T/PinNamesVar.h | 21 ------------------- .../F401V(B-C-D-E)H/PeripheralPins.c | 2 +- .../STM32F4xx/F401V(B-C-D-E)H/PinNamesVar.h | 21 ------------------- .../F401V(B-C-D-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F401V(B-C-D-E)T/PinNamesVar.h | 21 ------------------- .../F405O(E-G)Y_F415OGY/PeripheralPins.c | 2 +- .../F405O(E-G)Y_F415OGY/PinNamesVar.h | 21 ------------------- .../F405RGT_F415RGT/PeripheralPins.c | 2 +- .../STM32F4xx/F405RGT_F415RGT/PinNamesVar.h | 21 ------------------- .../F405VGT_F415VGT/PeripheralPins.c | 2 +- .../STM32F4xx/F405VGT_F415VGT/PinNamesVar.h | 21 ------------------- .../F405ZGT_F415ZGT/PeripheralPins.c | 2 +- .../STM32F4xx/F405ZGT_F415ZGT/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../F407V(E-G)T_F417V(E-G)T/PeripheralPins.c | 2 +- .../F407V(E-G)T_F417V(E-G)T/PinNamesVar.h | 21 ------------------- .../F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c | 2 +- .../F407Z(E-G)T_F417Z(E-G)T/PinNamesVar.h | 21 ------------------- .../STM32F4xx/F410C(8-B)T/PeripheralPins.c | 2 +- variants/STM32F4xx/F410C(8-B)T/PinNamesVar.h | 21 ------------------- .../STM32F4xx/F410C(8-B)U/PeripheralPins.c | 2 +- variants/STM32F4xx/F410C(8-B)U/PinNamesVar.h | 21 ------------------- .../F410R(8-B)(I-T)/PeripheralPins.c | 2 +- .../STM32F4xx/F410R(8-B)(I-T)/PinNamesVar.h | 15 ------------- .../STM32F4xx/F410T(8-B)Y/PeripheralPins.c | 2 +- variants/STM32F4xx/F410T(8-B)Y/PinNamesVar.h | 21 ------------------- .../F411C(C-E)(U-Y)/PeripheralPins.c | 2 +- .../STM32F4xx/F411C(C-E)(U-Y)/PinNamesVar.h | 21 ------------------- .../STM32F4xx/F411R(C-E)T/PeripheralPins.c | 2 +- variants/STM32F4xx/F411R(C-E)T/PinNamesVar.h | 21 ------------------- .../STM32F4xx/F411V(C-E)H/PeripheralPins.c | 2 +- variants/STM32F4xx/F411V(C-E)H/PinNamesVar.h | 21 ------------------- .../STM32F4xx/F411V(C-E)T/PeripheralPins.c | 2 +- variants/STM32F4xx/F411V(C-E)T/PinNamesVar.h | 21 ------------------- .../STM32F4xx/F412C(E-G)U/PeripheralPins.c | 2 +- variants/STM32F4xx/F412C(E-G)U/PinNamesVar.h | 21 ------------------- .../F412R(E-G)(T-Y)x(P)/PeripheralPins.c | 2 +- .../F412R(E-G)(T-Y)x(P)/PinNamesVar.h | 15 ------------- .../STM32F4xx/F412V(E-G)H/PeripheralPins.c | 2 +- variants/STM32F4xx/F412V(E-G)H/PinNamesVar.h | 15 ------------- .../STM32F4xx/F412V(E-G)T/PeripheralPins.c | 2 +- variants/STM32F4xx/F412V(E-G)T/PinNamesVar.h | 15 ------------- .../F412Z(E-G)(J-T)/PeripheralPins.c | 2 +- .../STM32F4xx/F412Z(E-G)(J-T)/PinNamesVar.h | 15 ------------- .../F413C(G-H)U_F423CHU/PeripheralPins.c | 2 +- .../F413C(G-H)U_F423CHU/PinNamesVar.h | 21 ------------------- .../F413M(G-H)Y_F423MHY/PeripheralPins.c | 2 +- .../F413M(G-H)Y_F423MHY/PinNamesVar.h | 15 ------------- .../F413R(G-H)T_F423RHT/PeripheralPins.c | 2 +- .../F413R(G-H)T_F423RHT/PinNamesVar.h | 15 ------------- .../F413V(G-H)H_F423VHH/PeripheralPins.c | 2 +- .../F413V(G-H)H_F423VHH/PinNamesVar.h | 15 ------------- .../F413V(G-H)T_F423VHT/PeripheralPins.c | 2 +- .../F413V(G-H)T_F423VHT/PinNamesVar.h | 15 ------------- .../PeripheralPins.c | 2 +- .../F413Z(G-H)(J-T)_F423ZH(J-T)/PinNamesVar.h | 15 ------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../STM32F4xx/F446M(C-E)Y/PeripheralPins.c | 2 +- variants/STM32F4xx/F446M(C-E)Y/PinNamesVar.h | 18 ---------------- .../STM32F4xx/F446R(C-E)T/PeripheralPins.c | 2 +- variants/STM32F4xx/F446R(C-E)T/PinNamesVar.h | 18 ---------------- .../STM32F4xx/F446V(C-E)T/PeripheralPins.c | 2 +- variants/STM32F4xx/F446V(C-E)T/PinNamesVar.h | 18 ---------------- .../F446Z(C-E)(H-J-T)/PeripheralPins.c | 2 +- .../STM32F4xx/F446Z(C-E)(H-J-T)/PinNamesVar.h | 18 ---------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../F469V(E-G-I)T_F479V(G-I)T/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../F469Z(E-G-I)T_F479Z(G-I)T/PinNamesVar.h | 21 ------------------- 88 files changed, 44 insertions(+), 896 deletions(-) diff --git a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c index 74962f52ba..4665c1f651 100644 --- a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F401C(B-C)Ux.xml, STM32F401C(B-C)Yx.xml * STM32F401C(D-E)Ux.xml, STM32F401C(D-E)Yx.xml * STM32F401CCFx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PinNamesVar.h b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PinNamesVar.h index 766cc2ca26..f05217092e 100644 --- a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PinNamesVar.h +++ b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PinNamesVar.h @@ -20,27 +20,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c b/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c index 177bbbaf19..5739f54e47 100644 --- a/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401R(B-C)Tx.xml, STM32F401R(D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401R(B-C-D-E)T/PinNamesVar.h b/variants/STM32F4xx/F401R(B-C-D-E)T/PinNamesVar.h index 766cc2ca26..f05217092e 100644 --- a/variants/STM32F4xx/F401R(B-C-D-E)T/PinNamesVar.h +++ b/variants/STM32F4xx/F401R(B-C-D-E)T/PinNamesVar.h @@ -20,27 +20,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c b/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c index 8649d6f527..7483d6dd4e 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c +++ b/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401V(B-C)Hx.xml, STM32F401V(D-E)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401V(B-C-D-E)H/PinNamesVar.h b/variants/STM32F4xx/F401V(B-C-D-E)H/PinNamesVar.h index 766cc2ca26..f05217092e 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)H/PinNamesVar.h +++ b/variants/STM32F4xx/F401V(B-C-D-E)H/PinNamesVar.h @@ -20,27 +20,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c b/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c index 1caf86b083..66e3bda321 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401V(B-C)Tx.xml, STM32F401V(D-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401V(B-C-D-E)T/PinNamesVar.h b/variants/STM32F4xx/F401V(B-C-D-E)T/PinNamesVar.h index 766cc2ca26..f05217092e 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)T/PinNamesVar.h +++ b/variants/STM32F4xx/F401V(B-C-D-E)T/PinNamesVar.h @@ -20,27 +20,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c index 10ae7f8134..1431e743e0 100644 --- a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c +++ b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405O(E-G)Yx.xml, STM32F415OGYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PinNamesVar.h b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PinNamesVar.h index 3ad483aaf5..6c2a384ca5 100644 --- a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PinNamesVar.h +++ b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PinNamesVar.h @@ -44,27 +44,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c b/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c index a9df9b559f..976138a399 100644 --- a/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405RGTx.xml, STM32F415RGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405RGT_F415RGT/PinNamesVar.h b/variants/STM32F4xx/F405RGT_F415RGT/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F4xx/F405RGT_F415RGT/PinNamesVar.h +++ b/variants/STM32F4xx/F405RGT_F415RGT/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c b/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c index f60f3328c2..58ece9a280 100644 --- a/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405VGTx.xml, STM32F415VGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405VGT_F415VGT/PinNamesVar.h b/variants/STM32F4xx/F405VGT_F415VGT/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F4xx/F405VGT_F415VGT/PinNamesVar.h +++ b/variants/STM32F4xx/F405VGT_F415VGT/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c b/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c index cf97ab1f9f..ca91b0db99 100644 --- a/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405ZGTx.xml, STM32F415ZGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405ZGT_F415ZGT/PinNamesVar.h b/variants/STM32F4xx/F405ZGT_F415ZGT/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F4xx/F405ZGT_F415ZGT/PinNamesVar.h +++ b/variants/STM32F4xx/F405ZGT_F415ZGT/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c index 1d17f137d3..107dba1813 100644 --- a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F407I(E-G)Hx.xml, STM32F407I(E-G)Tx.xml * STM32F417I(E-G)Hx.xml, STM32F417I(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PinNamesVar.h b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PinNamesVar.h index e287b8d21e..9665bfddb0 100644 --- a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PinNamesVar.h +++ b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c index fe227e3a01..dedc3926b9 100644 --- a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F407V(E-G)Tx.xml, STM32F417V(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PinNamesVar.h b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PinNamesVar.h +++ b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c index 453b561a58..89a974eec4 100644 --- a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F407Z(E-G)Tx.xml, STM32F417Z(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PinNamesVar.h b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PinNamesVar.h +++ b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c b/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c index 35f841718a..0019704df2 100644 --- a/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c +++ b/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410C(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410C(8-B)T/PinNamesVar.h b/variants/STM32F4xx/F410C(8-B)T/PinNamesVar.h index 6275fc5618..2a0af6630b 100644 --- a/variants/STM32F4xx/F410C(8-B)T/PinNamesVar.h +++ b/variants/STM32F4xx/F410C(8-B)T/PinNamesVar.h @@ -6,26 +6,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c b/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c index 3caf01806f..5693fc7dba 100644 --- a/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c +++ b/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410C(8-B)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410C(8-B)U/PinNamesVar.h b/variants/STM32F4xx/F410C(8-B)U/PinNamesVar.h index dfec5a9bc5..2ef055abaf 100644 --- a/variants/STM32F4xx/F410C(8-B)U/PinNamesVar.h +++ b/variants/STM32F4xx/F410C(8-B)U/PinNamesVar.h @@ -7,26 +7,5 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c b/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c index 0e8a9e4667..940e523b80 100644 --- a/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410R(8-B)Ix.xml, STM32F410R(8-B)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/PinNamesVar.h b/variants/STM32F4xx/F410R(8-B)(I-T)/PinNamesVar.h index 203f4a6164..567ba9ff92 100644 --- a/variants/STM32F4xx/F410R(8-B)(I-T)/PinNamesVar.h +++ b/variants/STM32F4xx/F410R(8-B)(I-T)/PinNamesVar.h @@ -13,20 +13,5 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c b/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c index 45de1556c5..029b6c77a7 100644 --- a/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c +++ b/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410T(8-B)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410T(8-B)Y/PinNamesVar.h b/variants/STM32F4xx/F410T(8-B)Y/PinNamesVar.h index 6275fc5618..2a0af6630b 100644 --- a/variants/STM32F4xx/F410T(8-B)Y/PinNamesVar.h +++ b/variants/STM32F4xx/F410T(8-B)Y/PinNamesVar.h @@ -6,26 +6,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c b/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c index 1c9c69a7d3..ce7216f859 100644 --- a/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411C(C-E)Ux.xml, STM32F411C(C-E)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411C(C-E)(U-Y)/PinNamesVar.h b/variants/STM32F4xx/F411C(C-E)(U-Y)/PinNamesVar.h index 0858f1355d..52b2269f4c 100644 --- a/variants/STM32F4xx/F411C(C-E)(U-Y)/PinNamesVar.h +++ b/variants/STM32F4xx/F411C(C-E)(U-Y)/PinNamesVar.h @@ -22,27 +22,6 @@ PB_13_ALT1 = PB_13 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c index 922738b468..4020d9f70a 100644 --- a/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411R(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411R(C-E)T/PinNamesVar.h b/variants/STM32F4xx/F411R(C-E)T/PinNamesVar.h index 0858f1355d..52b2269f4c 100644 --- a/variants/STM32F4xx/F411R(C-E)T/PinNamesVar.h +++ b/variants/STM32F4xx/F411R(C-E)T/PinNamesVar.h @@ -22,27 +22,6 @@ PB_13_ALT1 = PB_13 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c b/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c index e8a34279fd..522ae1b860 100644 --- a/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c +++ b/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411V(C-E)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411V(C-E)H/PinNamesVar.h b/variants/STM32F4xx/F411V(C-E)H/PinNamesVar.h index 0837294bf4..f5c7afa8c0 100644 --- a/variants/STM32F4xx/F411V(C-E)H/PinNamesVar.h +++ b/variants/STM32F4xx/F411V(C-E)H/PinNamesVar.h @@ -30,27 +30,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c index 1c80d5cd60..3edd5b78cc 100644 --- a/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411V(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411V(C-E)T/PinNamesVar.h b/variants/STM32F4xx/F411V(C-E)T/PinNamesVar.h index 0837294bf4..f5c7afa8c0 100644 --- a/variants/STM32F4xx/F411V(C-E)T/PinNamesVar.h +++ b/variants/STM32F4xx/F411V(C-E)T/PinNamesVar.h @@ -30,27 +30,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c b/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c index af9953db5b..936ce27b6f 100644 --- a/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c +++ b/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412C(E-G)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412C(E-G)U/PinNamesVar.h b/variants/STM32F4xx/F412C(E-G)U/PinNamesVar.h index 0fe78be3b0..1c34da5666 100644 --- a/variants/STM32F4xx/F412C(E-G)U/PinNamesVar.h +++ b/variants/STM32F4xx/F412C(E-G)U/PinNamesVar.h @@ -32,27 +32,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c index fe0c69ea29..6e8de3744c 100644 --- a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c +++ b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F412R(E-G)Tx.xml, STM32F412R(E-G)Yx.xml * STM32F412R(E-G)YxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PinNamesVar.h b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PinNamesVar.h index df59c759dd..45ab437e21 100644 --- a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PinNamesVar.h +++ b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PinNamesVar.h @@ -42,21 +42,6 @@ PC_9_ALT1 = PC_9 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c b/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c index 130f961598..73dbe2c5f0 100644 --- a/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c +++ b/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412V(E-G)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412V(E-G)H/PinNamesVar.h b/variants/STM32F4xx/F412V(E-G)H/PinNamesVar.h index 416f8df3c4..2982c43ad2 100644 --- a/variants/STM32F4xx/F412V(E-G)H/PinNamesVar.h +++ b/variants/STM32F4xx/F412V(E-G)H/PinNamesVar.h @@ -50,21 +50,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c index a5532740a9..05434b44af 100644 --- a/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412V(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412V(E-G)T/PinNamesVar.h b/variants/STM32F4xx/F412V(E-G)T/PinNamesVar.h index 416f8df3c4..2982c43ad2 100644 --- a/variants/STM32F4xx/F412V(E-G)T/PinNamesVar.h +++ b/variants/STM32F4xx/F412V(E-G)T/PinNamesVar.h @@ -50,21 +50,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c index 6022fb214d..2c9934b4f4 100644 --- a/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412Z(E-G)Jx.xml, STM32F412Z(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/PinNamesVar.h b/variants/STM32F4xx/F412Z(E-G)(J-T)/PinNamesVar.h index 416f8df3c4..2982c43ad2 100644 --- a/variants/STM32F4xx/F412Z(E-G)(J-T)/PinNamesVar.h +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/PinNamesVar.h @@ -50,21 +50,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c index 9a9a89caed..d4f55ca14d 100644 --- a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c +++ b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413C(G-H)Ux.xml, STM32F423CHUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PinNamesVar.h b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PinNamesVar.h index 3299221acc..1a00233f7a 100644 --- a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PinNamesVar.h +++ b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PinNamesVar.h @@ -35,27 +35,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c index 8ac9fda947..2e0053d541 100644 --- a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c +++ b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413M(G-H)Yx.xml, STM32F423MHYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PinNamesVar.h b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PinNamesVar.h index b63c66ce14..7db45be766 100644 --- a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PinNamesVar.h +++ b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PinNamesVar.h @@ -50,21 +50,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c index 9bc4874724..464f4c46d6 100644 --- a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c +++ b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413R(G-H)Tx.xml, STM32F423RHTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PinNamesVar.h b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PinNamesVar.h index cb831f3bb0..29805dd4d3 100644 --- a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PinNamesVar.h +++ b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PinNamesVar.h @@ -46,21 +46,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c index a3b789ef21..7a1aae695d 100644 --- a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c +++ b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413V(G-H)Hx.xml, STM32F423VHHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PinNamesVar.h b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PinNamesVar.h index a685cf3da9..7f51b6dfdb 100644 --- a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PinNamesVar.h +++ b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PinNamesVar.h @@ -54,21 +54,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c index 0bb16f17af..d35b874766 100644 --- a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c +++ b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413V(G-H)Tx.xml, STM32F423VHTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PinNamesVar.h b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PinNamesVar.h index a685cf3da9..7f51b6dfdb 100644 --- a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PinNamesVar.h +++ b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PinNamesVar.h @@ -54,21 +54,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c index 6f63904833..a74ecbc31d 100644 --- a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F413Z(G-H)Jx.xml, STM32F413Z(G-H)Tx.xml * STM32F423ZHJx.xml, STM32F423ZHTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PinNamesVar.h b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PinNamesVar.h index a685cf3da9..7f51b6dfdb 100644 --- a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PinNamesVar.h +++ b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PinNamesVar.h @@ -54,21 +54,6 @@ PE_14_ALT1 = PE_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c index 45dc44dc6a..c12f8837b8 100644 --- a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c +++ b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F427A(G-I)Hx.xml, STM32F429A(G-I)Hx.xml * STM32F437AIHx.xml, STM32F439AIHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PinNamesVar.h b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PinNamesVar.h index 4eaa418aa5..e538e6303d 100644 --- a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PinNamesVar.h +++ b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c index 217ec7f23e..e9ddca57b1 100644 --- a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32F429IITx.xml, STM32F437I(G-I)Hx.xml * STM32F437I(G-I)Tx.xml, STM32F439I(G-I)Hx.xml * STM32F439I(G-I)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PinNamesVar.h b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PinNamesVar.h index e287b8d21e..9665bfddb0 100644 --- a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PinNamesVar.h +++ b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c index d52543cbd4..b1ea51531b 100644 --- a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F427V(G-I)Tx.xml, STM32F429V(E-G)Tx.xml * STM32F429VITx.xml, STM32F437V(G-I)Tx.xml * STM32F439V(G-I)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PinNamesVar.h b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PinNamesVar.h +++ b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c index 937483940f..9f533bdd56 100644 --- a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F429ZGYx.xml, STM32F429ZITx.xml * STM32F429ZIYx.xml, STM32F437Z(G-I)Tx.xml * STM32F439Z(G-I)Tx.xml, STM32F439Z(G-I)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PinNamesVar.h b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PinNamesVar.h +++ b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c index 9d95cadf44..a8a5de137e 100644 --- a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c +++ b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F429B(E-G-I)Tx.xml, STM32F429N(E-G)Hx.xml * STM32F429NIHx.xml, STM32F439B(G-I)Tx.xml * STM32F439N(G-I)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PinNamesVar.h b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PinNamesVar.h index e287b8d21e..9665bfddb0 100644 --- a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PinNamesVar.h +++ b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c b/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c index 2f752b5679..cc057a0c72 100644 --- a/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c +++ b/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446M(C-E)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446M(C-E)Y/PinNamesVar.h b/variants/STM32F4xx/F446M(C-E)Y/PinNamesVar.h index 62f0cf7058..7fda0b4913 100644 --- a/variants/STM32F4xx/F446M(C-E)Y/PinNamesVar.h +++ b/variants/STM32F4xx/F446M(C-E)Y/PinNamesVar.h @@ -50,24 +50,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, /* SYS_WKUP1 */ #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c index e5ab76984d..5960b5ba0f 100644 --- a/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446R(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446R(C-E)T/PinNamesVar.h b/variants/STM32F4xx/F446R(C-E)T/PinNamesVar.h index 17b291f185..1595515c42 100644 --- a/variants/STM32F4xx/F446R(C-E)T/PinNamesVar.h +++ b/variants/STM32F4xx/F446R(C-E)T/PinNamesVar.h @@ -53,24 +53,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, /* SYS_WKUP1 */ #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c index 57733f614c..d1a255efc3 100644 --- a/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446V(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446V(C-E)T/PinNamesVar.h b/variants/STM32F4xx/F446V(C-E)T/PinNamesVar.h index 17b291f185..1595515c42 100644 --- a/variants/STM32F4xx/F446V(C-E)T/PinNamesVar.h +++ b/variants/STM32F4xx/F446V(C-E)T/PinNamesVar.h @@ -53,24 +53,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, /* SYS_WKUP1 */ #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c index 55e5dd9932..8108c3eb39 100644 --- a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F446Z(C-E)Hx.xml, STM32F446Z(C-E)Jx.xml * STM32F446Z(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PinNamesVar.h b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PinNamesVar.h index 17b291f185..1595515c42 100644 --- a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PinNamesVar.h +++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PinNamesVar.h @@ -53,24 +53,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, /* SYS_WKUP1 */ #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c index f12fbd9c3b..e70e2a7c91 100644 --- a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469A(E-G-I)Hx.xml, STM32F469A(E-G-I)Yx.xml * STM32F479A(G-I)Hx.xml, STM32F479A(G-I)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PinNamesVar.h b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PinNamesVar.h index 16affd2718..9093cdaa35 100644 --- a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PinNamesVar.h +++ b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PinNamesVar.h @@ -42,27 +42,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c index 317feed0b6..e8e7e81f2e 100644 --- a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c +++ b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F469B(E-G-I)Tx.xml, STM32F469N(E-G)Hx.xml * STM32F469NIHx.xml, STM32F479B(G-I)Tx.xml * STM32F479N(G-I)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PinNamesVar.h b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PinNamesVar.h index e287b8d21e..9665bfddb0 100644 --- a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PinNamesVar.h +++ b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c index 7d5791f1bd..e5d61d2e8f 100644 --- a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F469I(E-G)Tx.xml, STM32F469I(E-G-I)Hx.xml * STM32F469IITx.xml, STM32F479I(G-I)Hx.xml * STM32F479I(G-I)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PinNamesVar.h b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PinNamesVar.h index e287b8d21e..9665bfddb0 100644 --- a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PinNamesVar.h +++ b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c index c2a98f327f..f925e237e0 100644 --- a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469V(E-G)Tx.xml, STM32F469VITx.xml * STM32F479V(G-I)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PinNamesVar.h b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PinNamesVar.h index 80a2dace38..48551f7fe2 100644 --- a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PinNamesVar.h +++ b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PinNamesVar.h @@ -46,27 +46,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c index af3dc06eed..bdceca9722 100644 --- a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469Z(E-G)Tx.xml, STM32F469ZITx.xml * STM32F479Z(G-I)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PinNamesVar.h b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PinNamesVar.h index 0c22b1cd36..d90a4cdccb 100644 --- a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PinNamesVar.h +++ b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PinNamesVar.h @@ -48,27 +48,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From f53f44ffc66cde95cd6a568b51c789bae4fc8dc9 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:28:06 +0100 Subject: [PATCH 044/141] chore(f7): update variant after script update Signed-off-by: Frederic Pillon --- .../F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c | 2 +- .../F722I(C-E)(K-T)_F732IE(K-T)/PinNamesVar.h | 6 ------ .../F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c | 2 +- .../F722R(C-E)T_F730R8T_F732RET/PinNamesVar.h | 12 ------------ .../F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c | 2 +- .../F722V(C-E)T_F730V8T_F732VET/PinNamesVar.h | 12 ------------ .../STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c | 2 +- variants/STM32F7xx/F722Z(C-E)T_F732ZET/PinNamesVar.h | 12 ------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c | 2 +- .../F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h | 12 ------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 ------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 ------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 ------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 ------------ .../F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c | 2 +- .../F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PinNamesVar.h | 12 ------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c | 2 +- variants/STM32F7xx/F769I(G-I)T_F779IIT/PinNamesVar.h | 6 ------ 36 files changed, 18 insertions(+), 180 deletions(-) diff --git a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c index 34bea1601c..fd29acaa0e 100644 --- a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722I(C-E)Kx.xml, STM32F722I(C-E)Tx.xml * STM32F732IEKx.xml, STM32F732IETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PinNamesVar.h b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PinNamesVar.h index b1f28966cd..2d265f5167 100644 --- a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PinNamesVar.h @@ -63,12 +63,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c index 55b4bd7606..cb4030abb9 100644 --- a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c +++ b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722R(C-E)Tx.xml, STM32F730R8Tx.xml * STM32F732RETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PinNamesVar.h b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PinNamesVar.h index 2f126b90c5..1accada715 100644 --- a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PinNamesVar.h +++ b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PinNamesVar.h @@ -56,18 +56,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c index dab5ef47f9..fdd490ec6a 100644 --- a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c +++ b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722V(C-E)Tx.xml, STM32F730V8Tx.xml * STM32F732VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PinNamesVar.h b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PinNamesVar.h index 569cae4e9f..9c3ac72288 100644 --- a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PinNamesVar.h +++ b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PinNamesVar.h @@ -57,18 +57,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c index a2dd5211c2..dd91a399cb 100644 --- a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c +++ b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F722Z(C-E)Tx.xml, STM32F732ZETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PinNamesVar.h b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PinNamesVar.h index 569cae4e9f..9c3ac72288 100644 --- a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PinNamesVar.h +++ b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PinNamesVar.h @@ -57,18 +57,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c index f7cefda1a5..4a61346209 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F723I(C-E)Kx.xml, STM32F723I(C-E)Tx.xml * STM32F730I8Kx.xml, STM32F733IEKx.xml * STM32F733IETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PinNamesVar.h b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PinNamesVar.h index 8c6fb4290f..81135f8e89 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PinNamesVar.h @@ -59,12 +59,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c index ddd10ea078..63c225e2a4 100644 --- a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c +++ b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F723V(C-E)Tx.xml, STM32F723V(C-E)Yx.xml * STM32F733VETx.xml, STM32F733VEYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h index cca69bb5b3..e8272849b5 100644 --- a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h +++ b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h @@ -53,18 +53,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c index 26a8d4a05c..ac48713580 100644 --- a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F723Z(C-E)Ix.xml, STM32F723Z(C-E)Tx.xml * STM32F730Z8Tx.xml, STM32F733ZEIx.xml * STM32F733ZETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PinNamesVar.h b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PinNamesVar.h index cca69bb5b3..e8272849b5 100644 --- a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PinNamesVar.h @@ -53,18 +53,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c index 247b7234be..eff1202d87 100644 --- a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746I(E-G)Kx.xml, STM32F746IETx.xml * STM32F746IGTx.xml, STM32F756IGKx.xml * STM32F756IGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PinNamesVar.h b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PinNamesVar.h index b1f28966cd..2d265f5167 100644 --- a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PinNamesVar.h @@ -63,12 +63,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c index 924b3c70bd..b99b9d7a60 100644 --- a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746V(E-G)Hx.xml, STM32F746VETx.xml * STM32F746VGTx.xml, STM32F750V8Tx.xml * STM32F756VGHx.xml, STM32F756VGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PinNamesVar.h b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PinNamesVar.h index 569cae4e9f..9c3ac72288 100644 --- a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PinNamesVar.h @@ -57,18 +57,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c index 330b73b499..090e4b9d4a 100644 --- a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c +++ b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746ZETx.xml, STM32F746ZGTx.xml * STM32F750Z8Tx.xml, STM32F756ZGTx.xml * STM32F756ZGYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PinNamesVar.h b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PinNamesVar.h index 569cae4e9f..9c3ac72288 100644 --- a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PinNamesVar.h +++ b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PinNamesVar.h @@ -57,18 +57,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c index 1104403bb0..5e39029583 100644 --- a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c +++ b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F746B(E-G)Tx.xml, STM32F746NEHx.xml * STM32F746NGHx.xml, STM32F750N8Hx.xml * STM32F756BGTx.xml, STM32F756NGHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PinNamesVar.h b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PinNamesVar.h index b1f28966cd..2d265f5167 100644 --- a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PinNamesVar.h +++ b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PinNamesVar.h @@ -63,12 +63,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c index 8412f2dc75..916e4c0ba3 100644 --- a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c +++ b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F765B(G-I)Tx.xml, STM32F765N(G-I)Hx.xml * STM32F767B(G-I)Tx.xml, STM32F767N(G-I)Hx.xml * STM32F777BITx.xml, STM32F777NIHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PinNamesVar.h b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PinNamesVar.h index d55aec5c28..b24c78d7ad 100644 --- a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PinNamesVar.h +++ b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PinNamesVar.h @@ -70,12 +70,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c index 34e7ba6562..2f1c251a90 100644 --- a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F765I(G-I)Kx.xml, STM32F765I(G-I)Tx.xml * STM32F767I(G-I)Kx.xml, STM32F767I(G-I)Tx.xml * STM32F777IIKx.xml, STM32F777IITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PinNamesVar.h b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PinNamesVar.h index d55aec5c28..b24c78d7ad 100644 --- a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PinNamesVar.h @@ -70,12 +70,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c index aca69b7a5b..667b744721 100644 --- a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F767VGHx.xml, STM32F767VGTx.xml * STM32F767VIHx.xml, STM32F767VITx.xml * STM32F777VIHx.xml, STM32F777VITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PinNamesVar.h b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PinNamesVar.h index baf6e31f4d..76a00b7c86 100644 --- a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PinNamesVar.h @@ -64,18 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c index 3551d0cdf0..364ce0e1c5 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F765Z(G-I)Tx.xml, STM32F767ZGTx.xml * STM32F767ZITx.xml, STM32F777ZITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PinNamesVar.h b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PinNamesVar.h index baf6e31f4d..76a00b7c86 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PinNamesVar.h +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PinNamesVar.h @@ -64,18 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c index 1b55021b11..264cc69876 100644 --- a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c +++ b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F768AIYx.xml, STM32F769A(G-I)Yx.xml * STM32F778AIYx.xml, STM32F779AIYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PinNamesVar.h b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PinNamesVar.h index a8bf013646..e5b1673c1c 100644 --- a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PinNamesVar.h +++ b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PinNamesVar.h @@ -64,12 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c index df7e57466c..fa8b5b2305 100644 --- a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c +++ b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F769B(G-I)Tx.xml, STM32F769NGHx.xml * STM32F769NIHx.xml, STM32F779BITx.xml * STM32F779NIHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PinNamesVar.h b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PinNamesVar.h index d55aec5c28..b24c78d7ad 100644 --- a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PinNamesVar.h +++ b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PinNamesVar.h @@ -70,12 +70,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c index 5539742987..2f1ea8e946 100644 --- a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c +++ b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F769IGTx.xml, STM32F769IITx.xml * STM32F779IITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PinNamesVar.h b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PinNamesVar.h index d55aec5c28..b24c78d7ad 100644 --- a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PinNamesVar.h +++ b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PinNamesVar.h @@ -70,12 +70,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PI_11, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 154b1e2ac562b48e450457aaaeae508ca2785fe4 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:28:38 +0100 Subject: [PATCH 045/141] chore(g0): update variant after script update Signed-off-by: Frederic Pillon --- variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G030C(6-8)T/PinNamesVar.h | 6 ------ variants/STM32G0xx/G030F6P/PeripheralPins.c | 2 +- variants/STM32G0xx/G030F6P/PinNamesVar.h | 6 ------ variants/STM32G0xx/G030J6M/PeripheralPins.c | 2 +- variants/STM32G0xx/G030J6M/PinNamesVar.h | 6 ------ variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G030K(6-8)T/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c | 2 +- .../G031G(4-6-8)U_G041G(6-8)U/PinNamesVar.h | 6 ------ .../STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c | 2 +- variants/STM32G0xx/G031J(4-6)M_G041J6M/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PinNamesVar.h | 6 ------ variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G050C(6-8)T/PinNamesVar.h | 6 ------ variants/STM32G0xx/G050F6P/PeripheralPins.c | 2 +- variants/STM32G0xx/G050F6P/PinNamesVar.h | 6 ------ variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G050K(6-8)T/PinNamesVar.h | 6 ------ .../G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c | 2 +- .../G051C(6-8)(T-U)_G061C(6-8)(T-U)/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../G051G(6-8)U_G061G(6-8)U/PeripheralPins.c | 2 +- .../STM32G0xx/G051G(6-8)U_G061G(6-8)U/PinNamesVar.h | 6 ------ .../G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c | 2 +- .../G051K(6-8)(T-U)_G061K(6-8)(T-U)/PinNamesVar.h | 6 ------ variants/STM32G0xx/G070CBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070CBT/PinNamesVar.h | 6 ------ variants/STM32G0xx/G070KBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070KBT/PinNamesVar.h | 6 ------ variants/STM32G0xx/G070RBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070RBT/PinNamesVar.h | 6 ------ .../G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c | 2 +- .../G071C(6-8-B)(T-U)_G081CB(T-U)/PinNamesVar.h | 6 ------ variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c | 2 +- variants/STM32G0xx/G071EBY_G081EBY/PinNamesVar.h | 6 ------ .../STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c | 2 +- .../STM32G0xx/G071G(6-8-B)U_G081GBU/PinNamesVar.h | 6 ------ .../G071G(8-B)UxN_G081GBUxN/PeripheralPins.c | 2 +- .../STM32G0xx/G071G(8-B)UxN_G081GBUxN/PinNamesVar.h | 12 ------------ .../G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c | 2 +- .../G071K(6-8-B)(T-U)_G081KB(T-U)/PinNamesVar.h | 6 ------ .../G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c | 2 +- .../G071K(8-B)(T-U)xN_G081KB(T-U)xN/PinNamesVar.h | 12 ------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ variants/STM32G0xx/G0B0CET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0CET/PinNamesVar.h | 6 ------ variants/STM32G0xx/G0B0KET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0KET/PinNamesVar.h | 6 ------ variants/STM32G0xx/G0B0RET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0RET/PinNamesVar.h | 6 ------ variants/STM32G0xx/G0B0VET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0VET/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 ------------ .../G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c | 2 +- .../G0B1M(B-C-E)T_G0C1M(C-E)T/PinNamesVar.h | 6 ------ variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B1NEY_G0C1NEY/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c | 2 +- .../G0B1R(B-C-E)T_G0C1R(C-E)T/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PinNamesVar.h | 6 ------ 78 files changed, 39 insertions(+), 291 deletions(-) diff --git a/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c index 58c741c6fd..20adab0fdc 100644 --- a/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030C(6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030C(6-8)T/PinNamesVar.h b/variants/STM32G0xx/G030C(6-8)T/PinNamesVar.h index 5a76aea0e2..aced865242 100644 --- a/variants/STM32G0xx/G030C(6-8)T/PinNamesVar.h +++ b/variants/STM32G0xx/G030C(6-8)T/PinNamesVar.h @@ -31,11 +31,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G030F6P/PeripheralPins.c b/variants/STM32G0xx/G030F6P/PeripheralPins.c index cf75c10619..dd5b78512b 100644 --- a/variants/STM32G0xx/G030F6P/PeripheralPins.c +++ b/variants/STM32G0xx/G030F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030F6Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030F6P/PinNamesVar.h b/variants/STM32G0xx/G030F6P/PinNamesVar.h index 950c0c644f..c144558889 100644 --- a/variants/STM32G0xx/G030F6P/PinNamesVar.h +++ b/variants/STM32G0xx/G030F6P/PinNamesVar.h @@ -31,11 +31,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G030J6M/PeripheralPins.c b/variants/STM32G0xx/G030J6M/PeripheralPins.c index f100bffe24..e4b7fb228c 100644 --- a/variants/STM32G0xx/G030J6M/PeripheralPins.c +++ b/variants/STM32G0xx/G030J6M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030J6Mx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030J6M/PinNamesVar.h b/variants/STM32G0xx/G030J6M/PinNamesVar.h index 6a88d7c307..817d2822b9 100644 --- a/variants/STM32G0xx/G030J6M/PinNamesVar.h +++ b/variants/STM32G0xx/G030J6M/PinNamesVar.h @@ -27,11 +27,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c index 5669df3976..85e7275057 100644 --- a/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030K(6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030K(6-8)T/PinNamesVar.h b/variants/STM32G0xx/G030K(6-8)T/PinNamesVar.h index 950c0c644f..c144558889 100644 --- a/variants/STM32G0xx/G030K(6-8)T/PinNamesVar.h +++ b/variants/STM32G0xx/G030K(6-8)T/PinNamesVar.h @@ -31,11 +31,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c index 900a9b9a6e..22b7dea710 100644 --- a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031C(4-6-8)Tx.xml, STM32G031C(4-6-8)Ux.xml * STM32G041C(6-8)Tx.xml, STM32G041C(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PinNamesVar.h b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PinNamesVar.h index 9002f6c140..4d3fcee086 100644 --- a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PinNamesVar.h +++ b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PinNamesVar.h @@ -36,11 +36,5 @@ PC_7_ALT1 = PC_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c index 2dc97a1a0f..c93e656975 100644 --- a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c +++ b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031F(4-6-8)Px.xml, STM32G031Y8Yx.xml * STM32G041F(6-8)Px.xml, STM32G041Y8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PinNamesVar.h b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PinNamesVar.h index a347b21016..e0cdf3de1e 100644 --- a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PinNamesVar.h +++ b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PinNamesVar.h @@ -34,11 +34,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c index 47f493f542..1bdd83148b 100644 --- a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c +++ b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G031G(4-6-8)Ux.xml, STM32G041G(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PinNamesVar.h b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PinNamesVar.h index c9946f615e..08cd18d317 100644 --- a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PinNamesVar.h +++ b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PinNamesVar.h @@ -35,11 +35,5 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c index 06405e8c01..0f6103545c 100644 --- a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c +++ b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G031J(4-6)Mx.xml, STM32G041J6Mx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PinNamesVar.h b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PinNamesVar.h index 285ca58cb7..2a37e8961e 100644 --- a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PinNamesVar.h +++ b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PinNamesVar.h @@ -28,11 +28,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c index aa846eb46e..709fc990aa 100644 --- a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031K(4-6-8)Tx.xml, STM32G031K(4-6-8)Ux.xml * STM32G041K(6-8)Tx.xml, STM32G041K(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PinNamesVar.h b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PinNamesVar.h index c9946f615e..08cd18d317 100644 --- a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PinNamesVar.h +++ b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PinNamesVar.h @@ -35,11 +35,5 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c index 6f3c28ee77..d73026820b 100644 --- a/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050C6Tx.xml, STM32G050C8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050C(6-8)T/PinNamesVar.h b/variants/STM32G0xx/G050C(6-8)T/PinNamesVar.h index 8998ca66f0..6c1f228984 100644 --- a/variants/STM32G0xx/G050C(6-8)T/PinNamesVar.h +++ b/variants/STM32G0xx/G050C(6-8)T/PinNamesVar.h @@ -35,11 +35,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G050F6P/PeripheralPins.c b/variants/STM32G0xx/G050F6P/PeripheralPins.c index 61a47f5fd2..57e8579d18 100644 --- a/variants/STM32G0xx/G050F6P/PeripheralPins.c +++ b/variants/STM32G0xx/G050F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050F6Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050F6P/PinNamesVar.h b/variants/STM32G0xx/G050F6P/PinNamesVar.h index 950c0c644f..c144558889 100644 --- a/variants/STM32G0xx/G050F6P/PinNamesVar.h +++ b/variants/STM32G0xx/G050F6P/PinNamesVar.h @@ -31,11 +31,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c index 8a6cd9aa42..0ebe776f93 100644 --- a/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050K6Tx.xml, STM32G050K8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050K(6-8)T/PinNamesVar.h b/variants/STM32G0xx/G050K(6-8)T/PinNamesVar.h index 950c0c644f..c144558889 100644 --- a/variants/STM32G0xx/G050K(6-8)T/PinNamesVar.h +++ b/variants/STM32G0xx/G050K(6-8)T/PinNamesVar.h @@ -31,11 +31,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c index e203be94b9..9a19817cf1 100644 --- a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051C(6-8)Tx.xml, STM32G051C(6-8)Ux.xml * STM32G061C(6-8)Tx.xml, STM32G061C(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PinNamesVar.h b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PinNamesVar.h index 9d50b48b37..ca1a70be19 100644 --- a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PinNamesVar.h +++ b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PinNamesVar.h @@ -41,11 +41,5 @@ PC_7_ALT1 = PC_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c index 06c5ee4ca2..26a0a947b3 100644 --- a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c +++ b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051F(6-8)Px.xml, STM32G051F8Yx.xml * STM32G061F(6-8)Px.xml, STM32G061F8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PinNamesVar.h b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PinNamesVar.h index 4587d0dc3a..c58893a597 100644 --- a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PinNamesVar.h +++ b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PinNamesVar.h @@ -35,11 +35,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c index ae82739a50..9d473f1f5f 100644 --- a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c +++ b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G051G(6-8)Ux.xml, STM32G061G(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PinNamesVar.h b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PinNamesVar.h index ee36e0cc5b..44b36fa510 100644 --- a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PinNamesVar.h +++ b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PinNamesVar.h @@ -36,11 +36,5 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c index 413196b3bf..6114cf3013 100644 --- a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051K(6-8)Tx.xml, STM32G051K(6-8)Ux.xml * STM32G061K(6-8)Tx.xml, STM32G061K(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PinNamesVar.h b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PinNamesVar.h index ee36e0cc5b..44b36fa510 100644 --- a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PinNamesVar.h +++ b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PinNamesVar.h @@ -36,11 +36,5 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G070CBT/PeripheralPins.c b/variants/STM32G0xx/G070CBT/PeripheralPins.c index b91a476cd9..3f585ca446 100644 --- a/variants/STM32G0xx/G070CBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070CBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070CBT/PinNamesVar.h b/variants/STM32G0xx/G070CBT/PinNamesVar.h index 74e25d6bed..6ad84e20ce 100644 --- a/variants/STM32G0xx/G070CBT/PinNamesVar.h +++ b/variants/STM32G0xx/G070CBT/PinNamesVar.h @@ -36,11 +36,5 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G070KBT/PeripheralPins.c b/variants/STM32G0xx/G070KBT/PeripheralPins.c index 1e1555df09..7fed46efb4 100644 --- a/variants/STM32G0xx/G070KBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070KBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070KBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070KBT/PinNamesVar.h b/variants/STM32G0xx/G070KBT/PinNamesVar.h index 3dec5dd66a..6dc5bb5b54 100644 --- a/variants/STM32G0xx/G070KBT/PinNamesVar.h +++ b/variants/STM32G0xx/G070KBT/PinNamesVar.h @@ -32,11 +32,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G070RBT/PeripheralPins.c b/variants/STM32G0xx/G070RBT/PeripheralPins.c index 7edf79d579..73dff82f5b 100644 --- a/variants/STM32G0xx/G070RBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070RBT/PinNamesVar.h b/variants/STM32G0xx/G070RBT/PinNamesVar.h index 5ea000facc..28a10c4470 100644 --- a/variants/STM32G0xx/G070RBT/PinNamesVar.h +++ b/variants/STM32G0xx/G070RBT/PinNamesVar.h @@ -42,11 +42,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c index 447d8ce3a2..4bb0c13cda 100644 --- a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071C(6-8-B)Tx.xml, STM32G071C(6-8-B)Ux.xml * STM32G081CBTx.xml, STM32G081CBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PinNamesVar.h b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PinNamesVar.h index 4ffa7ffa6d..8ea1a7279d 100644 --- a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PinNamesVar.h +++ b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PinNamesVar.h @@ -42,11 +42,5 @@ PC_7_ALT1 = PC_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c b/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c index b6dda78977..9a207c30e3 100644 --- a/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c +++ b/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071EBYx.xml, STM32G081EBYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071EBY_G081EBY/PinNamesVar.h b/variants/STM32G0xx/G071EBY_G081EBY/PinNamesVar.h index 6243202154..da64d3b54b 100644 --- a/variants/STM32G0xx/G071EBY_G081EBY/PinNamesVar.h +++ b/variants/STM32G0xx/G071EBY_G081EBY/PinNamesVar.h @@ -35,11 +35,5 @@ PB_6_ALT1 = PB_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c index 67c6feec49..9d4506f686 100644 --- a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c +++ b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071G(6-8-B)Ux.xml, STM32G081GBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PinNamesVar.h b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PinNamesVar.h index 62b323b657..78b33afae1 100644 --- a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PinNamesVar.h +++ b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PinNamesVar.h @@ -37,11 +37,5 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c index bd49626f44..aab049b1fb 100644 --- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c +++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071G(8-B)UxN.xml, STM32G081GBUxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PinNamesVar.h b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PinNamesVar.h index e0013c0fc3..83d524aa67 100644 --- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PinNamesVar.h +++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PinNamesVar.h @@ -29,17 +29,5 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c index 3121ad477b..5b7e70a1aa 100644 --- a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071K(6-8-B)Tx.xml, STM32G071K(6-8-B)Ux.xml * STM32G081KBTx.xml, STM32G081KBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PinNamesVar.h b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PinNamesVar.h index 62b323b657..78b33afae1 100644 --- a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PinNamesVar.h +++ b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PinNamesVar.h @@ -37,11 +37,5 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c index 8f841910e0..5325b00a54 100644 --- a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071K(8-B)TxN.xml, STM32G071K(8-B)UxN.xml * STM32G081KBTxN.xml, STM32G081KBUxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PinNamesVar.h b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PinNamesVar.h index e4d0180ec2..cc01839acb 100644 --- a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PinNamesVar.h +++ b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PinNamesVar.h @@ -31,17 +31,5 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c index 394522b501..1bb23117a1 100644 --- a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c +++ b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071R(6-8-B)Tx.xml, STM32G071RBIx.xml * STM32G081RBIx.xml, STM32G081RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PinNamesVar.h b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PinNamesVar.h index a8ba9bbb67..a94f5c1936 100644 --- a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PinNamesVar.h +++ b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PinNamesVar.h @@ -48,11 +48,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G0xx/G0B0CET/PeripheralPins.c b/variants/STM32G0xx/G0B0CET/PeripheralPins.c index b117a348a5..c8b58b6236 100644 --- a/variants/STM32G0xx/G0B0CET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0CET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0CETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0CET/PinNamesVar.h b/variants/STM32G0xx/G0B0CET/PinNamesVar.h index 15f8134680..6433cb2dca 100644 --- a/variants/STM32G0xx/G0B0CET/PinNamesVar.h +++ b/variants/STM32G0xx/G0B0CET/PinNamesVar.h @@ -48,12 +48,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B0KET/PeripheralPins.c b/variants/STM32G0xx/G0B0KET/PeripheralPins.c index df14a5fe3f..2d25799291 100644 --- a/variants/STM32G0xx/G0B0KET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0KET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0KETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0KET/PinNamesVar.h b/variants/STM32G0xx/G0B0KET/PinNamesVar.h index e6065c5856..4c6e21f484 100644 --- a/variants/STM32G0xx/G0B0KET/PinNamesVar.h +++ b/variants/STM32G0xx/G0B0KET/PinNamesVar.h @@ -44,12 +44,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B0RET/PeripheralPins.c b/variants/STM32G0xx/G0B0RET/PeripheralPins.c index 5bdb2ab232..036adff7e8 100644 --- a/variants/STM32G0xx/G0B0RET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0RET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0RETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0RET/PinNamesVar.h b/variants/STM32G0xx/G0B0RET/PinNamesVar.h index a87ad50ace..6a12418fb1 100644 --- a/variants/STM32G0xx/G0B0RET/PinNamesVar.h +++ b/variants/STM32G0xx/G0B0RET/PinNamesVar.h @@ -55,12 +55,6 @@ PD_4_ALT1 = PD_4 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B0VET/PeripheralPins.c b/variants/STM32G0xx/G0B0VET/PeripheralPins.c index d19373a873..d80c2d77f6 100644 --- a/variants/STM32G0xx/G0B0VET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0VET/PinNamesVar.h b/variants/STM32G0xx/G0B0VET/PinNamesVar.h index d111f31ede..bd0902758d 100644 --- a/variants/STM32G0xx/G0B0VET/PinNamesVar.h +++ b/variants/STM32G0xx/G0B0VET/PinNamesVar.h @@ -55,12 +55,6 @@ PD_4_ALT1 = PD_4 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c index a30491f1b1..ecf1a5e2f2 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1C(B-C-E)Tx.xml, STM32G0B1C(B-C-E)Ux.xml * STM32G0C1C(C-E)Tx.xml, STM32G0C1C(C-E)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PinNamesVar.h b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PinNamesVar.h index 4e91fa322c..0c1eab1144 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PinNamesVar.h @@ -55,12 +55,6 @@ PC_7_ALT1 = PC_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c index 5fb5c17c71..cfa78484d7 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1C(B-C-E)TxN.xml, STM32G0B1C(B-C-E)UxN.xml * STM32G0C1C(C-E)TxN.xml, STM32G0C1C(C-E)UxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PinNamesVar.h b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PinNamesVar.h index baa0fa01a2..93e7806279 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PinNamesVar.h @@ -53,12 +53,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c index 84c6752a3a..32cc1f6660 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1K(B-C-E)Tx.xml, STM32G0B1K(B-C-E)Ux.xml * STM32G0C1K(C-E)Tx.xml, STM32G0C1K(C-E)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PinNamesVar.h b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PinNamesVar.h index 0b59db432e..c648d5a7e6 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PinNamesVar.h @@ -50,12 +50,6 @@ PC_6_ALT1 = PC_6 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c index 0260138755..ae1feb4ca0 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1K(B-C-E)TxN.xml, STM32G0B1K(B-C-E)UxN.xml * STM32G0C1K(C-E)TxN.xml, STM32G0C1K(C-E)UxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PinNamesVar.h b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PinNamesVar.h index 02022f2560..d8403ecbaa 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PinNamesVar.h @@ -40,18 +40,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c index 17fd414b42..f875d8dd34 100644 --- a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1M(B-C-E)Tx.xml, STM32G0C1M(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PinNamesVar.h b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PinNamesVar.h index 9fc0b87c90..d1ee849c19 100644 --- a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PinNamesVar.h @@ -64,12 +64,6 @@ PD_4_ALT1 = PD_4 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c index 2a078f008c..4df635d8c4 100644 --- a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1NEYx.xml, STM32G0C1NEYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PinNamesVar.h b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PinNamesVar.h index 4a2cc4cc96..e94080ac3a 100644 --- a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PinNamesVar.h @@ -57,12 +57,6 @@ PC_7_ALT1 = PC_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c index 0aaf1b7db1..2b166b4882 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1R(B-C-E)IxN.xml, STM32G0B1R(B-C-E)TxN.xml * STM32G0C1R(C-E)IxN.xml, STM32G0C1R(C-E)TxN.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PinNamesVar.h b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PinNamesVar.h index 9fc0b87c90..d1ee849c19 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PinNamesVar.h @@ -64,12 +64,6 @@ PD_4_ALT1 = PD_4 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c index 7f7574406a..6575d493a7 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1R(B-C-E)Tx.xml, STM32G0C1R(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PinNamesVar.h b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PinNamesVar.h index 9fc0b87c90..d1ee849c19 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PinNamesVar.h @@ -64,12 +64,6 @@ PD_4_ALT1 = PD_4 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c index c462fba174..39d8057867 100644 --- a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1V(B-C-E)Ix.xml, STM32G0B1V(B-C-E)Tx.xml * STM32G0C1V(C-E)Ix.xml, STM32G0C1V(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PinNamesVar.h b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PinNamesVar.h index 7d35869fe7..fa89026642 100644 --- a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PinNamesVar.h +++ b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PinNamesVar.h @@ -65,12 +65,6 @@ PF_7_ALT1 = PF_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PB_5, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 63a7d7c79352902c7d645d936ed5276287a9ac98 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:30:58 +0100 Subject: [PATCH 046/141] chore(g4): update variant after script update Signed-off-by: Frederic Pillon --- .../STM32G4xx/G411C(6-8-B)T/PeripheralPins.c | 2 +- .../STM32G4xx/G411C(6-8-B)T/PinNamesVar.h | 12 - .../STM32G4xx/G411C(6-8-B)T/boards_entry.txt | 3 + .../STM32G4xx/G411C(6-8-B)U/PeripheralPins.c | 2 +- .../STM32G4xx/G411C(6-8-B)U/PinNamesVar.h | 12 - .../STM32G4xx/G411C(6-8-B)U/boards_entry.txt | 3 + variants/STM32G4xx/G411CCT/PeripheralPins.c | 294 +++++++++++++++ variants/STM32G4xx/G411CCT/PinNamesVar.h | 56 +++ variants/STM32G4xx/G411CCT/boards_entry.txt | 14 + variants/STM32G4xx/G411CCT/generic_clock.c | 27 ++ .../STM32G4xx/G411CCT/variant_generic.cpp | 80 ++++ variants/STM32G4xx/G411CCT/variant_generic.h | 196 ++++++++++ variants/STM32G4xx/G411CCU/PeripheralPins.c | 303 +++++++++++++++ variants/STM32G4xx/G411CCU/PinNamesVar.h | 57 +++ variants/STM32G4xx/G411CCU/boards_entry.txt | 14 + variants/STM32G4xx/G411CCU/generic_clock.c | 27 ++ .../STM32G4xx/G411CCU/variant_generic.cpp | 85 +++++ variants/STM32G4xx/G411CCU/variant_generic.h | 201 ++++++++++ .../G411K(6-8-B)(T-U)/PeripheralPins.c | 2 +- .../STM32G4xx/G411K(6-8-B)(T-U)/PinNamesVar.h | 12 - .../G411K(6-8-B)(T-U)/boards_entry.txt | 6 + .../STM32G4xx/G411M(6-8-B)T/PeripheralPins.c | 2 +- .../STM32G4xx/G411M(6-8-B)T/PinNamesVar.h | 9 - .../STM32G4xx/G411M(6-8-B)T/boards_entry.txt | 3 + variants/STM32G4xx/G411MCT/PeripheralPins.c | 349 ++++++++++++++++++ variants/STM32G4xx/G411MCT/PinNamesVar.h | 68 ++++ variants/STM32G4xx/G411MCT/boards_entry.txt | 14 + variants/STM32G4xx/G411MCT/generic_clock.c | 27 ++ .../STM32G4xx/G411MCT/variant_generic.cpp | 122 ++++++ variants/STM32G4xx/G411MCT/variant_generic.h | 233 ++++++++++++ .../STM32G4xx/G411R(6-8-B)T/PeripheralPins.c | 2 +- .../STM32G4xx/G411R(6-8-B)T/PinNamesVar.h | 9 - .../STM32G4xx/G411R(6-8-B)T/boards_entry.txt | 3 + variants/STM32G4xx/G411RCT/PeripheralPins.c | 329 +++++++++++++++++ variants/STM32G4xx/G411RCT/PinNamesVar.h | 68 ++++ variants/STM32G4xx/G411RCT/boards_entry.txt | 14 + variants/STM32G4xx/G411RCT/generic_clock.c | 27 ++ .../STM32G4xx/G411RCT/variant_generic.cpp | 100 +++++ variants/STM32G4xx/G411RCT/variant_generic.h | 219 +++++++++++ .../STM32G4xx/G414C(B-C)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G414C(B-C)T/PinNamesVar.h | 12 - .../STM32G4xx/G414C(B-C)T/boards_entry.txt | 4 +- .../STM32G4xx/G414C(B-C)U/PeripheralPins.c | 2 +- variants/STM32G4xx/G414C(B-C)U/PinNamesVar.h | 12 - .../STM32G4xx/G414C(B-C)U/boards_entry.txt | 4 +- .../STM32G4xx/G414M(B-C)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G414M(B-C)T/PinNamesVar.h | 9 - .../STM32G4xx/G414M(B-C)T/boards_entry.txt | 4 +- .../STM32G4xx/G414R(B-C)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G414R(B-C)T/PinNamesVar.h | 9 - .../STM32G4xx/G414R(B-C)T/boards_entry.txt | 4 +- .../STM32G4xx/G414V(B-C)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G414V(B-C)T/PinNamesVar.h | 9 - .../STM32G4xx/G414V(B-C)T/boards_entry.txt | 4 +- .../G431C(6-8-B)T_G441CBT/PeripheralPins.c | 2 +- .../G431C(6-8-B)T_G441CBT/PinNamesVar.h | 12 - .../G431C(6-8-B)U_G441CBU/PeripheralPins.c | 2 +- .../G431C(6-8-B)U_G441CBU/PinNamesVar.h | 12 - variants/STM32G4xx/G431CBTxZ/PeripheralPins.c | 2 +- variants/STM32G4xx/G431CBTxZ/PinNamesVar.h | 12 - .../G431CBY_G441CBY/PeripheralPins.c | 2 +- .../STM32G4xx/G431CBY_G441CBY/PinNamesVar.h | 12 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 - .../G431M(6-8-B)T_G441MBT/PeripheralPins.c | 2 +- .../G431M(6-8-B)T_G441MBT/PinNamesVar.h | 9 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 - .../G431V(6-8-B)T_G441VBT/PeripheralPins.c | 2 +- .../G431V(6-8-B)T_G441VBT/PinNamesVar.h | 9 - .../STM32G4xx/G471C(C-E)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G471C(C-E)T/PinNamesVar.h | 12 - .../STM32G4xx/G471C(C-E)U/PeripheralPins.c | 2 +- variants/STM32G4xx/G471C(C-E)U/PinNamesVar.h | 12 - .../STM32G4xx/G471M(C-E)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G471M(C-E)T/PinNamesVar.h | 9 - variants/STM32G4xx/G471MEY/PeripheralPins.c | 2 +- variants/STM32G4xx/G471MEY/PinNamesVar.h | 9 - .../STM32G4xx/G471Q(C-E)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G471Q(C-E)T/PinNamesVar.h | 9 - .../STM32G4xx/G471R(C-E)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G471R(C-E)T/PinNamesVar.h | 9 - .../G471V(C-E)(H-I-T)/PeripheralPins.c | 2 +- .../STM32G4xx/G471V(C-E)(H-I-T)/PinNamesVar.h | 9 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 - .../G491C(C-E)T_G4A1CET/PeripheralPins.c | 2 +- .../G491C(C-E)T_G4A1CET/PinNamesVar.h | 12 - .../G491C(C-E)U_G4A1CEU/PeripheralPins.c | 2 +- .../G491C(C-E)U_G4A1CEU/PinNamesVar.h | 12 - .../G491K(C-E)U_G4A1KEU/PeripheralPins.c | 2 +- .../G491K(C-E)U_G4A1KEU/PinNamesVar.h | 12 - .../PeripheralPins.c | 2 +- .../G491M(C-E)(S-T)_G4A1ME(S-T)/PinNamesVar.h | 9 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 - .../G491V(C-E)T_G4A1VET/PeripheralPins.c | 2 +- .../G491V(C-E)T_G4A1VET/PinNamesVar.h | 9 - 112 files changed, 2991 insertions(+), 451 deletions(-) create mode 100644 variants/STM32G4xx/G411CCT/PeripheralPins.c create mode 100644 variants/STM32G4xx/G411CCT/PinNamesVar.h create mode 100644 variants/STM32G4xx/G411CCT/boards_entry.txt create mode 100644 variants/STM32G4xx/G411CCT/generic_clock.c create mode 100644 variants/STM32G4xx/G411CCT/variant_generic.cpp create mode 100644 variants/STM32G4xx/G411CCT/variant_generic.h create mode 100644 variants/STM32G4xx/G411CCU/PeripheralPins.c create mode 100644 variants/STM32G4xx/G411CCU/PinNamesVar.h create mode 100644 variants/STM32G4xx/G411CCU/boards_entry.txt create mode 100644 variants/STM32G4xx/G411CCU/generic_clock.c create mode 100644 variants/STM32G4xx/G411CCU/variant_generic.cpp create mode 100644 variants/STM32G4xx/G411CCU/variant_generic.h create mode 100644 variants/STM32G4xx/G411MCT/PeripheralPins.c create mode 100644 variants/STM32G4xx/G411MCT/PinNamesVar.h create mode 100644 variants/STM32G4xx/G411MCT/boards_entry.txt create mode 100644 variants/STM32G4xx/G411MCT/generic_clock.c create mode 100644 variants/STM32G4xx/G411MCT/variant_generic.cpp create mode 100644 variants/STM32G4xx/G411MCT/variant_generic.h create mode 100644 variants/STM32G4xx/G411RCT/PeripheralPins.c create mode 100644 variants/STM32G4xx/G411RCT/PinNamesVar.h create mode 100644 variants/STM32G4xx/G411RCT/boards_entry.txt create mode 100644 variants/STM32G4xx/G411RCT/generic_clock.c create mode 100644 variants/STM32G4xx/G411RCT/variant_generic.cpp create mode 100644 variants/STM32G4xx/G411RCT/variant_generic.h diff --git a/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c index dfae0c1383..c695892b9f 100644 --- a/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411C6Tx.xml, STM32G411C8Tx.xml * STM32G411CBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411C(6-8-B)T/PinNamesVar.h b/variants/STM32G4xx/G411C(6-8-B)T/PinNamesVar.h index a5ed67e53b..c5712d55e4 100644 --- a/variants/STM32G4xx/G411C(6-8-B)T/PinNamesVar.h +++ b/variants/STM32G4xx/G411C(6-8-B)T/PinNamesVar.h @@ -52,17 +52,5 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G411C(6-8-B)T/boards_entry.txt b/variants/STM32G4xx/G411C(6-8-B)T/boards_entry.txt index e22ce30274..1836d3de29 100644 --- a/variants/STM32G4xx/G411C(6-8-B)T/boards_entry.txt +++ b/variants/STM32G4xx/G411C(6-8-B)T/boards_entry.txt @@ -10,6 +10,7 @@ GenG4.menu.pnum.GENERIC_G411C6TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411C6TX.build.board=GENERIC_G411C6TX GenG4.menu.pnum.GENERIC_G411C6TX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411C6TX.build.variant=STM32G4xx/G411C(6-8-B)T +GenG4.menu.pnum.GENERIC_G411C6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411C8Tx GenG4.menu.pnum.GENERIC_G411C8TX=Generic G411C8Tx @@ -18,6 +19,7 @@ GenG4.menu.pnum.GENERIC_G411C8TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411C8TX.build.board=GENERIC_G411C8TX GenG4.menu.pnum.GENERIC_G411C8TX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411C8TX.build.variant=STM32G4xx/G411C(6-8-B)T +GenG4.menu.pnum.GENERIC_G411C8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411CBTx GenG4.menu.pnum.GENERIC_G411CBTX=Generic G411CBTx @@ -26,4 +28,5 @@ GenG4.menu.pnum.GENERIC_G411CBTX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411CBTX.build.board=GENERIC_G411CBTX GenG4.menu.pnum.GENERIC_G411CBTX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411CBTX.build.variant=STM32G4xx/G411C(6-8-B)T +GenG4.menu.pnum.GENERIC_G411CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd diff --git a/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c b/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c index e475ee06ea..ac120b68c9 100644 --- a/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c +++ b/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411C6Ux.xml, STM32G411C8Ux.xml * STM32G411CBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411C(6-8-B)U/PinNamesVar.h b/variants/STM32G4xx/G411C(6-8-B)U/PinNamesVar.h index 30a0312ec4..582bcf08c4 100644 --- a/variants/STM32G4xx/G411C(6-8-B)U/PinNamesVar.h +++ b/variants/STM32G4xx/G411C(6-8-B)U/PinNamesVar.h @@ -53,17 +53,5 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G411C(6-8-B)U/boards_entry.txt b/variants/STM32G4xx/G411C(6-8-B)U/boards_entry.txt index e102cc2f91..bd0d18cdb8 100644 --- a/variants/STM32G4xx/G411C(6-8-B)U/boards_entry.txt +++ b/variants/STM32G4xx/G411C(6-8-B)U/boards_entry.txt @@ -10,6 +10,7 @@ GenG4.menu.pnum.GENERIC_G411C6UX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411C6UX.build.board=GENERIC_G411C6UX GenG4.menu.pnum.GENERIC_G411C6UX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411C6UX.build.variant=STM32G4xx/G411C(6-8-B)U +GenG4.menu.pnum.GENERIC_G411C6UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411C8Ux GenG4.menu.pnum.GENERIC_G411C8UX=Generic G411C8Ux @@ -18,6 +19,7 @@ GenG4.menu.pnum.GENERIC_G411C8UX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411C8UX.build.board=GENERIC_G411C8UX GenG4.menu.pnum.GENERIC_G411C8UX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411C8UX.build.variant=STM32G4xx/G411C(6-8-B)U +GenG4.menu.pnum.GENERIC_G411C8UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411CBUx GenG4.menu.pnum.GENERIC_G411CBUX=Generic G411CBUx @@ -26,4 +28,5 @@ GenG4.menu.pnum.GENERIC_G411CBUX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411CBUX.build.board=GENERIC_G411CBUX GenG4.menu.pnum.GENERIC_G411CBUX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411CBUX.build.variant=STM32G4xx/G411C(6-8-B)U +GenG4.menu.pnum.GENERIC_G411CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd diff --git a/variants/STM32G4xx/G411CCT/PeripheralPins.c b/variants/STM32G4xx/G411CCT/PeripheralPins.c new file mode 100644 index 0000000000..fd8b8d7973 --- /dev/null +++ b/variants/STM32G4xx/G411CCT/PeripheralPins.c @@ -0,0 +1,294 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32G411CCTx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_11_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PB_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PB_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PB_15, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PF_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PF_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_8, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 + {PA_10_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_11_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 + {PA_11_ALT2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PA_12_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 + {PA_12_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 + {PA_13_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PA_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM20, 1, 0)}, // TIM20_CH1 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_4_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_5_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 + {PB_8_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1_COMP1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)}, // TIM8_CH3 + {PB_9_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)}, // TIM15_CH2 + {PC_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)}, // TIM1_CH1N + {PC_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM8, 4, 1)}, // TIM8_CH4N + {PF_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32G4xx/G411CCT/PinNamesVar.h b/variants/STM32G4xx/G411CCT/PinNamesVar.h new file mode 100644 index 0000000000..c5712d55e4 --- /dev/null +++ b/variants/STM32G4xx/G411CCT/PinNamesVar.h @@ -0,0 +1,56 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_11_ALT2 = PA_11 | ALT2, +PA_12_ALT1 = PA_12 | ALT1, +PA_12_ALT2 = PA_12 | ALT2, +PA_13_ALT1 = PA_13 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_8_ALT2 = PB_8 | ALT2, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_9_ALT3 = PB_9 | ALT3, +PB_11_ALT1 = PB_11 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_13_ALT1 = PC_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif + +/* No USB */ diff --git a/variants/STM32G4xx/G411CCT/boards_entry.txt b/variants/STM32G4xx/G411CCT/boards_entry.txt new file mode 100644 index 0000000000..838ed7ccc7 --- /dev/null +++ b/variants/STM32G4xx/G411CCT/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic G411CCTx +GenG4.menu.pnum.GENERIC_G411CCTX=Generic G411CCTx +GenG4.menu.pnum.GENERIC_G411CCTX.upload.maximum_size=262144 +GenG4.menu.pnum.GENERIC_G411CCTX.upload.maximum_data_size=262144 +GenG4.menu.pnum.GENERIC_G411CCTX.build.board=GENERIC_G411CCTX +GenG4.menu.pnum.GENERIC_G411CCTX.build.product_line=STM32G411xC +GenG4.menu.pnum.GENERIC_G411CCTX.build.variant=STM32G4xx/G411CCT +GenG4.menu.pnum.GENERIC_G411CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd + diff --git a/variants/STM32G4xx/G411CCT/generic_clock.c b/variants/STM32G4xx/G411CCT/generic_clock.c new file mode 100644 index 0000000000..59a90a69b9 --- /dev/null +++ b/variants/STM32G4xx/G411CCT/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G411CCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G411CCT/variant_generic.cpp b/variants/STM32G4xx/G411CCT/variant_generic.cpp new file mode 100644 index 0000000000..94d903d8c1 --- /dev/null +++ b/variants/STM32G4xx/G411CCT/variant_generic.cpp @@ -0,0 +1,80 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G411CCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27/A11 + PB_12, // D28/A12 + PB_13, // D29/A13 + PB_14, // D30/A14 + PB_15, // D31/A15 + PC_13, // D32 + PC_14, // D33 + PC_15, // D34 + PF_0, // D35/A16 + PF_1, // D36/A17 + PG_10 // D37 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 27, // A11, PB11 + 28, // A12, PB12 + 29, // A13, PB13 + 30, // A14, PB14 + 31, // A15, PB15 + 35, // A16, PF0 + 36 // A17, PF1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G411CCT/variant_generic.h b/variants/STM32G4xx/G411CCT/variant_generic.h new file mode 100644 index 0000000000..d5c7fec35a --- /dev/null +++ b/variants/STM32G4xx/G411CCT/variant_generic.h @@ -0,0 +1,196 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 PIN_A11 +#define PB12 PIN_A12 +#define PB13 PIN_A13 +#define PB14 PIN_A14 +#define PB15 PIN_A15 +#define PC13 32 +#define PC14 33 +#define PC15 34 +#define PF0 PIN_A16 +#define PF1 PIN_A17 +#define PG10 37 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA11_ALT2 (PA11 | ALT2) +#define PA12_ALT1 (PA12 | ALT1) +#define PA12_ALT2 (PA12 | ALT2) +#define PA13_ALT1 (PA13 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB8_ALT2 (PB8 | ALT2) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB9_ALT3 (PB9 | ALT3) +#define PB11_ALT1 (PB11 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC13_ALT1 (PC13 | ALT1) + +#define NUM_DIGITAL_PINS 38 +#define NUM_ANALOG_INPUTS 18 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA8 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32G4xx/G411CCU/PeripheralPins.c b/variants/STM32G4xx/G411CCU/PeripheralPins.c new file mode 100644 index 0000000000..8b73453b97 --- /dev/null +++ b/variants/STM32G4xx/G411CCU/PeripheralPins.c @@ -0,0 +1,303 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32G411CCUx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_11_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PB_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PB_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PB_15, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PF_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PF_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_8, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PC_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 + {PA_10_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_11_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 + {PA_11_ALT2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PA_12_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 + {PA_12_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 + {PA_13_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PA_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM20, 1, 0)}, // TIM20_CH1 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_4_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_5_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 + {PB_8_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1_COMP1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)}, // TIM8_CH3 + {PB_9_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 0)}, // TIM8_CH1 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PC_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)}, // TIM1_CH1N + {PC_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM8, 4, 1)}, // TIM8_CH4N + {PF_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32G4xx/G411CCU/PinNamesVar.h b/variants/STM32G4xx/G411CCU/PinNamesVar.h new file mode 100644 index 0000000000..582bcf08c4 --- /dev/null +++ b/variants/STM32G4xx/G411CCU/PinNamesVar.h @@ -0,0 +1,57 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_11_ALT2 = PA_11 | ALT2, +PA_12_ALT1 = PA_12 | ALT1, +PA_12_ALT2 = PA_12 | ALT2, +PA_13_ALT1 = PA_13 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_8_ALT2 = PB_8 | ALT2, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_9_ALT3 = PB_9 | ALT3, +PB_11_ALT1 = PB_11 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_13_ALT1 = PC_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif + +/* No USB */ diff --git a/variants/STM32G4xx/G411CCU/boards_entry.txt b/variants/STM32G4xx/G411CCU/boards_entry.txt new file mode 100644 index 0000000000..d5ba91f39b --- /dev/null +++ b/variants/STM32G4xx/G411CCU/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic G411CCUx +GenG4.menu.pnum.GENERIC_G411CCUX=Generic G411CCUx +GenG4.menu.pnum.GENERIC_G411CCUX.upload.maximum_size=262144 +GenG4.menu.pnum.GENERIC_G411CCUX.upload.maximum_data_size=262144 +GenG4.menu.pnum.GENERIC_G411CCUX.build.board=GENERIC_G411CCUX +GenG4.menu.pnum.GENERIC_G411CCUX.build.product_line=STM32G411xC +GenG4.menu.pnum.GENERIC_G411CCUX.build.variant=STM32G4xx/G411CCU +GenG4.menu.pnum.GENERIC_G411CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd + diff --git a/variants/STM32G4xx/G411CCU/generic_clock.c b/variants/STM32G4xx/G411CCU/generic_clock.c new file mode 100644 index 0000000000..7406c648ba --- /dev/null +++ b/variants/STM32G4xx/G411CCU/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G411CCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G411CCU/variant_generic.cpp b/variants/STM32G4xx/G411CCU/variant_generic.cpp new file mode 100644 index 0000000000..9b63d00ee1 --- /dev/null +++ b/variants/STM32G4xx/G411CCU/variant_generic.cpp @@ -0,0 +1,85 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G411CCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27/A11 + PB_12, // D28/A12 + PB_13, // D29/A13 + PB_14, // D30/A14 + PB_15, // D31/A15 + PC_4, // D32/A16 + PC_6, // D33 + PC_10, // D34 + PC_11, // D35 + PC_13, // D36 + PC_14, // D37 + PC_15, // D38 + PF_0, // D39/A17 + PF_1, // D40/A18 + PG_10 // D41 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 27, // A11, PB11 + 28, // A12, PB12 + 29, // A13, PB13 + 30, // A14, PB14 + 31, // A15, PB15 + 32, // A16, PC4 + 39, // A17, PF0 + 40 // A18, PF1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G411CCU/variant_generic.h b/variants/STM32G4xx/G411CCU/variant_generic.h new file mode 100644 index 0000000000..503fa7d61b --- /dev/null +++ b/variants/STM32G4xx/G411CCU/variant_generic.h @@ -0,0 +1,201 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 PIN_A11 +#define PB12 PIN_A12 +#define PB13 PIN_A13 +#define PB14 PIN_A14 +#define PB15 PIN_A15 +#define PC4 PIN_A16 +#define PC6 33 +#define PC10 34 +#define PC11 35 +#define PC13 36 +#define PC14 37 +#define PC15 38 +#define PF0 PIN_A17 +#define PF1 PIN_A18 +#define PG10 41 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA11_ALT2 (PA11 | ALT2) +#define PA12_ALT1 (PA12 | ALT1) +#define PA12_ALT2 (PA12 | ALT2) +#define PA13_ALT1 (PA13 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB8_ALT2 (PB8 | ALT2) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB9_ALT3 (PB9 | ALT3) +#define PB11_ALT1 (PB11 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC13_ALT1 (PC13 | ALT1) + +#define NUM_DIGITAL_PINS 42 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA8 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c b/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c index 712c9af7a4..597aceb102 100644 --- a/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G411K6Tx.xml, STM32G411K6Ux.xml * STM32G411K8Tx.xml, STM32G411K8Ux.xml * STM32G411KBTx.xml, STM32G411KBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411K(6-8-B)(T-U)/PinNamesVar.h b/variants/STM32G4xx/G411K(6-8-B)(T-U)/PinNamesVar.h index ea0e344568..c235bfffab 100644 --- a/variants/STM32G4xx/G411K(6-8-B)(T-U)/PinNamesVar.h +++ b/variants/STM32G4xx/G411K(6-8-B)(T-U)/PinNamesVar.h @@ -42,17 +42,5 @@ PB_8_ALT2 = PB_8 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G411K(6-8-B)(T-U)/boards_entry.txt b/variants/STM32G4xx/G411K(6-8-B)(T-U)/boards_entry.txt index 98920ac943..67869302e4 100644 --- a/variants/STM32G4xx/G411K(6-8-B)(T-U)/boards_entry.txt +++ b/variants/STM32G4xx/G411K(6-8-B)(T-U)/boards_entry.txt @@ -10,6 +10,7 @@ GenG4.menu.pnum.GENERIC_G411K6TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411K6TX.build.board=GENERIC_G411K6TX GenG4.menu.pnum.GENERIC_G411K6TX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411K6TX.build.variant=STM32G4xx/G411K(6-8-B)(T-U) +GenG4.menu.pnum.GENERIC_G411K6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411K6Ux GenG4.menu.pnum.GENERIC_G411K6UX=Generic G411K6Ux @@ -18,6 +19,7 @@ GenG4.menu.pnum.GENERIC_G411K6UX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411K6UX.build.board=GENERIC_G411K6UX GenG4.menu.pnum.GENERIC_G411K6UX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411K6UX.build.variant=STM32G4xx/G411K(6-8-B)(T-U) +GenG4.menu.pnum.GENERIC_G411K6UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411K8Tx GenG4.menu.pnum.GENERIC_G411K8TX=Generic G411K8Tx @@ -26,6 +28,7 @@ GenG4.menu.pnum.GENERIC_G411K8TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411K8TX.build.board=GENERIC_G411K8TX GenG4.menu.pnum.GENERIC_G411K8TX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411K8TX.build.variant=STM32G4xx/G411K(6-8-B)(T-U) +GenG4.menu.pnum.GENERIC_G411K8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411K8Ux GenG4.menu.pnum.GENERIC_G411K8UX=Generic G411K8Ux @@ -34,6 +37,7 @@ GenG4.menu.pnum.GENERIC_G411K8UX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411K8UX.build.board=GENERIC_G411K8UX GenG4.menu.pnum.GENERIC_G411K8UX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411K8UX.build.variant=STM32G4xx/G411K(6-8-B)(T-U) +GenG4.menu.pnum.GENERIC_G411K8UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411KBTx GenG4.menu.pnum.GENERIC_G411KBTX=Generic G411KBTx @@ -42,6 +46,7 @@ GenG4.menu.pnum.GENERIC_G411KBTX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411KBTX.build.board=GENERIC_G411KBTX GenG4.menu.pnum.GENERIC_G411KBTX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411KBTX.build.variant=STM32G4xx/G411K(6-8-B)(T-U) +GenG4.menu.pnum.GENERIC_G411KBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411KBUx GenG4.menu.pnum.GENERIC_G411KBUX=Generic G411KBUx @@ -50,4 +55,5 @@ GenG4.menu.pnum.GENERIC_G411KBUX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411KBUX.build.board=GENERIC_G411KBUX GenG4.menu.pnum.GENERIC_G411KBUX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411KBUX.build.variant=STM32G4xx/G411K(6-8-B)(T-U) +GenG4.menu.pnum.GENERIC_G411KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd diff --git a/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c index ef88a7e472..cc11e65663 100644 --- a/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411M6Tx.xml, STM32G411M8Tx.xml * STM32G411MBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411M(6-8-B)T/PinNamesVar.h b/variants/STM32G4xx/G411M(6-8-B)T/PinNamesVar.h index 5dce4eda40..217aca7312 100644 --- a/variants/STM32G4xx/G411M(6-8-B)T/PinNamesVar.h +++ b/variants/STM32G4xx/G411M(6-8-B)T/PinNamesVar.h @@ -63,14 +63,5 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G411M(6-8-B)T/boards_entry.txt b/variants/STM32G4xx/G411M(6-8-B)T/boards_entry.txt index e5ddad5525..849e9b8101 100644 --- a/variants/STM32G4xx/G411M(6-8-B)T/boards_entry.txt +++ b/variants/STM32G4xx/G411M(6-8-B)T/boards_entry.txt @@ -10,6 +10,7 @@ GenG4.menu.pnum.GENERIC_G411M6TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411M6TX.build.board=GENERIC_G411M6TX GenG4.menu.pnum.GENERIC_G411M6TX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411M6TX.build.variant=STM32G4xx/G411M(6-8-B)T +GenG4.menu.pnum.GENERIC_G411M6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411M8Tx GenG4.menu.pnum.GENERIC_G411M8TX=Generic G411M8Tx @@ -18,6 +19,7 @@ GenG4.menu.pnum.GENERIC_G411M8TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411M8TX.build.board=GENERIC_G411M8TX GenG4.menu.pnum.GENERIC_G411M8TX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411M8TX.build.variant=STM32G4xx/G411M(6-8-B)T +GenG4.menu.pnum.GENERIC_G411M8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411MBTx GenG4.menu.pnum.GENERIC_G411MBTX=Generic G411MBTx @@ -26,4 +28,5 @@ GenG4.menu.pnum.GENERIC_G411MBTX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411MBTX.build.board=GENERIC_G411MBTX GenG4.menu.pnum.GENERIC_G411MBTX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411MBTX.build.variant=STM32G4xx/G411M(6-8-B)T +GenG4.menu.pnum.GENERIC_G411MBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd diff --git a/variants/STM32G4xx/G411MCT/PeripheralPins.c b/variants/STM32G4xx/G411MCT/PeripheralPins.c new file mode 100644 index 0000000000..851c0d7c73 --- /dev/null +++ b/variants/STM32G4xx/G411MCT/PeripheralPins.c @@ -0,0 +1,349 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32G411MCTx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_11_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PB_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PB_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PB_15, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PD_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 + {PE_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PE_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 + {PE_11, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 + {PE_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_IN16 + {PE_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PF_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PF_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_8, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PC_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 + {PA_10_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_11_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 + {PA_11_ALT2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PA_12_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 + {PA_12_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 + {PA_13_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PA_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM20, 1, 0)}, // TIM20_CH1 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_4_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_5_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 + {PB_8_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1_COMP1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)}, // TIM8_CH3 + {PB_9_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)}, // TIM15_CH2 + {PC_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PC_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PC_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PC_2_ALT1, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 2, 0)}, // TIM20_CH2 + {PC_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 0)}, // TIM8_CH3 + {PC_8_ALT2, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 3, 0)}, // TIM20_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + {PC_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)}, // TIM1_CH1N + {PC_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM8, 4, 1)}, // TIM8_CH4N + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM8, 4, 1)}, // TIM8_CH4N + {PD_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)}, // TIM8_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 4, 1)}, // TIM1_CH4N + {PF_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32G4xx/G411MCT/PinNamesVar.h b/variants/STM32G4xx/G411MCT/PinNamesVar.h new file mode 100644 index 0000000000..1a8f6b3228 --- /dev/null +++ b/variants/STM32G4xx/G411MCT/PinNamesVar.h @@ -0,0 +1,68 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_11_ALT2 = PA_11 | ALT2, +PA_12_ALT1 = PA_12 | ALT1, +PA_12_ALT2 = PA_12 | ALT2, +PA_13_ALT1 = PA_13 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_8_ALT2 = PB_8 | ALT2, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_9_ALT3 = PB_9 | ALT3, +PB_11_ALT1 = PB_11 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_8_ALT2 = PC_8 | ALT2, +PC_9_ALT1 = PC_9 | ALT1, +PC_13_ALT1 = PC_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PC_5, +#endif + +/* No USB */ diff --git a/variants/STM32G4xx/G411MCT/boards_entry.txt b/variants/STM32G4xx/G411MCT/boards_entry.txt new file mode 100644 index 0000000000..0b49e05202 --- /dev/null +++ b/variants/STM32G4xx/G411MCT/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic G411MCTx +GenG4.menu.pnum.GENERIC_G411MCTX=Generic G411MCTx +GenG4.menu.pnum.GENERIC_G411MCTX.upload.maximum_size=262144 +GenG4.menu.pnum.GENERIC_G411MCTX.upload.maximum_data_size=262144 +GenG4.menu.pnum.GENERIC_G411MCTX.build.board=GENERIC_G411MCTX +GenG4.menu.pnum.GENERIC_G411MCTX.build.product_line=STM32G411xC +GenG4.menu.pnum.GENERIC_G411MCTX.build.variant=STM32G4xx/G411MCT +GenG4.menu.pnum.GENERIC_G411MCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd + diff --git a/variants/STM32G4xx/G411MCT/generic_clock.c b/variants/STM32G4xx/G411MCT/generic_clock.c new file mode 100644 index 0000000000..3c7a07a114 --- /dev/null +++ b/variants/STM32G4xx/G411MCT/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G411MCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G411MCT/variant_generic.cpp b/variants/STM32G4xx/G411MCT/variant_generic.cpp new file mode 100644 index 0000000000..a59adbd2b4 --- /dev/null +++ b/variants/STM32G4xx/G411MCT/variant_generic.cpp @@ -0,0 +1,122 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G411MCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27/A11 + PB_12, // D28/A12 + PB_13, // D29/A13 + PB_14, // D30/A14 + PB_15, // D31/A15 + PC_0, // D32/A16 + PC_1, // D33/A17 + PC_2, // D34/A18 + PC_3, // D35/A19 + PC_4, // D36/A20 + PC_5, // D37/A21 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_8, // D51 + PD_9, // D52 + PD_10, // D53/A22 + PE_7, // D54/A23 + PE_8, // D55/A24 + PE_9, // D56/A25 + PE_10, // D57/A26 + PE_11, // D58/A27 + PE_12, // D59/A28 + PE_13, // D60/A29 + PE_14, // D61 + PE_15, // D62 + PF_0, // D63/A30 + PF_1, // D64/A31 + PG_10 // D65 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 27, // A11, PB11 + 28, // A12, PB12 + 29, // A13, PB13 + 30, // A14, PB14 + 31, // A15, PB15 + 32, // A16, PC0 + 33, // A17, PC1 + 34, // A18, PC2 + 35, // A19, PC3 + 36, // A20, PC4 + 37, // A21, PC5 + 53, // A22, PD10 + 54, // A23, PE7 + 55, // A24, PE8 + 56, // A25, PE9 + 57, // A26, PE10 + 58, // A27, PE11 + 59, // A28, PE12 + 60, // A29, PE13 + 63, // A30, PF0 + 64 // A31, PF1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G411MCT/variant_generic.h b/variants/STM32G4xx/G411MCT/variant_generic.h new file mode 100644 index 0000000000..8abb0baa5d --- /dev/null +++ b/variants/STM32G4xx/G411MCT/variant_generic.h @@ -0,0 +1,233 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 PIN_A11 +#define PB12 PIN_A12 +#define PB13 PIN_A13 +#define PB14 PIN_A14 +#define PB15 PIN_A15 +#define PC0 PIN_A16 +#define PC1 PIN_A17 +#define PC2 PIN_A18 +#define PC3 PIN_A19 +#define PC4 PIN_A20 +#define PC5 PIN_A21 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD8 51 +#define PD9 52 +#define PD10 PIN_A22 +#define PE7 PIN_A23 +#define PE8 PIN_A24 +#define PE9 PIN_A25 +#define PE10 PIN_A26 +#define PE11 PIN_A27 +#define PE12 PIN_A28 +#define PE13 PIN_A29 +#define PE14 61 +#define PE15 62 +#define PF0 PIN_A30 +#define PF1 PIN_A31 +#define PG10 65 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA11_ALT2 (PA11 | ALT2) +#define PA12_ALT1 (PA12 | ALT1) +#define PA12_ALT2 (PA12 | ALT2) +#define PA13_ALT1 (PA13 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB8_ALT2 (PB8 | ALT2) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB9_ALT3 (PB9 | ALT3) +#define PB11_ALT1 (PB11 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC8_ALT2 (PC8 | ALT2) +#define PC9_ALT1 (PC9 | ALT1) +#define PC13_ALT1 (PC13 | ALT1) + +#define NUM_DIGITAL_PINS 66 +#define NUM_ANALOG_INPUTS 32 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA8 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c index b222af45c7..6e1d90a69a 100644 --- a/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411R6Tx.xml, STM32G411R8Tx.xml * STM32G411RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411R(6-8-B)T/PinNamesVar.h b/variants/STM32G4xx/G411R(6-8-B)T/PinNamesVar.h index 5dce4eda40..217aca7312 100644 --- a/variants/STM32G4xx/G411R(6-8-B)T/PinNamesVar.h +++ b/variants/STM32G4xx/G411R(6-8-B)T/PinNamesVar.h @@ -63,14 +63,5 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G411R(6-8-B)T/boards_entry.txt b/variants/STM32G4xx/G411R(6-8-B)T/boards_entry.txt index 5164fe822f..2630f0ab76 100644 --- a/variants/STM32G4xx/G411R(6-8-B)T/boards_entry.txt +++ b/variants/STM32G4xx/G411R(6-8-B)T/boards_entry.txt @@ -10,6 +10,7 @@ GenG4.menu.pnum.GENERIC_G411R6TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411R6TX.build.board=GENERIC_G411R6TX GenG4.menu.pnum.GENERIC_G411R6TX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411R6TX.build.variant=STM32G4xx/G411R(6-8-B)T +GenG4.menu.pnum.GENERIC_G411R6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411R8Tx GenG4.menu.pnum.GENERIC_G411R8TX=Generic G411R8Tx @@ -18,6 +19,7 @@ GenG4.menu.pnum.GENERIC_G411R8TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411R8TX.build.board=GENERIC_G411R8TX GenG4.menu.pnum.GENERIC_G411R8TX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411R8TX.build.variant=STM32G4xx/G411R(6-8-B)T +GenG4.menu.pnum.GENERIC_G411R8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G411RBTx GenG4.menu.pnum.GENERIC_G411RBTX=Generic G411RBTx @@ -26,4 +28,5 @@ GenG4.menu.pnum.GENERIC_G411RBTX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G411RBTX.build.board=GENERIC_G411RBTX GenG4.menu.pnum.GENERIC_G411RBTX.build.product_line=STM32G411xB GenG4.menu.pnum.GENERIC_G411RBTX.build.variant=STM32G4xx/G411R(6-8-B)T +GenG4.menu.pnum.GENERIC_G411RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd diff --git a/variants/STM32G4xx/G411RCT/PeripheralPins.c b/variants/STM32G4xx/G411RCT/PeripheralPins.c new file mode 100644 index 0000000000..c09f98aecf --- /dev/null +++ b/variants/STM32G4xx/G411RCT/PeripheralPins.c @@ -0,0 +1,329 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32G411RCTx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_11_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PB_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PB_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PB_15, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PF_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PF_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_8, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PC_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 + {PA_10_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_11_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 + {PA_11_ALT2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PA_12_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 + {PA_12_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 + {PA_13_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PA_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM20, 1, 0)}, // TIM20_CH1 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_4_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_5_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 + {PB_8_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1_COMP1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)}, // TIM8_CH3 + {PB_9_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)}, // TIM15_CH2 + {PC_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PC_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PC_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PC_2_ALT1, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 2, 0)}, // TIM20_CH2 + {PC_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 0)}, // TIM8_CH3 + {PC_8_ALT2, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 3, 0)}, // TIM20_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + {PC_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)}, // TIM1_CH1N + {PC_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM8, 4, 1)}, // TIM8_CH4N + {PF_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32G4xx/G411RCT/PinNamesVar.h b/variants/STM32G4xx/G411RCT/PinNamesVar.h new file mode 100644 index 0000000000..1a8f6b3228 --- /dev/null +++ b/variants/STM32G4xx/G411RCT/PinNamesVar.h @@ -0,0 +1,68 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_11_ALT2 = PA_11 | ALT2, +PA_12_ALT1 = PA_12 | ALT1, +PA_12_ALT2 = PA_12 | ALT2, +PA_13_ALT1 = PA_13 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_8_ALT2 = PB_8 | ALT2, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_9_ALT3 = PB_9 | ALT3, +PB_11_ALT1 = PB_11 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_8_ALT2 = PC_8 | ALT2, +PC_9_ALT1 = PC_9 | ALT1, +PC_13_ALT1 = PC_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PC_5, +#endif + +/* No USB */ diff --git a/variants/STM32G4xx/G411RCT/boards_entry.txt b/variants/STM32G4xx/G411RCT/boards_entry.txt new file mode 100644 index 0000000000..1bf5a2d523 --- /dev/null +++ b/variants/STM32G4xx/G411RCT/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic G411RCTx +GenG4.menu.pnum.GENERIC_G411RCTX=Generic G411RCTx +GenG4.menu.pnum.GENERIC_G411RCTX.upload.maximum_size=262144 +GenG4.menu.pnum.GENERIC_G411RCTX.upload.maximum_data_size=262144 +GenG4.menu.pnum.GENERIC_G411RCTX.build.board=GENERIC_G411RCTX +GenG4.menu.pnum.GENERIC_G411RCTX.build.product_line=STM32G411xC +GenG4.menu.pnum.GENERIC_G411RCTX.build.variant=STM32G4xx/G411RCT +GenG4.menu.pnum.GENERIC_G411RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd + diff --git a/variants/STM32G4xx/G411RCT/generic_clock.c b/variants/STM32G4xx/G411RCT/generic_clock.c new file mode 100644 index 0000000000..b6c52ab2cf --- /dev/null +++ b/variants/STM32G4xx/G411RCT/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G411RCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G411RCT/variant_generic.cpp b/variants/STM32G4xx/G411RCT/variant_generic.cpp new file mode 100644 index 0000000000..56bf5da950 --- /dev/null +++ b/variants/STM32G4xx/G411RCT/variant_generic.cpp @@ -0,0 +1,100 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G411RCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27/A11 + PB_12, // D28/A12 + PB_13, // D29/A13 + PB_14, // D30/A14 + PB_15, // D31/A15 + PC_0, // D32/A16 + PC_1, // D33/A17 + PC_2, // D34/A18 + PC_3, // D35/A19 + PC_4, // D36/A20 + PC_5, // D37/A21 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_2, // D48 + PF_0, // D49/A22 + PF_1, // D50/A23 + PG_10 // D51 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 27, // A11, PB11 + 28, // A12, PB12 + 29, // A13, PB13 + 30, // A14, PB14 + 31, // A15, PB15 + 32, // A16, PC0 + 33, // A17, PC1 + 34, // A18, PC2 + 35, // A19, PC3 + 36, // A20, PC4 + 37, // A21, PC5 + 49, // A22, PF0 + 50 // A23, PF1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G411RCT/variant_generic.h b/variants/STM32G4xx/G411RCT/variant_generic.h new file mode 100644 index 0000000000..c838423b7d --- /dev/null +++ b/variants/STM32G4xx/G411RCT/variant_generic.h @@ -0,0 +1,219 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 PIN_A11 +#define PB12 PIN_A12 +#define PB13 PIN_A13 +#define PB14 PIN_A14 +#define PB15 PIN_A15 +#define PC0 PIN_A16 +#define PC1 PIN_A17 +#define PC2 PIN_A18 +#define PC3 PIN_A19 +#define PC4 PIN_A20 +#define PC5 PIN_A21 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD2 48 +#define PF0 PIN_A22 +#define PF1 PIN_A23 +#define PG10 51 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA11_ALT2 (PA11 | ALT2) +#define PA12_ALT1 (PA12 | ALT1) +#define PA12_ALT2 (PA12 | ALT2) +#define PA13_ALT1 (PA13 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB8_ALT2 (PB8 | ALT2) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB9_ALT3 (PB9 | ALT3) +#define PB11_ALT1 (PB11 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC8_ALT2 (PC8 | ALT2) +#define PC9_ALT1 (PC9 | ALT1) +#define PC13_ALT1 (PC13 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 24 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA8 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c index 73de54e0e0..b76880dc15 100644 --- a/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414CBTx.xml, STM32G414CCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414C(B-C)T/PinNamesVar.h b/variants/STM32G4xx/G414C(B-C)T/PinNamesVar.h index 7706aeca6d..e955b5cb1d 100644 --- a/variants/STM32G4xx/G414C(B-C)T/PinNamesVar.h +++ b/variants/STM32G4xx/G414C(B-C)T/PinNamesVar.h @@ -54,17 +54,5 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G414C(B-C)T/boards_entry.txt b/variants/STM32G4xx/G414C(B-C)T/boards_entry.txt index 2d397d9fcb..21a759936f 100644 --- a/variants/STM32G4xx/G414C(B-C)T/boards_entry.txt +++ b/variants/STM32G4xx/G414C(B-C)T/boards_entry.txt @@ -6,7 +6,7 @@ # Generic G414CBTx GenG4.menu.pnum.GENERIC_G414CBTX=Generic G414CBTx GenG4.menu.pnum.GENERIC_G414CBTX.upload.maximum_size=131072 -GenG4.menu.pnum.GENERIC_G414CBTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414CBTX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414CBTX.build.board=GENERIC_G414CBTX GenG4.menu.pnum.GENERIC_G414CBTX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414CBTX.build.variant=STM32G4xx/G414C(B-C)T @@ -15,7 +15,7 @@ GenG4.menu.pnum.GENERIC_G414CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G414CCTx GenG4.menu.pnum.GENERIC_G414CCTX=Generic G414CCTx GenG4.menu.pnum.GENERIC_G414CCTX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G414CCTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414CCTX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414CCTX.build.board=GENERIC_G414CCTX GenG4.menu.pnum.GENERIC_G414CCTX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414CCTX.build.variant=STM32G4xx/G414C(B-C)T diff --git a/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c b/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c index 5d39d5c450..593effb697 100644 --- a/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c +++ b/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414CBUx.xml, STM32G414CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414C(B-C)U/PinNamesVar.h b/variants/STM32G4xx/G414C(B-C)U/PinNamesVar.h index c69e9b162a..4dc2187241 100644 --- a/variants/STM32G4xx/G414C(B-C)U/PinNamesVar.h +++ b/variants/STM32G4xx/G414C(B-C)U/PinNamesVar.h @@ -57,17 +57,5 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G414C(B-C)U/boards_entry.txt b/variants/STM32G4xx/G414C(B-C)U/boards_entry.txt index 08971ea4bf..2dbbe71c12 100644 --- a/variants/STM32G4xx/G414C(B-C)U/boards_entry.txt +++ b/variants/STM32G4xx/G414C(B-C)U/boards_entry.txt @@ -6,7 +6,7 @@ # Generic G414CBUx GenG4.menu.pnum.GENERIC_G414CBUX=Generic G414CBUx GenG4.menu.pnum.GENERIC_G414CBUX.upload.maximum_size=131072 -GenG4.menu.pnum.GENERIC_G414CBUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414CBUX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414CBUX.build.board=GENERIC_G414CBUX GenG4.menu.pnum.GENERIC_G414CBUX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414CBUX.build.variant=STM32G4xx/G414C(B-C)U @@ -15,7 +15,7 @@ GenG4.menu.pnum.GENERIC_G414CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G414CCUx GenG4.menu.pnum.GENERIC_G414CCUX=Generic G414CCUx GenG4.menu.pnum.GENERIC_G414CCUX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G414CCUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414CCUX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414CCUX.build.board=GENERIC_G414CCUX GenG4.menu.pnum.GENERIC_G414CCUX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414CCUX.build.variant=STM32G4xx/G414C(B-C)U diff --git a/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c index c30a44189b..945363a914 100644 --- a/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414MBTx.xml, STM32G414MCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414M(B-C)T/PinNamesVar.h b/variants/STM32G4xx/G414M(B-C)T/PinNamesVar.h index 2e127310ad..5e476c0721 100644 --- a/variants/STM32G4xx/G414M(B-C)T/PinNamesVar.h +++ b/variants/STM32G4xx/G414M(B-C)T/PinNamesVar.h @@ -68,14 +68,5 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G414M(B-C)T/boards_entry.txt b/variants/STM32G4xx/G414M(B-C)T/boards_entry.txt index aca62d129f..4cb6f3c77c 100644 --- a/variants/STM32G4xx/G414M(B-C)T/boards_entry.txt +++ b/variants/STM32G4xx/G414M(B-C)T/boards_entry.txt @@ -6,7 +6,7 @@ # Generic G414MBTx GenG4.menu.pnum.GENERIC_G414MBTX=Generic G414MBTx GenG4.menu.pnum.GENERIC_G414MBTX.upload.maximum_size=131072 -GenG4.menu.pnum.GENERIC_G414MBTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414MBTX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414MBTX.build.board=GENERIC_G414MBTX GenG4.menu.pnum.GENERIC_G414MBTX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414MBTX.build.variant=STM32G4xx/G414M(B-C)T @@ -15,7 +15,7 @@ GenG4.menu.pnum.GENERIC_G414MBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G414MCTx GenG4.menu.pnum.GENERIC_G414MCTX=Generic G414MCTx GenG4.menu.pnum.GENERIC_G414MCTX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G414MCTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414MCTX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414MCTX.build.board=GENERIC_G414MCTX GenG4.menu.pnum.GENERIC_G414MCTX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414MCTX.build.variant=STM32G4xx/G414M(B-C)T diff --git a/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c index 25342deac6..d38463de0c 100644 --- a/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414RBTx.xml, STM32G414RCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414R(B-C)T/PinNamesVar.h b/variants/STM32G4xx/G414R(B-C)T/PinNamesVar.h index 2e127310ad..5e476c0721 100644 --- a/variants/STM32G4xx/G414R(B-C)T/PinNamesVar.h +++ b/variants/STM32G4xx/G414R(B-C)T/PinNamesVar.h @@ -68,14 +68,5 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G414R(B-C)T/boards_entry.txt b/variants/STM32G4xx/G414R(B-C)T/boards_entry.txt index 30f8e7b6be..eaaf9a0aac 100644 --- a/variants/STM32G4xx/G414R(B-C)T/boards_entry.txt +++ b/variants/STM32G4xx/G414R(B-C)T/boards_entry.txt @@ -6,7 +6,7 @@ # Generic G414RBTx GenG4.menu.pnum.GENERIC_G414RBTX=Generic G414RBTx GenG4.menu.pnum.GENERIC_G414RBTX.upload.maximum_size=131072 -GenG4.menu.pnum.GENERIC_G414RBTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414RBTX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414RBTX.build.board=GENERIC_G414RBTX GenG4.menu.pnum.GENERIC_G414RBTX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414RBTX.build.variant=STM32G4xx/G414R(B-C)T @@ -15,7 +15,7 @@ GenG4.menu.pnum.GENERIC_G414RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G414RCTx GenG4.menu.pnum.GENERIC_G414RCTX=Generic G414RCTx GenG4.menu.pnum.GENERIC_G414RCTX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G414RCTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414RCTX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414RCTX.build.board=GENERIC_G414RCTX GenG4.menu.pnum.GENERIC_G414RCTX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414RCTX.build.variant=STM32G4xx/G414R(B-C)T diff --git a/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c index 2af449dae7..ac9427c1ba 100644 --- a/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414VBTx.xml, STM32G414VCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414V(B-C)T/PinNamesVar.h b/variants/STM32G4xx/G414V(B-C)T/PinNamesVar.h index 9e902403b7..22d3b4604d 100644 --- a/variants/STM32G4xx/G414V(B-C)T/PinNamesVar.h +++ b/variants/STM32G4xx/G414V(B-C)T/PinNamesVar.h @@ -74,14 +74,5 @@ PE_5_ALT1 = PE_5 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32G4xx/G414V(B-C)T/boards_entry.txt b/variants/STM32G4xx/G414V(B-C)T/boards_entry.txt index 87b5527c47..8faf22e64a 100644 --- a/variants/STM32G4xx/G414V(B-C)T/boards_entry.txt +++ b/variants/STM32G4xx/G414V(B-C)T/boards_entry.txt @@ -6,7 +6,7 @@ # Generic G414VBTx GenG4.menu.pnum.GENERIC_G414VBTX=Generic G414VBTx GenG4.menu.pnum.GENERIC_G414VBTX.upload.maximum_size=131072 -GenG4.menu.pnum.GENERIC_G414VBTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414VBTX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414VBTX.build.board=GENERIC_G414VBTX GenG4.menu.pnum.GENERIC_G414VBTX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414VBTX.build.variant=STM32G4xx/G414V(B-C)T @@ -15,7 +15,7 @@ GenG4.menu.pnum.GENERIC_G414VBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G414VCTx GenG4.menu.pnum.GENERIC_G414VCTX=Generic G414VCTx GenG4.menu.pnum.GENERIC_G414VCTX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G414VCTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G414VCTX.upload.maximum_data_size=262144 GenG4.menu.pnum.GENERIC_G414VCTX.build.board=GENERIC_G414VCTX GenG4.menu.pnum.GENERIC_G414VCTX.build.product_line=STM32G414xx GenG4.menu.pnum.GENERIC_G414VCTX.build.variant=STM32G4xx/G414V(B-C)T diff --git a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c index 19d1ef56e8..89dc45b6d6 100644 --- a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431C(6-8-B)Tx.xml, STM32G441CBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PinNamesVar.h b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PinNamesVar.h index a9622aee45..fe02db8243 100644 --- a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PinNamesVar.h +++ b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PinNamesVar.h @@ -54,18 +54,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c index 2a872f0ea4..cf0279cad1 100644 --- a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c +++ b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431C(6-8-B)Ux.xml, STM32G441CBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PinNamesVar.h b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PinNamesVar.h index 1b1ee448fe..2781fdc61e 100644 --- a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PinNamesVar.h +++ b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PinNamesVar.h @@ -57,18 +57,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c b/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c index c4b7e4f0e7..9907370ff7 100644 --- a/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c +++ b/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431CBTxZ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431CBTxZ/PinNamesVar.h b/variants/STM32G4xx/G431CBTxZ/PinNamesVar.h index a9622aee45..fe02db8243 100644 --- a/variants/STM32G4xx/G431CBTxZ/PinNamesVar.h +++ b/variants/STM32G4xx/G431CBTxZ/PinNamesVar.h @@ -54,18 +54,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c b/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c index f52a857fea..9dc9bf534b 100644 --- a/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c +++ b/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431CBYx.xml, STM32G441CBYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431CBY_G441CBY/PinNamesVar.h b/variants/STM32G4xx/G431CBY_G441CBY/PinNamesVar.h index b6e1fd3ed9..1954487517 100644 --- a/variants/STM32G4xx/G431CBY_G441CBY/PinNamesVar.h +++ b/variants/STM32G4xx/G431CBY_G441CBY/PinNamesVar.h @@ -55,18 +55,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c index e19c955cc5..d6b46a6b53 100644 --- a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c +++ b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G431K(6-8-B)Tx.xml, STM32G431K(6-8-B)Ux.xml * STM32G441KBTx.xml, STM32G441KBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PinNamesVar.h b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PinNamesVar.h index b8aec8f388..bf50ddaba4 100644 --- a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PinNamesVar.h +++ b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PinNamesVar.h @@ -43,18 +43,6 @@ PB_8_ALT2 = PB_8 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c index 3cc15e2504..a3d08a95d9 100644 --- a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431M(6-8-B)Tx.xml, STM32G441MBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PinNamesVar.h b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PinNamesVar.h index bda2363c44..33a3001c16 100644 --- a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PinNamesVar.h +++ b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PinNamesVar.h @@ -67,15 +67,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c index a95d0f3a7c..b99b33b224 100644 --- a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G431R(6-8-B)Ix.xml, STM32G431R(6-8-B)Tx.xml * STM32G431RBTxZ.xml, STM32G441RBIx.xml * STM32G441RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PinNamesVar.h b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PinNamesVar.h index bda2363c44..33a3001c16 100644 --- a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PinNamesVar.h +++ b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PinNamesVar.h @@ -67,15 +67,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c index d833dba4b2..162379f66a 100644 --- a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431V(6-8-B)Tx.xml, STM32G441VBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PinNamesVar.h b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PinNamesVar.h index c4af244028..6c0ef3dabb 100644 --- a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PinNamesVar.h +++ b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PinNamesVar.h @@ -67,15 +67,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c index 921de22606..1214843396 100644 --- a/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471C(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471C(C-E)T/PinNamesVar.h b/variants/STM32G4xx/G471C(C-E)T/PinNamesVar.h index a9622aee45..fe02db8243 100644 --- a/variants/STM32G4xx/G471C(C-E)T/PinNamesVar.h +++ b/variants/STM32G4xx/G471C(C-E)T/PinNamesVar.h @@ -54,18 +54,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c b/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c index 66ae87aae4..971b3690d5 100644 --- a/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c +++ b/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471C(C-E)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471C(C-E)U/PinNamesVar.h b/variants/STM32G4xx/G471C(C-E)U/PinNamesVar.h index 1b1ee448fe..2781fdc61e 100644 --- a/variants/STM32G4xx/G471C(C-E)U/PinNamesVar.h +++ b/variants/STM32G4xx/G471C(C-E)U/PinNamesVar.h @@ -57,18 +57,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c index 17ac4fbeaf..c7a2ca2f14 100644 --- a/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471M(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471M(C-E)T/PinNamesVar.h b/variants/STM32G4xx/G471M(C-E)T/PinNamesVar.h index a9fe00c69a..6dbd9ee5f6 100644 --- a/variants/STM32G4xx/G471M(C-E)T/PinNamesVar.h +++ b/variants/STM32G4xx/G471M(C-E)T/PinNamesVar.h @@ -68,15 +68,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G471MEY/PeripheralPins.c b/variants/STM32G4xx/G471MEY/PeripheralPins.c index f69adb64bd..d929fa3fb2 100644 --- a/variants/STM32G4xx/G471MEY/PeripheralPins.c +++ b/variants/STM32G4xx/G471MEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471MEYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471MEY/PinNamesVar.h b/variants/STM32G4xx/G471MEY/PinNamesVar.h index a9fe00c69a..6dbd9ee5f6 100644 --- a/variants/STM32G4xx/G471MEY/PinNamesVar.h +++ b/variants/STM32G4xx/G471MEY/PinNamesVar.h @@ -68,15 +68,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c index 1b639efc41..f7315dc866 100644 --- a/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471Q(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471Q(C-E)T/PinNamesVar.h b/variants/STM32G4xx/G471Q(C-E)T/PinNamesVar.h index d8628c9d08..04ad149ed7 100644 --- a/variants/STM32G4xx/G471Q(C-E)T/PinNamesVar.h +++ b/variants/STM32G4xx/G471Q(C-E)T/PinNamesVar.h @@ -74,15 +74,6 @@ PE_5_ALT1 = PE_5 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c index 764963df4f..fb43ece2b2 100644 --- a/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471R(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471R(C-E)T/PinNamesVar.h b/variants/STM32G4xx/G471R(C-E)T/PinNamesVar.h index a9fe00c69a..6dbd9ee5f6 100644 --- a/variants/STM32G4xx/G471R(C-E)T/PinNamesVar.h +++ b/variants/STM32G4xx/G471R(C-E)T/PinNamesVar.h @@ -68,15 +68,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c b/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c index 3a600dd8ec..1ad5651c64 100644 --- a/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G471V(C-E)Hx.xml, STM32G471V(C-E)Ix.xml * STM32G471V(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471V(C-E)(H-I-T)/PinNamesVar.h b/variants/STM32G4xx/G471V(C-E)(H-I-T)/PinNamesVar.h index d8628c9d08..04ad149ed7 100644 --- a/variants/STM32G4xx/G471V(C-E)(H-I-T)/PinNamesVar.h +++ b/variants/STM32G4xx/G471V(C-E)(H-I-T)/PinNamesVar.h @@ -74,15 +74,6 @@ PE_5_ALT1 = PE_5 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c index 3f2ea6b239..d15f4d9513 100644 --- a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c +++ b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473C(B-C-E)Tx.xml, STM32G474C(B-C-E)Tx.xml * STM32G483CETx.xml, STM32G484CETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PinNamesVar.h b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PinNamesVar.h index 51b57728b2..6e2b4c0b8c 100644 --- a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PinNamesVar.h +++ b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PinNamesVar.h @@ -59,18 +59,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c index a0420a55ab..a2fd01292a 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473C(B-C-E)Ux.xml, STM32G474C(B-C-E)Ux.xml * STM32G483CEUx.xml, STM32G484CEUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PinNamesVar.h b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PinNamesVar.h index 9af542a58e..520d0b025d 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PinNamesVar.h +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PinNamesVar.h @@ -62,18 +62,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c index db6b3daa6c..9535e57dd8 100644 --- a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c +++ b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473M(B-C-E)Tx.xml, STM32G474M(B-C-E)Tx.xml * STM32G483METx.xml, STM32G484METx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PinNamesVar.h b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PinNamesVar.h index 7500ea117b..051be0f7b5 100644 --- a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PinNamesVar.h +++ b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PinNamesVar.h @@ -87,15 +87,6 @@ PE_12_ALT2 = PE_12 | ALT2, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c index 410cd604ed..13ff9ba3d3 100644 --- a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c +++ b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473MEYx.xml, STM32G474MEYx.xml * STM32G483MEYx.xml, STM32G484MEYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PinNamesVar.h b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PinNamesVar.h index 4964ccbc15..98c9f5afd9 100644 --- a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PinNamesVar.h +++ b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PinNamesVar.h @@ -89,15 +89,6 @@ PE_12_ALT2 = PE_12 | ALT2, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c index 1391860f58..47a9220d3d 100644 --- a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c +++ b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473P(B-C-E)Ix.xml, STM32G474P(B-C-E)Ix.xml * STM32G483PEIx.xml, STM32G484PEIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PinNamesVar.h b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PinNamesVar.h index 58d7823509..cdcbd9e12a 100644 --- a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PinNamesVar.h +++ b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PinNamesVar.h @@ -103,15 +103,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c b/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c index 24e1ed4f6b..eb40f13645 100644 --- a/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c +++ b/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G473Q(B-C-E)Tx.xml, STM32G473QETxZ.xml * STM32G474Q(B-C-E)Tx.xml, STM32G483QETx.xml * STM32G484QETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PinNamesVar.h b/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PinNamesVar.h index 58d7823509..cdcbd9e12a 100644 --- a/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PinNamesVar.h +++ b/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PinNamesVar.h @@ -103,15 +103,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c b/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c index c43682b4ab..f564dba476 100644 --- a/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c +++ b/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G473R(B-C-E)Tx.xml, STM32G473RETxZ.xml * STM32G474R(B-C-E)Tx.xml, STM32G483RETx.xml * STM32G484RETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PinNamesVar.h b/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PinNamesVar.h index c5257f3dd6..125a3c35fc 100644 --- a/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PinNamesVar.h +++ b/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PinNamesVar.h @@ -74,15 +74,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c index 5680581302..7da4dd182c 100644 --- a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32G474V(B-C-E)Hx.xml, STM32G474V(B-C-E)Tx.xml * STM32G483VEHx.xml, STM32G483VETx.xml * STM32G484VEHx.xml, STM32G484VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PinNamesVar.h b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PinNamesVar.h index d67ad52608..1753fe5093 100644 --- a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PinNamesVar.h +++ b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PinNamesVar.h @@ -102,15 +102,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c index 1e38f84c86..abddd7b29b 100644 --- a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c +++ b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491C(C-E)Tx.xml, STM32G4A1CETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PinNamesVar.h b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PinNamesVar.h index a9622aee45..fe02db8243 100644 --- a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PinNamesVar.h +++ b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PinNamesVar.h @@ -54,18 +54,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c b/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c index d5c0ddf42b..8b7262373f 100644 --- a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c +++ b/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491C(C-E)Ux.xml, STM32G4A1CEUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PinNamesVar.h b/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PinNamesVar.h index b6e1fd3ed9..1954487517 100644 --- a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PinNamesVar.h +++ b/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PinNamesVar.h @@ -55,18 +55,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c index d05f0a3d81..b31655fc0f 100644 --- a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c +++ b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491K(C-E)Ux.xml, STM32G4A1KEUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PinNamesVar.h b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PinNamesVar.h index b8aec8f388..bf50ddaba4 100644 --- a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PinNamesVar.h +++ b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PinNamesVar.h @@ -43,18 +43,6 @@ PB_8_ALT2 = PB_8 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c index 9244ffa059..cce40a13bf 100644 --- a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G491M(C-E)Sx.xml, STM32G491M(C-E)Tx.xml * STM32G4A1MESx.xml, STM32G4A1METx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PinNamesVar.h b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PinNamesVar.h index a9fe00c69a..6dbd9ee5f6 100644 --- a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PinNamesVar.h +++ b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PinNamesVar.h @@ -68,15 +68,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c index 5861e12ecb..e26b0c071c 100644 --- a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c +++ b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32G491RETxZ.xml, STM32G491REYx.xml * STM32G4A1REIx.xml, STM32G4A1RETx.xml * STM32G4A1REYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PinNamesVar.h b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PinNamesVar.h index a9fe00c69a..6dbd9ee5f6 100644 --- a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PinNamesVar.h +++ b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PinNamesVar.h @@ -68,15 +68,6 @@ PC_13_ALT1 = PC_13 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c index b3f42698cc..99dcdc58ac 100644 --- a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c +++ b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491V(C-E)Tx.xml, STM32G4A1VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PinNamesVar.h b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PinNamesVar.h index d8628c9d08..04ad149ed7 100644 --- a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PinNamesVar.h +++ b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PinNamesVar.h @@ -74,15 +74,6 @@ PE_5_ALT1 = PE_5 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 57b20ded97d00ca9c336cb26dcdc7cc912c568a6 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:31:27 +0100 Subject: [PATCH 047/141] chore(h5): update variant after script update Signed-off-by: Frederic Pillon --- variants/STM32H5xx/H503CB(T-U)/PinNamesVar.h | 9 --------- variants/STM32H5xx/H503EBY/PinNamesVar.h | 9 --------- variants/STM32H5xx/H503KBU/PinNamesVar.h | 9 --------- variants/STM32H5xx/H503RBT/PinNamesVar.h | 9 --------- .../STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h | 9 --------- variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h | 9 --------- variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h | 3 --- variants/STM32H5xx/H562R(G-I)T/PinNamesVar.h | 3 --- variants/STM32H5xx/H562R(G-I)V/PinNamesVar.h | 6 ------ variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h | 3 --- variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h | 3 --- variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h | 6 ------ 12 files changed, 78 deletions(-) diff --git a/variants/STM32H5xx/H503CB(T-U)/PinNamesVar.h b/variants/STM32H5xx/H503CB(T-U)/PinNamesVar.h index 082574b44e..cd520335ed 100644 --- a/variants/STM32H5xx/H503CB(T-U)/PinNamesVar.h +++ b/variants/STM32H5xx/H503CB(T-U)/PinNamesVar.h @@ -50,15 +50,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PB_7, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H503EBY/PinNamesVar.h b/variants/STM32H5xx/H503EBY/PinNamesVar.h index 71f908c618..332658827c 100644 --- a/variants/STM32H5xx/H503EBY/PinNamesVar.h +++ b/variants/STM32H5xx/H503EBY/PinNamesVar.h @@ -39,15 +39,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PB_7, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H503KBU/PinNamesVar.h b/variants/STM32H5xx/H503KBU/PinNamesVar.h index aeacf15903..46ff446d16 100644 --- a/variants/STM32H5xx/H503KBU/PinNamesVar.h +++ b/variants/STM32H5xx/H503KBU/PinNamesVar.h @@ -46,15 +46,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PB_7, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H503RBT/PinNamesVar.h b/variants/STM32H5xx/H503RBT/PinNamesVar.h index 073e92a77f..3dca670bfa 100644 --- a/variants/STM32H5xx/H503RBT/PinNamesVar.h +++ b/variants/STM32H5xx/H503RBT/PinNamesVar.h @@ -58,15 +58,6 @@ PC_12_ALT1 = PC_12 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PB_7, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h index d521e25ca7..48d4c854b6 100644 --- a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h @@ -49,15 +49,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PB_7, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h b/variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h index 1acdb5135f..d51c94442e 100644 --- a/variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h +++ b/variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h @@ -40,15 +40,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PB_7, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h b/variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h index 248f1e4e24..0eb1c0df4a 100644 --- a/variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h @@ -67,9 +67,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PD_2, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H562R(G-I)T/PinNamesVar.h b/variants/STM32H5xx/H562R(G-I)T/PinNamesVar.h index c06b9e6d50..c7e5945643 100644 --- a/variants/STM32H5xx/H562R(G-I)T/PinNamesVar.h +++ b/variants/STM32H5xx/H562R(G-I)T/PinNamesVar.h @@ -72,9 +72,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PD_2, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H562R(G-I)V/PinNamesVar.h b/variants/STM32H5xx/H562R(G-I)V/PinNamesVar.h index 1ee6296ec3..8cd46fc96b 100644 --- a/variants/STM32H5xx/H562R(G-I)V/PinNamesVar.h +++ b/variants/STM32H5xx/H562R(G-I)V/PinNamesVar.h @@ -70,12 +70,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h index c06b9e6d50..c7e5945643 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h @@ -72,9 +72,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PD_2, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h index c06b9e6d50..c7e5945643 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h @@ -72,9 +72,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PD_2, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h index 1ee6296ec3..8cd46fc96b 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h @@ -70,12 +70,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 50326fec09fd6c559bf56a826cac5b4c43bf2e39 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:38:12 +0100 Subject: [PATCH 048/141] chore(h7): update variant after script update Signed-off-by: Frederic Pillon --- boards.txt | 30 +- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../H723Z(E-G)I_H730ZBI_H733ZGI/PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../H723Z(E-G)T_H730ZBT_H733ZGT/PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../H725R(E-G)V_H735RGV/PeripheralPins.c | 7 +- .../H725R(E-G)V_H735RGV/PinNamesVar.h | 7 +- .../H725R(E-G)V_H735RGV/variant_generic.h | 1 + .../H725V(E-G)H_H735VGH/PeripheralPins.c | 2 +- .../H725V(E-G)H_H735VGH/PinNamesVar.h | 6 - .../H725V(E-G)T_H735VGT/PeripheralPins.c | 2 +- .../H725V(E-G)T_H735VGT/PinNamesVar.h | 6 - .../H725VGY_H735VGY/PeripheralPins.c | 2 +- .../STM32H7xx/H725VGY_H735VGY/PinNamesVar.h | 6 - .../H725Z(E-G)T_H735ZGT/PeripheralPins.c | 2 +- .../H725Z(E-G)T_H735ZGT/PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../DAISY_SEED.ld | 0 .../PeripheralPins.c | 10 +- .../PeripheralPins_DAISY_PATCH_SM.c | 0 .../PeripheralPins_DAISY_PETAL_SM.c | 0 .../PeripheralPins_DAISY_SEED.c | 0 .../PinNamesVar.h | 6 - .../boards_entry.txt | 113 +++ .../generic_clock.c | 9 +- .../ldscript.ld | 0 .../variant_DAISY_PATCH_SM.cpp | 0 .../variant_DAISY_PATCH_SM.h | 0 .../variant_DAISY_PETAL_SM.cpp | 0 .../variant_DAISY_PETAL_SM.h | 0 .../variant_DAISY_SEED.cpp | 0 .../variant_DAISY_SEED.h | 0 .../variant_generic.cpp | 9 +- .../variant_generic.h | 0 .../CMakeLists.txt | 37 - .../PeripheralPins.c | 721 ------------------ .../PinNamesVar.h | 120 --- .../boards_entry.txt | 59 -- .../CMakeLists.txt | 31 - .../boards_entry.txt | 59 -- .../generic_clock.c | 104 --- .../ldscript.ld | 170 ----- .../variant_generic.cpp | 198 ----- .../variant_generic.h | 322 -------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../H745B(G-I)T_H755BIT/PeripheralPins.c | 2 +- .../H745B(G-I)T_H755BIT/PinNamesVar.h | 6 - .../H745I(G-I)K_H755IIK/PeripheralPins.c | 2 +- .../H745I(G-I)K_H755IIK/PinNamesVar.h | 6 - .../H745I(G-I)T_H755IIT/PeripheralPins.c | 2 +- .../H745I(G-I)T_H755IIT/PinNamesVar.h | 6 - .../H745Z(G-I)T_H755ZIT/PeripheralPins.c | 2 +- .../H745Z(G-I)T_H755ZIT/PinNamesVar.h | 6 - .../H747B(G-I)T_H757BIT/PeripheralPins.c | 2 +- .../H747B(G-I)T_H757BIT/PinNamesVar.h | 6 - .../H747ZIY_H757ZIY/PeripheralPins.c | 2 +- .../STM32H7xx/H747ZIY_H757ZIY/PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c | 2 +- .../H7A3I(G-I)TxQ_H7B3IITxQ/PinNamesVar.h | 6 - .../H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c | 2 +- .../H7A3L(G-I)HxQ_H7B3LIHxQ/PinNamesVar.h | 6 - .../H7A3N(G-I)H_H7B3NIH/PeripheralPins.c | 2 +- .../H7A3N(G-I)H_H7B3NIH/PinNamesVar.h | 6 - .../H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c | 2 +- .../H7A3QIYxQ_H7B3QIYxQ/PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../H7A3R(G-I)T_H7B0RBT_H7B3RIT/PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 - .../H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c | 2 +- .../H7A3V(G-I)HxQ_H7B3VIHxQ/PinNamesVar.h | 6 - .../H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c | 2 +- .../H7A3V(G-I)TxQ_H7B3VITxQ/PinNamesVar.h | 6 - .../PeripheralPins.c | 2 +- .../H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PinNamesVar.h | 6 - .../H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c | 2 +- .../H7A3Z(G-I)TxQ_H7B3ZITxQ/PinNamesVar.h | 6 - 99 files changed, 187 insertions(+), 2098 deletions(-) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/DAISY_SEED.ld (100%) rename variants/STM32H7xx/{H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/PeripheralPins.c (99%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/PeripheralPins_DAISY_PATCH_SM.c (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/PeripheralPins_DAISY_PETAL_SM.c (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/PeripheralPins_DAISY_SEED.c (100%) rename variants/STM32H7xx/{H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/PinNamesVar.h (96%) create mode 100644 variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/boards_entry.txt rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/generic_clock.c (94%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/ldscript.ld (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/variant_DAISY_PATCH_SM.cpp (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/variant_DAISY_PATCH_SM.h (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/variant_DAISY_PETAL_SM.cpp (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/variant_DAISY_PETAL_SM.h (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/variant_DAISY_SEED.cpp (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/variant_DAISY_SEED.h (100%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/variant_generic.cpp (93%) rename variants/STM32H7xx/{H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK => H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)}/variant_generic.h (100%) delete mode 100644 variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/CMakeLists.txt delete mode 100644 variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins.c delete mode 100644 variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PinNamesVar.h delete mode 100644 variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/boards_entry.txt delete mode 100644 variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/CMakeLists.txt delete mode 100644 variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/boards_entry.txt delete mode 100644 variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/generic_clock.c delete mode 100644 variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/ldscript.ld delete mode 100644 variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/variant_generic.cpp delete mode 100644 variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/variant_generic.h diff --git a/boards.txt b/boards.txt index 08b4d3fa7e..95da14df53 100644 --- a/boards.txt +++ b/boards.txt @@ -8934,7 +8934,7 @@ GenH7.menu.pnum.DAISY_SEED.upload.maximum_data_size=524288 GenH7.menu.pnum.DAISY_SEED.build.board=DAISY_SEED GenH7.menu.pnum.DAISY_SEED.build.product_line=STM32H750xx GenH7.menu.pnum.DAISY_SEED.build.variant_h=variant_{build.board}.h -GenH7.menu.pnum.DAISY_SEED.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.DAISY_SEED.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.DAISY_SEED.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS GenH7.menu.pnum.DAISY_SEED.build.ldscript=DAISY_SEED.ld GenH7.menu.pnum.DAISY_SEED.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd @@ -8946,7 +8946,7 @@ GenH7.menu.pnum.DAISY_PATCH_SM.upload.maximum_data_size=524288 GenH7.menu.pnum.DAISY_PATCH_SM.build.board=DAISY_PATCH_SM GenH7.menu.pnum.DAISY_PATCH_SM.build.product_line=STM32H750xx GenH7.menu.pnum.DAISY_PATCH_SM.build.variant_h=variant_{build.board}.h -GenH7.menu.pnum.DAISY_PATCH_SM.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.DAISY_PATCH_SM.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.DAISY_PATCH_SM.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS GenH7.menu.pnum.DAISY_PATCH_SM.build.ldscript=DAISY_SEED.ld GenH7.menu.pnum.DAISY_PATCH_SM.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd @@ -8958,7 +8958,7 @@ GenH7.menu.pnum.DAISY_PETAL_SM.upload.maximum_data_size=524288 GenH7.menu.pnum.DAISY_PETAL_SM.build.board=DAISY_PETAL_SM GenH7.menu.pnum.DAISY_PETAL_SM.build.product_line=STM32H750xx GenH7.menu.pnum.DAISY_PETAL_SM.build.variant_h=variant_{build.board}.h -GenH7.menu.pnum.DAISY_PETAL_SM.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.DAISY_PETAL_SM.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.DAISY_PETAL_SM.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS GenH7.menu.pnum.DAISY_PETAL_SM.build.ldscript=DAISY_SEED.ld GenH7.menu.pnum.DAISY_PETAL_SM.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd @@ -9049,7 +9049,7 @@ GenH7.menu.pnum.GENERIC_H742IGKX.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H742IGKX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H742IGKX.build.board=GENERIC_H742IGKX GenH7.menu.pnum.GENERIC_H742IGKX.build.product_line=STM32H742xx -GenH7.menu.pnum.GENERIC_H742IGKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.GENERIC_H742IGKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H742IGKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd # Generic H742IIKx @@ -9058,7 +9058,7 @@ GenH7.menu.pnum.GENERIC_H742IIKX.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H742IIKX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H742IIKX.build.board=GENERIC_H742IIKX GenH7.menu.pnum.GENERIC_H742IIKX.build.product_line=STM32H742xx -GenH7.menu.pnum.GENERIC_H742IIKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.GENERIC_H742IIKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H742IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd # Generic H742IGTx @@ -9067,7 +9067,7 @@ GenH7.menu.pnum.GENERIC_H742IGTX.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H742IGTX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H742IGTX.build.board=GENERIC_H742IGTX GenH7.menu.pnum.GENERIC_H742IGTX.build.product_line=STM32H742xx -GenH7.menu.pnum.GENERIC_H742IGTX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT +GenH7.menu.pnum.GENERIC_H742IGTX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H742IGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd # Generic H742IITx @@ -9076,7 +9076,7 @@ GenH7.menu.pnum.GENERIC_H742IITX.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H742IITX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H742IITX.build.board=GENERIC_H742IITX GenH7.menu.pnum.GENERIC_H742IITX.build.product_line=STM32H742xx -GenH7.menu.pnum.GENERIC_H742IITX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT +GenH7.menu.pnum.GENERIC_H742IITX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H742IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd # Generic H742VGHx @@ -9157,7 +9157,7 @@ GenH7.menu.pnum.GENERIC_H743IGKX.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H743IGKX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H743IGKX.build.board=GENERIC_H743IGKX GenH7.menu.pnum.GENERIC_H743IGKX.build.product_line=STM32H743xx -GenH7.menu.pnum.GENERIC_H743IGKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.GENERIC_H743IGKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H743IGKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd # Generic H743IGTx @@ -9166,7 +9166,7 @@ GenH7.menu.pnum.GENERIC_H743IGTX.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H743IGTX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H743IGTX.build.board=GENERIC_H743IGTX GenH7.menu.pnum.GENERIC_H743IGTX.build.product_line=STM32H743xx -GenH7.menu.pnum.GENERIC_H743IGTX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT +GenH7.menu.pnum.GENERIC_H743IGTX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H743IGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd # Generic H743IIKx @@ -9175,7 +9175,7 @@ GenH7.menu.pnum.GENERIC_H743IIKX.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H743IIKX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H743IIKX.build.board=GENERIC_H743IIKX GenH7.menu.pnum.GENERIC_H743IIKX.build.product_line=STM32H743xx -GenH7.menu.pnum.GENERIC_H743IIKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.GENERIC_H743IIKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H743IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd # Generic H743IITx @@ -9184,7 +9184,7 @@ GenH7.menu.pnum.GENERIC_H743IITX.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H743IITX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H743IITX.build.board=GENERIC_H743IITX GenH7.menu.pnum.GENERIC_H743IITX.build.product_line=STM32H743xx -GenH7.menu.pnum.GENERIC_H743IITX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT +GenH7.menu.pnum.GENERIC_H743IITX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H743IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd # Generic H743VGHx @@ -9337,7 +9337,7 @@ GenH7.menu.pnum.GENERIC_H750IBKX.upload.maximum_size=131072 GenH7.menu.pnum.GENERIC_H750IBKX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H750IBKX.build.board=GENERIC_H750IBKX GenH7.menu.pnum.GENERIC_H750IBKX.build.product_line=STM32H750xx -GenH7.menu.pnum.GENERIC_H750IBKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.GENERIC_H750IBKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H750IBKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd # Generic H750IBTx @@ -9346,7 +9346,7 @@ GenH7.menu.pnum.GENERIC_H750IBTX.upload.maximum_size=131072 GenH7.menu.pnum.GENERIC_H750IBTX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H750IBTX.build.board=GENERIC_H750IBTX GenH7.menu.pnum.GENERIC_H750IBTX.build.product_line=STM32H750xx -GenH7.menu.pnum.GENERIC_H750IBTX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT +GenH7.menu.pnum.GENERIC_H750IBTX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H750IBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd # Generic H750VBTx @@ -9382,7 +9382,7 @@ GenH7.menu.pnum.GENERIC_H753IIKX.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H753IIKX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H753IIKX.build.board=GENERIC_H753IIKX GenH7.menu.pnum.GENERIC_H753IIKX.build.product_line=STM32H753xx -GenH7.menu.pnum.GENERIC_H753IIKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK +GenH7.menu.pnum.GENERIC_H753IIKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H753IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd # Generic H753IITx @@ -9391,7 +9391,7 @@ GenH7.menu.pnum.GENERIC_H753IITX.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H753IITX.upload.maximum_data_size=524288 GenH7.menu.pnum.GENERIC_H753IITX.build.board=GENERIC_H753IITX GenH7.menu.pnum.GENERIC_H753IITX.build.product_line=STM32H753xx -GenH7.menu.pnum.GENERIC_H753IITX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT +GenH7.menu.pnum.GENERIC_H753IITX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) GenH7.menu.pnum.GENERIC_H753IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd # Generic H753VIHx diff --git a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c index 962fa5b7ca..2daf9fa6e5 100644 --- a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H723VGHx.xml, STM32H723VGTx.xml * STM32H730VBHx.xml, STM32H730VBTx.xml * STM32H733VGHx.xml, STM32H733VGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PinNamesVar.h b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PinNamesVar.h index 90114efeb5..fbccdd7a48 100644 --- a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PinNamesVar.h +++ b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PinNamesVar.h @@ -75,12 +75,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c index bc4228c78e..8468c6edd6 100644 --- a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c +++ b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H723ZEIx.xml, STM32H723ZGIx.xml * STM32H730ZBIx.xml, STM32H733ZGIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PinNamesVar.h b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PinNamesVar.h index 6ab9af55d8..b77a5b2b36 100644 --- a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PinNamesVar.h +++ b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PinNamesVar.h @@ -83,12 +83,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c index c6483fcc99..776247adf2 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H723ZETx.xml, STM32H723ZGTx.xml * STM32H730ZBTx.xml, STM32H733ZGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PinNamesVar.h b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PinNamesVar.h index cfce515279..1c77d7cf12 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PinNamesVar.h +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PinNamesVar.h @@ -84,12 +84,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c index f6bb9b82bf..d9920f55f4 100644 --- a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c +++ b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725AEIx.xml, STM32H725AGIx.xml * STM32H730ABIxQ.xml, STM32H735AGIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PinNamesVar.h b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PinNamesVar.h index 74f93b013e..a2f726b569 100644 --- a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PinNamesVar.h +++ b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PinNamesVar.h @@ -92,12 +92,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c index 2887470c7b..19a0fb3b49 100644 --- a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c +++ b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725IEKx.xml, STM32H725IGKx.xml * STM32H730IBKxQ.xml, STM32H735IGKx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PinNamesVar.h b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PinNamesVar.h index 4c78e5cbdb..13c6984b69 100644 --- a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PinNamesVar.h +++ b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PinNamesVar.h @@ -92,12 +92,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c index aaee885555..cce9834030 100644 --- a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725IETx.xml, STM32H725IGTx.xml * STM32H730IBTxQ.xml, STM32H735IGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PinNamesVar.h b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PinNamesVar.h index faf5affd97..61cf234173 100644 --- a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PinNamesVar.h +++ b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PinNamesVar.h @@ -90,12 +90,6 @@ PK_1_ALT1 = PK_1 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c index c4f977f99a..75fc37b60a 100644 --- a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c +++ b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725REVx.xml, STM32H725RGVx.xml * STM32H735RGVx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -85,6 +85,8 @@ WEAK const PinMap PinMap_I2C_SDA[] = { {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PC_9_ALT1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C5)}, + {PC_10, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, {NC, NP, 0} }; #endif @@ -92,11 +94,12 @@ WEAK const PinMap PinMap_I2C_SDA[] = { #ifdef HAL_I2C_MODULE_ENABLED WEAK const PinMap PinMap_I2C_SCL[] = { {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_8_ALT1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C5)}, {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_11, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, {NC, NP, 0} }; #endif diff --git a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PinNamesVar.h b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PinNamesVar.h index a5c809330e..ef1f562fc4 100644 --- a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PinNamesVar.h +++ b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PinNamesVar.h @@ -13,6 +13,7 @@ PA_6_ALT1 = PA_6 | ALT1, PA_7_ALT1 = PA_7 | ALT1, PA_7_ALT2 = PA_7 | ALT2, PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, PA_9_ALT1 = PA_9 | ALT1, PA_10_ALT1 = PA_10 | ALT1, PA_11_ALT1 = PA_11 | ALT1, @@ -69,12 +70,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H725R(E-G)V_H735RGV/variant_generic.h b/variants/STM32H7xx/H725R(E-G)V_H735RGV/variant_generic.h index c5407789ef..141b4d4667 100644 --- a/variants/STM32H7xx/H725R(E-G)V_H735RGV/variant_generic.h +++ b/variants/STM32H7xx/H725R(E-G)V_H735RGV/variant_generic.h @@ -77,6 +77,7 @@ #define PA7_ALT1 (PA7 | ALT1) #define PA7_ALT2 (PA7 | ALT2) #define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) #define PA9_ALT1 (PA9 | ALT1) #define PA10_ALT1 (PA10 | ALT1) #define PA11_ALT1 (PA11 | ALT1) diff --git a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c index 5fc49fdd85..0bca7d9495 100644 --- a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c +++ b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725VEHx.xml, STM32H725VGHx.xml * STM32H735VGHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PinNamesVar.h b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PinNamesVar.h index 90114efeb5..fbccdd7a48 100644 --- a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PinNamesVar.h +++ b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PinNamesVar.h @@ -75,12 +75,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c index bd365cbdec..9608d8e713 100644 --- a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725VETx.xml, STM32H725VGTx.xml * STM32H735VGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PinNamesVar.h b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PinNamesVar.h index 90114efeb5..fbccdd7a48 100644 --- a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PinNamesVar.h +++ b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PinNamesVar.h @@ -75,12 +75,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c b/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c index 4cbc0efcb4..f23f06c2c8 100644 --- a/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c +++ b/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H725VGYx.xml, STM32H735VGYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725VGY_H735VGY/PinNamesVar.h b/variants/STM32H7xx/H725VGY_H735VGY/PinNamesVar.h index 8886a3a544..10b8db3472 100644 --- a/variants/STM32H7xx/H725VGY_H735VGY/PinNamesVar.h +++ b/variants/STM32H7xx/H725VGY_H735VGY/PinNamesVar.h @@ -71,12 +71,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c index 5dab54ce6f..2bd6af6123 100644 --- a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725ZETx.xml, STM32H725ZGTx.xml * STM32H735ZGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PinNamesVar.h b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PinNamesVar.h index 01ed925beb..1a6ee5b504 100644 --- a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PinNamesVar.h +++ b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PinNamesVar.h @@ -82,12 +82,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c index fa106143fb..4893290acd 100644 --- a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c +++ b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H742A(G-I)Ix.xml, STM32H743A(G-I)Ix.xml * STM32H753AIIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PinNamesVar.h b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PinNamesVar.h index d6968bf963..0d02d77d4c 100644 --- a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PinNamesVar.h +++ b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PinNamesVar.h @@ -76,12 +76,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c index 6c03a8eb50..238d9f79ce 100644 --- a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H742B(G-I)Tx.xml, STM32H743BGTx.xml * STM32H743BITx.xml, STM32H753BITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PinNamesVar.h b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PinNamesVar.h index 5c248acda8..2eda82ecbf 100644 --- a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PinNamesVar.h +++ b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PinNamesVar.h @@ -82,12 +82,6 @@ PK_1_ALT1 = PK_1 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/DAISY_SEED.ld b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/DAISY_SEED.ld similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/DAISY_SEED.ld rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/DAISY_SEED.ld diff --git a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/PeripheralPins.c b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c similarity index 99% rename from variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/PeripheralPins.c rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c index 59e233306a..a8f4c7d7cd 100644 --- a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c @@ -11,10 +11,12 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H742I(G-I)Tx.xml, STM32H743IGTx.xml - * STM32H743IITx.xml, STM32H750IBTx.xml - * STM32H753IITx.xml - * CubeMX DB release 6.0.120 + * Automatically generated from STM32H742I(G-I)Kx.xml, STM32H742I(G-I)Tx.xml + * STM32H743IGKx.xml, STM32H743IGTx.xml + * STM32H743IIKx.xml, STM32H743IITx.xml + * STM32H750IBKx.xml, STM32H750IBTx.xml + * STM32H753IIKx.xml, STM32H753IITx.xml + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins_DAISY_PATCH_SM.c b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins_DAISY_PATCH_SM.c similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins_DAISY_PATCH_SM.c rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins_DAISY_PATCH_SM.c diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins_DAISY_PETAL_SM.c b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins_DAISY_PETAL_SM.c similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins_DAISY_PETAL_SM.c rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins_DAISY_PETAL_SM.c diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins_DAISY_SEED.c b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins_DAISY_SEED.c similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins_DAISY_SEED.c rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins_DAISY_SEED.c diff --git a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/PinNamesVar.h b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PinNamesVar.h similarity index 96% rename from variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/PinNamesVar.h rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PinNamesVar.h index 32b4518aa2..e0299c00d9 100644 --- a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/PinNamesVar.h +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PinNamesVar.h @@ -76,12 +76,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/boards_entry.txt b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/boards_entry.txt new file mode 100644 index 0000000000..4dfc5a103c --- /dev/null +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/boards_entry.txt @@ -0,0 +1,113 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H742IGKx +GenH7.menu.pnum.GENERIC_H742IGKX=Generic H742IGKx +GenH7.menu.pnum.GENERIC_H742IGKX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H742IGKX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H742IGKX.build.board=GENERIC_H742IGKX +GenH7.menu.pnum.GENERIC_H742IGKX.build.product_line=STM32H742xx +GenH7.menu.pnum.GENERIC_H742IGKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H742IGKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd + +# Generic H742IIKx +GenH7.menu.pnum.GENERIC_H742IIKX=Generic H742IIKx +GenH7.menu.pnum.GENERIC_H742IIKX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H742IIKX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H742IIKX.build.board=GENERIC_H742IIKX +GenH7.menu.pnum.GENERIC_H742IIKX.build.product_line=STM32H742xx +GenH7.menu.pnum.GENERIC_H742IIKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H742IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd + +# Generic H742IGTx +GenH7.menu.pnum.GENERIC_H742IGTX=Generic H742IGTx +GenH7.menu.pnum.GENERIC_H742IGTX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H742IGTX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H742IGTX.build.board=GENERIC_H742IGTX +GenH7.menu.pnum.GENERIC_H742IGTX.build.product_line=STM32H742xx +GenH7.menu.pnum.GENERIC_H742IGTX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H742IGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd + +# Generic H742IITx +GenH7.menu.pnum.GENERIC_H742IITX=Generic H742IITx +GenH7.menu.pnum.GENERIC_H742IITX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H742IITX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H742IITX.build.board=GENERIC_H742IITX +GenH7.menu.pnum.GENERIC_H742IITX.build.product_line=STM32H742xx +GenH7.menu.pnum.GENERIC_H742IITX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H742IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd + +# Generic H743IGKx +GenH7.menu.pnum.GENERIC_H743IGKX=Generic H743IGKx +GenH7.menu.pnum.GENERIC_H743IGKX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H743IGKX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H743IGKX.build.board=GENERIC_H743IGKX +GenH7.menu.pnum.GENERIC_H743IGKX.build.product_line=STM32H743xx +GenH7.menu.pnum.GENERIC_H743IGKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H743IGKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd + +# Generic H743IGTx +GenH7.menu.pnum.GENERIC_H743IGTX=Generic H743IGTx +GenH7.menu.pnum.GENERIC_H743IGTX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H743IGTX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H743IGTX.build.board=GENERIC_H743IGTX +GenH7.menu.pnum.GENERIC_H743IGTX.build.product_line=STM32H743xx +GenH7.menu.pnum.GENERIC_H743IGTX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H743IGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd + +# Generic H743IIKx +GenH7.menu.pnum.GENERIC_H743IIKX=Generic H743IIKx +GenH7.menu.pnum.GENERIC_H743IIKX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H743IIKX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H743IIKX.build.board=GENERIC_H743IIKX +GenH7.menu.pnum.GENERIC_H743IIKX.build.product_line=STM32H743xx +GenH7.menu.pnum.GENERIC_H743IIKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H743IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd + +# Generic H743IITx +GenH7.menu.pnum.GENERIC_H743IITX=Generic H743IITx +GenH7.menu.pnum.GENERIC_H743IITX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H743IITX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H743IITX.build.board=GENERIC_H743IITX +GenH7.menu.pnum.GENERIC_H743IITX.build.product_line=STM32H743xx +GenH7.menu.pnum.GENERIC_H743IITX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H743IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd + +# Generic H750IBKx +GenH7.menu.pnum.GENERIC_H750IBKX=Generic H750IBKx +GenH7.menu.pnum.GENERIC_H750IBKX.upload.maximum_size=131072 +GenH7.menu.pnum.GENERIC_H750IBKX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H750IBKX.build.board=GENERIC_H750IBKX +GenH7.menu.pnum.GENERIC_H750IBKX.build.product_line=STM32H750xx +GenH7.menu.pnum.GENERIC_H750IBKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H750IBKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd + +# Generic H750IBTx +GenH7.menu.pnum.GENERIC_H750IBTX=Generic H750IBTx +GenH7.menu.pnum.GENERIC_H750IBTX.upload.maximum_size=131072 +GenH7.menu.pnum.GENERIC_H750IBTX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H750IBTX.build.board=GENERIC_H750IBTX +GenH7.menu.pnum.GENERIC_H750IBTX.build.product_line=STM32H750xx +GenH7.menu.pnum.GENERIC_H750IBTX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H750IBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd + +# Generic H753IIKx +GenH7.menu.pnum.GENERIC_H753IIKX=Generic H753IIKx +GenH7.menu.pnum.GENERIC_H753IIKX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H753IIKX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H753IIKX.build.board=GENERIC_H753IIKX +GenH7.menu.pnum.GENERIC_H753IIKX.build.product_line=STM32H753xx +GenH7.menu.pnum.GENERIC_H753IIKX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H753IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd + +# Generic H753IITx +GenH7.menu.pnum.GENERIC_H753IITX=Generic H753IITx +GenH7.menu.pnum.GENERIC_H753IITX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H753IITX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H753IITX.build.board=GENERIC_H753IITX +GenH7.menu.pnum.GENERIC_H753IITX.build.product_line=STM32H753xx +GenH7.menu.pnum.GENERIC_H753IITX.build.variant=STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T) +GenH7.menu.pnum.GENERIC_H753IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd + diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/generic_clock.c b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/generic_clock.c similarity index 94% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/generic_clock.c rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/generic_clock.c index fd5def3ea6..3d3e9484fd 100644 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/generic_clock.c +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/generic_clock.c @@ -10,9 +10,12 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H742IGKX) || defined(ARDUINO_GENERIC_H742IIKX) ||\ - defined(ARDUINO_GENERIC_H743IGKX) || defined(ARDUINO_GENERIC_H743IIKX) ||\ - defined(ARDUINO_GENERIC_H750IBKX) || defined(ARDUINO_GENERIC_H753IIKX) +#if defined(ARDUINO_GENERIC_H742IGKX) || defined(ARDUINO_GENERIC_H742IGTX) ||\ + defined(ARDUINO_GENERIC_H742IIKX) || defined(ARDUINO_GENERIC_H742IITX) ||\ + defined(ARDUINO_GENERIC_H743IGKX) || defined(ARDUINO_GENERIC_H743IGTX) ||\ + defined(ARDUINO_GENERIC_H743IIKX) || defined(ARDUINO_GENERIC_H743IITX) ||\ + defined(ARDUINO_GENERIC_H750IBKX) || defined(ARDUINO_GENERIC_H750IBTX) ||\ + defined(ARDUINO_GENERIC_H753IIKX) || defined(ARDUINO_GENERIC_H753IITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/ldscript.ld b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/ldscript.ld similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/ldscript.ld rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/ldscript.ld diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.cpp b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_PATCH_SM.cpp similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.cpp rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_PATCH_SM.cpp diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_PATCH_SM.h similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_PATCH_SM.h diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.cpp b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_PETAL_SM.cpp similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.cpp rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_PETAL_SM.cpp diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_PETAL_SM.h similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_PETAL_SM.h diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.cpp b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_SEED.cpp similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.cpp rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_SEED.cpp diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_SEED.h similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_DAISY_SEED.h diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_generic.cpp b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_generic.cpp similarity index 93% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_generic.cpp rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_generic.cpp index 6383e460af..d815ac1b22 100644 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_generic.cpp +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_generic.cpp @@ -10,9 +10,12 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H742IGKX) || defined(ARDUINO_GENERIC_H742IIKX) ||\ - defined(ARDUINO_GENERIC_H743IGKX) || defined(ARDUINO_GENERIC_H743IIKX) ||\ - defined(ARDUINO_GENERIC_H750IBKX) || defined(ARDUINO_GENERIC_H753IIKX) +#if defined(ARDUINO_GENERIC_H742IGKX) || defined(ARDUINO_GENERIC_H742IGTX) ||\ + defined(ARDUINO_GENERIC_H742IIKX) || defined(ARDUINO_GENERIC_H742IITX) ||\ + defined(ARDUINO_GENERIC_H743IGKX) || defined(ARDUINO_GENERIC_H743IGTX) ||\ + defined(ARDUINO_GENERIC_H743IIKX) || defined(ARDUINO_GENERIC_H743IITX) ||\ + defined(ARDUINO_GENERIC_H750IBKX) || defined(ARDUINO_GENERIC_H750IBTX) ||\ + defined(ARDUINO_GENERIC_H753IIKX) || defined(ARDUINO_GENERIC_H753IITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_generic.h b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_generic.h similarity index 100% rename from variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_generic.h rename to variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/variant_generic.h diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/CMakeLists.txt b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/CMakeLists.txt deleted file mode 100644 index 271b27c96b..0000000000 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - PeripheralPins_DAISY_PATCH_SM.c - PeripheralPins_DAISY_PETAL_SM.c - PeripheralPins_DAISY_SEED.c - variant_DAISY_PATCH_SM.cpp - variant_DAISY_PETAL_SM.cpp - variant_DAISY_SEED.cpp - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins.c b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins.c deleted file mode 100644 index 6d1a86c132..0000000000 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PeripheralPins.c +++ /dev/null @@ -1,721 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H742I(G-I)Kx.xml, STM32H743IGKx.xml - * STM32H743IIKx.xml, STM32H750IBKx.xml - * STM32H753IIKx.xml - * CubeMX DB release 6.0.120 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_0_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_1_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 - {PC_2_C, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 - {PC_3_C, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {PF_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 - {PF_4, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 - {PF_5, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 - {PF_6, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 - {PF_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 - {PF_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 - {PF_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 - {PF_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 - {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 - {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 - {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 - {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 - {PH_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 - {PH_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 - {PH_4, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 - {PH_5, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_14, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** No I3C *** - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PH_6, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PH_9, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PH_10, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PH_11, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3_C, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2_C, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PI_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED) -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2_C, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3_C, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {NC, NP, 0} -}; -#endif - -//*** QUADSPI *** - -#ifdef HAL_QSPI_MODULE_ENABLED -WEAK const PinMap PinMap_QUADSPI_DATA0[] = { - {PC_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 - {PD_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 - {PE_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 - {PF_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 - {PH_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_QSPI_MODULE_ENABLED -WEAK const PinMap PinMap_QUADSPI_DATA1[] = { - {PC_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 - {PD_12, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 - {PE_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 - {PF_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 - {PH_3, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_QSPI_MODULE_ENABLED -WEAK const PinMap PinMap_QUADSPI_DATA2[] = { - {PE_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 - {PE_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 - {PF_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 - {PG_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_QSPI_MODULE_ENABLED -WEAK const PinMap PinMap_QUADSPI_DATA3[] = { - {PA_1, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 - {PD_13, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 - {PE_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 - {PF_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 - {PG_14, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_QSPI_MODULE_ENABLED -WEAK const PinMap PinMap_QUADSPI_SCLK[] = { - {PB_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK - {PF_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_QSPI_MODULE_ENABLED -WEAK const PinMap PinMap_QUADSPI_SSEL[] = { - {PB_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS - {PB_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS - {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS - {PG_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_OTG_FS[] = { - {PA_8, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF - {PA_9, USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS - {PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID - {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM - {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP - {NC, NP, 0} -}; -#endif - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_OTG_HS[] = { -#ifdef USE_USB_HS_IN_FS - {PA_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF - {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID - {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS - {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM - {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP -#else - {PA_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 - {PA_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK - {PB_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 - {PB_1, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 - {PB_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 - {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 - {PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 - {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 - {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 - {PC_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP - {PC_2_C, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR - {PC_3_C, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT - {PH_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT - {PI_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR -#endif /* USE_USB_HS_IN_FS */ - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDIO2)}, // SDMMC2_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO1)}, // SDMMC1_CMD - {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDIO2)}, // SDMMC2_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDIO2)}, // SDMMC2_CK - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO1)}, // SDMMC1_CK - {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDIO2)}, // SDMMC2_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D1 - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D2 - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D2 - {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D3 - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D4 - {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D5 - {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D6 - {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D7 - {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDIO1)}, // SDMMC1_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDIO1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDIO1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDIO1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PinNamesVar.h b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PinNamesVar.h deleted file mode 100644 index 32b4518aa2..0000000000 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/PinNamesVar.h +++ /dev/null @@ -1,120 +0,0 @@ -/* Dual pad pin name */ -PC_2_C = PC_2 | PDUAL, -PC_3_C = PC_3 | PDUAL, - -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_0_ALT2 = PC_0 | ALT2, -PC_1_ALT1 = PC_1 | ALT1, -PC_1_ALT2 = PC_1 | ALT2, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, -PF_8_ALT1 = PF_8 | ALT1, -PF_9_ALT1 = PF_9 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = PI_8, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PI_11, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif - -/* USB */ -#ifdef USBCON - USB_OTG_FS_DM = PA_11, - USB_OTG_FS_DP = PA_12, - USB_OTG_FS_ID = PA_10, - USB_OTG_FS_SOF = PA_8, - USB_OTG_FS_VBUS = PA_9, - USB_OTG_HS_DM = PB_14, - USB_OTG_HS_DP = PB_15, - USB_OTG_HS_ID = PB_12, - USB_OTG_HS_SOF = PA_4, - USB_OTG_HS_ULPI_CK = PA_5, - USB_OTG_HS_ULPI_D0 = PA_3, - USB_OTG_HS_ULPI_D1 = PB_0, - USB_OTG_HS_ULPI_D2 = PB_1, - USB_OTG_HS_ULPI_D3 = PB_10, - USB_OTG_HS_ULPI_D4 = PB_11, - USB_OTG_HS_ULPI_D5 = PB_12, - USB_OTG_HS_ULPI_D6 = PB_13, - USB_OTG_HS_ULPI_D7 = PB_5, - #ifdef USB_OTG_HS_ULPI_DIR_PC_2_C - USB_OTG_HS_ULPI_DIR = PC_2_C, - #endif - #ifdef USB_OTG_HS_ULPI_DIR_PI_11 - USB_OTG_HS_ULPI_DIR = PI_11, - #endif - #ifdef USB_OTG_HS_ULPI_NXT_PC_3_C - USB_OTG_HS_ULPI_NXT = PC_3_C, - #endif - #ifdef USB_OTG_HS_ULPI_NXT_PH_4 - USB_OTG_HS_ULPI_NXT = PH_4, - #endif - USB_OTG_HS_ULPI_STP = PC_0, - USB_OTG_HS_VBUS = PB_13, -#endif diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/boards_entry.txt b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/boards_entry.txt deleted file mode 100644 index ad6cc14a20..0000000000 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/boards_entry.txt +++ /dev/null @@ -1,59 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H742IGKx -GenH7.menu.pnum.GENERIC_H742IGKX=Generic H742IGKx -GenH7.menu.pnum.GENERIC_H742IGKX.upload.maximum_size=1048576 -GenH7.menu.pnum.GENERIC_H742IGKX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H742IGKX.build.board=GENERIC_H742IGKX -GenH7.menu.pnum.GENERIC_H742IGKX.build.product_line=STM32H742xx -GenH7.menu.pnum.GENERIC_H742IGKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK -GenH7.menu.pnum.GENERIC_H742IGKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd - -# Generic H742IIKx -GenH7.menu.pnum.GENERIC_H742IIKX=Generic H742IIKx -GenH7.menu.pnum.GENERIC_H742IIKX.upload.maximum_size=2097152 -GenH7.menu.pnum.GENERIC_H742IIKX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H742IIKX.build.board=GENERIC_H742IIKX -GenH7.menu.pnum.GENERIC_H742IIKX.build.product_line=STM32H742xx -GenH7.menu.pnum.GENERIC_H742IIKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK -GenH7.menu.pnum.GENERIC_H742IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd - -# Generic H743IGKx -GenH7.menu.pnum.GENERIC_H743IGKX=Generic H743IGKx -GenH7.menu.pnum.GENERIC_H743IGKX.upload.maximum_size=1048576 -GenH7.menu.pnum.GENERIC_H743IGKX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H743IGKX.build.board=GENERIC_H743IGKX -GenH7.menu.pnum.GENERIC_H743IGKX.build.product_line=STM32H743xx -GenH7.menu.pnum.GENERIC_H743IGKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK -GenH7.menu.pnum.GENERIC_H743IGKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd - -# Generic H743IIKx -GenH7.menu.pnum.GENERIC_H743IIKX=Generic H743IIKx -GenH7.menu.pnum.GENERIC_H743IIKX.upload.maximum_size=2097152 -GenH7.menu.pnum.GENERIC_H743IIKX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H743IIKX.build.board=GENERIC_H743IIKX -GenH7.menu.pnum.GENERIC_H743IIKX.build.product_line=STM32H743xx -GenH7.menu.pnum.GENERIC_H743IIKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK -GenH7.menu.pnum.GENERIC_H743IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd - -# Generic H750IBKx -GenH7.menu.pnum.GENERIC_H750IBKX=Generic H750IBKx -GenH7.menu.pnum.GENERIC_H750IBKX.upload.maximum_size=131072 -GenH7.menu.pnum.GENERIC_H750IBKX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H750IBKX.build.board=GENERIC_H750IBKX -GenH7.menu.pnum.GENERIC_H750IBKX.build.product_line=STM32H750xx -GenH7.menu.pnum.GENERIC_H750IBKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK -GenH7.menu.pnum.GENERIC_H750IBKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd - -# Generic H753IIKx -GenH7.menu.pnum.GENERIC_H753IIKX=Generic H753IIKx -GenH7.menu.pnum.GENERIC_H753IIKX.upload.maximum_size=2097152 -GenH7.menu.pnum.GENERIC_H753IIKX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H753IIKX.build.board=GENERIC_H753IIKX -GenH7.menu.pnum.GENERIC_H753IIKX.build.product_line=STM32H753xx -GenH7.menu.pnum.GENERIC_H753IIKX.build.variant=STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK -GenH7.menu.pnum.GENERIC_H753IIKX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd - diff --git a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/CMakeLists.txt b/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/boards_entry.txt b/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/boards_entry.txt deleted file mode 100644 index 3b95ba2dd6..0000000000 --- a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/boards_entry.txt +++ /dev/null @@ -1,59 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H742IGTx -GenH7.menu.pnum.GENERIC_H742IGTX=Generic H742IGTx -GenH7.menu.pnum.GENERIC_H742IGTX.upload.maximum_size=1048576 -GenH7.menu.pnum.GENERIC_H742IGTX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H742IGTX.build.board=GENERIC_H742IGTX -GenH7.menu.pnum.GENERIC_H742IGTX.build.product_line=STM32H742xx -GenH7.menu.pnum.GENERIC_H742IGTX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT -GenH7.menu.pnum.GENERIC_H742IGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd - -# Generic H742IITx -GenH7.menu.pnum.GENERIC_H742IITX=Generic H742IITx -GenH7.menu.pnum.GENERIC_H742IITX.upload.maximum_size=2097152 -GenH7.menu.pnum.GENERIC_H742IITX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H742IITX.build.board=GENERIC_H742IITX -GenH7.menu.pnum.GENERIC_H742IITX.build.product_line=STM32H742xx -GenH7.menu.pnum.GENERIC_H742IITX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT -GenH7.menu.pnum.GENERIC_H742IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H742.svd - -# Generic H743IGTx -GenH7.menu.pnum.GENERIC_H743IGTX=Generic H743IGTx -GenH7.menu.pnum.GENERIC_H743IGTX.upload.maximum_size=1048576 -GenH7.menu.pnum.GENERIC_H743IGTX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H743IGTX.build.board=GENERIC_H743IGTX -GenH7.menu.pnum.GENERIC_H743IGTX.build.product_line=STM32H743xx -GenH7.menu.pnum.GENERIC_H743IGTX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT -GenH7.menu.pnum.GENERIC_H743IGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd - -# Generic H743IITx -GenH7.menu.pnum.GENERIC_H743IITX=Generic H743IITx -GenH7.menu.pnum.GENERIC_H743IITX.upload.maximum_size=2097152 -GenH7.menu.pnum.GENERIC_H743IITX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H743IITX.build.board=GENERIC_H743IITX -GenH7.menu.pnum.GENERIC_H743IITX.build.product_line=STM32H743xx -GenH7.menu.pnum.GENERIC_H743IITX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT -GenH7.menu.pnum.GENERIC_H743IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd - -# Generic H750IBTx -GenH7.menu.pnum.GENERIC_H750IBTX=Generic H750IBTx -GenH7.menu.pnum.GENERIC_H750IBTX.upload.maximum_size=131072 -GenH7.menu.pnum.GENERIC_H750IBTX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H750IBTX.build.board=GENERIC_H750IBTX -GenH7.menu.pnum.GENERIC_H750IBTX.build.product_line=STM32H750xx -GenH7.menu.pnum.GENERIC_H750IBTX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT -GenH7.menu.pnum.GENERIC_H750IBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd - -# Generic H753IITx -GenH7.menu.pnum.GENERIC_H753IITX=Generic H753IITx -GenH7.menu.pnum.GENERIC_H753IITX.upload.maximum_size=2097152 -GenH7.menu.pnum.GENERIC_H753IITX.upload.maximum_data_size=884736 -GenH7.menu.pnum.GENERIC_H753IITX.build.board=GENERIC_H753IITX -GenH7.menu.pnum.GENERIC_H753IITX.build.product_line=STM32H753xx -GenH7.menu.pnum.GENERIC_H753IITX.build.variant=STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT -GenH7.menu.pnum.GENERIC_H753IITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd - diff --git a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/generic_clock.c b/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/generic_clock.c deleted file mode 100644 index 43599d3b1b..0000000000 --- a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/generic_clock.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H742IGTX) || defined(ARDUINO_GENERIC_H742IITX) ||\ - defined(ARDUINO_GENERIC_H743IGTX) || defined(ARDUINO_GENERIC_H743IITX) ||\ - defined(ARDUINO_GENERIC_H750IBTX) || defined(ARDUINO_GENERIC_H753IITX) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - - /** Supply configuration update enable - */ - HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); - /** Configure the main internal regulator output voltage - */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); - - while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 4; - RCC_OscInitStruct.PLL.PLLN = 60; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 5; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; - RCC_OscInitStruct.PLL.PLLFRACN = 0; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - Error_Handler(); - } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 - | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { - Error_Handler(); - } - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_QSPI - | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_ADC - | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USART16 - | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_I2C123 - | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 - | RCC_PERIPHCLK_SPI6; - PeriphClkInitStruct.PLL2.PLL2M = 4; - PeriphClkInitStruct.PLL2.PLL2N = 10; - PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 2; - PeriphClkInitStruct.PLL2.PLL2R = 2; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; - PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM; - PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; - PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1; - PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; - PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; - PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; - PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; - PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1; - PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_D3PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - Error_Handler(); - } -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/ldscript.ld b/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/ldscript.ld deleted file mode 100644 index 80e6928044..0000000000 --- a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/ldscript.ld +++ /dev/null @@ -1,170 +0,0 @@ -/** - ****************************************************************************** - * @file LinkerScript.ld - * @author Auto-generated by STM32CubeIDE - * @brief Linker script for STM32H750IBTx Device from STM32H7 series - * 128Kbytes FLASH - * 128Kbytes DTCMRAM - * 64Kbytes ITCMRAM - * 512Kbytes RAM_D1 - * 288Kbytes RAM_D2 - * 64Kbytes RAM_D3 - * - * Set heap size, stack size and stack location according - * to application requirements. - * - * Set memory bank area and size if external memory is used - ****************************************************************************** - * @attention - * - *

                                                    © Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

                                                    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1); /* end of "RAM_D1" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ - DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K - ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K - RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = LD_MAX_DATA_SIZE - RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K - RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K - FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM (READONLY) : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array (READONLY) : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array (READONLY) : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array (READONLY) : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM_D1" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM_D1 AT> FLASH - - /* Uninitialized data section into "RAM_D1" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM_D1 - - /* User_heap_stack section, used to check that there is enough "RAM_D1" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM_D1 - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/variant_generic.cpp b/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/variant_generic.cpp deleted file mode 100644 index dca4de2a47..0000000000 --- a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/variant_generic.cpp +++ /dev/null @@ -1,198 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H742IGTX) || defined(ARDUINO_GENERIC_H742IITX) ||\ - defined(ARDUINO_GENERIC_H743IGTX) || defined(ARDUINO_GENERIC_H743IITX) ||\ - defined(ARDUINO_GENERIC_H750IBTX) || defined(ARDUINO_GENERIC_H753IITX) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_11, // D27 - PB_12, // D28 - PB_13, // D29 - PB_14, // D30 - PB_15, // D31 - PC_0, // D32/A10 - PC_1, // D33/A11 - PC_4, // D34/A12 - PC_5, // D35/A13 - PC_6, // D36 - PC_7, // D37 - PC_8, // D38 - PC_9, // D39 - PC_10, // D40 - PC_11, // D41 - PC_12, // D42 - PC_13, // D43 - PC_14, // D44 - PC_15, // D45 - PD_0, // D46 - PD_1, // D47 - PD_2, // D48 - PD_3, // D49 - PD_4, // D50 - PD_5, // D51 - PD_6, // D52 - PD_7, // D53 - PD_8, // D54 - PD_9, // D55 - PD_10, // D56 - PD_11, // D57 - PD_12, // D58 - PD_13, // D59 - PD_14, // D60 - PD_15, // D61 - PE_0, // D62 - PE_1, // D63 - PE_2, // D64 - PE_3, // D65 - PE_4, // D66 - PE_5, // D67 - PE_6, // D68 - PE_7, // D69 - PE_8, // D70 - PE_9, // D71 - PE_10, // D72 - PE_11, // D73 - PE_12, // D74 - PE_13, // D75 - PE_14, // D76 - PE_15, // D77 - PF_0, // D78 - PF_1, // D79 - PF_2, // D80 - PF_3, // D81/A14 - PF_4, // D82/A15 - PF_5, // D83/A16 - PF_6, // D84/A17 - PF_7, // D85/A18 - PF_8, // D86/A19 - PF_9, // D87/A20 - PF_10, // D88/A21 - PF_11, // D89/A22 - PF_12, // D90/A23 - PF_13, // D91/A24 - PF_14, // D92/A25 - PF_15, // D93 - PG_0, // D94 - PG_1, // D95 - PG_2, // D96 - PG_3, // D97 - PG_4, // D98 - PG_5, // D99 - PG_6, // D100 - PG_7, // D101 - PG_8, // D102 - PG_9, // D103 - PG_10, // D104 - PG_11, // D105 - PG_12, // D106 - PG_13, // D107 - PG_14, // D108 - PG_15, // D109 - PH_0, // D110 - PH_1, // D111 - PH_2, // D112/A26 - PH_3, // D113/A27 - PH_4, // D114/A28 - PH_5, // D115/A29 - PH_6, // D116 - PH_7, // D117 - PH_8, // D118 - PH_9, // D119 - PH_10, // D120 - PH_11, // D121 - PH_12, // D122 - PH_13, // D123 - PH_14, // D124 - PH_15, // D125 - PI_0, // D126 - PI_1, // D127 - PI_2, // D128 - PI_3, // D129 - PI_4, // D130 - PI_5, // D131 - PI_6, // D132 - PI_7, // D133 - PI_8, // D134 - PI_9, // D135 - PI_10, // D136 - PI_11, // D137 - PC_2_C, // D138/A30 - PC_3_C // D139/A31 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 32, // A10, PC0 - 33, // A11, PC1 - 34, // A12, PC4 - 35, // A13, PC5 - 81, // A14, PF3 - 82, // A15, PF4 - 83, // A16, PF5 - 84, // A17, PF6 - 85, // A18, PF7 - 86, // A19, PF8 - 87, // A20, PF9 - 88, // A21, PF10 - 89, // A22, PF11 - 90, // A23, PF12 - 91, // A24, PF13 - 92, // A25, PF14 - 112, // A26, PH2 - 113, // A27, PH3 - 114, // A28, PH4 - 115, // A29, PH5 - 138, // A30, PC2_C - 139 // A31, PC3_C -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/variant_generic.h b/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/variant_generic.h deleted file mode 100644 index 6cb43b54d6..0000000000 --- a/variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT/variant_generic.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB11 27 -#define PB12 28 -#define PB13 29 -#define PB14 30 -#define PB15 31 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC4 PIN_A12 -#define PC5 PIN_A13 -#define PC6 36 -#define PC7 37 -#define PC8 38 -#define PC9 39 -#define PC10 40 -#define PC11 41 -#define PC12 42 -#define PC13 43 -#define PC14 44 -#define PC15 45 -#define PD0 46 -#define PD1 47 -#define PD2 48 -#define PD3 49 -#define PD4 50 -#define PD5 51 -#define PD6 52 -#define PD7 53 -#define PD8 54 -#define PD9 55 -#define PD10 56 -#define PD11 57 -#define PD12 58 -#define PD13 59 -#define PD14 60 -#define PD15 61 -#define PE0 62 -#define PE1 63 -#define PE2 64 -#define PE3 65 -#define PE4 66 -#define PE5 67 -#define PE6 68 -#define PE7 69 -#define PE8 70 -#define PE9 71 -#define PE10 72 -#define PE11 73 -#define PE12 74 -#define PE13 75 -#define PE14 76 -#define PE15 77 -#define PF0 78 -#define PF1 79 -#define PF2 80 -#define PF3 PIN_A14 -#define PF4 PIN_A15 -#define PF5 PIN_A16 -#define PF6 PIN_A17 -#define PF7 PIN_A18 -#define PF8 PIN_A19 -#define PF9 PIN_A20 -#define PF10 PIN_A21 -#define PF11 PIN_A22 -#define PF12 PIN_A23 -#define PF13 PIN_A24 -#define PF14 PIN_A25 -#define PF15 93 -#define PG0 94 -#define PG1 95 -#define PG2 96 -#define PG3 97 -#define PG4 98 -#define PG5 99 -#define PG6 100 -#define PG7 101 -#define PG8 102 -#define PG9 103 -#define PG10 104 -#define PG11 105 -#define PG12 106 -#define PG13 107 -#define PG14 108 -#define PG15 109 -#define PH0 110 -#define PH1 111 -#define PH2 PIN_A26 -#define PH3 PIN_A27 -#define PH4 PIN_A28 -#define PH5 PIN_A29 -#define PH6 116 -#define PH7 117 -#define PH8 118 -#define PH9 119 -#define PH10 120 -#define PH11 121 -#define PH12 122 -#define PH13 123 -#define PH14 124 -#define PH15 125 -#define PI0 126 -#define PI1 127 -#define PI2 128 -#define PI3 129 -#define PI4 130 -#define PI5 131 -#define PI6 132 -#define PI7 133 -#define PI8 134 -#define PI9 135 -#define PI10 136 -#define PI11 137 -#define PC2_C PIN_A30 -#define PC3_C PIN_A31 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC0_ALT2 (PC0 | ALT2) -#define PC1_ALT1 (PC1 | ALT1) -#define PC1_ALT2 (PC1 | ALT2) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) -#define PF8_ALT1 (PF8 | ALT1) -#define PF9_ALT1 (PF9 | ALT1) - -#define NUM_DIGITAL_PINS 140 -#define NUM_DUALPAD_PINS 2 -#define NUM_ANALOG_INPUTS 32 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PG10 -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB7 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB6 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_QSPI_MODULE_DISABLED) - #define HAL_QSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c index 5285f572c6..3e7c02e444 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H743V(G-I)Hx.xml, STM32H743VGTx.xml * STM32H743VITx.xml, STM32H750VBTx.xml * STM32H753VIHx.xml, STM32H753VITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PinNamesVar.h b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PinNamesVar.h index be78aa1a18..cb79334683 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PinNamesVar.h +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PinNamesVar.h @@ -74,12 +74,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c index 7d6f4c7973..22e9d01361 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c @@ -17,7 +17,7 @@ * STM32H747XIHx.xml, STM32H750XBHx.xml * STM32H753XIHx.xml, STM32H755XIHx.xml * STM32H757XIHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PinNamesVar.h b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PinNamesVar.h index 3a377570fd..79be657313 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PinNamesVar.h +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PinNamesVar.h @@ -90,12 +90,6 @@ PK_1_ALT1 = PK_1 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c index 7cc5f17582..7c8fb81649 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32H747IGTx.xml, STM32H747IITx.xml * STM32H750ZBTx.xml, STM32H753ZITx.xml * STM32H757AIIx.xml, STM32H757IITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PinNamesVar.h b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PinNamesVar.h index 981376a269..b2e6fbc4be 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PinNamesVar.h +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PinNamesVar.h @@ -76,12 +76,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c index 6efd0f14f9..faee874343 100644 --- a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745BGTx.xml, STM32H745BITx.xml * STM32H755BITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PinNamesVar.h b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PinNamesVar.h index 5c248acda8..2eda82ecbf 100644 --- a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PinNamesVar.h +++ b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PinNamesVar.h @@ -82,12 +82,6 @@ PK_1_ALT1 = PK_1 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c index 16fc4a6737..c085ce1614 100644 --- a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c +++ b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745IGKx.xml, STM32H745IIKx.xml * STM32H755IIKx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PinNamesVar.h b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PinNamesVar.h index 1597969ce7..5f0e6a649f 100644 --- a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PinNamesVar.h +++ b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PinNamesVar.h @@ -84,12 +84,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c index 04b6acd88b..cc901911e2 100644 --- a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745IGTx.xml, STM32H745IITx.xml * STM32H755IITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PinNamesVar.h b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PinNamesVar.h index 7ad9deab71..f00075a205 100644 --- a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PinNamesVar.h +++ b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PinNamesVar.h @@ -82,12 +82,6 @@ PK_1_ALT1 = PK_1 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c index 5be88a955a..9602de3581 100644 --- a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745ZGTx.xml, STM32H745ZITx.xml * STM32H755ZITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PinNamesVar.h b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PinNamesVar.h index 981376a269..b2e6fbc4be 100644 --- a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PinNamesVar.h +++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PinNamesVar.h @@ -76,12 +76,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c index e72a387415..f7fa0c56d6 100644 --- a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H747BGTx.xml, STM32H747BITx.xml * STM32H757BITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PinNamesVar.h b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PinNamesVar.h index 32b4518aa2..e0299c00d9 100644 --- a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PinNamesVar.h +++ b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PinNamesVar.h @@ -76,12 +76,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c b/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c index 15213cc11a..60d07b5f3d 100644 --- a/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c +++ b/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H747ZIYx.xml, STM32H757ZIYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H747ZIY_H757ZIY/PinNamesVar.h b/variants/STM32H7xx/H747ZIY_H757ZIY/PinNamesVar.h index be78aa1a18..cb79334683 100644 --- a/variants/STM32H7xx/H747ZIY_H757ZIY/PinNamesVar.h +++ b/variants/STM32H7xx/H747ZIY_H757ZIY/PinNamesVar.h @@ -74,12 +74,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c index 7a63281319..0cd9a862bb 100644 --- a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3A(G-I)IxQ.xml, STM32H7B0ABIxQ.xml * STM32H7B3AIIxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PinNamesVar.h b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PinNamesVar.h index e552ada857..8cf7194cba 100644 --- a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PinNamesVar.h @@ -82,12 +82,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c index 33af17368c..4ee18586a8 100644 --- a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H7A3I(G-I)Kx.xml, STM32H7A3I(G-I)Tx.xml * STM32H7B0IBTx.xml, STM32H7B3IIKx.xml * STM32H7B3IITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PinNamesVar.h b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PinNamesVar.h index 2ac9ba87ba..9d9c6667f7 100644 --- a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PinNamesVar.h @@ -75,12 +75,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c index 80521be031..9f9c090fc1 100644 --- a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3I(G-I)KxQ.xml, STM32H7B0IBKxQ.xml * STM32H7B3IIKxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PinNamesVar.h b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PinNamesVar.h index dfd88a82da..ccae09fc26 100644 --- a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PinNamesVar.h @@ -82,12 +82,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c index f19dec2448..26ec47a011 100644 --- a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3I(G-I)TxQ.xml, STM32H7B3IITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PinNamesVar.h b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PinNamesVar.h index ff2a31d676..8ff670af0d 100644 --- a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PinNamesVar.h @@ -81,12 +81,6 @@ PK_1_ALT1 = PK_1 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c index 9ea5ba13ff..42e6ead792 100644 --- a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3L(G-I)HxQ.xml, STM32H7B3LIHxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PinNamesVar.h b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PinNamesVar.h index 8727482802..f7a38f7e25 100644 --- a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PinNamesVar.h @@ -88,12 +88,6 @@ PK_1_ALT1 = PK_1 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c index 3b764152b0..f7c4c06371 100644 --- a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3N(G-I)Hx.xml, STM32H7B3NIHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PinNamesVar.h b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PinNamesVar.h index a7a137b5a9..c7baae46a4 100644 --- a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PinNamesVar.h @@ -81,12 +81,6 @@ PK_1_ALT1 = PK_1 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c index 7a9027bea9..65be772b56 100644 --- a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3QIYxQ.xml, STM32H7B3QIYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PinNamesVar.h b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PinNamesVar.h index 6cbb64372f..60931cd323 100644 --- a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PinNamesVar.h @@ -70,12 +70,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c index dc75cd1985..7f9e09a7a4 100644 --- a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3R(G-I)Tx.xml, STM32H7B0RBTx.xml * STM32H7B3RITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PinNamesVar.h b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PinNamesVar.h index 56c54ccc59..2855d4e96b 100644 --- a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PinNamesVar.h @@ -69,12 +69,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c index cba7f512a7..8668749814 100644 --- a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H7A3V(G-I)Hx.xml, STM32H7A3V(G-I)Tx.xml * STM32H7B0VBTx.xml, STM32H7B3VIHx.xml * STM32H7B3VITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PinNamesVar.h b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PinNamesVar.h index 503c618152..19f5328ed4 100644 --- a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PinNamesVar.h @@ -72,12 +72,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c index cbc8e2a1b0..01637636da 100644 --- a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3V(G-I)HxQ.xml, STM32H7B3VIHxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PinNamesVar.h b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PinNamesVar.h index 503c618152..19f5328ed4 100644 --- a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PinNamesVar.h @@ -72,12 +72,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c index 5bf3345696..08ebaf05dd 100644 --- a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3V(G-I)TxQ.xml, STM32H7B3VITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PinNamesVar.h b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PinNamesVar.h index 503c618152..19f5328ed4 100644 --- a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PinNamesVar.h @@ -72,12 +72,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c index d44b200513..b661f77b59 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3Z(G-I)Tx.xml, STM32H7B0ZBTx.xml * STM32H7B3ZITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PinNamesVar.h b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PinNamesVar.h index 01fe1dbd6a..8235bb14b1 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PinNamesVar.h @@ -75,12 +75,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c index b433b72e99..f98c576a55 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3Z(G-I)TxQ.xml, STM32H7B3ZITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PinNamesVar.h b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PinNamesVar.h index 01fe1dbd6a..8235bb14b1 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PinNamesVar.h +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PinNamesVar.h @@ -75,12 +75,6 @@ PG_13_ALT1 = PG_13 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 0ff21777f862732c6f44d55701de349d3ac983e9 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:38:41 +0100 Subject: [PATCH 049/141] chore(l0): update variant after script update Signed-off-by: Frederic Pillon --- variants/STM32L0xx/L010C6T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010C6T/PinNamesVar.h | 15 ------------- .../PeripheralPins.c | 2 +- .../L010F4P_L011F(3-4)P_L021F4P/PinNamesVar.h | 15 ------------- .../PeripheralPins.c | 2 +- .../L010K4T_L011K(3-4)T_L021K4T/PinNamesVar.h | 15 ------------- variants/STM32L0xx/L010K8T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010K8T/PinNamesVar.h | 21 ------------------- variants/STM32L0xx/L010R8T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010R8T/PinNamesVar.h | 18 ---------------- variants/STM32L0xx/L010RBT/PeripheralPins.c | 2 +- variants/STM32L0xx/L010RBT/PinNamesVar.h | 18 ---------------- .../L011D(3-4)P_L021D4P/PeripheralPins.c | 2 +- .../L011D(3-4)P_L021D4P/PinNamesVar.h | 21 ------------------- .../STM32L0xx/L011E(3-4)Y/PeripheralPins.c | 2 +- variants/STM32L0xx/L011E(3-4)Y/PinNamesVar.h | 15 ------------- .../L011F(3-4)U_L021F4U/PeripheralPins.c | 2 +- .../L011F(3-4)U_L021F4U/PinNamesVar.h | 21 ------------------- .../L011G(3-4)U_L021G4U/PeripheralPins.c | 2 +- .../L011G(3-4)U_L021G4U/PinNamesVar.h | 15 ------------- .../L011K(3-4)U_L021K4U/PeripheralPins.c | 2 +- .../L011K(3-4)U_L021K4U/PinNamesVar.h | 15 ------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 15 ------------- .../L031E(4-6)Y_L041E6Y/PeripheralPins.c | 2 +- .../L031E(4-6)Y_L041E6Y/PinNamesVar.h | 15 ------------- .../L031F(4-6)P_L041F6P/PeripheralPins.c | 2 +- .../L031F(4-6)P_L041F6P/PinNamesVar.h | 15 ------------- .../L031G(4-6)U_L041G6U/PeripheralPins.c | 2 +- .../L031G(4-6)U_L041G6U/PinNamesVar.h | 15 ------------- .../L031G6UxS_L041G6UxS/PeripheralPins.c | 2 +- .../L031G6UxS_L041G6UxS/PinNamesVar.h | 15 ------------- .../L031K(4-6)T_L041K6T/PeripheralPins.c | 2 +- .../L031K(4-6)T_L041K6T/PinNamesVar.h | 15 ------------- .../L031K(4-6)U_L041K6U/PeripheralPins.c | 2 +- .../L031K(4-6)U_L041K6U/PinNamesVar.h | 15 ------------- .../L051C(6-8)(T-U)/PeripheralPins.c | 2 +- .../STM32L0xx/L051C(6-8)(T-U)/PinNamesVar.h | 18 ---------------- .../STM32L0xx/L051K(6-8)T/PeripheralPins.c | 2 +- variants/STM32L0xx/L051K(6-8)T/PinNamesVar.h | 21 ------------------- .../STM32L0xx/L051K(6-8)U/PeripheralPins.c | 2 +- variants/STM32L0xx/L051K(6-8)U/PinNamesVar.h | 21 ------------------- .../STM32L0xx/L051R(6-8)H/PeripheralPins.c | 2 +- variants/STM32L0xx/L051R(6-8)H/PinNamesVar.h | 18 ---------------- .../STM32L0xx/L051R(6-8)T/PeripheralPins.c | 2 +- variants/STM32L0xx/L051R(6-8)T/PinNamesVar.h | 18 ---------------- .../STM32L0xx/L051T(6-8)Y/PeripheralPins.c | 2 +- variants/STM32L0xx/L051T(6-8)Y/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ---------------- .../L052K(6-8)T_L062K8T/PeripheralPins.c | 2 +- .../L052K(6-8)T_L062K8T/PinNamesVar.h | 21 ------------------- .../L052K(6-8)U_L062K8U/PeripheralPins.c | 2 +- .../L052K(6-8)U_L062K8U/PinNamesVar.h | 21 ------------------- .../L052R(6-8)H_L053R(6-8)H/PeripheralPins.c | 2 +- .../L052R(6-8)H_L053R(6-8)H/PinNamesVar.h | 18 ---------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ---------------- .../L052T6Y_L052T8(F-Y)/PeripheralPins.c | 2 +- .../L052T6Y_L052T8(F-Y)/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ---------------- .../STM32L0xx/L071C(B-Z)Y/PeripheralPins.c | 2 +- variants/STM32L0xx/L071C(B-Z)Y/PinNamesVar.h | 18 ---------------- .../L071K(8-B-Z)U_L081KZU/PeripheralPins.c | 2 +- .../L071K(8-B-Z)U_L081KZU/PinNamesVar.h | 21 ------------------- .../L071K(B-Z)T_L081KZT/PeripheralPins.c | 2 +- .../L071K(B-Z)T_L081KZT/PinNamesVar.h | 21 ------------------- .../STM32L0xx/L071R(B-Z)H/PeripheralPins.c | 2 +- variants/STM32L0xx/L071R(B-Z)H/PinNamesVar.h | 18 ---------------- .../STM32L0xx/L071R(B-Z)T/PeripheralPins.c | 2 +- variants/STM32L0xx/L071R(B-Z)T/PinNamesVar.h | 18 ---------------- .../L071V(8-B-Z)(I-T)/PeripheralPins.c | 2 +- .../STM32L0xx/L071V(8-B-Z)(I-T)/PinNamesVar.h | 15 ------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ---------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ---------------- .../L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c | 2 +- .../L072K(B-Z)T_L082K(B-Z)T/PinNamesVar.h | 21 ------------------- .../L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c | 2 +- .../L072K(B-Z)U_L082K(B-Z)U/PinNamesVar.h | 21 ------------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ---------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ---------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 15 ------------- 88 files changed, 44 insertions(+), 830 deletions(-) diff --git a/variants/STM32L0xx/L010C6T/PeripheralPins.c b/variants/STM32L0xx/L010C6T/PeripheralPins.c index 04233d3cbb..1835597202 100644 --- a/variants/STM32L0xx/L010C6T/PeripheralPins.c +++ b/variants/STM32L0xx/L010C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010C6Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010C6T/PinNamesVar.h b/variants/STM32L0xx/L010C6T/PinNamesVar.h index 4c3b41ec63..e027051884 100644 --- a/variants/STM32L0xx/L010C6T/PinNamesVar.h +++ b/variants/STM32L0xx/L010C6T/PinNamesVar.h @@ -13,20 +13,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c index c323ddce8b..82fe0fa5c3 100644 --- a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c +++ b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L010F4Px.xml, STM32L011F(3-4)Px.xml * STM32L021F4Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PinNamesVar.h b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PinNamesVar.h index 1e840e6061..663b6f8c59 100644 --- a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PinNamesVar.h +++ b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PinNamesVar.h @@ -15,20 +15,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c index 09c61671cb..622c694808 100644 --- a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c +++ b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L010K4Tx.xml, STM32L011K(3-4)Tx.xml * STM32L021K4Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PinNamesVar.h b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PinNamesVar.h index a26735e902..428beaac10 100644 --- a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PinNamesVar.h +++ b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PinNamesVar.h @@ -18,20 +18,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L010K8T/PeripheralPins.c b/variants/STM32L0xx/L010K8T/PeripheralPins.c index c15c99ee23..efba8dd844 100644 --- a/variants/STM32L0xx/L010K8T/PeripheralPins.c +++ b/variants/STM32L0xx/L010K8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010K8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010K8T/PinNamesVar.h b/variants/STM32L0xx/L010K8T/PinNamesVar.h index 6275fc5618..2a0af6630b 100644 --- a/variants/STM32L0xx/L010K8T/PinNamesVar.h +++ b/variants/STM32L0xx/L010K8T/PinNamesVar.h @@ -6,26 +6,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L010R8T/PeripheralPins.c b/variants/STM32L0xx/L010R8T/PeripheralPins.c index fffb91a4fd..3d67c769c8 100644 --- a/variants/STM32L0xx/L010R8T/PeripheralPins.c +++ b/variants/STM32L0xx/L010R8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010R8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010R8T/PinNamesVar.h b/variants/STM32L0xx/L010R8T/PinNamesVar.h index 2ca0c66576..d762849a99 100644 --- a/variants/STM32L0xx/L010R8T/PinNamesVar.h +++ b/variants/STM32L0xx/L010R8T/PinNamesVar.h @@ -9,23 +9,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L010RBT/PeripheralPins.c b/variants/STM32L0xx/L010RBT/PeripheralPins.c index fee8a48a1f..cfdecf6c3c 100644 --- a/variants/STM32L0xx/L010RBT/PeripheralPins.c +++ b/variants/STM32L0xx/L010RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010RBT/PinNamesVar.h b/variants/STM32L0xx/L010RBT/PinNamesVar.h index d797b2240b..d1b026914d 100644 --- a/variants/STM32L0xx/L010RBT/PinNamesVar.h +++ b/variants/STM32L0xx/L010RBT/PinNamesVar.h @@ -10,23 +10,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c index c5480ef203..768052fee9 100644 --- a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c +++ b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011D(3-4)Px.xml, STM32L021D4Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PinNamesVar.h b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PinNamesVar.h index d51031d9a2..6161f31905 100644 --- a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PinNamesVar.h +++ b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PinNamesVar.h @@ -7,26 +7,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c b/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c index aa87280b88..483c8d0250 100644 --- a/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011E(3-4)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011E(3-4)Y/PinNamesVar.h b/variants/STM32L0xx/L011E(3-4)Y/PinNamesVar.h index a26735e902..428beaac10 100644 --- a/variants/STM32L0xx/L011E(3-4)Y/PinNamesVar.h +++ b/variants/STM32L0xx/L011E(3-4)Y/PinNamesVar.h @@ -18,20 +18,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c index d5334db6ef..922c30272b 100644 --- a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011F(3-4)Ux.xml, STM32L021F4Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PinNamesVar.h b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PinNamesVar.h index 2979637ea4..39adc087fd 100644 --- a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PinNamesVar.h +++ b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PinNamesVar.h @@ -9,26 +9,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c index 283efef23b..36ba656314 100644 --- a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011G(3-4)Ux.xml, STM32L021G4Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PinNamesVar.h b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PinNamesVar.h index a26735e902..428beaac10 100644 --- a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PinNamesVar.h +++ b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PinNamesVar.h @@ -18,20 +18,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c index ac31b87699..872fe95d3a 100644 --- a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011K(3-4)Ux.xml, STM32L021K4Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PinNamesVar.h b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PinNamesVar.h index a26735e902..428beaac10 100644 --- a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PinNamesVar.h +++ b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PinNamesVar.h @@ -18,20 +18,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c index 3cc9db271d..50f6698fe7 100644 --- a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L031C(4-6)Tx.xml, STM32L031C(4-6)Ux.xml * STM32L041C(4-6)Tx.xml, STM32L041C6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PinNamesVar.h b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PinNamesVar.h index 4c3b41ec63..e027051884 100644 --- a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PinNamesVar.h +++ b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PinNamesVar.h @@ -13,20 +13,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c index 21c9add7cc..ca1fd7d225 100644 --- a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c +++ b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031E(4-6)Yx.xml, STM32L041E6Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PinNamesVar.h b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PinNamesVar.h index 940599c2f1..ddb04c83b7 100644 --- a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PinNamesVar.h +++ b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PinNamesVar.h @@ -13,20 +13,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c index 0b0033bee4..4e96fe4f54 100644 --- a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c +++ b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031F(4-6)Px.xml, STM32L041F6Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PinNamesVar.h b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PinNamesVar.h index 940599c2f1..ddb04c83b7 100644 --- a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PinNamesVar.h +++ b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PinNamesVar.h @@ -13,20 +13,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c index c71200ebff..a9633f489e 100644 --- a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c +++ b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031G(4-6)Ux.xml, STM32L041G6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PinNamesVar.h b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PinNamesVar.h index 940599c2f1..ddb04c83b7 100644 --- a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PinNamesVar.h +++ b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PinNamesVar.h @@ -13,20 +13,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c index c1c36e7d99..fc7ba05fa8 100644 --- a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c +++ b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031G6UxS.xml, STM32L041G6UxS.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PinNamesVar.h b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PinNamesVar.h index 940599c2f1..ddb04c83b7 100644 --- a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PinNamesVar.h +++ b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PinNamesVar.h @@ -13,20 +13,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c index 3adebe1390..517e10a0c4 100644 --- a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c +++ b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031K(4-6)Tx.xml, STM32L041K6Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PinNamesVar.h b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PinNamesVar.h index 940599c2f1..ddb04c83b7 100644 --- a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PinNamesVar.h +++ b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PinNamesVar.h @@ -13,20 +13,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c index 942561f67a..5de234b4ee 100644 --- a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c +++ b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031K(4-6)Ux.xml, STM32L041K6Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PinNamesVar.h b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PinNamesVar.h index 940599c2f1..ddb04c83b7 100644 --- a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PinNamesVar.h +++ b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PinNamesVar.h @@ -13,20 +13,5 @@ PA_14_ALT1 = PA_14 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c b/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c index b0b2bdbd3b..15595185d0 100644 --- a/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051C(6-8)Tx.xml, STM32L051C(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051C(6-8)(T-U)/PinNamesVar.h b/variants/STM32L0xx/L051C(6-8)(T-U)/PinNamesVar.h index 2ca0c66576..d762849a99 100644 --- a/variants/STM32L0xx/L051C(6-8)(T-U)/PinNamesVar.h +++ b/variants/STM32L0xx/L051C(6-8)(T-U)/PinNamesVar.h @@ -9,23 +9,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c b/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c index 4ca5d02aad..0c56d82b36 100644 --- a/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c +++ b/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051K(6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051K(6-8)T/PinNamesVar.h b/variants/STM32L0xx/L051K(6-8)T/PinNamesVar.h index 6275fc5618..2a0af6630b 100644 --- a/variants/STM32L0xx/L051K(6-8)T/PinNamesVar.h +++ b/variants/STM32L0xx/L051K(6-8)T/PinNamesVar.h @@ -6,26 +6,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c b/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c index e3d4a02418..c5c87c6497 100644 --- a/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c +++ b/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051K(6-8)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051K(6-8)U/PinNamesVar.h b/variants/STM32L0xx/L051K(6-8)U/PinNamesVar.h index 6275fc5618..2a0af6630b 100644 --- a/variants/STM32L0xx/L051K(6-8)U/PinNamesVar.h +++ b/variants/STM32L0xx/L051K(6-8)U/PinNamesVar.h @@ -6,26 +6,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c b/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c index 5d01c29a59..cbce63753e 100644 --- a/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c +++ b/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051R(6-8)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051R(6-8)H/PinNamesVar.h b/variants/STM32L0xx/L051R(6-8)H/PinNamesVar.h index 2ca0c66576..d762849a99 100644 --- a/variants/STM32L0xx/L051R(6-8)H/PinNamesVar.h +++ b/variants/STM32L0xx/L051R(6-8)H/PinNamesVar.h @@ -9,23 +9,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c b/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c index 3160f780ac..11e24f6bb6 100644 --- a/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c +++ b/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051R(6-8)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051R(6-8)T/PinNamesVar.h b/variants/STM32L0xx/L051R(6-8)T/PinNamesVar.h index 2ca0c66576..d762849a99 100644 --- a/variants/STM32L0xx/L051R(6-8)T/PinNamesVar.h +++ b/variants/STM32L0xx/L051R(6-8)T/PinNamesVar.h @@ -9,23 +9,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c b/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c index 8007f7a368..54aa5d1e73 100644 --- a/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051T(6-8)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051T(6-8)Y/PinNamesVar.h b/variants/STM32L0xx/L051T(6-8)Y/PinNamesVar.h index 6275fc5618..2a0af6630b 100644 --- a/variants/STM32L0xx/L051T(6-8)Y/PinNamesVar.h +++ b/variants/STM32L0xx/L051T(6-8)Y/PinNamesVar.h @@ -6,26 +6,5 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c index 806271a7a3..ed80dc9a5c 100644 --- a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L053C(6-8)Tx.xml, STM32L053C(6-8)Ux.xml * STM32L062C8Ux.xml, STM32L063C8Tx.xml * STM32L063C8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PinNamesVar.h b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PinNamesVar.h index c21ba96edd..dbdbfecf84 100644 --- a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PinNamesVar.h +++ b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PinNamesVar.h @@ -9,24 +9,6 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c index 61a1ecddbf..6320a038ea 100644 --- a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c +++ b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052K(6-8)Tx.xml, STM32L062K8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PinNamesVar.h b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PinNamesVar.h index 25f5e063c3..c402affc5a 100644 --- a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PinNamesVar.h +++ b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PinNamesVar.h @@ -6,27 +6,6 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c index d8b2b95020..cadcb804b8 100644 --- a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c +++ b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052K(6-8)Ux.xml, STM32L062K8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PinNamesVar.h b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PinNamesVar.h index 25f5e063c3..c402affc5a 100644 --- a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PinNamesVar.h +++ b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PinNamesVar.h @@ -6,27 +6,6 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c index 7d76f98666..0729c737ca 100644 --- a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c +++ b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052R(6-8)Hx.xml, STM32L053R(6-8)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PinNamesVar.h b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PinNamesVar.h index 3b6bcf29e4..643a4b738d 100644 --- a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PinNamesVar.h +++ b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PinNamesVar.h @@ -9,24 +9,6 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c index 06f8fcaf61..305603f4b4 100644 --- a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c +++ b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L052R(6-8)Tx.xml, STM32L053R(6-8)Tx.xml * STM32L063R8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PinNamesVar.h b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PinNamesVar.h index 3b6bcf29e4..643a4b738d 100644 --- a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PinNamesVar.h +++ b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PinNamesVar.h @@ -9,24 +9,6 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c index c44b3dc908..03099e28e4 100644 --- a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c +++ b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052T(6-8)Yx.xml, STM32L052T8Fx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PinNamesVar.h b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PinNamesVar.h index 25f5e063c3..c402affc5a 100644 --- a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PinNamesVar.h +++ b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PinNamesVar.h @@ -6,27 +6,6 @@ PA_3_ALT1 = PA_3 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c index 0b60ae7926..685e56cfe3 100644 --- a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L071C(B-Z)Tx.xml, STM32L071C(B-Z)Ux.xml * STM32L071C8Tx.xml, STM32L071C8Ux.xml * STM32L081C(B-Z)Tx.xml, STM32L081CZUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PinNamesVar.h b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PinNamesVar.h index ba4da5cae6..06caad5f09 100644 --- a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PinNamesVar.h +++ b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PinNamesVar.h @@ -14,23 +14,5 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c b/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c index a83235fbb3..538c899c78 100644 --- a/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071C(B-Z)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071C(B-Z)Y/PinNamesVar.h b/variants/STM32L0xx/L071C(B-Z)Y/PinNamesVar.h index ba4da5cae6..06caad5f09 100644 --- a/variants/STM32L0xx/L071C(B-Z)Y/PinNamesVar.h +++ b/variants/STM32L0xx/L071C(B-Z)Y/PinNamesVar.h @@ -14,23 +14,5 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c index 44eec62c2e..74b8bd1197 100644 --- a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c +++ b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L071K(B-Z)Ux.xml, STM32L071K8Ux.xml * STM32L081KZUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PinNamesVar.h b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PinNamesVar.h index 6273bea820..6d20c920f8 100644 --- a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PinNamesVar.h +++ b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PinNamesVar.h @@ -11,26 +11,5 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c index bd537ea394..449c30d180 100644 --- a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c +++ b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071K(B-Z)Tx.xml, STM32L081KZTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PinNamesVar.h b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PinNamesVar.h index 6273bea820..6d20c920f8 100644 --- a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PinNamesVar.h +++ b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PinNamesVar.h @@ -11,26 +11,5 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c b/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c index 60798a51a0..b86aa78615 100644 --- a/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c +++ b/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071R(B-Z)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071R(B-Z)H/PinNamesVar.h b/variants/STM32L0xx/L071R(B-Z)H/PinNamesVar.h index 5766717da5..48c6469a80 100644 --- a/variants/STM32L0xx/L071R(B-Z)H/PinNamesVar.h +++ b/variants/STM32L0xx/L071R(B-Z)H/PinNamesVar.h @@ -18,23 +18,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c index e1261912f2..4e79ac886c 100644 --- a/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071R(B-Z)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071R(B-Z)T/PinNamesVar.h b/variants/STM32L0xx/L071R(B-Z)T/PinNamesVar.h index 5766717da5..48c6469a80 100644 --- a/variants/STM32L0xx/L071R(B-Z)T/PinNamesVar.h +++ b/variants/STM32L0xx/L071R(B-Z)T/PinNamesVar.h @@ -18,23 +18,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c index 18def2b3de..45ac624c70 100644 --- a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c +++ b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L071V(B-Z)Ix.xml, STM32L071V(B-Z)Tx.xml * STM32L071V8Ix.xml, STM32L071V8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PinNamesVar.h b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PinNamesVar.h index 8bb7fc6280..c56cb452cb 100644 --- a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PinNamesVar.h +++ b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PinNamesVar.h @@ -25,20 +25,5 @@ PE_6_ALT1 = PE_6 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c index 47ef769e70..b2618547c4 100644 --- a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L073C(B-Z)Tx.xml, STM32L073C(B-Z)Ux.xml * STM32L082CZUx.xml, STM32L083C(B-Z)Tx.xml * STM32L083CZUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PinNamesVar.h b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PinNamesVar.h index f3b2543c1b..3958b75bec 100644 --- a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PinNamesVar.h +++ b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PinNamesVar.h @@ -14,24 +14,6 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c index d916c555f6..14bc265d4b 100644 --- a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c +++ b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L072C(B-Z)Yx.xml, STM32L072CZEx.xml * STM32L073CZYx.xml, STM32L082CZYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PinNamesVar.h b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PinNamesVar.h index f3b2543c1b..3958b75bec 100644 --- a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PinNamesVar.h +++ b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PinNamesVar.h @@ -14,24 +14,6 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c index 23a81af550..e237cc61cb 100644 --- a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L072K(B-Z)Tx.xml, STM32L082K(B-Z)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PinNamesVar.h b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PinNamesVar.h index 686ec4578a..362c2f51f1 100644 --- a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PinNamesVar.h +++ b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PinNamesVar.h @@ -11,27 +11,6 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c index 5f08e18ad1..7d4d6cbeb1 100644 --- a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c +++ b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L072K(B-Z)Ux.xml, STM32L082K(B-Z)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PinNamesVar.h b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PinNamesVar.h index 686ec4578a..362c2f51f1 100644 --- a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PinNamesVar.h +++ b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PinNamesVar.h @@ -11,27 +11,6 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN1 SYS_WKUP1 = PA_0, #endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = NC, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c index efbafc7931..5c28d3c5cc 100644 --- a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c +++ b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L072R(B-Z)Hx.xml, STM32L072R(B-Z)Ix.xml * STM32L073R(B-Z)Hx.xml, STM32L073RZIx.xml * STM32L083R(B-Z)Hx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PinNamesVar.h b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PinNamesVar.h index 9653942764..316c3cffa7 100644 --- a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PinNamesVar.h +++ b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PinNamesVar.h @@ -18,24 +18,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c index ab8dd6931a..014901eef2 100644 --- a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L072R(B-Z)Tx.xml, STM32L073R(B-Z)Tx.xml * STM32L083R(B-Z)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PinNamesVar.h b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PinNamesVar.h index 9653942764..316c3cffa7 100644 --- a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PinNamesVar.h +++ b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PinNamesVar.h @@ -18,24 +18,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c index a7fcd88e4e..e4f6efbb42 100644 --- a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c +++ b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c @@ -17,7 +17,7 @@ * STM32L073V8Ix.xml, STM32L073V8Tx.xml * STM32L083V(B-Z)Ix.xml, STM32L083V(B-Z)Tx.xml * STM32L083V8Ix.xml, STM32L083V8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PinNamesVar.h b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PinNamesVar.h index 80d4da8d6d..270c748a7a 100644 --- a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PinNamesVar.h +++ b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PinNamesVar.h @@ -25,21 +25,6 @@ PE_6_ALT1 = PE_6 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 0dbd4da408c7b66303b30bc52f7eab025edd544c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:38:55 +0100 Subject: [PATCH 050/141] chore(l1): update variant after script update Signed-off-by: Frederic Pillon --- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ------------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ------------------ variants/STM32L1xx/L100RCT/PeripheralPins.c | 2 +- variants/STM32L1xx/L100RCT/PinNamesVar.h | 18 ------------------ .../L151CC(T-U)_L152CC(T-U)/PeripheralPins.c | 2 +- .../L151CC(T-U)_L152CC(T-U)/PinNamesVar.h | 18 ------------------ .../L151QCH_L152QCH_L162QCH/PeripheralPins.c | 2 +- .../L151QCH_L152QCH_L162QCH/PinNamesVar.h | 15 --------------- .../L151QDH_L152QDH_L162QDH/PeripheralPins.c | 2 +- .../L151QDH_L152QDH_L162QDH/PinNamesVar.h | 15 --------------- .../STM32L1xx/L151QEH_L152QEH/PeripheralPins.c | 2 +- .../STM32L1xx/L151QEH_L152QEH/PinNamesVar.h | 15 --------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ------------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ------------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 18 ------------------ .../L151RET_L152RET_L162RET/PeripheralPins.c | 2 +- .../L151RET_L152RET_L162RET/PinNamesVar.h | 18 ------------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 15 --------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 15 --------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 15 --------------- .../L151VDT_L152VDT_L162VDT/PeripheralPins.c | 2 +- .../L151VDT_L152VDT_L162VDT/PinNamesVar.h | 15 --------------- .../L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c | 2 +- .../L151ZCT_L152ZCT_L162ZCT/PinNamesVar.h | 15 --------------- .../L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c | 2 +- .../L151ZDT_L152ZDT_L162ZDT/PinNamesVar.h | 15 --------------- .../L151ZET_L152ZET_L162ZET/PeripheralPins.c | 2 +- .../L151ZET_L152ZET_L162ZET/PinNamesVar.h | 15 --------------- 36 files changed, 18 insertions(+), 312 deletions(-) diff --git a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c index 5244c886cc..2dfd0dd834 100644 --- a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L151C(6-8-B)Ux.xml, STM32L151C(6-8-B)UxA.xml * STM32L152C(6-8-B)Tx.xml, STM32L152C(6-8-B)TxA.xml * STM32L152C(6-8-B)Ux.xml, STM32L152C(6-8-B)UxA.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PinNamesVar.h b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PinNamesVar.h index 282a3b2e1a..37a57a73fc 100644 --- a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PinNamesVar.h +++ b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PinNamesVar.h @@ -13,24 +13,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c index 4a4710023d..ffb69f2ae4 100644 --- a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L100R(8-B)Tx.xml, STM32L100R(8-B)TxA.xml * STM32L151R(6-8-B)Tx.xml, STM32L151R(6-8-B)TxA.xml * STM32L152R(6-8-B)Tx.xml, STM32L152R(6-8-B)TxA.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PinNamesVar.h b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PinNamesVar.h index 282a3b2e1a..37a57a73fc 100644 --- a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PinNamesVar.h +++ b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PinNamesVar.h @@ -13,24 +13,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L100RCT/PeripheralPins.c b/variants/STM32L1xx/L100RCT/PeripheralPins.c index 42c27163b7..082bba10fe 100644 --- a/variants/STM32L1xx/L100RCT/PeripheralPins.c +++ b/variants/STM32L1xx/L100RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L100RCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100RCT/PinNamesVar.h b/variants/STM32L1xx/L100RCT/PinNamesVar.h index 3f3cac2914..7bfc741f6f 100644 --- a/variants/STM32L1xx/L100RCT/PinNamesVar.h +++ b/variants/STM32L1xx/L100RCT/PinNamesVar.h @@ -18,24 +18,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c index 3b41a13de2..4b021d4e7e 100644 --- a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c +++ b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151CCTx.xml, STM32L151CCUx.xml * STM32L152CCTx.xml, STM32L152CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PinNamesVar.h b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PinNamesVar.h index 5aef7b7054..ff5b89dcef 100644 --- a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PinNamesVar.h +++ b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PinNamesVar.h @@ -22,24 +22,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c index 0ec3d9ca8b..0ac03132c6 100644 --- a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151QCHx.xml, STM32L152QCHx.xml * STM32L162QCHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PinNamesVar.h b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PinNamesVar.h index fb1bd5032c..e88359cf5b 100644 --- a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PinNamesVar.h +++ b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PinNamesVar.h @@ -25,21 +25,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c index d8ab40a775..7fe8e8e591 100644 --- a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151QDHx.xml, STM32L152QDHx.xml * STM32L162QDHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PinNamesVar.h b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PinNamesVar.h index b68f1291fa..da27a6fd2d 100644 --- a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PinNamesVar.h +++ b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PinNamesVar.h @@ -27,21 +27,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c b/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c index 9e39b164e2..e40a88cb38 100644 --- a/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L151QEHx.xml, STM32L152QEHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QEH_L152QEH/PinNamesVar.h b/variants/STM32L1xx/L151QEH_L152QEH/PinNamesVar.h index b68f1291fa..da27a6fd2d 100644 --- a/variants/STM32L1xx/L151QEH_L152QEH/PinNamesVar.h +++ b/variants/STM32L1xx/L151QEH_L152QEH/PinNamesVar.h @@ -27,21 +27,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c index f5b70eb152..a340e4e227 100644 --- a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151R(6-8-B)Hx.xml, STM32L151R(6-8-B)HxA.xml * STM32L152R(6-8-B)Hx.xml, STM32L152R(6-8-B)HxA.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PinNamesVar.h b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PinNamesVar.h index 282a3b2e1a..37a57a73fc 100644 --- a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PinNamesVar.h +++ b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PinNamesVar.h @@ -13,24 +13,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c index b8b3110ca6..d35a609fc0 100644 --- a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152RCTx.xml, STM32L152RCTxA.xml * STM32L152UCYx.xml, STM32L162RCTx.xml * STM32L162RCTxA.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PinNamesVar.h b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PinNamesVar.h index 5aef7b7054..ff5b89dcef 100644 --- a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PinNamesVar.h +++ b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PinNamesVar.h @@ -22,24 +22,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c index 9edf98f2b0..4cbb37e256 100644 --- a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c +++ b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L151RDTx.xml, STM32L151RDYx.xml * STM32L152RDTx.xml, STM32L152RDYx.xml * STM32L162RDTx.xml, STM32L162RDYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PinNamesVar.h b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PinNamesVar.h index 2a62930628..fc6f7ebfc4 100644 --- a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PinNamesVar.h +++ b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PinNamesVar.h @@ -24,24 +24,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c b/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c index ca8b1907d7..5c3d70cdcb 100644 --- a/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c +++ b/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151RETx.xml, STM32L152RETx.xml * STM32L162RETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RET_L152RET_L162RET/PinNamesVar.h b/variants/STM32L1xx/L151RET_L152RET_L162RET/PinNamesVar.h index 2a62930628..fc6f7ebfc4 100644 --- a/variants/STM32L1xx/L151RET_L152RET_L162RET/PinNamesVar.h +++ b/variants/STM32L1xx/L151RET_L152RET_L162RET/PinNamesVar.h @@ -24,24 +24,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN2 SYS_WKUP2 = PC_13, #endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c index 1a58a577f8..d2e4c022a7 100644 --- a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L151V(8-B)Tx.xml, STM32L151V(8-B)TxA.xml * STM32L152V(8-B)Hx.xml, STM32L152V(8-B)HxA.xml * STM32L152V(8-B)Tx.xml, STM32L152V(8-B)TxA.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PinNamesVar.h b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PinNamesVar.h index e402998469..d4314b6cd2 100644 --- a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PinNamesVar.h +++ b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PinNamesVar.h @@ -16,21 +16,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c index 55bec47839..b9713f07ee 100644 --- a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152VCTx.xml, STM32L152VCTxA.xml * STM32L162VCHx.xml, STM32L162VCTx.xml * STM32L162VCTxA.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PinNamesVar.h b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PinNamesVar.h index fb1bd5032c..e88359cf5b 100644 --- a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PinNamesVar.h +++ b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PinNamesVar.h @@ -25,21 +25,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c index c336cf52f3..96cc30ad95 100644 --- a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c +++ b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152VDTxX.xml, STM32L152VETx.xml * STM32L152VEYx.xml, STM32L162VDYxX.xml * STM32L162VETx.xml, STM32L162VEYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PinNamesVar.h b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PinNamesVar.h index b68f1291fa..da27a6fd2d 100644 --- a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PinNamesVar.h +++ b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PinNamesVar.h @@ -27,21 +27,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c index 109e04d03f..e7eee924d3 100644 --- a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c +++ b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151VDTx.xml, STM32L152VDTx.xml * STM32L162VDTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PinNamesVar.h b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PinNamesVar.h index b68f1291fa..da27a6fd2d 100644 --- a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PinNamesVar.h +++ b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PinNamesVar.h @@ -27,21 +27,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c index a3872e46a0..7f1c8178de 100644 --- a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZCTx.xml, STM32L152ZCTx.xml * STM32L162ZCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PinNamesVar.h b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PinNamesVar.h index fb1bd5032c..e88359cf5b 100644 --- a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PinNamesVar.h +++ b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PinNamesVar.h @@ -25,21 +25,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c index 6be18ca8f3..2edf74e2bc 100644 --- a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZDTx.xml, STM32L152ZDTx.xml * STM32L162ZDTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PinNamesVar.h b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PinNamesVar.h index b68f1291fa..da27a6fd2d 100644 --- a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PinNamesVar.h +++ b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PinNamesVar.h @@ -27,21 +27,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c index 84691c2569..31a3518ba9 100644 --- a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZETx.xml, STM32L152ZETx.xml * STM32L162ZETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PinNamesVar.h b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PinNamesVar.h index b68f1291fa..da27a6fd2d 100644 --- a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PinNamesVar.h +++ b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PinNamesVar.h @@ -27,21 +27,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PE_6, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 8cff58790346cd862f1383be3e5d02e13cda580f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:39:27 +0100 Subject: [PATCH 051/141] chore(l4): update variant after script update Signed-off-by: Frederic Pillon --- .../L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c | 2 +- .../L412C(8-B)(T-U)_L422CB(T-U)/PinNamesVar.h | 12 ------------ variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c | 2 +- variants/STM32L4xx/L412CB(T-U)xP/PinNamesVar.h | 12 ------------ .../L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c | 2 +- .../L412K(8-B)(T-U)_L422KB(T-U)/PinNamesVar.h | 12 ------------ .../L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c | 2 +- .../L412R(8-B)(I-T)_L422RB(I-T)/PinNamesVar.h | 9 --------- variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c | 2 +- variants/STM32L4xx/L412RB(I-T)xP/PinNamesVar.h | 12 ------------ .../STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c | 2 +- variants/STM32L4xx/L412T(8-B)Y_L422TBY/PinNamesVar.h | 12 ------------ variants/STM32L4xx/L412TBYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L412TBYxP/PinNamesVar.h | 12 ------------ variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c | 2 +- variants/STM32L4xx/L431C(B-C)(T-U)/PinNamesVar.h | 12 ------------ variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c | 2 +- variants/STM32L4xx/L431C(B-C)Y/PinNamesVar.h | 12 ------------ variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c | 2 +- variants/STM32L4xx/L431K(B-C)U/PinNamesVar.h | 12 ------------ .../STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c | 2 +- variants/STM32L4xx/L431R(B-C)(I-T-Y)/PinNamesVar.h | 9 --------- variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c | 2 +- variants/STM32L4xx/L431VC(I-T)/PinNamesVar.h | 9 --------- .../STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c | 2 +- variants/STM32L4xx/L432K(B-C)U_L442KCU/PinNamesVar.h | 12 ------------ .../L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c | 2 +- .../L433C(B-C)(T-U)_L443CC(T-U)/PinNamesVar.h | 12 ------------ .../L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c | 2 +- .../STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PinNamesVar.h | 12 ------------ .../L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c | 2 +- .../L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PinNamesVar.h | 9 --------- variants/STM32L4xx/L433RCTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L433RCTxP/PinNamesVar.h | 12 ------------ .../L433VC(I-T)_L443VC(I-T)/PeripheralPins.c | 2 +- .../STM32L4xx/L433VC(I-T)_L443VC(I-T)/PinNamesVar.h | 9 --------- .../STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c | 2 +- variants/STM32L4xx/L451CCU_L451CE(T-U)/PinNamesVar.h | 12 ------------ .../STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c | 2 +- variants/STM32L4xx/L451R(C-E)(I-T-Y)/PinNamesVar.h | 9 --------- variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c | 2 +- variants/STM32L4xx/L451V(C-E)(I-T)/PinNamesVar.h | 9 --------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 12 ------------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 --------- variants/STM32L4xx/L452RETxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L452RETxP/PinNamesVar.h | 12 ------------ .../L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c | 2 +- .../L452V(C-E)(I-T)_L462VE(I-T)/PinNamesVar.h | 9 --------- variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c | 2 +- variants/STM32L4xx/L471Q(E-G)I/PinNamesVar.h | 9 --------- variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c | 2 +- variants/STM32L4xx/L471R(E-G)T/PinNamesVar.h | 9 --------- variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c | 2 +- variants/STM32L4xx/L471V(E-G)T/PinNamesVar.h | 9 --------- variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c | 2 +- variants/STM32L4xx/L471Z(E-G)(J-T)/PinNamesVar.h | 9 --------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 --------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 --------- .../L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c | 2 +- .../L476J(E-G)Y_L485J(C-E)Y_L486JGY/PinNamesVar.h | 9 --------- variants/STM32L4xx/L476JGYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L476JGYxP/PinNamesVar.h | 12 ------------ variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c | 2 +- variants/STM32L4xx/L476M(E-G)Y/PinNamesVar.h | 9 --------- .../L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c | 2 +- .../L476QEI_L476QGIx(P)_L486QGI/PinNamesVar.h | 9 --------- variants/STM32L4xx/L476VGYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L476VGYxP/PinNamesVar.h | 12 ------------ .../L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c | 2 +- .../L476ZET_L476ZG(J-T)_L486ZGT/PinNamesVar.h | 9 --------- variants/STM32L4xx/L476ZGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L476ZGTxP/PinNamesVar.h | 9 --------- .../STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c | 2 +- variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PinNamesVar.h | 9 --------- .../STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PinNamesVar.h | 9 --------- .../L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c | 2 +- .../L496QEI_L496QGIx(S)_L4A6QGI/PinNamesVar.h | 9 --------- .../STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PinNamesVar.h | 9 --------- .../STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PinNamesVar.h | 9 --------- variants/STM32L4xx/L496RGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496RGTxP/PinNamesVar.h | 12 ------------ .../STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PinNamesVar.h | 9 --------- .../STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PinNamesVar.h | 9 --------- variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c | 2 +- variants/STM32L4xx/L496VGY_L4A6VGY/PinNamesVar.h | 9 --------- .../STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PinNamesVar.h | 12 ------------ variants/STM32L4xx/L496WGYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496WGYxP/PinNamesVar.h | 9 --------- .../STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PinNamesVar.h | 9 --------- .../STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PinNamesVar.h | 9 --------- variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4A6RGTxP/PinNamesVar.h | 12 ------------ .../STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PinNamesVar.h | 9 --------- .../STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PinNamesVar.h | 9 --------- .../L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c | 2 +- .../L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PinNamesVar.h | 12 ------------ .../L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c | 2 +- .../L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PinNamesVar.h | 12 ------------ .../STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PinNamesVar.h | 9 --------- .../L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c | 2 +- .../STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PinNamesVar.h | 9 --------- .../STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PinNamesVar.h | 9 --------- .../STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PinNamesVar.h | 12 ------------ .../STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PinNamesVar.h | 9 --------- .../STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PinNamesVar.h | 9 --------- .../STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PinNamesVar.h | 9 --------- .../STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PinNamesVar.h | 12 ------------ .../STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PinNamesVar.h | 9 --------- .../STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PinNamesVar.h | 9 --------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 --------- .../L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c | 2 +- .../L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PinNamesVar.h | 9 --------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 --------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 --------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 9 --------- variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R5ZITxP/PinNamesVar.h | 9 --------- .../STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PinNamesVar.h | 12 ------------ .../STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PinNamesVar.h | 12 ------------ .../STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PinNamesVar.h | 9 --------- .../STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PinNamesVar.h | 12 ------------ variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R9ZIYxP/PinNamesVar.h | 9 --------- 154 files changed, 77 insertions(+), 854 deletions(-) diff --git a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c index 32c0368502..a48cea41aa 100644 --- a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412C8Tx.xml, STM32L412C8Ux.xml * STM32L412CBTx.xml, STM32L412CBUx.xml * STM32L422CBTx.xml, STM32L422CBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PinNamesVar.h b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PinNamesVar.h index ae03aba5e4..08cd2843c8 100644 --- a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PinNamesVar.h +++ b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PinNamesVar.h @@ -25,18 +25,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c index 7a9ca1db5e..704330631c 100644 --- a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412CBTxP.xml, STM32L412CBUxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412CB(T-U)xP/PinNamesVar.h b/variants/STM32L4xx/L412CB(T-U)xP/PinNamesVar.h index ae03aba5e4..08cd2843c8 100644 --- a/variants/STM32L4xx/L412CB(T-U)xP/PinNamesVar.h +++ b/variants/STM32L4xx/L412CB(T-U)xP/PinNamesVar.h @@ -25,18 +25,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c index d74f23fa9f..120bb50ddb 100644 --- a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412K8Tx.xml, STM32L412K8Ux.xml * STM32L412KBTx.xml, STM32L412KBUx.xml * STM32L422KBTx.xml, STM32L422KBUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PinNamesVar.h b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PinNamesVar.h index 7a9ea449f9..810200afdd 100644 --- a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PinNamesVar.h +++ b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PinNamesVar.h @@ -22,18 +22,6 @@ PB_1_ALT1 = PB_1 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c index d3ed64a6ee..71a83d1bef 100644 --- a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412R8Ix.xml, STM32L412R8Tx.xml * STM32L412RBIx.xml, STM32L412RBTx.xml * STM32L422RBIx.xml, STM32L422RBTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PinNamesVar.h b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PinNamesVar.h index f53e6c12a2..84ff04c18e 100644 --- a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PinNamesVar.h +++ b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PinNamesVar.h @@ -34,15 +34,6 @@ PC_5_ALT1 = PC_5 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c index 443be5aa42..33a4b7f938 100644 --- a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412RBIxP.xml, STM32L412RBTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412RB(I-T)xP/PinNamesVar.h b/variants/STM32L4xx/L412RB(I-T)xP/PinNamesVar.h index 66dac299d1..a78bf0d08d 100644 --- a/variants/STM32L4xx/L412RB(I-T)xP/PinNamesVar.h +++ b/variants/STM32L4xx/L412RB(I-T)xP/PinNamesVar.h @@ -30,18 +30,6 @@ PC_4_ALT1 = PC_4 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c index c56017f824..a8a27f7faa 100644 --- a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c +++ b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L412T8Yx.xml, STM32L412TBYx.xml * STM32L422TBYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PinNamesVar.h b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PinNamesVar.h index 7a9ea449f9..810200afdd 100644 --- a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PinNamesVar.h +++ b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PinNamesVar.h @@ -22,18 +22,6 @@ PB_1_ALT1 = PB_1 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c index 68d4981fbb..b692a26cb1 100644 --- a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412TBYxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412TBYxP/PinNamesVar.h b/variants/STM32L4xx/L412TBYxP/PinNamesVar.h index 7a9ea449f9..810200afdd 100644 --- a/variants/STM32L4xx/L412TBYxP/PinNamesVar.h +++ b/variants/STM32L4xx/L412TBYxP/PinNamesVar.h @@ -22,18 +22,6 @@ PB_1_ALT1 = PB_1 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c index 35a1475199..afe422d2a6 100644 --- a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431C(B-C)Tx.xml, STM32L431C(B-C)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431C(B-C)(T-U)/PinNamesVar.h b/variants/STM32L4xx/L431C(B-C)(T-U)/PinNamesVar.h index aaf98ed4ac..b171989fac 100644 --- a/variants/STM32L4xx/L431C(B-C)(T-U)/PinNamesVar.h +++ b/variants/STM32L4xx/L431C(B-C)(T-U)/PinNamesVar.h @@ -26,17 +26,5 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c index eed840c330..dd90fd55e8 100644 --- a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c +++ b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431C(B-C)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431C(B-C)Y/PinNamesVar.h b/variants/STM32L4xx/L431C(B-C)Y/PinNamesVar.h index aaf98ed4ac..b171989fac 100644 --- a/variants/STM32L4xx/L431C(B-C)Y/PinNamesVar.h +++ b/variants/STM32L4xx/L431C(B-C)Y/PinNamesVar.h @@ -26,17 +26,5 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c index 5f820d224f..acf27c2062 100644 --- a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c +++ b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431K(B-C)Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431K(B-C)U/PinNamesVar.h b/variants/STM32L4xx/L431K(B-C)U/PinNamesVar.h index 847c7417bc..ba7ae4861f 100644 --- a/variants/STM32L4xx/L431K(B-C)U/PinNamesVar.h +++ b/variants/STM32L4xx/L431K(B-C)U/PinNamesVar.h @@ -21,17 +21,5 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c index fb48a85477..8099a8969f 100644 --- a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L431R(B-C)Ix.xml, STM32L431R(B-C)Tx.xml * STM32L431R(B-C)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PinNamesVar.h b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PinNamesVar.h index 6189b8f2b1..c9fba61bb1 100644 --- a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PinNamesVar.h +++ b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PinNamesVar.h @@ -29,14 +29,5 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c index c43f5de2e6..7be7497dd6 100644 --- a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431VCIx.xml, STM32L431VCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431VC(I-T)/PinNamesVar.h b/variants/STM32L4xx/L431VC(I-T)/PinNamesVar.h index 4838dbebf0..daf39b189e 100644 --- a/variants/STM32L4xx/L431VC(I-T)/PinNamesVar.h +++ b/variants/STM32L4xx/L431VC(I-T)/PinNamesVar.h @@ -29,14 +29,5 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c index 98a8727910..1e6706a553 100644 --- a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c +++ b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L432K(B-C)Ux.xml, STM32L442KCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PinNamesVar.h b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PinNamesVar.h index e4df642567..97af10ac63 100644 --- a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PinNamesVar.h +++ b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PinNamesVar.h @@ -21,18 +21,6 @@ PB_5_ALT1 = PB_5 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c index a15f090088..ae775b6d1e 100644 --- a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433C(B-C)Tx.xml, STM32L433C(B-C)Ux.xml * STM32L443CCTx.xml, STM32L443CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PinNamesVar.h b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PinNamesVar.h index 0993a84af3..b52fd18e7e 100644 --- a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PinNamesVar.h +++ b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PinNamesVar.h @@ -26,18 +26,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c index e67dc95d6b..9918b91507 100644 --- a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433C(B-C)Yx.xml, STM32L443CCFx.xml * STM32L443CCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PinNamesVar.h b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PinNamesVar.h index 0993a84af3..b52fd18e7e 100644 --- a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PinNamesVar.h +++ b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PinNamesVar.h @@ -26,18 +26,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c index a6d03e307d..8df89ea9bc 100644 --- a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L433R(B-C)Ix.xml, STM32L433R(B-C)Tx.xml * STM32L433R(B-C)Yx.xml, STM32L443RCIx.xml * STM32L443RCTx.xml, STM32L443RCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PinNamesVar.h b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PinNamesVar.h index ed142d6604..4c998e42dd 100644 --- a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PinNamesVar.h +++ b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PinNamesVar.h @@ -29,15 +29,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c index 6e93047656..f2c168578e 100644 --- a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L433RCTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433RCTxP/PinNamesVar.h b/variants/STM32L4xx/L433RCTxP/PinNamesVar.h index 303e24ed1a..b6532f4ae7 100644 --- a/variants/STM32L4xx/L433RCTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L433RCTxP/PinNamesVar.h @@ -26,18 +26,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c index 348b921d56..a287bacc66 100644 --- a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433VCIx.xml, STM32L433VCTx.xml * STM32L443VCIx.xml, STM32L443VCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PinNamesVar.h b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PinNamesVar.h index 201a42bd39..8850f60ae4 100644 --- a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PinNamesVar.h +++ b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PinNamesVar.h @@ -29,15 +29,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c index 621665b849..ef0e9d309b 100644 --- a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L451C(C-E)Ux.xml, STM32L451CETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PinNamesVar.h b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PinNamesVar.h index 5b2aa7df79..ddd18dc478 100644 --- a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PinNamesVar.h +++ b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PinNamesVar.h @@ -32,17 +32,5 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c index ba39a04354..796530527a 100644 --- a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L451R(C-E)Ix.xml, STM32L451R(C-E)Tx.xml * STM32L451R(C-E)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PinNamesVar.h b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PinNamesVar.h index bbf497dbb2..06de37f850 100644 --- a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PinNamesVar.h +++ b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PinNamesVar.h @@ -39,14 +39,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c index 6e34d200e4..ba9228c715 100644 --- a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L451V(C-E)Ix.xml, STM32L451V(C-E)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451V(C-E)(I-T)/PinNamesVar.h b/variants/STM32L4xx/L451V(C-E)(I-T)/PinNamesVar.h index 39e1720b3c..af5c23683f 100644 --- a/variants/STM32L4xx/L451V(C-E)(I-T)/PinNamesVar.h +++ b/variants/STM32L4xx/L451V(C-E)(I-T)/PinNamesVar.h @@ -39,14 +39,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c index 7ad9a1acab..897b01cb0a 100644 --- a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L452C(C-E)Ux.xml, STM32L452CETx.xml * STM32L452CETxP.xml, STM32L462CETx.xml * STM32L462CEUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PinNamesVar.h b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PinNamesVar.h index 3e5b63c663..527039a9e9 100644 --- a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PinNamesVar.h +++ b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PinNamesVar.h @@ -32,18 +32,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c index 4437d82ded..7dc2c3071f 100644 --- a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L452R(C-E)Yx.xml, STM32L452REYxP.xml * STM32L462REIx.xml, STM32L462RETx.xml * STM32L462REYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PinNamesVar.h b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PinNamesVar.h index 606ac8931b..bb9e438799 100644 --- a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PinNamesVar.h +++ b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PinNamesVar.h @@ -39,15 +39,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L452RETxP/PeripheralPins.c b/variants/STM32L4xx/L452RETxP/PeripheralPins.c index 281aaedd5c..930e406bdd 100644 --- a/variants/STM32L4xx/L452RETxP/PeripheralPins.c +++ b/variants/STM32L4xx/L452RETxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L452RETxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452RETxP/PinNamesVar.h b/variants/STM32L4xx/L452RETxP/PinNamesVar.h index 43bb220f82..5ec2c898dd 100644 --- a/variants/STM32L4xx/L452RETxP/PinNamesVar.h +++ b/variants/STM32L4xx/L452RETxP/PinNamesVar.h @@ -36,18 +36,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c index 864f1d706f..d0b11dffd6 100644 --- a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L452V(C-E)Ix.xml, STM32L452V(C-E)Tx.xml * STM32L462VEIx.xml, STM32L462VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PinNamesVar.h b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PinNamesVar.h index f34cff687c..b29bb74d25 100644 --- a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PinNamesVar.h +++ b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PinNamesVar.h @@ -39,15 +39,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c index 3ff22d95a2..b2cbcb449f 100644 --- a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c +++ b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471Q(E-G)Ix.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471Q(E-G)I/PinNamesVar.h b/variants/STM32L4xx/L471Q(E-G)I/PinNamesVar.h index f668d83737..f3b1a04913 100644 --- a/variants/STM32L4xx/L471Q(E-G)I/PinNamesVar.h +++ b/variants/STM32L4xx/L471Q(E-G)I/PinNamesVar.h @@ -62,14 +62,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c index 8171795b89..35e6e2031e 100644 --- a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c +++ b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471R(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471R(E-G)T/PinNamesVar.h b/variants/STM32L4xx/L471R(E-G)T/PinNamesVar.h index bbc9c27b12..fdc8eda833 100644 --- a/variants/STM32L4xx/L471R(E-G)T/PinNamesVar.h +++ b/variants/STM32L4xx/L471R(E-G)T/PinNamesVar.h @@ -62,14 +62,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c index 8b1f1c9435..cd22092599 100644 --- a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c +++ b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471V(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471V(E-G)T/PinNamesVar.h b/variants/STM32L4xx/L471V(E-G)T/PinNamesVar.h index f668d83737..f3b1a04913 100644 --- a/variants/STM32L4xx/L471V(E-G)T/PinNamesVar.h +++ b/variants/STM32L4xx/L471V(E-G)T/PinNamesVar.h @@ -62,14 +62,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c index 78c4c5b702..9142d477cb 100644 --- a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471Z(E-G)Jx.xml, STM32L471Z(E-G)Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471Z(E-G)(J-T)/PinNamesVar.h b/variants/STM32L4xx/L471Z(E-G)(J-T)/PinNamesVar.h index 0d82226003..c2a71edfb9 100644 --- a/variants/STM32L4xx/L471Z(E-G)(J-T)/PinNamesVar.h +++ b/variants/STM32L4xx/L471Z(E-G)(J-T)/PinNamesVar.h @@ -63,14 +63,5 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c index fa069681cb..9a1fc26e39 100644 --- a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L475R(C-E-G)Tx.xml, STM32L476R(C-E-G)Tx.xml * STM32L486RGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PinNamesVar.h b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PinNamesVar.h index e94e148697..a8ed860281 100644 --- a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PinNamesVar.h +++ b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PinNamesVar.h @@ -62,15 +62,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c index 32505b71b8..e92d96f36a 100644 --- a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L475V(C-E-G)Tx.xml, STM32L476V(C-E-G)Tx.xml * STM32L486VGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PinNamesVar.h b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PinNamesVar.h index b694eb4d56..cb3726623c 100644 --- a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PinNamesVar.h +++ b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PinNamesVar.h @@ -62,15 +62,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c index 5b98653bc8..920a811b9c 100644 --- a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c +++ b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476J(E-G)Yx.xml, STM32L485J(C-E)Yx.xml * STM32L486JGYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PinNamesVar.h b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PinNamesVar.h index e94e148697..a8ed860281 100644 --- a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PinNamesVar.h +++ b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PinNamesVar.h @@ -62,15 +62,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c index 3e5893767b..847a9c7f09 100644 --- a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476JGYxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476JGYxP/PinNamesVar.h b/variants/STM32L4xx/L476JGYxP/PinNamesVar.h index bea9d510f7..c54f481ba0 100644 --- a/variants/STM32L4xx/L476JGYxP/PinNamesVar.h +++ b/variants/STM32L4xx/L476JGYxP/PinNamesVar.h @@ -58,18 +58,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c index e9756bee9d..631bcc6d26 100644 --- a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c +++ b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476M(E-G)Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476M(E-G)Y/PinNamesVar.h b/variants/STM32L4xx/L476M(E-G)Y/PinNamesVar.h index e94e148697..a8ed860281 100644 --- a/variants/STM32L4xx/L476M(E-G)Y/PinNamesVar.h +++ b/variants/STM32L4xx/L476M(E-G)Y/PinNamesVar.h @@ -62,15 +62,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c index de839cd9b8..93730eac83 100644 --- a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476Q(E-G)Ix.xml, STM32L476QGIxP.xml * STM32L486QGIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PinNamesVar.h b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PinNamesVar.h index b694eb4d56..cb3726623c 100644 --- a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PinNamesVar.h +++ b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PinNamesVar.h @@ -62,15 +62,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c index 84f2ec18ab..90a11406b3 100644 --- a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476VGYxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476VGYxP/PinNamesVar.h b/variants/STM32L4xx/L476VGYxP/PinNamesVar.h index bea9d510f7..c54f481ba0 100644 --- a/variants/STM32L4xx/L476VGYxP/PinNamesVar.h +++ b/variants/STM32L4xx/L476VGYxP/PinNamesVar.h @@ -58,18 +58,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c index 46ec52fccb..4619ca72d0 100644 --- a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476Z(E-G)Tx.xml, STM32L476ZGJx.xml * STM32L486ZGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PinNamesVar.h b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PinNamesVar.h index 659a9c42fe..ff13e6697c 100644 --- a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PinNamesVar.h +++ b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PinNamesVar.h @@ -63,15 +63,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c index eb7dcb2323..ce39674010 100644 --- a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476ZGTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476ZGTxP/PinNamesVar.h b/variants/STM32L4xx/L476ZGTxP/PinNamesVar.h index 659a9c42fe..ff13e6697c 100644 --- a/variants/STM32L4xx/L476ZGTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L476ZGTxP/PinNamesVar.h @@ -63,15 +63,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c index f0b05b6511..82641d29db 100644 --- a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c +++ b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496A(E-G)Ix.xml, STM32L4A6AGIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PinNamesVar.h b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PinNamesVar.h index cc23df3a50..38ec3aca48 100644 --- a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PinNamesVar.h +++ b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PinNamesVar.h @@ -64,15 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c index 00e7b91e0c..f579c55d64 100644 --- a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496AGIxP.xml, STM32L4A6AGIxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PinNamesVar.h b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PinNamesVar.h index cc23df3a50..38ec3aca48 100644 --- a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PinNamesVar.h +++ b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PinNamesVar.h @@ -64,15 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c index eb39c72dff..d32d3dc23e 100644 --- a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L496Q(E-G)Ix.xml, STM32L496QGIxS.xml * STM32L4A6QGIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PinNamesVar.h b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PinNamesVar.h index cc23df3a50..38ec3aca48 100644 --- a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PinNamesVar.h +++ b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PinNamesVar.h @@ -64,15 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c index 4aa9d55c19..4e3ee8a34d 100644 --- a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496QGIxP.xml, STM32L4A6QGIxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PinNamesVar.h b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PinNamesVar.h index 35233bfab8..d2c0d91329 100644 --- a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PinNamesVar.h +++ b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PinNamesVar.h @@ -63,15 +63,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c index 374c3e6b13..25c4ed143f 100644 --- a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496R(E-G)Tx.xml, STM32L4A6RGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PinNamesVar.h b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PinNamesVar.h index 9f96b9d025..c3c4e41825 100644 --- a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PinNamesVar.h +++ b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PinNamesVar.h @@ -64,15 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c index 4f0f68850a..9c0dd2d685 100644 --- a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496RGTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496RGTxP/PinNamesVar.h b/variants/STM32L4xx/L496RGTxP/PinNamesVar.h index 631236b94c..94c9e17db1 100644 --- a/variants/STM32L4xx/L496RGTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L496RGTxP/PinNamesVar.h @@ -60,18 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c index 1320e982e8..c2a61a2ca7 100644 --- a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496V(E-G)Tx.xml, STM32L4A6VGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PinNamesVar.h b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PinNamesVar.h index cc23df3a50..38ec3aca48 100644 --- a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PinNamesVar.h +++ b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PinNamesVar.h @@ -64,15 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c index 89cc39ed3b..2e54b11252 100644 --- a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGTxP.xml, STM32L4A6VGTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PinNamesVar.h b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PinNamesVar.h index 35233bfab8..d2c0d91329 100644 --- a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PinNamesVar.h @@ -63,15 +63,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c index 879c564a55..80c4ea2281 100644 --- a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGYx.xml, STM32L4A6VGYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGY_L4A6VGY/PinNamesVar.h b/variants/STM32L4xx/L496VGY_L4A6VGY/PinNamesVar.h index cc23df3a50..38ec3aca48 100644 --- a/variants/STM32L4xx/L496VGY_L4A6VGY/PinNamesVar.h +++ b/variants/STM32L4xx/L496VGY_L4A6VGY/PinNamesVar.h @@ -64,15 +64,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c index 4684de3c00..0f4fd68b2f 100644 --- a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGYxP.xml, STM32L4A6VGYxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PinNamesVar.h b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PinNamesVar.h index e18da4c0db..438415fc9d 100644 --- a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PinNamesVar.h +++ b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PinNamesVar.h @@ -60,18 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c index 66c8a33130..64f80cc05d 100644 --- a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496WGYxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496WGYxP/PinNamesVar.h b/variants/STM32L4xx/L496WGYxP/PinNamesVar.h index b391aa6e8f..a0b71a8127 100644 --- a/variants/STM32L4xx/L496WGYxP/PinNamesVar.h +++ b/variants/STM32L4xx/L496WGYxP/PinNamesVar.h @@ -61,15 +61,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c index c575098073..336fd023b0 100644 --- a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496Z(E-G)Tx.xml, STM32L4A6ZGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PinNamesVar.h b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PinNamesVar.h index 6a35144cef..2697d90bbb 100644 --- a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PinNamesVar.h +++ b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PinNamesVar.h @@ -65,15 +65,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c index 595c7221ed..8930721675 100644 --- a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496ZGTxP.xml, STM32L4A6ZGTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PinNamesVar.h b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PinNamesVar.h index 139433515e..253e8578b9 100644 --- a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PinNamesVar.h @@ -64,15 +64,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c index 112ad590ae..033af3726c 100644 --- a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4A6RGTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4A6RGTxP/PinNamesVar.h b/variants/STM32L4xx/L4A6RGTxP/PinNamesVar.h index 631236b94c..94c9e17db1 100644 --- a/variants/STM32L4xx/L4A6RGTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4A6RGTxP/PinNamesVar.h @@ -60,18 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c index 8ab93bbfe8..fbe7221175 100644 --- a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5A(G-E)Ix.xml, STM32L4Q5AGIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PinNamesVar.h b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PinNamesVar.h index 642cc5173e..65470a636f 100644 --- a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c index 86e3140be9..3c36b33dd9 100644 --- a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5AGIxP.xml, STM32L4Q5AGIxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PinNamesVar.h b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PinNamesVar.h index 642cc5173e..65470a636f 100644 --- a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c index 44e9c664b2..5afdc5a8a2 100644 --- a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5C(G-E)Tx.xml, STM32L4P5C(G-E)Ux.xml * STM32L4Q5CGTx.xml, STM32L4Q5CGUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PinNamesVar.h b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PinNamesVar.h index d8afa27f9b..c4336b877d 100644 --- a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PinNamesVar.h @@ -45,18 +45,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c index 9ff6270da4..a6ada97910 100644 --- a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5CGTxP.xml, STM32L4P5CGUxP.xml * STM32L4Q5CGTxP.xml, STM32L4Q5CGUxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PinNamesVar.h b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PinNamesVar.h index 46f31a08b5..655bfd7374 100644 --- a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PinNamesVar.h @@ -43,18 +43,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c index 5e2568e0cb..1d99c9b6a7 100644 --- a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5Q(G-E)Ix.xml, STM32L4Q5QGIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PinNamesVar.h b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PinNamesVar.h index 642cc5173e..65470a636f 100644 --- a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c index be7a4009c1..8daca3f310 100644 --- a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5QGIxP.xml, STM32L4P5QGIxS.xml * STM32L4Q5QGIxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PinNamesVar.h b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PinNamesVar.h index 58efc1212b..86cb33d951 100644 --- a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PinNamesVar.h @@ -59,15 +59,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c index 195f2e1871..19f64b8ba2 100644 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5R(G-E)Tx.xml, STM32L4Q5RGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PinNamesVar.h b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PinNamesVar.h index 0e90677743..14383c6f50 100644 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c index c213d75fbd..d9cf360d2e 100644 --- a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5RGTxP.xml, STM32L4Q5RGTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PinNamesVar.h b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PinNamesVar.h index b8c0989aa4..943b9ea01d 100644 --- a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PinNamesVar.h @@ -56,18 +56,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c index a4c1b94421..402fbb5824 100644 --- a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5V(G-E)Tx.xml, STM32L4Q5VGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PinNamesVar.h b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PinNamesVar.h index 642cc5173e..65470a636f 100644 --- a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c index 06e19e0de4..34ed182e83 100644 --- a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5V(G-E)Yx.xml, STM32L4Q5VGYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PinNamesVar.h b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PinNamesVar.h index 642cc5173e..65470a636f 100644 --- a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c index 23c3e6ee55..6545ee685f 100644 --- a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5VGTxP.xml, STM32L4Q5VGTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PinNamesVar.h b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PinNamesVar.h index 58efc1212b..86cb33d951 100644 --- a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PinNamesVar.h @@ -59,15 +59,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c index ab1bf1d52b..4cd2432cb2 100644 --- a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5VGYxP.xml, STM32L4Q5VGYxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PinNamesVar.h b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PinNamesVar.h index 47be5710d3..c7da6d24ef 100644 --- a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PinNamesVar.h @@ -56,18 +56,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c index 1ec9fbfce6..bce63abb73 100644 --- a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5Z(G-E)Tx.xml, STM32L4Q5ZGTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PinNamesVar.h b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PinNamesVar.h index ae9c148695..58d5632a23 100644 --- a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PinNamesVar.h @@ -61,15 +61,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c index 0c1535cedd..d2bb1dfb7f 100644 --- a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5ZGTxP.xml, STM32L4Q5ZGTxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PinNamesVar.h b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PinNamesVar.h index 887753b71d..dcbac22bb3 100644 --- a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PinNamesVar.h @@ -60,15 +60,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c index f28dab5f87..64d167a721 100644 --- a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L4R5A(G-I)Ix.xml, STM32L4R5AIIxP.xml * STM32L4R7AIIx.xml, STM32L4S5AIIx.xml * STM32L4S7AIIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PinNamesVar.h b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PinNamesVar.h index e5251add7d..9a58a37b23 100644 --- a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PinNamesVar.h +++ b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PinNamesVar.h @@ -54,15 +54,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c index beb0ba8071..acb5398be3 100644 --- a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Q(G-I)Ix.xml, STM32L4R5QGIxS.xml * STM32L4R5QIIxP.xml, STM32L4S5QIIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PinNamesVar.h b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PinNamesVar.h index e5251add7d..9a58a37b23 100644 --- a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PinNamesVar.h +++ b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PinNamesVar.h @@ -54,15 +54,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c index ecb6d534c7..87a7f471af 100644 --- a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5V(G-I)Tx.xml, STM32L4R7VITx.xml * STM32L4S5VITx.xml, STM32L4S7VITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PinNamesVar.h b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PinNamesVar.h index e5251add7d..9a58a37b23 100644 --- a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PinNamesVar.h +++ b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PinNamesVar.h @@ -54,15 +54,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c index 63846e250b..c66c8c2917 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Z(G-I)Tx.xml, STM32L4R7ZITx.xml * STM32L4S5ZITx.xml, STM32L4S7ZITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PinNamesVar.h b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PinNamesVar.h index 777288883b..3ac63d543a 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PinNamesVar.h +++ b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PinNamesVar.h @@ -55,15 +55,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c index a1d4368fc1..d7deadcda2 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Z(G-I)Yx.xml, STM32L4R9Z(G-I)Yx.xml * STM32L4S5ZIYx.xml, STM32L4S9ZIYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PinNamesVar.h b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PinNamesVar.h index e5251add7d..9a58a37b23 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PinNamesVar.h +++ b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PinNamesVar.h @@ -54,15 +54,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c index e14b3926d1..673576cce7 100644 --- a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R5ZITxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5ZITxP/PinNamesVar.h b/variants/STM32L4xx/L4R5ZITxP/PinNamesVar.h index e20355f757..5334eee104 100644 --- a/variants/STM32L4xx/L4R5ZITxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4R5ZITxP/PinNamesVar.h @@ -54,15 +54,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c index 668d114dd6..152c92e702 100644 --- a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9A(G-I)Ix.xml, STM32L4S9AIIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PinNamesVar.h b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PinNamesVar.h index 4f0c235f4f..e1464461fa 100644 --- a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PinNamesVar.h +++ b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PinNamesVar.h @@ -51,18 +51,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c index e4ad7cfd7c..602a5d59bf 100644 --- a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9V(G-I)Tx.xml, STM32L4S9VITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PinNamesVar.h b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PinNamesVar.h index 4f0c235f4f..e1464461fa 100644 --- a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PinNamesVar.h +++ b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PinNamesVar.h @@ -51,18 +51,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c index 7245c19cd0..293cf4fdde 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9Z(G-I)Jx.xml, STM32L4S9ZIJx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PinNamesVar.h b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PinNamesVar.h index 777288883b..3ac63d543a 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PinNamesVar.h +++ b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PinNamesVar.h @@ -55,15 +55,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c index b2510e97bb..b6ec83853b 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9Z(G-I)Tx.xml, STM32L4S9ZITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PinNamesVar.h b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PinNamesVar.h index 4f0c235f4f..e1464461fa 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PinNamesVar.h +++ b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PinNamesVar.h @@ -51,18 +51,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c index 3b8ee79403..ca18124f24 100644 --- a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9ZIYxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9ZIYxP/PinNamesVar.h b/variants/STM32L4xx/L4R9ZIYxP/PinNamesVar.h index 1d9c04c16a..ad08ff9798 100644 --- a/variants/STM32L4xx/L4R9ZIYxP/PinNamesVar.h +++ b/variants/STM32L4xx/L4R9ZIYxP/PinNamesVar.h @@ -53,15 +53,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 254e786e441c4250c4cb0b27a9df384ab2b59a6b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:39:37 +0100 Subject: [PATCH 052/141] chore(l5): update variant after script update Signed-off-by: Frederic Pillon --- .../L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c | 2 +- .../L552C(C-E)(T-U)_L562CE(T-U)/PinNamesVar.h | 12 ------------ .../L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c | 2 +- .../L552CE(T-U)xP_L562CE(T-U)xP/PinNamesVar.h | 12 ------------ .../STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c | 2 +- variants/STM32L5xx/L552MEYxP_L562MEYxP/PinNamesVar.h | 12 ------------ .../STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c | 2 +- variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PinNamesVar.h | 12 ------------ .../L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c | 2 +- .../STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PinNamesVar.h | 9 --------- variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c | 2 +- variants/STM32L5xx/L552QEI_L562QEI/PinNamesVar.h | 9 --------- .../STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c | 2 +- variants/STM32L5xx/L552QEIxP_L562QEIxP/PinNamesVar.h | 9 --------- .../STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c | 2 +- variants/STM32L5xx/L552R(C-E)T_L562RET/PinNamesVar.h | 9 --------- .../STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c | 2 +- variants/STM32L5xx/L552RETxP_L562RETxP/PinNamesVar.h | 12 ------------ .../STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c | 2 +- variants/STM32L5xx/L552RETxQ_L562RETxQ/PinNamesVar.h | 12 ------------ .../L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c | 2 +- .../STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PinNamesVar.h | 12 ------------ variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c | 2 +- variants/STM32L5xx/L552VET_L562VET/PinNamesVar.h | 9 --------- .../L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c | 2 +- .../STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PinNamesVar.h | 12 ------------ variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c | 2 +- variants/STM32L5xx/L552ZET_L562ZET/PinNamesVar.h | 9 --------- 28 files changed, 14 insertions(+), 164 deletions(-) diff --git a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c index 9e0538f70d..348bcb3a14 100644 --- a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c +++ b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L552C(C-E)Tx.xml, STM32L552C(C-E)Ux.xml * STM32L562CETx.xml, STM32L562CEUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PinNamesVar.h b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PinNamesVar.h index 75534daf8a..a2812a7720 100644 --- a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PinNamesVar.h +++ b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PinNamesVar.h @@ -45,18 +45,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c index a992ddae2c..d385c92dba 100644 --- a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c +++ b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L552CETxP.xml, STM32L552CEUxP.xml * STM32L562CETxP.xml, STM32L562CEUxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PinNamesVar.h b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PinNamesVar.h index 3b96137f37..f014212a11 100644 --- a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PinNamesVar.h +++ b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PinNamesVar.h @@ -43,18 +43,6 @@ PB_15_ALT2 = PB_15 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c index bd7dd347c9..b3bc69befe 100644 --- a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552MEYxP.xml, STM32L562MEYxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PinNamesVar.h b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PinNamesVar.h index c27b44ceb7..771dd484bd 100644 --- a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PinNamesVar.h +++ b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PinNamesVar.h @@ -56,18 +56,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c index 497d4a18a9..86f38b9c23 100644 --- a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552MEYxQ.xml, STM32L562MEYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PinNamesVar.h b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PinNamesVar.h index c27b44ceb7..771dd484bd 100644 --- a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PinNamesVar.h +++ b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PinNamesVar.h @@ -56,18 +56,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c index 01b5783529..4984e835a8 100644 --- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552Q(C-E)IxQ.xml, STM32L562QEIxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PinNamesVar.h b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PinNamesVar.h index 9c4200b24d..34f47f0a93 100644 --- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PinNamesVar.h +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c b/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c index f81c552721..8224dba49d 100644 --- a/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c +++ b/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552QEIx.xml, STM32L562QEIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552QEI_L562QEI/PinNamesVar.h b/variants/STM32L5xx/L552QEI_L562QEI/PinNamesVar.h index 9c4200b24d..34f47f0a93 100644 --- a/variants/STM32L5xx/L552QEI_L562QEI/PinNamesVar.h +++ b/variants/STM32L5xx/L552QEI_L562QEI/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c index 95cd4245c0..876051e18e 100644 --- a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552QEIxP.xml, STM32L562QEIxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PinNamesVar.h b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PinNamesVar.h index 9c4200b24d..34f47f0a93 100644 --- a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PinNamesVar.h +++ b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c b/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c index 908789b131..6a01df847d 100644 --- a/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c +++ b/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552R(C-E)Tx.xml, STM32L562RETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552R(C-E)T_L562RET/PinNamesVar.h b/variants/STM32L5xx/L552R(C-E)T_L562RET/PinNamesVar.h index bf5d70dd70..860be13882 100644 --- a/variants/STM32L5xx/L552R(C-E)T_L562RET/PinNamesVar.h +++ b/variants/STM32L5xx/L552R(C-E)T_L562RET/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c b/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c index fbf9fe7764..4118da08a2 100644 --- a/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552RETxP.xml, STM32L562RETxP.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552RETxP_L562RETxP/PinNamesVar.h b/variants/STM32L5xx/L552RETxP_L562RETxP/PinNamesVar.h index c27b44ceb7..771dd484bd 100644 --- a/variants/STM32L5xx/L552RETxP_L562RETxP/PinNamesVar.h +++ b/variants/STM32L5xx/L552RETxP_L562RETxP/PinNamesVar.h @@ -56,18 +56,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c index 79bd1e20fe..b88baf7c16 100644 --- a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552RETxQ.xml, STM32L562RETxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PinNamesVar.h b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PinNamesVar.h index 23635b1b63..6eeaa5db17 100644 --- a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PinNamesVar.h +++ b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PinNamesVar.h @@ -53,18 +53,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c index f3896f1a9e..968126b7c4 100644 --- a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552V(C-E)TxQ.xml, STM32L562VETxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PinNamesVar.h b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PinNamesVar.h index 98383a4d7c..f400b7f8db 100644 --- a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PinNamesVar.h +++ b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PinNamesVar.h @@ -55,18 +55,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c b/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c index a256d278a6..b29e1c1d3f 100644 --- a/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c +++ b/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552VETx.xml, STM32L562VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552VET_L562VET/PinNamesVar.h b/variants/STM32L5xx/L552VET_L562VET/PinNamesVar.h index 9c4200b24d..34f47f0a93 100644 --- a/variants/STM32L5xx/L552VET_L562VET/PinNamesVar.h +++ b/variants/STM32L5xx/L552VET_L562VET/PinNamesVar.h @@ -60,15 +60,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c index 20463beee5..524fd8eb24 100644 --- a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552Z(C-E)TxQ.xml, STM32L562ZETxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PinNamesVar.h b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PinNamesVar.h index 2851eeeddf..575b75b1ac 100644 --- a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PinNamesVar.h +++ b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PinNamesVar.h @@ -56,18 +56,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c b/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c index 618f9723d9..4a289a957d 100644 --- a/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c +++ b/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552ZETx.xml, STM32L562ZETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552ZET_L562ZET/PinNamesVar.h b/variants/STM32L5xx/L552ZET_L562ZET/PinNamesVar.h index 4823d2aa4c..87778b5eaa 100644 --- a/variants/STM32L5xx/L552ZET_L562ZET/PinNamesVar.h +++ b/variants/STM32L5xx/L552ZET_L562ZET/PinNamesVar.h @@ -61,15 +61,6 @@ PF_9_ALT1 = PF_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 444152f43daf0ee1759d7f71048db680bb1b2056 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:39:52 +0100 Subject: [PATCH 053/141] chore(mp1): update variant after script update Signed-off-by: Frederic Pillon --- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c | 2 +- .../MP151AAA_MP151CAA_MP151DAA_MP151FAA/PinNamesVar.h | 6 ------ .../MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c | 2 +- .../MP151AAC_MP151CAC_MP151DAC_MP151FAC/PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 6 ------ 12 files changed, 6 insertions(+), 42 deletions(-) diff --git a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c index 1f32314791..d0273077cb 100644 --- a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP151CABx.xml, STM32MP151CADx.xml * STM32MP151DABx.xml, STM32MP151DADx.xml * STM32MP151FABx.xml, STM32MP151FADx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PinNamesVar.h b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PinNamesVar.h index 122c76a6cd..3561e4f7b9 100644 --- a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PinNamesVar.h +++ b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PinNamesVar.h @@ -81,12 +81,6 @@ PG_11_ALT1 = PG_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c index 3bc52c553d..1cde0e86c6 100644 --- a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32MP151AAAx.xml, STM32MP151CAAx.xml * STM32MP151DAAx.xml, STM32MP151FAAx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PinNamesVar.h b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PinNamesVar.h index 7e673544de..9b94d5a049 100644 --- a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PinNamesVar.h +++ b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PinNamesVar.h @@ -111,12 +111,6 @@ PZ_7_ALT1 = PZ_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c index 588407ecb7..1330b70dc3 100644 --- a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32MP151AACx.xml, STM32MP151CACx.xml * STM32MP151DACx.xml, STM32MP151FACx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PinNamesVar.h b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PinNamesVar.h index 2fbc6960f4..abe8f59652 100644 --- a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PinNamesVar.h +++ b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PinNamesVar.h @@ -105,12 +105,6 @@ PZ_7_ALT1 = PZ_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c index 22792b3748..2099284bb7 100644 --- a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c @@ -19,7 +19,7 @@ * STM32MP157CABx.xml, STM32MP157CADx.xml * STM32MP157DABx.xml, STM32MP157DADx.xml * STM32MP157FABx.xml, STM32MP157FADx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PinNamesVar.h b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PinNamesVar.h index 122c76a6cd..3561e4f7b9 100644 --- a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PinNamesVar.h +++ b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PinNamesVar.h @@ -81,12 +81,6 @@ PG_11_ALT1 = PG_11 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c index 47329f2e85..9831f5202b 100644 --- a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP153DAAx.xml, STM32MP153FAAx.xml * STM32MP157AAAx.xml, STM32MP157CAAx.xml * STM32MP157DAAx.xml, STM32MP157FAAx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PinNamesVar.h b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PinNamesVar.h index 7e673544de..9b94d5a049 100644 --- a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PinNamesVar.h +++ b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PinNamesVar.h @@ -111,12 +111,6 @@ PZ_7_ALT1 = PZ_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c index 64dfa43b58..677733b6e6 100644 --- a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP153DACx.xml, STM32MP153FACx.xml * STM32MP157AACx.xml, STM32MP157CACx.xml * STM32MP157DACx.xml, STM32MP157FACx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PinNamesVar.h b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PinNamesVar.h index 2fbc6960f4..abe8f59652 100644 --- a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PinNamesVar.h +++ b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PinNamesVar.h @@ -105,12 +105,6 @@ PZ_7_ALT1 = PZ_7 | ALT1, #ifdef PWR_WAKEUP_PIN6 SYS_WKUP6 = PC_1, #endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 3eb068fdc49fc7a79d3c1ae904d62ae8b08dac24 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:40:05 +0100 Subject: [PATCH 054/141] chore(u0): update variant after script update Signed-off-by: Frederic Pillon --- variants/STM32U0xx/U031C(6-8)(T-U)/PinNamesVar.h | 3 --- variants/STM32U0xx/U031F(4-6-8)P/PinNamesVar.h | 12 ------------ variants/STM32U0xx/U031G(6-8)Y/PinNamesVar.h | 12 ------------ variants/STM32U0xx/U031K(4-6-8)U/PinNamesVar.h | 12 ------------ variants/STM32U0xx/U031R(6-8)(I-T)/PinNamesVar.h | 3 --- .../U073C(8-B-C)(T-U)_U083CC(T-U)/PinNamesVar.h | 3 --- .../STM32U0xx/U073H(8-B-C)Y_U083HCY/PinNamesVar.h | 12 ------------ .../STM32U0xx/U073K(8-B-C)U_U083KCU/PinNamesVar.h | 12 ------------ .../STM32U0xx/U073M(8-B-C)I_U083MCI/PinNamesVar.h | 3 --- .../STM32U0xx/U073M(8-B-C)T_U083MCT/PinNamesVar.h | 3 --- .../U073R(8-B-C)(I-T)_U083RC(I-T)/PinNamesVar.h | 3 --- 11 files changed, 78 deletions(-) diff --git a/variants/STM32U0xx/U031C(6-8)(T-U)/PinNamesVar.h b/variants/STM32U0xx/U031C(6-8)(T-U)/PinNamesVar.h index 6b4a5c1ea5..414c23bf2e 100644 --- a/variants/STM32U0xx/U031C(6-8)(T-U)/PinNamesVar.h +++ b/variants/STM32U0xx/U031C(6-8)(T-U)/PinNamesVar.h @@ -46,8 +46,5 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32U0xx/U031F(4-6-8)P/PinNamesVar.h b/variants/STM32U0xx/U031F(4-6-8)P/PinNamesVar.h index c3eecd7239..4b8e2c0c19 100644 --- a/variants/STM32U0xx/U031F(4-6-8)P/PinNamesVar.h +++ b/variants/STM32U0xx/U031F(4-6-8)P/PinNamesVar.h @@ -30,17 +30,5 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32U0xx/U031G(6-8)Y/PinNamesVar.h b/variants/STM32U0xx/U031G(6-8)Y/PinNamesVar.h index 988c6d7958..71cd3284d8 100644 --- a/variants/STM32U0xx/U031G(6-8)Y/PinNamesVar.h +++ b/variants/STM32U0xx/U031G(6-8)Y/PinNamesVar.h @@ -27,17 +27,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32U0xx/U031K(4-6-8)U/PinNamesVar.h b/variants/STM32U0xx/U031K(4-6-8)U/PinNamesVar.h index 0cf9afded8..fd0de15dba 100644 --- a/variants/STM32U0xx/U031K(4-6-8)U/PinNamesVar.h +++ b/variants/STM32U0xx/U031K(4-6-8)U/PinNamesVar.h @@ -30,17 +30,5 @@ PB_7_ALT1 = PB_7 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32U0xx/U031R(6-8)(I-T)/PinNamesVar.h b/variants/STM32U0xx/U031R(6-8)(I-T)/PinNamesVar.h index 948781c914..c77719441b 100644 --- a/variants/STM32U0xx/U031R(6-8)(I-T)/PinNamesVar.h +++ b/variants/STM32U0xx/U031R(6-8)(I-T)/PinNamesVar.h @@ -48,8 +48,5 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PinNamesVar.h b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PinNamesVar.h index b08eef8240..73d338b11a 100644 --- a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PinNamesVar.h +++ b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PinNamesVar.h @@ -50,9 +50,6 @@ PB_15_ALT1 = PB_15 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PinNamesVar.h b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PinNamesVar.h index 48d10b8b61..2d23a23968 100644 --- a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PinNamesVar.h +++ b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PinNamesVar.h @@ -36,18 +36,6 @@ PB_10_ALT1 = PB_10 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PinNamesVar.h b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PinNamesVar.h index 8c30aa0a58..99d3e075a8 100644 --- a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PinNamesVar.h +++ b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PinNamesVar.h @@ -34,18 +34,6 @@ PB_7_ALT2 = PB_7 | ALT2, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PinNamesVar.h b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PinNamesVar.h index 73edb586a0..b58dfd829f 100644 --- a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PinNamesVar.h +++ b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PinNamesVar.h @@ -60,9 +60,6 @@ PD_12_ALT1 = PD_12 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PinNamesVar.h b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PinNamesVar.h index 73edb586a0..b58dfd829f 100644 --- a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PinNamesVar.h +++ b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PinNamesVar.h @@ -60,9 +60,6 @@ PD_12_ALT1 = PD_12 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PinNamesVar.h b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PinNamesVar.h index 4e13f413a0..891f84ab80 100644 --- a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PinNamesVar.h +++ b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PinNamesVar.h @@ -56,9 +56,6 @@ PC_11_ALT1 = PC_11 | ALT1, #ifdef PWR_WAKEUP_PIN7 SYS_WKUP7 = PB_15, #endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From 27ef26ca8bd789bae65e4e4913e271a40e957f29 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:41:41 +0100 Subject: [PATCH 055/141] chore(u5): update variant after script update Signed-off-by: Frederic Pillon --- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535JEYxQ_U545JEYxQ/PeripheralPins.c | 2 +- .../U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c | 2 +- .../U535R(B-C-E)I_U545REI/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535R(B-C-E)T_U545RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535V(C-E)I_U545VEI/PeripheralPins.c | 2 +- .../U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c | 2 +- .../U535V(C-E)T_U545VET/PeripheralPins.c | 2 +- .../U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c | 2 +- .../U575A(G-I)I_U585AII/PeripheralPins.c | 2 +- .../U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c | 2 +- .../U575Q(G-I)I_U585QII/PeripheralPins.c | 2 +- .../U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c | 2 +- .../U575R(G-I)T_U585RIT/PeripheralPins.c | 2 +- .../U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c | 2 +- .../U575V(G-I)T_U585VIT/PeripheralPins.c | 2 +- .../U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c | 2 +- .../U575Z(G-I)T_U585ZIT/PeripheralPins.c | 2 +- .../U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c | 2 +- .../U595A(I-J)H_U5A5AJH/PeripheralPins.c | 2 +- .../U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c | 2 +- .../U595Q(I-J)I_U5A5QJI/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595R(I-J)T_U5A5RJT/PeripheralPins.c | 2 +- .../U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595Z(I-J)T_U5A5ZJT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c | 2 +- .../U599BJYxQ_U5A9BJYxQ/PeripheralPins.c | 2 +- .../U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c | 2 +- .../U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F7V(I-J)T/PeripheralPins.c | 602 +++++++++++++++ .../PinNamesVar.h | 0 .../boards_entry.txt | 17 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 .../U5F7V(I-J)T_U5G7VJT/CMakeLists.txt | 31 - .../STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c | 594 +++++++++++++++ .../PinNamesVar.h | 0 .../boards_entry.txt | 17 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 .../U5F7V(I-J)TxQ_U5G7VJTxQ/CMakeLists.txt | 31 - .../U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c | 2 +- .../U5F9BJYxQ_U5G9BJYxQ/boards_entry.txt | 2 +- variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c | 714 ++++++++++++++++++ .../PinNamesVar.h | 0 .../boards_entry.txt | 13 +- .../generic_clock.c | 2 +- .../variant_generic.cpp | 2 +- .../variant_generic.h | 0 .../U5F9NJHxQ_U5G9NJHxQ/CMakeLists.txt | 31 - .../STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c | 497 ++++++++++++ .../PinNamesVar.h | 0 .../boards_entry.txt | 17 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 2 + .../U5F9V(I-J)TxQ_U5G9VJTxQ/CMakeLists.txt | 31 - .../STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c | 642 ++++++++++++++++ .../PinNamesVar.h | 0 .../boards_entry.txt | 17 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 .../U5F9Z(I-J)JxQ_U5G9ZJJxQ/CMakeLists.txt | 31 - .../STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c | 642 ++++++++++++++++ .../PinNamesVar.h | 0 .../boards_entry.txt | 17 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 .../U5F9Z(I-J)TxQ_U5G9ZJTxQ/CMakeLists.txt | 31 - .../PeripheralPins.c | 5 +- variants/STM32U5xx/U5G7VJT/PinNamesVar.h | 141 ++++ variants/STM32U5xx/U5G7VJT/boards_entry.txt | 14 + variants/STM32U5xx/U5G7VJT/generic_clock.c | 27 + .../STM32U5xx/U5G7VJT/variant_generic.cpp | 126 ++++ variants/STM32U5xx/U5G7VJT/variant_generic.h | 279 +++++++ .../PeripheralPins.c | 5 +- variants/STM32U5xx/U5G7VJTxQ/PinNamesVar.h | 135 ++++ variants/STM32U5xx/U5G7VJTxQ/boards_entry.txt | 14 + variants/STM32U5xx/U5G7VJTxQ/generic_clock.c | 27 + .../STM32U5xx/U5G7VJTxQ/variant_generic.cpp | 121 +++ .../STM32U5xx/U5G7VJTxQ/variant_generic.h | 272 +++++++ .../PeripheralPins.c | 4 +- variants/STM32U5xx/U5G9NJHxQ/PinNamesVar.h | 149 ++++ variants/STM32U5xx/U5G9NJHxQ/boards_entry.txt | 14 + variants/STM32U5xx/U5G9NJHxQ/generic_clock.c | 27 + .../STM32U5xx/U5G9NJHxQ/variant_generic.cpp | 204 +++++ .../STM32U5xx/U5G9NJHxQ/variant_generic.h | 359 +++++++++ .../PeripheralPins.c | 44 +- variants/STM32U5xx/U5G9VJTxQ/PinNamesVar.h | 118 +++ variants/STM32U5xx/U5G9VJTxQ/boards_entry.txt | 14 + variants/STM32U5xx/U5G9VJTxQ/generic_clock.c | 27 + .../STM32U5xx/U5G9VJTxQ/variant_generic.cpp | 102 +++ .../STM32U5xx/U5G9VJTxQ/variant_generic.h | 253 +++++++ .../PeripheralPins.c | 5 +- variants/STM32U5xx/U5G9ZJJxQ/PinNamesVar.h | 141 ++++ variants/STM32U5xx/U5G9ZJJxQ/boards_entry.txt | 14 + variants/STM32U5xx/U5G9ZJJxQ/generic_clock.c | 27 + .../STM32U5xx/U5G9ZJJxQ/variant_generic.cpp | 145 ++++ .../STM32U5xx/U5G9ZJJxQ/variant_generic.h | 298 ++++++++ .../PeripheralPins.c | 5 +- variants/STM32U5xx/U5G9ZJTxQ/PinNamesVar.h | 141 ++++ variants/STM32U5xx/U5G9ZJTxQ/boards_entry.txt | 14 + variants/STM32U5xx/U5G9ZJTxQ/generic_clock.c | 27 + .../STM32U5xx/U5G9ZJTxQ/variant_generic.cpp | 145 ++++ .../STM32U5xx/U5G9ZJTxQ/variant_generic.h | 298 ++++++++ 119 files changed, 7462 insertions(+), 372 deletions(-) create mode 100644 variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c rename variants/STM32U5xx/{U5F7V(I-J)T_U5G7VJT => U5F7V(I-J)T}/PinNamesVar.h (100%) rename variants/STM32U5xx/{U5F7V(I-J)T_U5G7VJT => U5F7V(I-J)T}/boards_entry.txt (64%) rename variants/STM32U5xx/{U5F7V(I-J)T_U5G7VJT => U5F7V(I-J)T}/generic_clock.c (94%) rename variants/STM32U5xx/{U5F7V(I-J)T_U5G7VJT => U5F7V(I-J)T}/variant_generic.cpp (97%) rename variants/STM32U5xx/{U5F7V(I-J)T_U5G7VJT => U5F7V(I-J)T}/variant_generic.h (100%) delete mode 100644 variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c rename variants/STM32U5xx/{U5F7V(I-J)TxQ_U5G7VJTxQ => U5F7V(I-J)TxQ}/PinNamesVar.h (100%) rename variants/STM32U5xx/{U5F7V(I-J)TxQ_U5G7VJTxQ => U5F7V(I-J)TxQ}/boards_entry.txt (63%) rename variants/STM32U5xx/{U5F7V(I-J)TxQ_U5G7VJTxQ => U5F7V(I-J)TxQ}/generic_clock.c (94%) rename variants/STM32U5xx/{U5F7V(I-J)TxQ_U5G7VJTxQ => U5F7V(I-J)TxQ}/variant_generic.cpp (97%) rename variants/STM32U5xx/{U5F7V(I-J)TxQ_U5G7VJTxQ => U5F7V(I-J)TxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c rename variants/STM32U5xx/{U5F9NJHxQ_U5G9NJHxQ => U5F9NJHxQ}/PinNamesVar.h (100%) rename variants/STM32U5xx/{U5F9NJHxQ_U5G9NJHxQ => U5F9NJHxQ}/boards_entry.txt (54%) rename variants/STM32U5xx/{U5F9NJHxQ_U5G9NJHxQ => U5F9NJHxQ}/generic_clock.c (91%) rename variants/STM32U5xx/{U5F9NJHxQ_U5G9NJHxQ => U5F9NJHxQ}/variant_generic.cpp (98%) rename variants/STM32U5xx/{U5F9NJHxQ_U5G9NJHxQ => U5F9NJHxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c rename variants/STM32U5xx/{U5F9V(I-J)TxQ_U5G9VJTxQ => U5F9V(I-J)TxQ}/PinNamesVar.h (100%) rename variants/STM32U5xx/{U5F9V(I-J)TxQ_U5G9VJTxQ => U5F9V(I-J)TxQ}/boards_entry.txt (63%) rename variants/STM32U5xx/{U5F9V(I-J)TxQ_U5G9VJTxQ => U5F9V(I-J)TxQ}/generic_clock.c (94%) rename variants/STM32U5xx/{U5F9V(I-J)TxQ_U5G9VJTxQ => U5F9V(I-J)TxQ}/variant_generic.cpp (97%) rename variants/STM32U5xx/{U5F9V(I-J)TxQ_U5G9VJTxQ => U5F9V(I-J)TxQ}/variant_generic.h (99%) delete mode 100644 variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c rename variants/STM32U5xx/{U5F9Z(I-J)JxQ_U5G9ZJJxQ => U5F9Z(I-J)JxQ}/PinNamesVar.h (100%) rename variants/STM32U5xx/{U5F9Z(I-J)JxQ_U5G9ZJJxQ => U5F9Z(I-J)JxQ}/boards_entry.txt (63%) rename variants/STM32U5xx/{U5F9Z(I-J)JxQ_U5G9ZJJxQ => U5F9Z(I-J)JxQ}/generic_clock.c (94%) rename variants/STM32U5xx/{U5F9Z(I-J)JxQ_U5G9ZJJxQ => U5F9Z(I-J)JxQ}/variant_generic.cpp (98%) rename variants/STM32U5xx/{U5F9Z(I-J)JxQ_U5G9ZJJxQ => U5F9Z(I-J)JxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c rename variants/STM32U5xx/{U5F9Z(I-J)TxQ_U5G9ZJTxQ => U5F9Z(I-J)TxQ}/PinNamesVar.h (100%) rename variants/STM32U5xx/{U5F9Z(I-J)TxQ_U5G9ZJTxQ => U5F9Z(I-J)TxQ}/boards_entry.txt (63%) rename variants/STM32U5xx/{U5F9Z(I-J)TxQ_U5G9ZJTxQ => U5F9Z(I-J)TxQ}/generic_clock.c (94%) rename variants/STM32U5xx/{U5F9Z(I-J)TxQ_U5G9ZJTxQ => U5F9Z(I-J)TxQ}/variant_generic.cpp (98%) rename variants/STM32U5xx/{U5F9Z(I-J)TxQ_U5G9ZJTxQ => U5F9Z(I-J)TxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/CMakeLists.txt rename variants/STM32U5xx/{U5F7V(I-J)T_U5G7VJT => U5G7VJT}/PeripheralPins.c (99%) create mode 100644 variants/STM32U5xx/U5G7VJT/PinNamesVar.h create mode 100644 variants/STM32U5xx/U5G7VJT/boards_entry.txt create mode 100644 variants/STM32U5xx/U5G7VJT/generic_clock.c create mode 100644 variants/STM32U5xx/U5G7VJT/variant_generic.cpp create mode 100644 variants/STM32U5xx/U5G7VJT/variant_generic.h rename variants/STM32U5xx/{U5F7V(I-J)TxQ_U5G7VJTxQ => U5G7VJTxQ}/PeripheralPins.c (99%) create mode 100644 variants/STM32U5xx/U5G7VJTxQ/PinNamesVar.h create mode 100644 variants/STM32U5xx/U5G7VJTxQ/boards_entry.txt create mode 100644 variants/STM32U5xx/U5G7VJTxQ/generic_clock.c create mode 100644 variants/STM32U5xx/U5G7VJTxQ/variant_generic.cpp create mode 100644 variants/STM32U5xx/U5G7VJTxQ/variant_generic.h rename variants/STM32U5xx/{U5F9NJHxQ_U5G9NJHxQ => U5G9NJHxQ}/PeripheralPins.c (99%) create mode 100644 variants/STM32U5xx/U5G9NJHxQ/PinNamesVar.h create mode 100644 variants/STM32U5xx/U5G9NJHxQ/boards_entry.txt create mode 100644 variants/STM32U5xx/U5G9NJHxQ/generic_clock.c create mode 100644 variants/STM32U5xx/U5G9NJHxQ/variant_generic.cpp create mode 100644 variants/STM32U5xx/U5G9NJHxQ/variant_generic.h rename variants/STM32U5xx/{U5F9V(I-J)TxQ_U5G9VJTxQ => U5G9VJTxQ}/PeripheralPins.c (94%) create mode 100644 variants/STM32U5xx/U5G9VJTxQ/PinNamesVar.h create mode 100644 variants/STM32U5xx/U5G9VJTxQ/boards_entry.txt create mode 100644 variants/STM32U5xx/U5G9VJTxQ/generic_clock.c create mode 100644 variants/STM32U5xx/U5G9VJTxQ/variant_generic.cpp create mode 100644 variants/STM32U5xx/U5G9VJTxQ/variant_generic.h rename variants/STM32U5xx/{U5F9Z(I-J)TxQ_U5G9ZJTxQ => U5G9ZJJxQ}/PeripheralPins.c (99%) create mode 100644 variants/STM32U5xx/U5G9ZJJxQ/PinNamesVar.h create mode 100644 variants/STM32U5xx/U5G9ZJJxQ/boards_entry.txt create mode 100644 variants/STM32U5xx/U5G9ZJJxQ/generic_clock.c create mode 100644 variants/STM32U5xx/U5G9ZJJxQ/variant_generic.cpp create mode 100644 variants/STM32U5xx/U5G9ZJJxQ/variant_generic.h rename variants/STM32U5xx/{U5F9Z(I-J)JxQ_U5G9ZJJxQ => U5G9ZJTxQ}/PeripheralPins.c (99%) create mode 100644 variants/STM32U5xx/U5G9ZJTxQ/PinNamesVar.h create mode 100644 variants/STM32U5xx/U5G9ZJTxQ/boards_entry.txt create mode 100644 variants/STM32U5xx/U5G9ZJTxQ/generic_clock.c create mode 100644 variants/STM32U5xx/U5G9ZJTxQ/variant_generic.cpp create mode 100644 variants/STM32U5xx/U5G9ZJTxQ/variant_generic.h diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c index ac8c486f71..2d42139e5f 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTx.xml, STM32U535CCUx.xml * STM32U535CETx.xml, STM32U535CEUx.xml * STM32U545CETx.xml, STM32U545CEUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c index 318a29854c..a274687d5d 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTxQ.xml, STM32U535CCUxQ.xml * STM32U535CETxQ.xml, STM32U535CEUxQ.xml * STM32U545CETxQ.xml, STM32U545CEUxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c index a85abf159c..1645c09c21 100644 --- a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U535JEYxQ.xml, STM32U545JEYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c index 8945af39fb..9221dbbc40 100644 --- a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535NCYxQ.xml, STM32U535NEYxQ.xml * STM32U545NEYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c index e123f5dac7..e3f682a8ba 100644 --- a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIx.xml, STM32U535RCIx.xml * STM32U535REIx.xml, STM32U545REIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c index c01013aea0..67da26a307 100644 --- a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIxQ.xml, STM32U535RCIxQ.xml * STM32U535REIxQ.xml, STM32U545REIxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c index 58edc0cc10..c84369d57a 100644 --- a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTx.xml, STM32U535RCTx.xml * STM32U535RETx.xml, STM32U545RETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c index 3405ac7e41..0687d6fe70 100644 --- a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTxQ.xml, STM32U535RCTxQ.xml * STM32U535RETxQ.xml, STM32U545RETxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c index 4aad8699ae..f8e974a8eb 100644 --- a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIx.xml, STM32U535VEIx.xml * STM32U545VEIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c index c4e420a726..f6b9ec69b7 100644 --- a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIxQ.xml, STM32U535VEIxQ.xml * STM32U545VEIxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c index f9cc09ecdb..fd491452db 100644 --- a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTx.xml, STM32U535VETx.xml * STM32U545VETx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c index 21028d05b0..a7e40a134a 100644 --- a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTxQ.xml, STM32U535VETxQ.xml * STM32U545VETxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c index 2e187e47a0..1a98338b18 100644 --- a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIx.xml, STM32U575AIIx.xml * STM32U585AIIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c index 57e91b9eb5..92d4b09ef0 100644 --- a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIxQ.xml, STM32U575AIIxQ.xml * STM32U585AIIxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c index ba30df7682..66ccddd18e 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTx.xml, STM32U575CGUx.xml * STM32U575CITx.xml, STM32U575CIUx.xml * STM32U585CITx.xml, STM32U585CIUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c index 20e85f5993..6234d72e19 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTxQ.xml, STM32U575CGUxQ.xml * STM32U575CITxQ.xml, STM32U575CIUxQ.xml * STM32U585CITxQ.xml, STM32U585CIUxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c index 562da56db3..31e920c441 100644 --- a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575OGYxQ.xml, STM32U575OIYxQ.xml * STM32U585OIYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c index 14792d306e..473f541d64 100644 --- a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIx.xml, STM32U575QIIx.xml * STM32U585QIIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c index b02b4bfae4..a1223b32f2 100644 --- a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIxQ.xml, STM32U575QIIxQ.xml * STM32U585QIIxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c index f17c12f1f9..b6f657ac36 100644 --- a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTx.xml, STM32U575RITx.xml * STM32U585RITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c index 71161af49e..e3686aa25c 100644 --- a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTxQ.xml, STM32U575RITxQ.xml * STM32U585RITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c index 72ac22be3a..1f7d873d9b 100644 --- a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTx.xml, STM32U575VITx.xml * STM32U585VITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c index f58734c33b..e014047004 100644 --- a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTxQ.xml, STM32U575VITxQ.xml * STM32U585VITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c index 22070e83ef..6e477257e3 100644 --- a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTx.xml, STM32U575ZITx.xml * STM32U585ZITx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c index c9eda1e5ec..a43dd82b20 100644 --- a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTxQ.xml, STM32U575ZITxQ.xml * STM32U585ZITxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c index 916c9f26fc..a312d0c095 100644 --- a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHx.xml, STM32U595AJHx.xml * STM32U5A5AJHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c index 0e311d85c2..e8e4617fb1 100644 --- a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHxQ.xml, STM32U595AJHxQ.xml * STM32U5A5AJHxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c index 52c9d23ef5..23cccddf64 100644 --- a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIx.xml, STM32U595QJIx.xml * STM32U5A5QJIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c index 6f53a49263..c6c554a807 100644 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIxQ.xml, STM32U595QJIxQ.xml * STM32U5A5QIIxQ.xml, STM32U5A5QJIxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c index f00edf6774..e32be5237c 100644 --- a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITx.xml, STM32U595RJTx.xml * STM32U5A5RJTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c index d0c2cdf5ec..e3e46a11aa 100644 --- a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITxQ.xml, STM32U595RJTxQ.xml * STM32U5A5RJTxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c index 62c9b066af..1d5c58541c 100644 --- a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595VITx.xml, STM32U595VJTx.xml * STM32U599VJTx.xml, STM32U5A5VJTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c index badfe6ba89..1921962517 100644 --- a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595VITxQ.xml, STM32U595VJTxQ.xml * STM32U599VITxQ.xml, STM32U599VJTxQ.xml * STM32U5A5VJTxQ.xml, STM32U5A9VJTxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c index 24b4677035..ed543ff8b2 100644 --- a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZITx.xml, STM32U595ZJTx.xml * STM32U5A5ZJTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c index 0fac7f7e47..bb0030a888 100644 --- a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595ZITxQ.xml, STM32U595ZJTxQ.xml * STM32U599ZITxQ.xml, STM32U599ZJTxQ.xml * STM32U5A5ZJTxQ.xml, STM32U5A9ZJTxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c index 637f9b4853..c8e5bfa280 100644 --- a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZIYxQ.xml, STM32U595ZJYxQ.xml * STM32U5A5ZJYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c index fcfde57570..5fcdb2e826 100644 --- a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U599BJYxQ.xml, STM32U5A9BJYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c index 5847687b91..89e6622132 100644 --- a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599NIHxQ.xml, STM32U599NJHxQ.xml * STM32U5A9NJHxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c index eb84452437..0282e3a05d 100644 --- a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599ZIYxQ.xml, STM32U599ZJYxQ.xml * STM32U5A9ZJYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c new file mode 100644 index 0000000000..48aaa3130f --- /dev/null +++ b/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c @@ -0,0 +1,602 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U5F7VITx.xml, STM32U5F7VJTx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PA_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_6_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PA_7_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC4_IN20 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC4_IN18 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PB_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC4_IN19 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PC_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PC_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PC_3_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PC_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 22, 0)}, // ADC4_IN22 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PC_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 23, 0)}, // ADC4_IN23 + {PD_11, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC4_IN15 + {PD_12, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC4_IN16 + {PD_13, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC4_IN17 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_0, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_2, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PD_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_HS[] = { +#ifdef USE_USB_HS_IN_FS + {PA_8, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF + {PA_9, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID + {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM + {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF +#endif /* USE_USB_HS_IN_FS */ + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PA_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SDMMC2)}, // SDMMC2_D1 + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5 + {PC_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PinNamesVar.h b/variants/STM32U5xx/U5F7V(I-J)T/PinNamesVar.h similarity index 100% rename from variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PinNamesVar.h rename to variants/STM32U5xx/U5F7V(I-J)T/PinNamesVar.h diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/boards_entry.txt b/variants/STM32U5xx/U5F7V(I-J)T/boards_entry.txt similarity index 64% rename from variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/boards_entry.txt rename to variants/STM32U5xx/U5F7V(I-J)T/boards_entry.txt index 4c40ad51cd..e526a5f4a6 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/boards_entry.txt +++ b/variants/STM32U5xx/U5F7V(I-J)T/boards_entry.txt @@ -9,8 +9,8 @@ GenU5.menu.pnum.GENERIC_U5F7VITX.upload.maximum_size=2097152 GenU5.menu.pnum.GENERIC_U5F7VITX.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F7VITX.build.board=GENERIC_U5F7VITX GenU5.menu.pnum.GENERIC_U5F7VITX.build.product_line=STM32U5F7xx -GenU5.menu.pnum.GENERIC_U5F7VITX.build.variant=STM32U5xx/U5F7V(I-J)T_U5G7VJT -GenU5.menu.pnum.GENERIC_U5F7VITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd +GenU5.menu.pnum.GENERIC_U5F7VITX.build.variant=STM32U5xx/U5F7V(I-J)T +GenU5.menu.pnum.GENERIC_U5F7VITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F7.svd # Generic U5F7VJTx GenU5.menu.pnum.GENERIC_U5F7VJTX=Generic U5F7VJTx @@ -18,15 +18,6 @@ GenU5.menu.pnum.GENERIC_U5F7VJTX.upload.maximum_size=4194304 GenU5.menu.pnum.GENERIC_U5F7VJTX.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F7VJTX.build.board=GENERIC_U5F7VJTX GenU5.menu.pnum.GENERIC_U5F7VJTX.build.product_line=STM32U5F7xx -GenU5.menu.pnum.GENERIC_U5F7VJTX.build.variant=STM32U5xx/U5F7V(I-J)T_U5G7VJT -GenU5.menu.pnum.GENERIC_U5F7VJTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd - -# Generic U5G7VJTx -GenU5.menu.pnum.GENERIC_U5G7VJTX=Generic U5G7VJTx -GenU5.menu.pnum.GENERIC_U5G7VJTX.upload.maximum_size=4194304 -GenU5.menu.pnum.GENERIC_U5G7VJTX.upload.maximum_data_size=3098624 -GenU5.menu.pnum.GENERIC_U5G7VJTX.build.board=GENERIC_U5G7VJTX -GenU5.menu.pnum.GENERIC_U5G7VJTX.build.product_line=STM32U5G7xx -GenU5.menu.pnum.GENERIC_U5G7VJTX.build.variant=STM32U5xx/U5F7V(I-J)T_U5G7VJT -GenU5.menu.pnum.GENERIC_U5G7VJTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd +GenU5.menu.pnum.GENERIC_U5F7VJTX.build.variant=STM32U5xx/U5F7V(I-J)T +GenU5.menu.pnum.GENERIC_U5F7VJTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F7.svd diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/generic_clock.c b/variants/STM32U5xx/U5F7V(I-J)T/generic_clock.c similarity index 94% rename from variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/generic_clock.c rename to variants/STM32U5xx/U5F7V(I-J)T/generic_clock.c index abbac46244..e7b2146499 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/generic_clock.c +++ b/variants/STM32U5xx/U5F7V(I-J)T/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F7VITX) || defined(ARDUINO_GENERIC_U5F7VJTX) ||\ - defined(ARDUINO_GENERIC_U5G7VJTX) +#if defined(ARDUINO_GENERIC_U5F7VITX) || defined(ARDUINO_GENERIC_U5F7VJTX) #include "pins_arduino.h" /** diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/variant_generic.cpp b/variants/STM32U5xx/U5F7V(I-J)T/variant_generic.cpp similarity index 97% rename from variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/variant_generic.cpp rename to variants/STM32U5xx/U5F7V(I-J)T/variant_generic.cpp index 7ebe7896ab..783a91a613 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/variant_generic.cpp +++ b/variants/STM32U5xx/U5F7V(I-J)T/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F7VITX) || defined(ARDUINO_GENERIC_U5F7VJTX) ||\ - defined(ARDUINO_GENERIC_U5G7VJTX) +#if defined(ARDUINO_GENERIC_U5F7VITX) || defined(ARDUINO_GENERIC_U5F7VJTX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/variant_generic.h b/variants/STM32U5xx/U5F7V(I-J)T/variant_generic.h similarity index 100% rename from variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/variant_generic.h rename to variants/STM32U5xx/U5F7V(I-J)T/variant_generic.h diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/CMakeLists.txt b/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c new file mode 100644 index 0000000000..4a5e23edda --- /dev/null +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c @@ -0,0 +1,594 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U5F7VITxQ.xml, STM32U5F7VJTxQ.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PA_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_6_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PA_7_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC4_IN20 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC4_IN18 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PB_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC4_IN19 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PC_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PC_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PC_3_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PD_11, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC4_IN15 + {PD_12, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC4_IN16 + {PD_13, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC4_IN17 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_11_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_0, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_2, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PB_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PD_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_HS[] = { +#ifdef USE_USB_HS_IN_FS + {PA_8, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF + {PA_9, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID + {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM + {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF +#endif /* USE_USB_HS_IN_FS */ + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PA_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SDMMC2)}, // SDMMC2_D1 + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5 + {PC_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5F7V(I-J)TxQ/PinNamesVar.h similarity index 100% rename from variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PinNamesVar.h rename to variants/STM32U5xx/U5F7V(I-J)TxQ/PinNamesVar.h diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/boards_entry.txt b/variants/STM32U5xx/U5F7V(I-J)TxQ/boards_entry.txt similarity index 63% rename from variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/boards_entry.txt rename to variants/STM32U5xx/U5F7V(I-J)TxQ/boards_entry.txt index 2f65b0edaf..18868f7955 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/boards_entry.txt +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ/boards_entry.txt @@ -9,8 +9,8 @@ GenU5.menu.pnum.GENERIC_U5F7VITXQ.upload.maximum_size=2097152 GenU5.menu.pnum.GENERIC_U5F7VITXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F7VITXQ.build.board=GENERIC_U5F7VITXQ GenU5.menu.pnum.GENERIC_U5F7VITXQ.build.product_line=STM32U5F7xx -GenU5.menu.pnum.GENERIC_U5F7VITXQ.build.variant=STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ -GenU5.menu.pnum.GENERIC_U5F7VITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd +GenU5.menu.pnum.GENERIC_U5F7VITXQ.build.variant=STM32U5xx/U5F7V(I-J)TxQ +GenU5.menu.pnum.GENERIC_U5F7VITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F7.svd # Generic U5F7VJTxQ GenU5.menu.pnum.GENERIC_U5F7VJTXQ=Generic U5F7VJTxQ @@ -18,15 +18,6 @@ GenU5.menu.pnum.GENERIC_U5F7VJTXQ.upload.maximum_size=4194304 GenU5.menu.pnum.GENERIC_U5F7VJTXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F7VJTXQ.build.board=GENERIC_U5F7VJTXQ GenU5.menu.pnum.GENERIC_U5F7VJTXQ.build.product_line=STM32U5F7xx -GenU5.menu.pnum.GENERIC_U5F7VJTXQ.build.variant=STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ -GenU5.menu.pnum.GENERIC_U5F7VJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd - -# Generic U5G7VJTxQ -GenU5.menu.pnum.GENERIC_U5G7VJTXQ=Generic U5G7VJTxQ -GenU5.menu.pnum.GENERIC_U5G7VJTXQ.upload.maximum_size=4194304 -GenU5.menu.pnum.GENERIC_U5G7VJTXQ.upload.maximum_data_size=3098624 -GenU5.menu.pnum.GENERIC_U5G7VJTXQ.build.board=GENERIC_U5G7VJTXQ -GenU5.menu.pnum.GENERIC_U5G7VJTXQ.build.product_line=STM32U5G7xx -GenU5.menu.pnum.GENERIC_U5G7VJTXQ.build.variant=STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ -GenU5.menu.pnum.GENERIC_U5G7VJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd +GenU5.menu.pnum.GENERIC_U5F7VJTXQ.build.variant=STM32U5xx/U5F7V(I-J)TxQ +GenU5.menu.pnum.GENERIC_U5F7VJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F7.svd diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/generic_clock.c b/variants/STM32U5xx/U5F7V(I-J)TxQ/generic_clock.c similarity index 94% rename from variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/generic_clock.c rename to variants/STM32U5xx/U5F7V(I-J)TxQ/generic_clock.c index 3f07eb6201..dc23788ffb 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/generic_clock.c +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F7VITXQ) || defined(ARDUINO_GENERIC_U5F7VJTXQ) ||\ - defined(ARDUINO_GENERIC_U5G7VJTXQ) +#if defined(ARDUINO_GENERIC_U5F7VITXQ) || defined(ARDUINO_GENERIC_U5F7VJTXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/variant_generic.cpp b/variants/STM32U5xx/U5F7V(I-J)TxQ/variant_generic.cpp similarity index 97% rename from variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/variant_generic.cpp rename to variants/STM32U5xx/U5F7V(I-J)TxQ/variant_generic.cpp index 02443c86da..8174800a60 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/variant_generic.cpp +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F7VITXQ) || defined(ARDUINO_GENERIC_U5F7VJTXQ) ||\ - defined(ARDUINO_GENERIC_U5G7VJTXQ) +#if defined(ARDUINO_GENERIC_U5F7VITXQ) || defined(ARDUINO_GENERIC_U5F7VJTXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/variant_generic.h b/variants/STM32U5xx/U5F7V(I-J)TxQ/variant_generic.h similarity index 100% rename from variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/variant_generic.h rename to variants/STM32U5xx/U5F7V(I-J)TxQ/variant_generic.h diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/CMakeLists.txt b/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c index d30751d67d..7bfb73d651 100644 --- a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9BJYxQ.xml, STM32U5G9BJYxQ.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/boards_entry.txt b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/boards_entry.txt index c77ee42ebd..1a52b69336 100644 --- a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/boards_entry.txt +++ b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/boards_entry.txt @@ -10,7 +10,7 @@ GenU5.menu.pnum.GENERIC_U5F9BJYXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F9BJYXQ.build.board=GENERIC_U5F9BJYXQ GenU5.menu.pnum.GENERIC_U5F9BJYXQ.build.product_line=STM32U5F9xx GenU5.menu.pnum.GENERIC_U5F9BJYXQ.build.variant=STM32U5xx/U5F9BJYxQ_U5G9BJYxQ -GenU5.menu.pnum.GENERIC_U5F9BJYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd +GenU5.menu.pnum.GENERIC_U5F9BJYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F9.svd # Generic U5G9BJYxQ GenU5.menu.pnum.GENERIC_U5G9BJYXQ=Generic U5G9BJYxQ diff --git a/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c new file mode 100644 index 0000000000..ca0da3f1b4 --- /dev/null +++ b/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c @@ -0,0 +1,714 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U5F9NJHxQ.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PA_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_6_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PA_7_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC4_IN20 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC4_IN18 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PB_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC4_IN19 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PC_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PC_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PC_3_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PC_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 22, 0)}, // ADC4_IN22 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PC_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 23, 0)}, // ADC4_IN23 + {PD_11, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC4_IN15 + {PD_12, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC4_IN16 + {PD_13, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC4_IN17 + {PF_14, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC4_IN5 + {PF_15, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC4_IN6 + {PG_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PG_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_11_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_0, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PG_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PH_4, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C5)}, + {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PJ_1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PJ_9, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PF_14, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PG_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_5, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C5)}, + {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PJ_2, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PJ_10, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PF_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PF_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PF_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PF_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PF_9_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PF_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PG_9, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PG_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PG_11, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PH_10, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_11, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PF_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PF_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PG_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PJ_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_2, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PF_1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PF_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PG_8, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PJ_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PF_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PJ_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PF_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PJ_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PF_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PI_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PF_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PI_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PF_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PI_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {PF_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {PH_8, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PG_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO4 + {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PH_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PG_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO5 + {PG_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PH_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO5 + {PI_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PG_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {PH_11, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {PH_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PG_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO7 + {PH_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PF_4, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_CLK + {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PH_6, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_CLK + {PI_6, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PB_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PD_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PF_6, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PG_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PI_5, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_HS[] = { +#ifdef USE_USB_HS_IN_FS + {PA_8, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF + {PA_9, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID + {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM + {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF +#endif /* USE_USB_HS_IN_FS */ + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PA_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SDMMC2)}, // SDMMC2_D1 + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5 + {PC_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9NJHxQ/PinNamesVar.h similarity index 100% rename from variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PinNamesVar.h rename to variants/STM32U5xx/U5F9NJHxQ/PinNamesVar.h diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/boards_entry.txt b/variants/STM32U5xx/U5F9NJHxQ/boards_entry.txt similarity index 54% rename from variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/boards_entry.txt rename to variants/STM32U5xx/U5F9NJHxQ/boards_entry.txt index 0801c8ef42..ff2b15324d 100644 --- a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/boards_entry.txt +++ b/variants/STM32U5xx/U5F9NJHxQ/boards_entry.txt @@ -9,15 +9,6 @@ GenU5.menu.pnum.GENERIC_U5F9NJHXQ.upload.maximum_size=4194304 GenU5.menu.pnum.GENERIC_U5F9NJHXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F9NJHXQ.build.board=GENERIC_U5F9NJHXQ GenU5.menu.pnum.GENERIC_U5F9NJHXQ.build.product_line=STM32U5F9xx -GenU5.menu.pnum.GENERIC_U5F9NJHXQ.build.variant=STM32U5xx/U5F9NJHxQ_U5G9NJHxQ -GenU5.menu.pnum.GENERIC_U5F9NJHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd - -# Generic U5G9NJHxQ -GenU5.menu.pnum.GENERIC_U5G9NJHXQ=Generic U5G9NJHxQ -GenU5.menu.pnum.GENERIC_U5G9NJHXQ.upload.maximum_size=4194304 -GenU5.menu.pnum.GENERIC_U5G9NJHXQ.upload.maximum_data_size=3098624 -GenU5.menu.pnum.GENERIC_U5G9NJHXQ.build.board=GENERIC_U5G9NJHXQ -GenU5.menu.pnum.GENERIC_U5G9NJHXQ.build.product_line=STM32U5G9xx -GenU5.menu.pnum.GENERIC_U5G9NJHXQ.build.variant=STM32U5xx/U5F9NJHxQ_U5G9NJHxQ -GenU5.menu.pnum.GENERIC_U5G9NJHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd +GenU5.menu.pnum.GENERIC_U5F9NJHXQ.build.variant=STM32U5xx/U5F9NJHxQ +GenU5.menu.pnum.GENERIC_U5F9NJHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F9.svd diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/generic_clock.c b/variants/STM32U5xx/U5F9NJHxQ/generic_clock.c similarity index 91% rename from variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/generic_clock.c rename to variants/STM32U5xx/U5F9NJHxQ/generic_clock.c index ce4ed130df..5425cd99ae 100644 --- a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/generic_clock.c +++ b/variants/STM32U5xx/U5F9NJHxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F9NJHXQ) || defined(ARDUINO_GENERIC_U5G9NJHXQ) +#if defined(ARDUINO_GENERIC_U5F9NJHXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/variant_generic.cpp b/variants/STM32U5xx/U5F9NJHxQ/variant_generic.cpp similarity index 98% rename from variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/variant_generic.cpp rename to variants/STM32U5xx/U5F9NJHxQ/variant_generic.cpp index 9248b11cda..dc8d429bfe 100644 --- a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/variant_generic.cpp +++ b/variants/STM32U5xx/U5F9NJHxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F9NJHXQ) || defined(ARDUINO_GENERIC_U5G9NJHXQ) +#if defined(ARDUINO_GENERIC_U5F9NJHXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/variant_generic.h b/variants/STM32U5xx/U5F9NJHxQ/variant_generic.h similarity index 100% rename from variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/variant_generic.h rename to variants/STM32U5xx/U5F9NJHxQ/variant_generic.h diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/CMakeLists.txt b/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c new file mode 100644 index 0000000000..3c125de1cb --- /dev/null +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c @@ -0,0 +1,497 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U5F9VITxQ.xml, STM32U5F9VJTxQ.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PA_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_6_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PA_7_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC4_IN20 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC4_IN18 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PB_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC4_IN19 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PC_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PC_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PC_3_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_0, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PH_10, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_11, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_2, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PI_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PI_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PI_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PH_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PH_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO5 + {PI_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PH_11, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {PH_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PH_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PD_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_HS[] = { +#ifdef USE_USB_HS_IN_FS + {PA_8, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF + {PA_9, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID + {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM + {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF +#endif /* USE_USB_HS_IN_FS */ + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PA_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SDMMC2)}, // SDMMC2_D1 + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9V(I-J)TxQ/PinNamesVar.h similarity index 100% rename from variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PinNamesVar.h rename to variants/STM32U5xx/U5F9V(I-J)TxQ/PinNamesVar.h diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/boards_entry.txt b/variants/STM32U5xx/U5F9V(I-J)TxQ/boards_entry.txt similarity index 63% rename from variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/boards_entry.txt rename to variants/STM32U5xx/U5F9V(I-J)TxQ/boards_entry.txt index bd6c1ff635..560ff53dff 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/boards_entry.txt +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ/boards_entry.txt @@ -9,8 +9,8 @@ GenU5.menu.pnum.GENERIC_U5F9VITXQ.upload.maximum_size=2097152 GenU5.menu.pnum.GENERIC_U5F9VITXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F9VITXQ.build.board=GENERIC_U5F9VITXQ GenU5.menu.pnum.GENERIC_U5F9VITXQ.build.product_line=STM32U5F9xx -GenU5.menu.pnum.GENERIC_U5F9VITXQ.build.variant=STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ -GenU5.menu.pnum.GENERIC_U5F9VITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd +GenU5.menu.pnum.GENERIC_U5F9VITXQ.build.variant=STM32U5xx/U5F9V(I-J)TxQ +GenU5.menu.pnum.GENERIC_U5F9VITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F9.svd # Generic U5F9VJTxQ GenU5.menu.pnum.GENERIC_U5F9VJTXQ=Generic U5F9VJTxQ @@ -18,15 +18,6 @@ GenU5.menu.pnum.GENERIC_U5F9VJTXQ.upload.maximum_size=4194304 GenU5.menu.pnum.GENERIC_U5F9VJTXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F9VJTXQ.build.board=GENERIC_U5F9VJTXQ GenU5.menu.pnum.GENERIC_U5F9VJTXQ.build.product_line=STM32U5F9xx -GenU5.menu.pnum.GENERIC_U5F9VJTXQ.build.variant=STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ -GenU5.menu.pnum.GENERIC_U5F9VJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd - -# Generic U5G9VJTxQ -GenU5.menu.pnum.GENERIC_U5G9VJTXQ=Generic U5G9VJTxQ -GenU5.menu.pnum.GENERIC_U5G9VJTXQ.upload.maximum_size=4194304 -GenU5.menu.pnum.GENERIC_U5G9VJTXQ.upload.maximum_data_size=3098624 -GenU5.menu.pnum.GENERIC_U5G9VJTXQ.build.board=GENERIC_U5G9VJTXQ -GenU5.menu.pnum.GENERIC_U5G9VJTXQ.build.product_line=STM32U5G9xx -GenU5.menu.pnum.GENERIC_U5G9VJTXQ.build.variant=STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ -GenU5.menu.pnum.GENERIC_U5G9VJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd +GenU5.menu.pnum.GENERIC_U5F9VJTXQ.build.variant=STM32U5xx/U5F9V(I-J)TxQ +GenU5.menu.pnum.GENERIC_U5F9VJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F9.svd diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/generic_clock.c b/variants/STM32U5xx/U5F9V(I-J)TxQ/generic_clock.c similarity index 94% rename from variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/generic_clock.c rename to variants/STM32U5xx/U5F9V(I-J)TxQ/generic_clock.c index 2536c95134..faeaac1825 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/generic_clock.c +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F9VITXQ) || defined(ARDUINO_GENERIC_U5F9VJTXQ) ||\ - defined(ARDUINO_GENERIC_U5G9VJTXQ) +#if defined(ARDUINO_GENERIC_U5F9VITXQ) || defined(ARDUINO_GENERIC_U5F9VJTXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/variant_generic.cpp b/variants/STM32U5xx/U5F9V(I-J)TxQ/variant_generic.cpp similarity index 97% rename from variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/variant_generic.cpp rename to variants/STM32U5xx/U5F9V(I-J)TxQ/variant_generic.cpp index bcf5c32e9c..d97abfccb4 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/variant_generic.cpp +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F9VITXQ) || defined(ARDUINO_GENERIC_U5F9VJTXQ) ||\ - defined(ARDUINO_GENERIC_U5G9VJTXQ) +#if defined(ARDUINO_GENERIC_U5F9VITXQ) || defined(ARDUINO_GENERIC_U5F9VJTXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/variant_generic.h b/variants/STM32U5xx/U5F9V(I-J)TxQ/variant_generic.h similarity index 99% rename from variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/variant_generic.h rename to variants/STM32U5xx/U5F9V(I-J)TxQ/variant_generic.h index 3066b88d70..a8a08b28c3 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/variant_generic.h +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ/variant_generic.h @@ -196,6 +196,8 @@ #endif // SDMMC signals not available +#define SDMMC_CKIN_NA +#define SDMMC_CDIR_NA #define SDMMC_D0DIR_NA #define SDMMC_D123DIR_NA diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/CMakeLists.txt b/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c new file mode 100644 index 0000000000..3ec330e493 --- /dev/null +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c @@ -0,0 +1,642 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U5F9ZIJxQ.xml, STM32U5F9ZJJxQ.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PA_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_6_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PA_7_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC4_IN20 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC4_IN18 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PB_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC4_IN19 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PC_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PC_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PC_3_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PD_11, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC4_IN15 + {PD_12, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC4_IN16 + {PD_13, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC4_IN17 + {PG_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PG_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_11_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_0, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PG_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PG_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PG_9, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PG_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PH_10, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_11, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PF_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_2, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PF_1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PF_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO0 + {PI_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PF_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO1 + {PI_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PF_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO2 + {PI_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PG_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO4 + {PH_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PG_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO5 + {PH_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO5 + {PI_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PG_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {PH_11, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {PH_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PG_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO7 + {PH_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PB_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PD_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PG_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_HS[] = { +#ifdef USE_USB_HS_IN_FS + {PA_8, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF + {PA_9, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID + {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM + {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF +#endif /* USE_USB_HS_IN_FS */ + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PA_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SDMMC2)}, // SDMMC2_D1 + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5 + {PC_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9Z(I-J)JxQ/PinNamesVar.h similarity index 100% rename from variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PinNamesVar.h rename to variants/STM32U5xx/U5F9Z(I-J)JxQ/PinNamesVar.h diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/boards_entry.txt b/variants/STM32U5xx/U5F9Z(I-J)JxQ/boards_entry.txt similarity index 63% rename from variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/boards_entry.txt rename to variants/STM32U5xx/U5F9Z(I-J)JxQ/boards_entry.txt index d95d2d8f1c..03db0d61c2 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/boards_entry.txt +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ/boards_entry.txt @@ -9,8 +9,8 @@ GenU5.menu.pnum.GENERIC_U5F9ZIJXQ.upload.maximum_size=2097152 GenU5.menu.pnum.GENERIC_U5F9ZIJXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F9ZIJXQ.build.board=GENERIC_U5F9ZIJXQ GenU5.menu.pnum.GENERIC_U5F9ZIJXQ.build.product_line=STM32U5F9xx -GenU5.menu.pnum.GENERIC_U5F9ZIJXQ.build.variant=STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ -GenU5.menu.pnum.GENERIC_U5F9ZIJXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd +GenU5.menu.pnum.GENERIC_U5F9ZIJXQ.build.variant=STM32U5xx/U5F9Z(I-J)JxQ +GenU5.menu.pnum.GENERIC_U5F9ZIJXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F9.svd # Generic U5F9ZJJxQ GenU5.menu.pnum.GENERIC_U5F9ZJJXQ=Generic U5F9ZJJxQ @@ -18,15 +18,6 @@ GenU5.menu.pnum.GENERIC_U5F9ZJJXQ.upload.maximum_size=4194304 GenU5.menu.pnum.GENERIC_U5F9ZJJXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F9ZJJXQ.build.board=GENERIC_U5F9ZJJXQ GenU5.menu.pnum.GENERIC_U5F9ZJJXQ.build.product_line=STM32U5F9xx -GenU5.menu.pnum.GENERIC_U5F9ZJJXQ.build.variant=STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ -GenU5.menu.pnum.GENERIC_U5F9ZJJXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd - -# Generic U5G9ZJJxQ -GenU5.menu.pnum.GENERIC_U5G9ZJJXQ=Generic U5G9ZJJxQ -GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.upload.maximum_size=4194304 -GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.upload.maximum_data_size=3098624 -GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.build.board=GENERIC_U5G9ZJJXQ -GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.build.product_line=STM32U5G9xx -GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.build.variant=STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ -GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd +GenU5.menu.pnum.GENERIC_U5F9ZJJXQ.build.variant=STM32U5xx/U5F9Z(I-J)JxQ +GenU5.menu.pnum.GENERIC_U5F9ZJJXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F9.svd diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/generic_clock.c b/variants/STM32U5xx/U5F9Z(I-J)JxQ/generic_clock.c similarity index 94% rename from variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/generic_clock.c rename to variants/STM32U5xx/U5F9Z(I-J)JxQ/generic_clock.c index bf50637c5a..6158061ae9 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/generic_clock.c +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F9ZIJXQ) || defined(ARDUINO_GENERIC_U5F9ZJJXQ) ||\ - defined(ARDUINO_GENERIC_U5G9ZJJXQ) +#if defined(ARDUINO_GENERIC_U5F9ZIJXQ) || defined(ARDUINO_GENERIC_U5F9ZJJXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/variant_generic.cpp b/variants/STM32U5xx/U5F9Z(I-J)JxQ/variant_generic.cpp similarity index 98% rename from variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/variant_generic.cpp rename to variants/STM32U5xx/U5F9Z(I-J)JxQ/variant_generic.cpp index d090f3aba4..0a2f95c625 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/variant_generic.cpp +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F9ZIJXQ) || defined(ARDUINO_GENERIC_U5F9ZJJXQ) ||\ - defined(ARDUINO_GENERIC_U5G9ZJJXQ) +#if defined(ARDUINO_GENERIC_U5F9ZIJXQ) || defined(ARDUINO_GENERIC_U5F9ZJJXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/variant_generic.h b/variants/STM32U5xx/U5F9Z(I-J)JxQ/variant_generic.h similarity index 100% rename from variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/variant_generic.h rename to variants/STM32U5xx/U5F9Z(I-J)JxQ/variant_generic.h diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/CMakeLists.txt b/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c new file mode 100644 index 0000000000..9de12e9ffc --- /dev/null +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c @@ -0,0 +1,642 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U5F9ZITxQ.xml, STM32U5F9ZJTxQ.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PA_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_6_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PA_7_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC4_IN20 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC4_IN18 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PB_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC4_IN19 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PB_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PC_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PC_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PC_3_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PD_11, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC4_IN15 + {PD_12, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC4_IN16 + {PD_13, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC4_IN17 + {PG_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PG_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_11_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_0, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PG_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)}, + {PG_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PG_9, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PG_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PH_10, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_11, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PF_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_2, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PF_1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PE_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {PF_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO0 + {PI_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {PF_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO1 + {PI_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {PF_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO2 + {PI_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4 + {PG_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO4 + {PH_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {PG_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO5 + {PH_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO5 + {PI_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6 + {PG_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {PH_11, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {PH_15, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7 + {PG_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO7 + {PH_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PB_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PD_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PG_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_HS[] = { +#ifdef USE_USB_HS_IN_FS + {PA_8, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF + {PA_9, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID + {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM + {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF +#endif /* USE_USB_HS_IN_FS */ + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PA_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SDMMC2)}, // SDMMC2_D1 + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5 + {PC_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9Z(I-J)TxQ/PinNamesVar.h similarity index 100% rename from variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PinNamesVar.h rename to variants/STM32U5xx/U5F9Z(I-J)TxQ/PinNamesVar.h diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/boards_entry.txt b/variants/STM32U5xx/U5F9Z(I-J)TxQ/boards_entry.txt similarity index 63% rename from variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/boards_entry.txt rename to variants/STM32U5xx/U5F9Z(I-J)TxQ/boards_entry.txt index 1af2425160..7b4556b3ec 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/boards_entry.txt +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ/boards_entry.txt @@ -9,8 +9,8 @@ GenU5.menu.pnum.GENERIC_U5F9ZITXQ.upload.maximum_size=2097152 GenU5.menu.pnum.GENERIC_U5F9ZITXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F9ZITXQ.build.board=GENERIC_U5F9ZITXQ GenU5.menu.pnum.GENERIC_U5F9ZITXQ.build.product_line=STM32U5F9xx -GenU5.menu.pnum.GENERIC_U5F9ZITXQ.build.variant=STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ -GenU5.menu.pnum.GENERIC_U5F9ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd +GenU5.menu.pnum.GENERIC_U5F9ZITXQ.build.variant=STM32U5xx/U5F9Z(I-J)TxQ +GenU5.menu.pnum.GENERIC_U5F9ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F9.svd # Generic U5F9ZJTxQ GenU5.menu.pnum.GENERIC_U5F9ZJTXQ=Generic U5F9ZJTxQ @@ -18,15 +18,6 @@ GenU5.menu.pnum.GENERIC_U5F9ZJTXQ.upload.maximum_size=4194304 GenU5.menu.pnum.GENERIC_U5F9ZJTXQ.upload.maximum_data_size=3098624 GenU5.menu.pnum.GENERIC_U5F9ZJTXQ.build.board=GENERIC_U5F9ZJTXQ GenU5.menu.pnum.GENERIC_U5F9ZJTXQ.build.product_line=STM32U5F9xx -GenU5.menu.pnum.GENERIC_U5F9ZJTXQ.build.variant=STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ -GenU5.menu.pnum.GENERIC_U5F9ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Fx.svd - -# Generic U5G9ZJTxQ -GenU5.menu.pnum.GENERIC_U5G9ZJTXQ=Generic U5G9ZJTxQ -GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.upload.maximum_size=4194304 -GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.upload.maximum_data_size=3098624 -GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.build.board=GENERIC_U5G9ZJTXQ -GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.build.product_line=STM32U5G9xx -GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.build.variant=STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ -GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd +GenU5.menu.pnum.GENERIC_U5F9ZJTXQ.build.variant=STM32U5xx/U5F9Z(I-J)TxQ +GenU5.menu.pnum.GENERIC_U5F9ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5F9.svd diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/generic_clock.c b/variants/STM32U5xx/U5F9Z(I-J)TxQ/generic_clock.c similarity index 94% rename from variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/generic_clock.c rename to variants/STM32U5xx/U5F9Z(I-J)TxQ/generic_clock.c index 7d2bd459a1..9a76b19a3e 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/generic_clock.c +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F9ZITXQ) || defined(ARDUINO_GENERIC_U5F9ZJTXQ) ||\ - defined(ARDUINO_GENERIC_U5G9ZJTXQ) +#if defined(ARDUINO_GENERIC_U5F9ZITXQ) || defined(ARDUINO_GENERIC_U5F9ZJTXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/variant_generic.cpp b/variants/STM32U5xx/U5F9Z(I-J)TxQ/variant_generic.cpp similarity index 98% rename from variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/variant_generic.cpp rename to variants/STM32U5xx/U5F9Z(I-J)TxQ/variant_generic.cpp index 89363ea175..95502cfa19 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/variant_generic.cpp +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_U5F9ZITXQ) || defined(ARDUINO_GENERIC_U5F9ZJTXQ) ||\ - defined(ARDUINO_GENERIC_U5G9ZJTXQ) +#if defined(ARDUINO_GENERIC_U5F9ZITXQ) || defined(ARDUINO_GENERIC_U5F9ZJTXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/variant_generic.h b/variants/STM32U5xx/U5F9Z(I-J)TxQ/variant_generic.h similarity index 100% rename from variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/variant_generic.h rename to variants/STM32U5xx/U5F9Z(I-J)TxQ/variant_generic.h diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/CMakeLists.txt b/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c b/variants/STM32U5xx/U5G7VJT/PeripheralPins.c similarity index 99% rename from variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c rename to variants/STM32U5xx/U5G7VJT/PeripheralPins.c index c9a0a459fc..01089ec025 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U5G7VJT/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32U5F7VITx.xml, STM32U5F7VJTx.xml - * STM32U5G7VJTx.xml - * CubeMX DB release 6.0.120 + * Automatically generated from STM32U5G7VJTx.xml + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G7VJT/PinNamesVar.h b/variants/STM32U5xx/U5G7VJT/PinNamesVar.h new file mode 100644 index 0000000000..c1062b7395 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJT/PinNamesVar.h @@ -0,0 +1,141 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_6_ALT2 = PA_6 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_0_ALT2 = PC_0 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_1_ALT2 = PC_1 | ALT2, +PC_2_ALT1 = PC_2 | ALT1, +PC_2_ALT2 = PC_2 | ALT2, +PC_3_ALT1 = PC_3 | ALT1, +PC_3_ALT2 = PC_3 | ALT2, +PC_4_ALT1 = PC_4 | ALT1, +PC_4_ALT2 = PC_4 | ALT2, +PC_5_ALT1 = PC_5 | ALT1, +PC_5_ALT2 = PC_5 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PD_0_ALT1 = PD_0 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PE_5, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_2 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PC_5, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_2 = PB_8, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PE_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_2 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PE_8, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_OTG_HS_DM = PA_11, + USB_OTG_HS_DP = PA_12, + USB_OTG_HS_ID = PA_10, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif + USB_OTG_HS_VBUS = PA_9, +#endif diff --git a/variants/STM32U5xx/U5G7VJT/boards_entry.txt b/variants/STM32U5xx/U5G7VJT/boards_entry.txt new file mode 100644 index 0000000000..d278cddcb2 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJT/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U5G7VJTx +GenU5.menu.pnum.GENERIC_U5G7VJTX=Generic U5G7VJTx +GenU5.menu.pnum.GENERIC_U5G7VJTX.upload.maximum_size=4194304 +GenU5.menu.pnum.GENERIC_U5G7VJTX.upload.maximum_data_size=3098624 +GenU5.menu.pnum.GENERIC_U5G7VJTX.build.board=GENERIC_U5G7VJTX +GenU5.menu.pnum.GENERIC_U5G7VJTX.build.product_line=STM32U5G7xx +GenU5.menu.pnum.GENERIC_U5G7VJTX.build.variant=STM32U5xx/U5G7VJT +GenU5.menu.pnum.GENERIC_U5G7VJTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd + diff --git a/variants/STM32U5xx/U5G7VJT/generic_clock.c b/variants/STM32U5xx/U5G7VJT/generic_clock.c new file mode 100644 index 0000000000..48f675554d --- /dev/null +++ b/variants/STM32U5xx/U5G7VJT/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G7VJTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G7VJT/variant_generic.cpp b/variants/STM32U5xx/U5G7VJT/variant_generic.cpp new file mode 100644 index 0000000000..fa0a8608d8 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJT/variant_generic.cpp @@ -0,0 +1,126 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G7VJTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58/A17 + PD_12, // D59/A18 + PD_13, // D60/A19 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70 + PE_8, // D71 + PE_9, // D72 + PE_10, // D73 + PE_11, // D74 + PE_12, // D75 + PE_13, // D76 + PE_14, // D77 + PE_15, // D78 + PH_0, // D79 + PH_1, // D80 + PH_3 // D81 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 58, // A17, PD11 + 59, // A18, PD12 + 60 // A19, PD13 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G7VJT/variant_generic.h b/variants/STM32U5xx/U5G7VJT/variant_generic.h new file mode 100644 index 0000000000..ec0d384eee --- /dev/null +++ b/variants/STM32U5xx/U5G7VJT/variant_generic.h @@ -0,0 +1,279 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 PIN_A17 +#define PD12 PIN_A18 +#define PD13 PIN_A19 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 70 +#define PE8 71 +#define PE9 72 +#define PE10 73 +#define PE11 74 +#define PE12 75 +#define PE13 76 +#define PE14 77 +#define PE15 78 +#define PH0 79 +#define PH1 80 +#define PH3 81 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA6_ALT2 (PA6 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC0_ALT2 (PC0 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC1_ALT2 (PC1 | ALT2) +#define PC2_ALT1 (PC2 | ALT1) +#define PC2_ALT2 (PC2 | ALT2) +#define PC3_ALT1 (PC3 | ALT1) +#define PC3_ALT2 (PC3 | ALT2) +#define PC4_ALT1 (PC4 | ALT1) +#define PC4_ALT2 (PC4 | ALT2) +#define PC5_ALT1 (PC5 | ALT1) +#define PC5_ALT2 (PC5 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD0_ALT1 (PD0 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) + +#define NUM_DIGITAL_PINS 82 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN5_2 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c similarity index 99% rename from variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c rename to variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c index f9535973d2..764dd19937 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32U5F7VITxQ.xml, STM32U5F7VJTxQ.xml - * STM32U5G7VJTxQ.xml - * CubeMX DB release 6.0.120 + * Automatically generated from STM32U5G7VJTxQ.xml + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G7VJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5G7VJTxQ/PinNamesVar.h new file mode 100644 index 0000000000..cd5687d087 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJTxQ/PinNamesVar.h @@ -0,0 +1,135 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_6_ALT2 = PA_6 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_0_ALT2 = PC_0 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_1_ALT2 = PC_1 | ALT2, +PC_2_ALT1 = PC_2 | ALT1, +PC_2_ALT2 = PC_2 | ALT2, +PC_3_ALT1 = PC_3 | ALT1, +PC_3_ALT2 = PC_3 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PD_0_ALT1 = PD_0 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PE_5, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_2 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PE_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_2 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PE_8, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_OTG_HS_DM = PA_11, + USB_OTG_HS_DP = PA_12, + USB_OTG_HS_ID = PA_10, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif + USB_OTG_HS_VBUS = PA_9, +#endif diff --git a/variants/STM32U5xx/U5G7VJTxQ/boards_entry.txt b/variants/STM32U5xx/U5G7VJTxQ/boards_entry.txt new file mode 100644 index 0000000000..8b93c7ddb8 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJTxQ/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U5G7VJTxQ +GenU5.menu.pnum.GENERIC_U5G7VJTXQ=Generic U5G7VJTxQ +GenU5.menu.pnum.GENERIC_U5G7VJTXQ.upload.maximum_size=4194304 +GenU5.menu.pnum.GENERIC_U5G7VJTXQ.upload.maximum_data_size=3098624 +GenU5.menu.pnum.GENERIC_U5G7VJTXQ.build.board=GENERIC_U5G7VJTXQ +GenU5.menu.pnum.GENERIC_U5G7VJTXQ.build.product_line=STM32U5G7xx +GenU5.menu.pnum.GENERIC_U5G7VJTXQ.build.variant=STM32U5xx/U5G7VJTxQ +GenU5.menu.pnum.GENERIC_U5G7VJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd + diff --git a/variants/STM32U5xx/U5G7VJTxQ/generic_clock.c b/variants/STM32U5xx/U5G7VJTxQ/generic_clock.c new file mode 100644 index 0000000000..b9def588c5 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJTxQ/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G7VJTXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G7VJTxQ/variant_generic.cpp b/variants/STM32U5xx/U5G7VJTxQ/variant_generic.cpp new file mode 100644 index 0000000000..6c0c00b100 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJTxQ/variant_generic.cpp @@ -0,0 +1,121 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G7VJTXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_6, // D35 + PC_7, // D36 + PC_8, // D37 + PC_9, // D38 + PC_10, // D39 + PC_11, // D40 + PC_12, // D41 + PC_13, // D42 + PC_14, // D43 + PC_15, // D44 + PD_0, // D45 + PD_1, // D46 + PD_2, // D47 + PD_3, // D48 + PD_4, // D49 + PD_5, // D50 + PD_6, // D51 + PD_7, // D52 + PD_8, // D53 + PD_9, // D54 + PD_10, // D55 + PD_11, // D56/A15 + PD_12, // D57/A16 + PD_13, // D58/A17 + PD_14, // D59 + PD_15, // D60 + PE_0, // D61 + PE_2, // D62 + PE_3, // D63 + PE_4, // D64 + PE_5, // D65 + PE_6, // D66 + PE_7, // D67 + PE_8, // D68 + PE_9, // D69 + PE_10, // D70 + PE_11, // D71 + PE_12, // D72 + PE_13, // D73 + PE_14, // D74 + PE_15, // D75 + PH_0, // D76 + PH_1, // D77 + PH_3 // D78 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 56, // A15, PD11 + 57, // A16, PD12 + 58 // A17, PD13 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G7VJTxQ/variant_generic.h b/variants/STM32U5xx/U5G7VJTxQ/variant_generic.h new file mode 100644 index 0000000000..c2137766bd --- /dev/null +++ b/variants/STM32U5xx/U5G7VJTxQ/variant_generic.h @@ -0,0 +1,272 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC6 35 +#define PC7 36 +#define PC8 37 +#define PC9 38 +#define PC10 39 +#define PC11 40 +#define PC12 41 +#define PC13 42 +#define PC14 43 +#define PC15 44 +#define PD0 45 +#define PD1 46 +#define PD2 47 +#define PD3 48 +#define PD4 49 +#define PD5 50 +#define PD6 51 +#define PD7 52 +#define PD8 53 +#define PD9 54 +#define PD10 55 +#define PD11 PIN_A15 +#define PD12 PIN_A16 +#define PD13 PIN_A17 +#define PD14 59 +#define PD15 60 +#define PE0 61 +#define PE2 62 +#define PE3 63 +#define PE4 64 +#define PE5 65 +#define PE6 66 +#define PE7 67 +#define PE8 68 +#define PE9 69 +#define PE10 70 +#define PE11 71 +#define PE12 72 +#define PE13 73 +#define PE14 74 +#define PE15 75 +#define PH0 76 +#define PH1 77 +#define PH3 78 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA6_ALT2 (PA6 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC0_ALT2 (PC0 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC1_ALT2 (PC1 | ALT2) +#define PC2_ALT1 (PC2 | ALT1) +#define PC2_ALT2 (PC2 | ALT2) +#define PC3_ALT1 (PC3 | ALT1) +#define PC3_ALT2 (PC3 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD0_ALT1 (PD0 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) + +#define NUM_DIGITAL_PINS 79 +#define NUM_ANALOG_INPUTS 18 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c similarity index 99% rename from variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c rename to variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c index 17a03d10a3..201c2ca974 100644 --- a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32U5F9NJHxQ.xml, STM32U5G9NJHxQ.xml - * CubeMX DB release 6.0.120 + * Automatically generated from STM32U5G9NJHxQ.xml + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9NJHxQ/PinNamesVar.h b/variants/STM32U5xx/U5G9NJHxQ/PinNamesVar.h new file mode 100644 index 0000000000..c8d62f315c --- /dev/null +++ b/variants/STM32U5xx/U5G9NJHxQ/PinNamesVar.h @@ -0,0 +1,149 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_6_ALT2 = PA_6 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_0_ALT2 = PC_0 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_1_ALT2 = PC_1 | ALT2, +PC_2_ALT1 = PC_2 | ALT1, +PC_2_ALT2 = PC_2 | ALT2, +PC_3_ALT1 = PC_3 | ALT1, +PC_3_ALT2 = PC_3 | ALT2, +PC_4_ALT1 = PC_4 | ALT1, +PC_4_ALT2 = PC_4 | ALT2, +PC_5_ALT1 = PC_5 | ALT1, +PC_5_ALT2 = PC_5 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PD_0_ALT1 = PD_0 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PF_0_ALT1 = PF_0 | ALT1, +PF_1_ALT1 = PF_1 | ALT1, +PF_9_ALT1 = PF_9 | ALT1, +PH_12_ALT1 = PH_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PE_5, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_2 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_2 = PC_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PE_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_2 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PE_8, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PF_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_10, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_2 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_OTG_HS_DM = PA_11, + USB_OTG_HS_DP = PA_12, + USB_OTG_HS_ID = PA_10, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif + USB_OTG_HS_VBUS = PA_9, +#endif diff --git a/variants/STM32U5xx/U5G9NJHxQ/boards_entry.txt b/variants/STM32U5xx/U5G9NJHxQ/boards_entry.txt new file mode 100644 index 0000000000..f26fdae5a2 --- /dev/null +++ b/variants/STM32U5xx/U5G9NJHxQ/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U5G9NJHxQ +GenU5.menu.pnum.GENERIC_U5G9NJHXQ=Generic U5G9NJHxQ +GenU5.menu.pnum.GENERIC_U5G9NJHXQ.upload.maximum_size=4194304 +GenU5.menu.pnum.GENERIC_U5G9NJHXQ.upload.maximum_data_size=3098624 +GenU5.menu.pnum.GENERIC_U5G9NJHXQ.build.board=GENERIC_U5G9NJHXQ +GenU5.menu.pnum.GENERIC_U5G9NJHXQ.build.product_line=STM32U5G9xx +GenU5.menu.pnum.GENERIC_U5G9NJHXQ.build.variant=STM32U5xx/U5G9NJHxQ +GenU5.menu.pnum.GENERIC_U5G9NJHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd + diff --git a/variants/STM32U5xx/U5G9NJHxQ/generic_clock.c b/variants/STM32U5xx/U5G9NJHxQ/generic_clock.c new file mode 100644 index 0000000000..0be85f7601 --- /dev/null +++ b/variants/STM32U5xx/U5G9NJHxQ/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G9NJHXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G9NJHxQ/variant_generic.cpp b/variants/STM32U5xx/U5G9NJHxQ/variant_generic.cpp new file mode 100644 index 0000000000..2623586c42 --- /dev/null +++ b/variants/STM32U5xx/U5G9NJHxQ/variant_generic.cpp @@ -0,0 +1,204 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G9NJHXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32/A11 + PC_1, // D33/A12 + PC_2, // D34/A13 + PC_3, // D35/A14 + PC_4, // D36/A15 + PC_5, // D37/A16 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_3, // D51 + PD_4, // D52 + PD_5, // D53 + PD_6, // D54 + PD_7, // D55 + PD_8, // D56 + PD_9, // D57 + PD_10, // D58 + PD_11, // D59/A17 + PD_12, // D60/A18 + PD_13, // D61/A19 + PD_14, // D62 + PD_15, // D63 + PE_0, // D64 + PE_1, // D65 + PE_2, // D66 + PE_3, // D67 + PE_4, // D68 + PE_5, // D69 + PE_6, // D70 + PE_7, // D71 + PE_8, // D72 + PE_9, // D73 + PE_10, // D74 + PE_11, // D75 + PE_12, // D76 + PE_13, // D77 + PE_14, // D78 + PE_15, // D79 + PF_0, // D80 + PF_1, // D81 + PF_2, // D82 + PF_3, // D83 + PF_4, // D84 + PF_5, // D85 + PF_6, // D86 + PF_7, // D87 + PF_8, // D88 + PF_9, // D89 + PF_10, // D90 + PF_11, // D91 + PF_12, // D92 + PF_13, // D93 + PF_14, // D94/A20 + PF_15, // D95/A21 + PG_0, // D96/A22 + PG_1, // D97/A23 + PG_2, // D98 + PG_3, // D99 + PG_4, // D100 + PG_5, // D101 + PG_6, // D102 + PG_7, // D103 + PG_8, // D104 + PG_9, // D105 + PG_10, // D106 + PG_11, // D107 + PG_12, // D108 + PG_13, // D109 + PG_14, // D110 + PG_15, // D111 + PH_0, // D112 + PH_1, // D113 + PH_2, // D114 + PH_3, // D115 + PH_4, // D116 + PH_5, // D117 + PH_6, // D118 + PH_7, // D119 + PH_8, // D120 + PH_9, // D121 + PH_10, // D122 + PH_11, // D123 + PH_12, // D124 + PH_13, // D125 + PH_14, // D126 + PH_15, // D127 + PI_0, // D128 + PI_1, // D129 + PI_2, // D130 + PI_3, // D131 + PI_4, // D132 + PI_5, // D133 + PI_6, // D134 + PI_7, // D135 + PI_8, // D136 + PI_9, // D137 + PI_10, // D138 + PI_11, // D139 + PI_12, // D140 + PI_13, // D141 + PI_14, // D142 + PI_15, // D143 + PJ_0, // D144 + PJ_1, // D145 + PJ_2, // D146 + PJ_3, // D147 + PJ_4, // D148 + PJ_5, // D149 + PJ_6, // D150 + PJ_7, // D151 + PJ_8, // D152 + PJ_9, // D153 + PJ_10, // D154 + PJ_11 // D155 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 32, // A11, PC0 + 33, // A12, PC1 + 34, // A13, PC2 + 35, // A14, PC3 + 36, // A15, PC4 + 37, // A16, PC5 + 59, // A17, PD11 + 60, // A18, PD12 + 61, // A19, PD13 + 94, // A20, PF14 + 95, // A21, PF15 + 96, // A22, PG0 + 97 // A23, PG1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G9NJHxQ/variant_generic.h b/variants/STM32U5xx/U5G9NJHxQ/variant_generic.h new file mode 100644 index 0000000000..f139f3ee63 --- /dev/null +++ b/variants/STM32U5xx/U5G9NJHxQ/variant_generic.h @@ -0,0 +1,359 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 PIN_A17 +#define PD12 PIN_A18 +#define PD13 PIN_A19 +#define PD14 62 +#define PD15 63 +#define PE0 64 +#define PE1 65 +#define PE2 66 +#define PE3 67 +#define PE4 68 +#define PE5 69 +#define PE6 70 +#define PE7 71 +#define PE8 72 +#define PE9 73 +#define PE10 74 +#define PE11 75 +#define PE12 76 +#define PE13 77 +#define PE14 78 +#define PE15 79 +#define PF0 80 +#define PF1 81 +#define PF2 82 +#define PF3 83 +#define PF4 84 +#define PF5 85 +#define PF6 86 +#define PF7 87 +#define PF8 88 +#define PF9 89 +#define PF10 90 +#define PF11 91 +#define PF12 92 +#define PF13 93 +#define PF14 PIN_A20 +#define PF15 PIN_A21 +#define PG0 PIN_A22 +#define PG1 PIN_A23 +#define PG2 98 +#define PG3 99 +#define PG4 100 +#define PG5 101 +#define PG6 102 +#define PG7 103 +#define PG8 104 +#define PG9 105 +#define PG10 106 +#define PG11 107 +#define PG12 108 +#define PG13 109 +#define PG14 110 +#define PG15 111 +#define PH0 112 +#define PH1 113 +#define PH2 114 +#define PH3 115 +#define PH4 116 +#define PH5 117 +#define PH6 118 +#define PH7 119 +#define PH8 120 +#define PH9 121 +#define PH10 122 +#define PH11 123 +#define PH12 124 +#define PH13 125 +#define PH14 126 +#define PH15 127 +#define PI0 128 +#define PI1 129 +#define PI2 130 +#define PI3 131 +#define PI4 132 +#define PI5 133 +#define PI6 134 +#define PI7 135 +#define PI8 136 +#define PI9 137 +#define PI10 138 +#define PI11 139 +#define PI12 140 +#define PI13 141 +#define PI14 142 +#define PI15 143 +#define PJ0 144 +#define PJ1 145 +#define PJ2 146 +#define PJ3 147 +#define PJ4 148 +#define PJ5 149 +#define PJ6 150 +#define PJ7 151 +#define PJ8 152 +#define PJ9 153 +#define PJ10 154 +#define PJ11 155 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA6_ALT2 (PA6 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC0_ALT2 (PC0 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC1_ALT2 (PC1 | ALT2) +#define PC2_ALT1 (PC2 | ALT1) +#define PC2_ALT2 (PC2 | ALT2) +#define PC3_ALT1 (PC3 | ALT1) +#define PC3_ALT2 (PC3 | ALT2) +#define PC4_ALT1 (PC4 | ALT1) +#define PC4_ALT2 (PC4 | ALT2) +#define PC5_ALT1 (PC5 | ALT1) +#define PC5_ALT2 (PC5 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD0_ALT1 (PD0 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PF0_ALT1 (PF0 | ALT1) +#define PF1_ALT1 (PF1 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PH12_ALT1 (PH12 | ALT1) + +#define NUM_DIGITAL_PINS 156 +#define NUM_ANALOG_INPUTS 24 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN5_2 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 +#define PWR_WAKEUP_PIN8_2 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c similarity index 94% rename from variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c rename to variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c index 06297f761c..ac801f1a50 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32U5F9VITxQ.xml, STM32U5F9VJTxQ.xml - * STM32U5G9VJTxQ.xml - * CubeMX DB release 6.0.120 + * Automatically generated from STM32U5G9VJTxQ.xml + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -461,16 +460,14 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { #ifdef HAL_SD_MODULE_ENABLED WEAK const PinMap PinMap_SD_CMD[] = { {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD {NC, NP, 0} }; #endif #ifdef HAL_SD_MODULE_ENABLED WEAK const PinMap PinMap_SD_CK[] = { - {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {NC, NP, 0} + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} }; #endif @@ -491,47 +488,28 @@ WEAK const PinMap PinMap_SD_DATA1[] = { #ifdef HAL_SD_MODULE_ENABLED WEAK const PinMap PinMap_SD_DATA2[] = { - {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {NC, NP, 0} + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 + {NC, NP, 0} }; #endif #ifdef HAL_SD_MODULE_ENABLED WEAK const PinMap PinMap_SD_DATA3[] = { - {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {NC, NP, 0} + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} }; #endif #ifdef HAL_SD_MODULE_ENABLED WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5 - {PC_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CKIN + {PB_8, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4 {NC, NP, 0} }; #endif #ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CDIR +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5 {NC, NP, 0} }; #endif diff --git a/variants/STM32U5xx/U5G9VJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5G9VJTxQ/PinNamesVar.h new file mode 100644 index 0000000000..b43d93664c --- /dev/null +++ b/variants/STM32U5xx/U5G9VJTxQ/PinNamesVar.h @@ -0,0 +1,118 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_6_ALT2 = PA_6 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_0_ALT2 = PC_0 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_1_ALT2 = PC_1 | ALT2, +PC_2_ALT1 = PC_2 | ALT1, +PC_2_ALT2 = PC_2 | ALT2, +PC_3_ALT1 = PC_3 | ALT1, +PC_3_ALT2 = PC_3 | ALT2, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PD_0_ALT1 = PD_0 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PH_12_ALT1 = PH_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PE_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_2 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PE_8, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_OTG_HS_DM = PA_11, + USB_OTG_HS_DP = PA_12, + USB_OTG_HS_ID = PA_10, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif + USB_OTG_HS_VBUS = PA_9, +#endif diff --git a/variants/STM32U5xx/U5G9VJTxQ/boards_entry.txt b/variants/STM32U5xx/U5G9VJTxQ/boards_entry.txt new file mode 100644 index 0000000000..b1865c44be --- /dev/null +++ b/variants/STM32U5xx/U5G9VJTxQ/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U5G9VJTxQ +GenU5.menu.pnum.GENERIC_U5G9VJTXQ=Generic U5G9VJTxQ +GenU5.menu.pnum.GENERIC_U5G9VJTXQ.upload.maximum_size=4194304 +GenU5.menu.pnum.GENERIC_U5G9VJTXQ.upload.maximum_data_size=3098624 +GenU5.menu.pnum.GENERIC_U5G9VJTXQ.build.board=GENERIC_U5G9VJTXQ +GenU5.menu.pnum.GENERIC_U5G9VJTXQ.build.product_line=STM32U5G9xx +GenU5.menu.pnum.GENERIC_U5G9VJTXQ.build.variant=STM32U5xx/U5G9VJTxQ +GenU5.menu.pnum.GENERIC_U5G9VJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd + diff --git a/variants/STM32U5xx/U5G9VJTxQ/generic_clock.c b/variants/STM32U5xx/U5G9VJTxQ/generic_clock.c new file mode 100644 index 0000000000..c2e0899a04 --- /dev/null +++ b/variants/STM32U5xx/U5G9VJTxQ/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G9VJTXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G9VJTxQ/variant_generic.cpp b/variants/STM32U5xx/U5G9VJTxQ/variant_generic.cpp new file mode 100644 index 0000000000..952124c36f --- /dev/null +++ b/variants/STM32U5xx/U5G9VJTxQ/variant_generic.cpp @@ -0,0 +1,102 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G9VJTXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_13, // D26 + PB_14, // D27 + PB_15, // D28 + PC_0, // D29/A11 + PC_1, // D30/A12 + PC_2, // D31/A13 + PC_3, // D32/A14 + PC_10, // D33 + PC_11, // D34 + PC_12, // D35 + PC_13, // D36 + PC_14, // D37 + PC_15, // D38 + PD_0, // D39 + PD_1, // D40 + PD_2, // D41 + PD_3, // D42 + PD_4, // D43 + PD_5, // D44 + PE_7, // D45 + PE_8, // D46 + PE_9, // D47 + PE_10, // D48 + PH_0, // D49 + PH_1, // D50 + PH_3, // D51 + PH_9, // D52 + PH_10, // D53 + PH_11, // D54 + PH_12, // D55 + PH_13, // D56 + PH_14, // D57 + PH_15, // D58 + PI_0, // D59 + PI_1, // D60 + PI_2, // D61 + PI_3 // D62 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 29, // A11, PC0 + 30, // A12, PC1 + 31, // A13, PC2 + 32 // A14, PC3 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G9VJTxQ/variant_generic.h b/variants/STM32U5xx/U5G9VJTxQ/variant_generic.h new file mode 100644 index 0000000000..a8a08b28c3 --- /dev/null +++ b/variants/STM32U5xx/U5G9VJTxQ/variant_generic.h @@ -0,0 +1,253 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB13 26 +#define PB14 27 +#define PB15 28 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC10 33 +#define PC11 34 +#define PC12 35 +#define PC13 36 +#define PC14 37 +#define PC15 38 +#define PD0 39 +#define PD1 40 +#define PD2 41 +#define PD3 42 +#define PD4 43 +#define PD5 44 +#define PE7 45 +#define PE8 46 +#define PE9 47 +#define PE10 48 +#define PH0 49 +#define PH1 50 +#define PH3 51 +#define PH9 52 +#define PH10 53 +#define PH11 54 +#define PH12 55 +#define PH13 56 +#define PH14 57 +#define PH15 58 +#define PI0 59 +#define PI1 60 +#define PI2 61 +#define PI3 62 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA6_ALT2 (PA6 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC0_ALT2 (PC0 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC1_ALT2 (PC1 | ALT2) +#define PC2_ALT1 (PC2 | ALT1) +#define PC2_ALT2 (PC2 | ALT2) +#define PC3_ALT1 (PC3 | ALT1) +#define PC3_ALT2 (PC3 | ALT2) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD0_ALT1 (PD0 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PH12_ALT1 (PH12 | ALT1) + +#define NUM_DIGITAL_PINS 63 +#define NUM_ANALOG_INPUTS 15 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// SDMMC signals not available +#define SDMMC_CKIN_NA +#define SDMMC_CDIR_NA +#define SDMMC_D0DIR_NA +#define SDMMC_D123DIR_NA + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c similarity index 99% rename from variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c rename to variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c index 3293cfab1d..99fdd02bdd 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32U5F9ZITxQ.xml, STM32U5F9ZJTxQ.xml - * STM32U5G9ZJTxQ.xml - * CubeMX DB release 6.0.120 + * Automatically generated from STM32U5G9ZJJxQ.xml + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9ZJJxQ/PinNamesVar.h b/variants/STM32U5xx/U5G9ZJJxQ/PinNamesVar.h new file mode 100644 index 0000000000..dea12a7967 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJJxQ/PinNamesVar.h @@ -0,0 +1,141 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_6_ALT2 = PA_6 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_0_ALT2 = PC_0 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_1_ALT2 = PC_1 | ALT2, +PC_2_ALT1 = PC_2 | ALT1, +PC_2_ALT2 = PC_2 | ALT2, +PC_3_ALT1 = PC_3 | ALT1, +PC_3_ALT2 = PC_3 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PD_0_ALT1 = PD_0 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PF_0_ALT1 = PF_0 | ALT1, +PF_1_ALT1 = PF_1 | ALT1, +PH_12_ALT1 = PH_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PE_5, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_2 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_2 = PE_7, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PE_8, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PF_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_10, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_2 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_OTG_HS_DM = PA_11, + USB_OTG_HS_DP = PA_12, + USB_OTG_HS_ID = PA_10, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif + USB_OTG_HS_VBUS = PA_9, +#endif diff --git a/variants/STM32U5xx/U5G9ZJJxQ/boards_entry.txt b/variants/STM32U5xx/U5G9ZJJxQ/boards_entry.txt new file mode 100644 index 0000000000..034870e360 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJJxQ/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U5G9ZJJxQ +GenU5.menu.pnum.GENERIC_U5G9ZJJXQ=Generic U5G9ZJJxQ +GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.upload.maximum_size=4194304 +GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.upload.maximum_data_size=3098624 +GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.build.board=GENERIC_U5G9ZJJXQ +GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.build.product_line=STM32U5G9xx +GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.build.variant=STM32U5xx/U5G9ZJJxQ +GenU5.menu.pnum.GENERIC_U5G9ZJJXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd + diff --git a/variants/STM32U5xx/U5G9ZJJxQ/generic_clock.c b/variants/STM32U5xx/U5G9ZJJxQ/generic_clock.c new file mode 100644 index 0000000000..14098e5f25 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJJxQ/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G9ZJJXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G9ZJJxQ/variant_generic.cpp b/variants/STM32U5xx/U5G9ZJJxQ/variant_generic.cpp new file mode 100644 index 0000000000..e4733f4290 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJJxQ/variant_generic.cpp @@ -0,0 +1,145 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G9ZJJXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_6, // D35 + PC_7, // D36 + PC_8, // D37 + PC_9, // D38 + PC_10, // D39 + PC_11, // D40 + PC_12, // D41 + PC_13, // D42 + PC_14, // D43 + PC_15, // D44 + PD_0, // D45 + PD_1, // D46 + PD_2, // D47 + PD_3, // D48 + PD_4, // D49 + PD_5, // D50 + PD_6, // D51 + PD_7, // D52 + PD_8, // D53 + PD_9, // D54 + PD_10, // D55 + PD_11, // D56/A15 + PD_12, // D57/A16 + PD_13, // D58/A17 + PD_14, // D59 + PD_15, // D60 + PE_0, // D61 + PE_2, // D62 + PE_3, // D63 + PE_4, // D64 + PE_5, // D65 + PE_6, // D66 + PE_7, // D67 + PE_8, // D68 + PE_9, // D69 + PE_10, // D70 + PE_11, // D71 + PE_12, // D72 + PE_13, // D73 + PE_14, // D74 + PE_15, // D75 + PF_0, // D76 + PF_1, // D77 + PF_2, // D78 + PG_0, // D79/A18 + PG_1, // D80/A19 + PG_9, // D81 + PG_10, // D82 + PG_12, // D83 + PG_13, // D84 + PG_14, // D85 + PG_15, // D86 + PH_0, // D87 + PH_1, // D88 + PH_3, // D89 + PH_9, // D90 + PH_10, // D91 + PH_11, // D92 + PH_12, // D93 + PH_13, // D94 + PH_14, // D95 + PH_15, // D96 + PI_0, // D97 + PI_1, // D98 + PI_2, // D99 + PI_3 // D100 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 56, // A15, PD11 + 57, // A16, PD12 + 58, // A17, PD13 + 79, // A18, PG0 + 80 // A19, PG1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G9ZJJxQ/variant_generic.h b/variants/STM32U5xx/U5G9ZJJxQ/variant_generic.h new file mode 100644 index 0000000000..d93492a1f9 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJJxQ/variant_generic.h @@ -0,0 +1,298 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC6 35 +#define PC7 36 +#define PC8 37 +#define PC9 38 +#define PC10 39 +#define PC11 40 +#define PC12 41 +#define PC13 42 +#define PC14 43 +#define PC15 44 +#define PD0 45 +#define PD1 46 +#define PD2 47 +#define PD3 48 +#define PD4 49 +#define PD5 50 +#define PD6 51 +#define PD7 52 +#define PD8 53 +#define PD9 54 +#define PD10 55 +#define PD11 PIN_A15 +#define PD12 PIN_A16 +#define PD13 PIN_A17 +#define PD14 59 +#define PD15 60 +#define PE0 61 +#define PE2 62 +#define PE3 63 +#define PE4 64 +#define PE5 65 +#define PE6 66 +#define PE7 67 +#define PE8 68 +#define PE9 69 +#define PE10 70 +#define PE11 71 +#define PE12 72 +#define PE13 73 +#define PE14 74 +#define PE15 75 +#define PF0 76 +#define PF1 77 +#define PF2 78 +#define PG0 PIN_A18 +#define PG1 PIN_A19 +#define PG9 81 +#define PG10 82 +#define PG12 83 +#define PG13 84 +#define PG14 85 +#define PG15 86 +#define PH0 87 +#define PH1 88 +#define PH3 89 +#define PH9 90 +#define PH10 91 +#define PH11 92 +#define PH12 93 +#define PH13 94 +#define PH14 95 +#define PH15 96 +#define PI0 97 +#define PI1 98 +#define PI2 99 +#define PI3 100 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA6_ALT2 (PA6 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC0_ALT2 (PC0 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC1_ALT2 (PC1 | ALT2) +#define PC2_ALT1 (PC2 | ALT1) +#define PC2_ALT2 (PC2 | ALT2) +#define PC3_ALT1 (PC3 | ALT1) +#define PC3_ALT2 (PC3 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD0_ALT1 (PD0 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PF0_ALT1 (PF0 | ALT1) +#define PF1_ALT1 (PF1 | ALT1) +#define PH12_ALT1 (PH12 | ALT1) + +#define NUM_DIGITAL_PINS 101 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 +#define PWR_WAKEUP_PIN8_2 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c similarity index 99% rename from variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c rename to variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c index d74b9b3868..7e7aa3e7b4 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32U5F9ZIJxQ.xml, STM32U5F9ZJJxQ.xml - * STM32U5G9ZJJxQ.xml - * CubeMX DB release 6.0.120 + * Automatically generated from STM32U5G9ZJTxQ.xml + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9ZJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5G9ZJTxQ/PinNamesVar.h new file mode 100644 index 0000000000..aac7681c49 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJTxQ/PinNamesVar.h @@ -0,0 +1,141 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_6_ALT1 = PA_6 | ALT1, +PA_6_ALT2 = PA_6 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_0_ALT2 = PC_0 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_1_ALT2 = PC_1 | ALT2, +PC_2_ALT1 = PC_2 | ALT1, +PC_2_ALT2 = PC_2 | ALT2, +PC_3_ALT1 = PC_3 | ALT1, +PC_3_ALT2 = PC_3 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PD_0_ALT1 = PD_0 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PF_0_ALT1 = PF_0 | ALT1, +PF_1_ALT1 = PF_1 | ALT1, +PH_12_ALT1 = PH_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PE_5, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_2 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PE_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_2 = PB_5, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PE_8, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PF_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_2 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_OTG_HS_DM = PA_11, + USB_OTG_HS_DP = PA_12, + USB_OTG_HS_ID = PA_10, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif + USB_OTG_HS_VBUS = PA_9, +#endif diff --git a/variants/STM32U5xx/U5G9ZJTxQ/boards_entry.txt b/variants/STM32U5xx/U5G9ZJTxQ/boards_entry.txt new file mode 100644 index 0000000000..6961ebc40f --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJTxQ/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U5G9ZJTxQ +GenU5.menu.pnum.GENERIC_U5G9ZJTXQ=Generic U5G9ZJTxQ +GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.upload.maximum_size=4194304 +GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.upload.maximum_data_size=3098624 +GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.build.board=GENERIC_U5G9ZJTXQ +GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.build.product_line=STM32U5G9xx +GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.build.variant=STM32U5xx/U5G9ZJTxQ +GenU5.menu.pnum.GENERIC_U5G9ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5Gx.svd + diff --git a/variants/STM32U5xx/U5G9ZJTxQ/generic_clock.c b/variants/STM32U5xx/U5G9ZJTxQ/generic_clock.c new file mode 100644 index 0000000000..56530fffee --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJTxQ/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G9ZJTXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G9ZJTxQ/variant_generic.cpp b/variants/STM32U5xx/U5G9ZJTxQ/variant_generic.cpp new file mode 100644 index 0000000000..88da4d9a51 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJTxQ/variant_generic.cpp @@ -0,0 +1,145 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U5G9ZJTXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_6, // D35 + PC_7, // D36 + PC_8, // D37 + PC_9, // D38 + PC_10, // D39 + PC_11, // D40 + PC_12, // D41 + PC_13, // D42 + PC_14, // D43 + PC_15, // D44 + PD_0, // D45 + PD_1, // D46 + PD_2, // D47 + PD_3, // D48 + PD_4, // D49 + PD_5, // D50 + PD_6, // D51 + PD_7, // D52 + PD_8, // D53 + PD_9, // D54 + PD_10, // D55 + PD_11, // D56/A15 + PD_12, // D57/A16 + PD_13, // D58/A17 + PD_14, // D59 + PD_15, // D60 + PE_0, // D61 + PE_2, // D62 + PE_3, // D63 + PE_4, // D64 + PE_5, // D65 + PE_6, // D66 + PE_7, // D67 + PE_8, // D68 + PE_9, // D69 + PE_10, // D70 + PE_11, // D71 + PE_12, // D72 + PE_13, // D73 + PE_14, // D74 + PE_15, // D75 + PF_0, // D76 + PF_1, // D77 + PF_2, // D78 + PG_0, // D79/A18 + PG_1, // D80/A19 + PG_9, // D81 + PG_10, // D82 + PG_12, // D83 + PG_13, // D84 + PG_14, // D85 + PG_15, // D86 + PH_0, // D87 + PH_1, // D88 + PH_3, // D89 + PH_9, // D90 + PH_10, // D91 + PH_11, // D92 + PH_12, // D93 + PH_13, // D94 + PH_14, // D95 + PH_15, // D96 + PI_0, // D97 + PI_1, // D98 + PI_2, // D99 + PI_3 // D100 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 56, // A15, PD11 + 57, // A16, PD12 + 58, // A17, PD13 + 79, // A18, PG0 + 80 // A19, PG1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U5G9ZJTxQ/variant_generic.h b/variants/STM32U5xx/U5G9ZJTxQ/variant_generic.h new file mode 100644 index 0000000000..d93492a1f9 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJTxQ/variant_generic.h @@ -0,0 +1,298 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC6 35 +#define PC7 36 +#define PC8 37 +#define PC9 38 +#define PC10 39 +#define PC11 40 +#define PC12 41 +#define PC13 42 +#define PC14 43 +#define PC15 44 +#define PD0 45 +#define PD1 46 +#define PD2 47 +#define PD3 48 +#define PD4 49 +#define PD5 50 +#define PD6 51 +#define PD7 52 +#define PD8 53 +#define PD9 54 +#define PD10 55 +#define PD11 PIN_A15 +#define PD12 PIN_A16 +#define PD13 PIN_A17 +#define PD14 59 +#define PD15 60 +#define PE0 61 +#define PE2 62 +#define PE3 63 +#define PE4 64 +#define PE5 65 +#define PE6 66 +#define PE7 67 +#define PE8 68 +#define PE9 69 +#define PE10 70 +#define PE11 71 +#define PE12 72 +#define PE13 73 +#define PE14 74 +#define PE15 75 +#define PF0 76 +#define PF1 77 +#define PF2 78 +#define PG0 PIN_A18 +#define PG1 PIN_A19 +#define PG9 81 +#define PG10 82 +#define PG12 83 +#define PG13 84 +#define PG14 85 +#define PG15 86 +#define PH0 87 +#define PH1 88 +#define PH3 89 +#define PH9 90 +#define PH10 91 +#define PH11 92 +#define PH12 93 +#define PH13 94 +#define PH14 95 +#define PH15 96 +#define PI0 97 +#define PI1 98 +#define PI2 99 +#define PI3 100 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA6_ALT1 (PA6 | ALT1) +#define PA6_ALT2 (PA6 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC0_ALT2 (PC0 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC1_ALT2 (PC1 | ALT2) +#define PC2_ALT1 (PC2 | ALT1) +#define PC2_ALT2 (PC2 | ALT2) +#define PC3_ALT1 (PC3 | ALT1) +#define PC3_ALT2 (PC3 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD0_ALT1 (PD0 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PF0_ALT1 (PF0 | ALT1) +#define PF1_ALT1 (PF1 | ALT1) +#define PH12_ALT1 (PH12 | ALT1) + +#define NUM_DIGITAL_PINS 101 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 +#define PWR_WAKEUP_PIN8_2 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 4e9e0b3be42f70dd8d42ea76277c8fa1f93e69a2 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:42:07 +0100 Subject: [PATCH 056/141] chore(wba): update variant after script update Signed-off-by: Frederic Pillon --- variants/STM32WBAxx/WBA50KGU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c | 2 +- .../STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA5MJGH/PeripheralPins.c | 216 ++++++++++++++++++ variants/STM32WBAxx/WBA5MJGH/PinNamesVar.h | 65 ++++++ variants/STM32WBAxx/WBA5MJGH/boards_entry.txt | 14 ++ variants/STM32WBAxx/WBA5MJGH/generic_clock.c | 27 +++ .../STM32WBAxx/WBA5MJGH/variant_generic.cpp | 67 ++++++ .../STM32WBAxx/WBA5MJGH/variant_generic.h | 169 ++++++++++++++ 11 files changed, 563 insertions(+), 5 deletions(-) create mode 100644 variants/STM32WBAxx/WBA5MJGH/PeripheralPins.c create mode 100644 variants/STM32WBAxx/WBA5MJGH/PinNamesVar.h create mode 100644 variants/STM32WBAxx/WBA5MJGH/boards_entry.txt create mode 100644 variants/STM32WBAxx/WBA5MJGH/generic_clock.c create mode 100644 variants/STM32WBAxx/WBA5MJGH/variant_generic.cpp create mode 100644 variants/STM32WBAxx/WBA5MJGH/variant_generic.h diff --git a/variants/STM32WBAxx/WBA50KGU/PeripheralPins.c b/variants/STM32WBAxx/WBA50KGU/PeripheralPins.c index 80c89d549d..2896894dbb 100644 --- a/variants/STM32WBAxx/WBA50KGU/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA50KGU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA50KGUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PeripheralPins.c b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PeripheralPins.c index 1e4f1d665e..2cd4822bd7 100644 --- a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32WBA52CEUx.xml, STM32WBA52CGUx.xml * STM32WBA54CEUx.xml, STM32WBA54CGUx.xml * STM32WBA55HEFx.xml, STM32WBA55HGFx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c index 1d052929de..04e1007f18 100644 --- a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WBA52KEUx.xml, STM32WBA52KGUx.xml * STM32WBA54KEUx.xml, STM32WBA54KGUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c b/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c index 96779ffd89..e19bd95220 100644 --- a/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA55CEUx.xml, STM32WBA55CGUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c b/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c index 9676124388..d12c618b5b 100644 --- a/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA55UEIx.xml, STM32WBA55UGIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA5MJGH/PeripheralPins.c b/variants/STM32WBAxx/WBA5MJGH/PeripheralPins.c new file mode 100644 index 0000000000..b99fd0fa33 --- /dev/null +++ b/variants/STM32WBAxx/WBA5MJGH/PeripheralPins.c @@ -0,0 +1,216 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32WBA5MJGHx.xml + * CubeMX DB release 6.0.130 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {PA_2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PA_3, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC4_IN6 + {PA_4, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC4_IN5 + {PA_5, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PA_6, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PA_7, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PA_8, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PB_9, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_1_ALT1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_2_ALT1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PA_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_2_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PA_4, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_8, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_10, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_3_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_4_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_9_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_12, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_13, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_15, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32WBAxx/WBA5MJGH/PinNamesVar.h b/variants/STM32WBAxx/WBA5MJGH/PinNamesVar.h new file mode 100644 index 0000000000..533c42d007 --- /dev/null +++ b/variants/STM32WBAxx/WBA5MJGH/PinNamesVar.h @@ -0,0 +1,65 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PA_12, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PB_14, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_9, +#endif + +/* No USB */ diff --git a/variants/STM32WBAxx/WBA5MJGH/boards_entry.txt b/variants/STM32WBAxx/WBA5MJGH/boards_entry.txt new file mode 100644 index 0000000000..638de3441c --- /dev/null +++ b/variants/STM32WBAxx/WBA5MJGH/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic WBA5MJGHx +GenWBA.menu.pnum.GENERIC_WBA5MJGHX=Generic WBA5MJGHx +GenWBA.menu.pnum.GENERIC_WBA5MJGHX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA5MJGHX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA5MJGHX.build.board=GENERIC_WBA5MJGHX +GenWBA.menu.pnum.GENERIC_WBA5MJGHX.build.product_line= +GenWBA.menu.pnum.GENERIC_WBA5MJGHX.build.variant=STM32WBAxx/WBA5MJGH +GenWBA.menu.pnum.GENERIC_WBA5MJGHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBAxx/STM32WBA55.svd + diff --git a/variants/STM32WBAxx/WBA5MJGH/generic_clock.c b/variants/STM32WBAxx/WBA5MJGH/generic_clock.c new file mode 100644 index 0000000000..ddee313af2 --- /dev/null +++ b/variants/STM32WBAxx/WBA5MJGH/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA5MJGHX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA5MJGH/variant_generic.cpp b/variants/STM32WBAxx/WBA5MJGH/variant_generic.cpp new file mode 100644 index 0000000000..489097a9dc --- /dev/null +++ b/variants/STM32WBAxx/WBA5MJGH/variant_generic.cpp @@ -0,0 +1,67 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA5MJGHX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16 + PB_1, // D17 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25/A9 + PB_11, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PH_3 // D32 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 25 // A9, PB9 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA5MJGH/variant_generic.h b/variants/STM32WBAxx/WBA5MJGH/variant_generic.h new file mode 100644 index 0000000000..d0d703b9d0 --- /dev/null +++ b/variants/STM32WBAxx/WBA5MJGH/variant_generic.h @@ -0,0 +1,169 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 PIN_A9 +#define PB11 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PH3 32 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 33 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA12 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA15 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB3 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB4 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 20d7d3e8fd6b2223c77150c15c191188455d1f8c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:42:36 +0100 Subject: [PATCH 057/141] chore(wb): update variant after script update Signed-off-by: Frederic Pillon --- variants/STM32WBxx/WB10CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB10CCU/PinNamesVar.h | 12 ------------ variants/STM32WBxx/WB15CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCU/PinNamesVar.h | 12 ------------ variants/STM32WBxx/WB15CCUxE/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCUxE/PinNamesVar.h | 12 ------------ variants/STM32WBxx/WB15CCY/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCY/PinNamesVar.h | 12 ------------ variants/STM32WBxx/WB1MMCH/PeripheralPins.c | 2 +- variants/STM32WBxx/WB1MMCH/PinNamesVar.h | 12 ------------ .../STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB30CEUxA_WB50CGU/PinNamesVar.h | 12 ------------ .../WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c | 2 +- .../WB35C(C-E)UxA_WB55C(C-E-G)U/PinNamesVar.h | 12 ------------ variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c | 2 +- variants/STM32WBxx/WB55R(C-E-G)V/PinNamesVar.h | 9 --------- .../WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c | 2 +- .../WB55V(C-E-G)(Q-Y)_WB55VYY/PinNamesVar.h | 9 --------- variants/STM32WBxx/WB5MMGH/PeripheralPins.c | 2 +- variants/STM32WBxx/WB5MMGH/PinNamesVar.h | 9 --------- 20 files changed, 10 insertions(+), 121 deletions(-) diff --git a/variants/STM32WBxx/WB10CCU/PeripheralPins.c b/variants/STM32WBxx/WB10CCU/PeripheralPins.c index 33afa2242e..1e965187f1 100644 --- a/variants/STM32WBxx/WB10CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB10CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB10CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB10CCU/PinNamesVar.h b/variants/STM32WBxx/WB10CCU/PinNamesVar.h index 0634e79338..e8754fb7b0 100644 --- a/variants/STM32WBxx/WB10CCU/PinNamesVar.h +++ b/variants/STM32WBxx/WB10CCU/PinNamesVar.h @@ -13,17 +13,5 @@ #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32WBxx/WB15CCU/PeripheralPins.c b/variants/STM32WBxx/WB15CCU/PeripheralPins.c index 7470b5fcd8..7b1d987c33 100644 --- a/variants/STM32WBxx/WB15CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCU/PinNamesVar.h b/variants/STM32WBxx/WB15CCU/PinNamesVar.h index 0634e79338..e8754fb7b0 100644 --- a/variants/STM32WBxx/WB15CCU/PinNamesVar.h +++ b/variants/STM32WBxx/WB15CCU/PinNamesVar.h @@ -13,17 +13,5 @@ #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c index 4c44c5f3be..60c7afb4b5 100644 --- a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUxE.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCUxE/PinNamesVar.h b/variants/STM32WBxx/WB15CCUxE/PinNamesVar.h index 0634e79338..e8754fb7b0 100644 --- a/variants/STM32WBxx/WB15CCUxE/PinNamesVar.h +++ b/variants/STM32WBxx/WB15CCUxE/PinNamesVar.h @@ -13,17 +13,5 @@ #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32WBxx/WB15CCY/PeripheralPins.c b/variants/STM32WBxx/WB15CCY/PeripheralPins.c index e6f9447e91..0cb7e04c1e 100644 --- a/variants/STM32WBxx/WB15CCY/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCY/PinNamesVar.h b/variants/STM32WBxx/WB15CCY/PinNamesVar.h index 0634e79338..e8754fb7b0 100644 --- a/variants/STM32WBxx/WB15CCY/PinNamesVar.h +++ b/variants/STM32WBxx/WB15CCY/PinNamesVar.h @@ -13,17 +13,5 @@ #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c index 9457c1398b..ccf803f225 100644 --- a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c +++ b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB1MMCHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB1MMCH/PinNamesVar.h b/variants/STM32WBxx/WB1MMCH/PinNamesVar.h index 0634e79338..e8754fb7b0 100644 --- a/variants/STM32WBxx/WB1MMCH/PinNamesVar.h +++ b/variants/STM32WBxx/WB1MMCH/PinNamesVar.h @@ -13,17 +13,5 @@ #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c index 0f013e24fc..0e94776ea9 100644 --- a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c +++ b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB30CEUxA.xml, STM32WB50CGUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PinNamesVar.h b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PinNamesVar.h index cb0eb9240d..5cb1abe197 100644 --- a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PinNamesVar.h +++ b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PinNamesVar.h @@ -16,17 +16,5 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c index 455b12cd19..e7f33e9044 100644 --- a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c +++ b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB35C(C-E)UxA.xml, STM32WB55CCUx.xml * STM32WB55CEUx.xml, STM32WB55CGUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PinNamesVar.h b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PinNamesVar.h index 456b373ea4..c6fbac4603 100644 --- a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PinNamesVar.h +++ b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PinNamesVar.h @@ -16,18 +16,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN4 SYS_WKUP4 = PA_2, #endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c index 6529d91569..32f0ac6418 100644 --- a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c +++ b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB55RCVx.xml, STM32WB55REVx.xml * STM32WB55RGVx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55R(C-E-G)V/PinNamesVar.h b/variants/STM32WBxx/WB55R(C-E-G)V/PinNamesVar.h index 221de2b3ff..4e465af212 100644 --- a/variants/STM32WBxx/WB55R(C-E-G)V/PinNamesVar.h +++ b/variants/STM32WBxx/WB55R(C-E-G)V/PinNamesVar.h @@ -19,15 +19,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c index 1b9db56127..4f276972d8 100644 --- a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c +++ b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WB55VEQx.xml, STM32WB55VEYx.xml * STM32WB55VGQx.xml, STM32WB55VGYx.xml * STM32WB55VYYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PinNamesVar.h b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PinNamesVar.h index 6a88a5417b..de93d2a16a 100644 --- a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PinNamesVar.h +++ b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PinNamesVar.h @@ -19,15 +19,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON diff --git a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c index 2112b534d9..3fb3908c6e 100644 --- a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c +++ b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB5MMGHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB5MMGH/PinNamesVar.h b/variants/STM32WBxx/WB5MMGH/PinNamesVar.h index 6a88a5417b..de93d2a16a 100644 --- a/variants/STM32WBxx/WB5MMGH/PinNamesVar.h +++ b/variants/STM32WBxx/WB5MMGH/PinNamesVar.h @@ -19,15 +19,6 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN5 SYS_WKUP5 = PC_5, #endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* USB */ #ifdef USBCON From fe7fb43e77ffd23420027e0f7893f4f88f7691a3 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:42:46 +0100 Subject: [PATCH 058/141] chore(wl): update variant after script update Signed-off-by: Frederic Pillon --- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 15 --------------- .../PeripheralPins.c | 2 +- .../PinNamesVar.h | 15 --------------- variants/STM32WLxx/WL5MOCH/PeripheralPins.c | 2 +- variants/STM32WLxx/WL5MOCH/PinNamesVar.h | 15 --------------- 6 files changed, 3 insertions(+), 48 deletions(-) diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c index 6f408f96db..e7d052dc9c 100644 --- a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WLE4C8Ux.xml, STM32WLE4CBUx.xml * STM32WLE4CCUx.xml, STM32WLE5C8Ux.xml * STM32WLE5CBUx.xml, STM32WLE5CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PinNamesVar.h b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PinNamesVar.h index b36a4a9d2f..ebc797561b 100644 --- a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PinNamesVar.h +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PinNamesVar.h @@ -18,20 +18,5 @@ PB_8_ALT1 = PB_8 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PB_3, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c index 91e6fcd5e9..cefe726e02 100644 --- a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c +++ b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WLE4J8Ix.xml, STM32WLE4JBIx.xml * STM32WLE4JCIx.xml, STM32WLE5J8Ix.xml * STM32WLE5JBIx.xml, STM32WLE5JCIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PinNamesVar.h b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PinNamesVar.h index 83bd4524b6..da3a6751ae 100644 --- a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PinNamesVar.h +++ b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PinNamesVar.h @@ -19,20 +19,5 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PB_3, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ diff --git a/variants/STM32WLxx/WL5MOCH/PeripheralPins.c b/variants/STM32WLxx/WL5MOCH/PeripheralPins.c index 70918aed27..fb205cb4c7 100644 --- a/variants/STM32WLxx/WL5MOCH/PeripheralPins.c +++ b/variants/STM32WLxx/WL5MOCH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WL5MOCHx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL5MOCH/PinNamesVar.h b/variants/STM32WLxx/WL5MOCH/PinNamesVar.h index 83bd4524b6..da3a6751ae 100644 --- a/variants/STM32WLxx/WL5MOCH/PinNamesVar.h +++ b/variants/STM32WLxx/WL5MOCH/PinNamesVar.h @@ -19,20 +19,5 @@ PB_9_ALT1 = PB_9 | ALT1, #ifdef PWR_WAKEUP_PIN3 SYS_WKUP3 = PB_3, #endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = NC, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = NC, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = NC, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif /* No USB */ From 778bfb5012f7b8fca621bde1701a9800dbca914e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:44:29 +0100 Subject: [PATCH 059/141] chore: update cmake after variants update Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 30 +++++++-------- variants/STM32G4xx/G411CCT/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32G4xx/G411CCU/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32G4xx/G411MCT/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32G4xx/G411RCT/CMakeLists.txt | 31 ++++++++++++++++ .../CMakeLists.txt | 37 +++++++++++++++++++ variants/STM32U5xx/U5F7V(I-J)T/CMakeLists.txt | 31 ++++++++++++++++ .../STM32U5xx/U5F7V(I-J)TxQ/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32U5xx/U5F9NJHxQ/CMakeLists.txt | 31 ++++++++++++++++ .../STM32U5xx/U5F9V(I-J)TxQ/CMakeLists.txt | 31 ++++++++++++++++ .../STM32U5xx/U5F9Z(I-J)JxQ/CMakeLists.txt | 31 ++++++++++++++++ .../STM32U5xx/U5F9Z(I-J)TxQ/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32U5xx/U5G7VJT/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32U5xx/U5G7VJTxQ/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32U5xx/U5G9NJHxQ/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32U5xx/U5G9VJTxQ/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32U5xx/U5G9ZJJxQ/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32U5xx/U5G9ZJTxQ/CMakeLists.txt | 31 ++++++++++++++++ variants/STM32WBAxx/WBA5MJGH/CMakeLists.txt | 31 ++++++++++++++++ 19 files changed, 579 insertions(+), 15 deletions(-) create mode 100644 variants/STM32G4xx/G411CCT/CMakeLists.txt create mode 100644 variants/STM32G4xx/G411CCU/CMakeLists.txt create mode 100644 variants/STM32G4xx/G411MCT/CMakeLists.txt create mode 100644 variants/STM32G4xx/G411RCT/CMakeLists.txt create mode 100644 variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F7V(I-J)T/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F7V(I-J)TxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F9NJHxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F9V(I-J)TxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F9Z(I-J)JxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5F9Z(I-J)TxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5G7VJT/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5G7VJTxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5G9NJHxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5G9VJTxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5G9ZJJxQ/CMakeLists.txt create mode 100644 variants/STM32U5xx/U5G9ZJTxQ/CMakeLists.txt create mode 100644 variants/STM32WBAxx/WBA5MJGH/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 06cfe9a4a8..2c5a97e85e 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -4251,7 +4251,7 @@ target_compile_options(CYGNET_xusb_HSFS INTERFACE # DAISY_PATCH_SM # ----------------------------------------------------------------------------- -set(DAISY_PATCH_SM_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(DAISY_PATCH_SM_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(DAISY_PATCH_SM_MAXSIZE 131072) set(DAISY_PATCH_SM_MAXDATASIZE 524288) set(DAISY_PATCH_SM_MCU cortex-m7) @@ -4333,7 +4333,7 @@ target_compile_options(DAISY_PATCH_SM_xusb_HSFS INTERFACE # DAISY_PETAL_SM # ----------------------------------------------------------------------------- -set(DAISY_PETAL_SM_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(DAISY_PETAL_SM_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(DAISY_PETAL_SM_MAXSIZE 131072) set(DAISY_PETAL_SM_MAXDATASIZE 524288) set(DAISY_PETAL_SM_MCU cortex-m7) @@ -4415,7 +4415,7 @@ target_compile_options(DAISY_PETAL_SM_xusb_HSFS INTERFACE # DAISY_SEED # ----------------------------------------------------------------------------- -set(DAISY_SEED_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(DAISY_SEED_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(DAISY_SEED_MAXSIZE 131072) set(DAISY_SEED_MAXDATASIZE 524288) set(DAISY_SEED_MCU cortex-m7) @@ -75657,7 +75657,7 @@ target_compile_options(GENERIC_H733ZGTX_xusb_HSFS INTERFACE # GENERIC_H742IGKX # ----------------------------------------------------------------------------- -set(GENERIC_H742IGKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(GENERIC_H742IGKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H742IGKX_MAXSIZE 1048576) set(GENERIC_H742IGKX_MAXDATASIZE 524288) set(GENERIC_H742IGKX_MCU cortex-m7) @@ -75739,7 +75739,7 @@ target_compile_options(GENERIC_H742IGKX_xusb_HSFS INTERFACE # GENERIC_H742IGTX # ----------------------------------------------------------------------------- -set(GENERIC_H742IGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT") +set(GENERIC_H742IGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H742IGTX_MAXSIZE 1048576) set(GENERIC_H742IGTX_MAXDATASIZE 524288) set(GENERIC_H742IGTX_MCU cortex-m7) @@ -75821,7 +75821,7 @@ target_compile_options(GENERIC_H742IGTX_xusb_HSFS INTERFACE # GENERIC_H742IIKX # ----------------------------------------------------------------------------- -set(GENERIC_H742IIKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(GENERIC_H742IIKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H742IIKX_MAXSIZE 2097152) set(GENERIC_H742IIKX_MAXDATASIZE 524288) set(GENERIC_H742IIKX_MCU cortex-m7) @@ -75903,7 +75903,7 @@ target_compile_options(GENERIC_H742IIKX_xusb_HSFS INTERFACE # GENERIC_H742IITX # ----------------------------------------------------------------------------- -set(GENERIC_H742IITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT") +set(GENERIC_H742IITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H742IITX_MAXSIZE 2097152) set(GENERIC_H742IITX_MAXDATASIZE 524288) set(GENERIC_H742IITX_MCU cortex-m7) @@ -76641,7 +76641,7 @@ target_compile_options(GENERIC_H742ZITX_xusb_HSFS INTERFACE # GENERIC_H743IGKX # ----------------------------------------------------------------------------- -set(GENERIC_H743IGKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(GENERIC_H743IGKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H743IGKX_MAXSIZE 1048576) set(GENERIC_H743IGKX_MAXDATASIZE 524288) set(GENERIC_H743IGKX_MCU cortex-m7) @@ -76723,7 +76723,7 @@ target_compile_options(GENERIC_H743IGKX_xusb_HSFS INTERFACE # GENERIC_H743IGTX # ----------------------------------------------------------------------------- -set(GENERIC_H743IGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT") +set(GENERIC_H743IGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H743IGTX_MAXSIZE 1048576) set(GENERIC_H743IGTX_MAXDATASIZE 524288) set(GENERIC_H743IGTX_MCU cortex-m7) @@ -76805,7 +76805,7 @@ target_compile_options(GENERIC_H743IGTX_xusb_HSFS INTERFACE # GENERIC_H743IIKX # ----------------------------------------------------------------------------- -set(GENERIC_H743IIKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(GENERIC_H743IIKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H743IIKX_MAXSIZE 2097152) set(GENERIC_H743IIKX_MAXDATASIZE 524288) set(GENERIC_H743IIKX_MCU cortex-m7) @@ -76887,7 +76887,7 @@ target_compile_options(GENERIC_H743IIKX_xusb_HSFS INTERFACE # GENERIC_H743IITX # ----------------------------------------------------------------------------- -set(GENERIC_H743IITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT") +set(GENERIC_H743IITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H743IITX_MAXSIZE 2097152) set(GENERIC_H743IITX_MAXDATASIZE 524288) set(GENERIC_H743IITX_MCU cortex-m7) @@ -78281,7 +78281,7 @@ target_compile_options(GENERIC_H747XIHX_xusb_HSFS INTERFACE # GENERIC_H750IBKX # ----------------------------------------------------------------------------- -set(GENERIC_H750IBKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(GENERIC_H750IBKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H750IBKX_MAXSIZE 131072) set(GENERIC_H750IBKX_MAXDATASIZE 524288) set(GENERIC_H750IBKX_MCU cortex-m7) @@ -78363,7 +78363,7 @@ target_compile_options(GENERIC_H750IBKX_xusb_HSFS INTERFACE # GENERIC_H750IBTX # ----------------------------------------------------------------------------- -set(GENERIC_H750IBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT") +set(GENERIC_H750IBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H750IBTX_MAXSIZE 131072) set(GENERIC_H750IBTX_MAXDATASIZE 524288) set(GENERIC_H750IBTX_MCU cortex-m7) @@ -78691,7 +78691,7 @@ target_compile_options(GENERIC_H750ZBTX_xusb_HSFS INTERFACE # GENERIC_H753IIKX # ----------------------------------------------------------------------------- -set(GENERIC_H753IIKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK") +set(GENERIC_H753IIKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H753IIKX_MAXSIZE 2097152) set(GENERIC_H753IIKX_MAXDATASIZE 524288) set(GENERIC_H753IIKX_MCU cortex-m7) @@ -78773,7 +78773,7 @@ target_compile_options(GENERIC_H753IIKX_xusb_HSFS INTERFACE # GENERIC_H753IITX # ----------------------------------------------------------------------------- -set(GENERIC_H753IITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)T_H743I(G-I)T_H750IBT_H753IIT") +set(GENERIC_H753IITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)") set(GENERIC_H753IITX_MAXSIZE 2097152) set(GENERIC_H753IITX_MAXDATASIZE 524288) set(GENERIC_H753IITX_MCU cortex-m7) diff --git a/variants/STM32G4xx/G411CCT/CMakeLists.txt b/variants/STM32G4xx/G411CCT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32G4xx/G411CCT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32G4xx/G411CCU/CMakeLists.txt b/variants/STM32G4xx/G411CCU/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32G4xx/G411CCU/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32G4xx/G411MCT/CMakeLists.txt b/variants/STM32G4xx/G411MCT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32G4xx/G411MCT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32G4xx/G411RCT/CMakeLists.txt b/variants/STM32G4xx/G411RCT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32G4xx/G411RCT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/CMakeLists.txt b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/CMakeLists.txt new file mode 100644 index 0000000000..271b27c96b --- /dev/null +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/CMakeLists.txt @@ -0,0 +1,37 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + PeripheralPins_DAISY_PATCH_SM.c + PeripheralPins_DAISY_PETAL_SM.c + PeripheralPins_DAISY_SEED.c + variant_DAISY_PATCH_SM.cpp + variant_DAISY_PETAL_SM.cpp + variant_DAISY_SEED.cpp + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5F7V(I-J)T/CMakeLists.txt b/variants/STM32U5xx/U5F7V(I-J)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5F7V(I-J)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ/CMakeLists.txt b/variants/STM32U5xx/U5F7V(I-J)TxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5F9NJHxQ/CMakeLists.txt b/variants/STM32U5xx/U5F9NJHxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5F9NJHxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ/CMakeLists.txt b/variants/STM32U5xx/U5F9V(I-J)TxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ/CMakeLists.txt b/variants/STM32U5xx/U5F9Z(I-J)JxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ/CMakeLists.txt b/variants/STM32U5xx/U5F9Z(I-J)TxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5G7VJT/CMakeLists.txt b/variants/STM32U5xx/U5G7VJT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5G7VJTxQ/CMakeLists.txt b/variants/STM32U5xx/U5G7VJTxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5G7VJTxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5G9NJHxQ/CMakeLists.txt b/variants/STM32U5xx/U5G9NJHxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5G9NJHxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5G9VJTxQ/CMakeLists.txt b/variants/STM32U5xx/U5G9VJTxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5G9VJTxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5G9ZJJxQ/CMakeLists.txt b/variants/STM32U5xx/U5G9ZJJxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJJxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U5G9ZJTxQ/CMakeLists.txt b/variants/STM32U5xx/U5G9ZJTxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U5G9ZJTxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32WBAxx/WBA5MJGH/CMakeLists.txt b/variants/STM32WBAxx/WBA5MJGH/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32WBAxx/WBA5MJGH/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + From a7e15f1f8904c1fb8aee2fa72d8bb1a7a7826c0a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 8 Jan 2025 14:46:59 +0100 Subject: [PATCH 060/141] chore(ci): update generics list to skip Signed-off-by: Frederic Pillon --- CI/build/conf/cores_config.json | 8 ++++++++ CI/build/conf/cores_config_ci.json | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index baf56c80e4..7a1c3c10cd 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -476,8 +476,11 @@ "GENERIC_G471VEHX", "GENERIC_G471VEIX", "GENERIC_G473CBTX", + "GENERIC_G473CBUX", "GENERIC_G473CCTX", + "GENERIC_G473CCUX", "GENERIC_G473CETX", + "GENERIC_G473CEUX", "GENERIC_G473MBTX", "GENERIC_G473MCTX", "GENERIC_G473METX", @@ -499,8 +502,11 @@ "GENERIC_G473VEHX", "GENERIC_G473VETX", "GENERIC_G474CBTX", + "GENERIC_G474CBUX", "GENERIC_G474CCTX", + "GENERIC_G474CCUX", "GENERIC_G474CETX", + "GENERIC_G474CEUX", "GENERIC_G474MBTX", "GENERIC_G474MCTX", "GENERIC_G474METX", @@ -520,6 +526,7 @@ "GENERIC_G474VEHX", "GENERIC_G474VETX", "GENERIC_G483CETX", + "GENERIC_G483CEUX", "GENERIC_G483METX", "GENERIC_G483PEIX", "GENERIC_G483QETX", @@ -593,6 +600,7 @@ "GENERIC_H750VBTX", "GENERIC_H750XBHX", "GENERIC_H750ZBTX", + "GENERIC_H753IIKX", "GENERIC_H753VIHX", "GENERIC_H753XIHX", "GENERIC_H753ZITX", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index c8f42cb299..5b9d2f6954 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -476,8 +476,11 @@ "GENERIC_G471VEHX", "GENERIC_G471VEIX", "GENERIC_G473CBTX", + "GENERIC_G473CBUX", "GENERIC_G473CCTX", + "GENERIC_G473CCUX", "GENERIC_G473CETX", + "GENERIC_G473CEUX", "GENERIC_G473MBTX", "GENERIC_G473MCTX", "GENERIC_G473METX", @@ -499,8 +502,11 @@ "GENERIC_G473VEHX", "GENERIC_G473VETX", "GENERIC_G474CBTX", + "GENERIC_G474CBUX", "GENERIC_G474CCTX", + "GENERIC_G474CCUX", "GENERIC_G474CETX", + "GENERIC_G474CEUX", "GENERIC_G474MBTX", "GENERIC_G474MCTX", "GENERIC_G474METX", @@ -520,6 +526,7 @@ "GENERIC_G474VEHX", "GENERIC_G474VETX", "GENERIC_G483CETX", + "GENERIC_G483CEUX", "GENERIC_G483METX", "GENERIC_G483PEIX", "GENERIC_G483QETX", @@ -593,6 +600,7 @@ "GENERIC_H750VBTX", "GENERIC_H750XBHX", "GENERIC_H750ZBTX", + "GENERIC_H753IIKX", "GENERIC_H753VIHX", "GENERIC_H753XIHX", "GENERIC_H753ZITX", From 00c813b871d18e27c09ea0e049c1850dd29d934c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Jan 2025 09:29:21 +0100 Subject: [PATCH 061/141] system(WBA) update STM32WBAxx HAL Drivers to v1.5.0 Included in STM32CubeWBA FW v1.5.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 46 +++- .../Inc/stm32wbaxx_hal.h | 2 +- .../Inc/stm32wbaxx_hal_comp.h | 46 ++-- .../Inc/stm32wbaxx_hal_conf_template.h | 8 +- .../Inc/stm32wbaxx_hal_def.h | 15 +- .../Inc/stm32wbaxx_hal_dma.h | 2 +- .../Inc/stm32wbaxx_hal_dma_ex.h | 14 +- .../Inc/stm32wbaxx_hal_flash.h | 36 +-- .../Inc/stm32wbaxx_hal_flash_ex.h | 3 + .../Inc/stm32wbaxx_hal_gpio_ex.h | 13 +- .../Inc/stm32wbaxx_hal_gtzc.h | 4 +- .../Inc/stm32wbaxx_hal_lptim.h | 21 +- .../Inc/stm32wbaxx_hal_pka.h | 3 + .../Inc/stm32wbaxx_hal_pwr.h | 123 +++++++--- .../Inc/stm32wbaxx_hal_pwr_ex.h | 13 +- .../Inc/stm32wbaxx_hal_rcc.h | 21 +- .../Inc/stm32wbaxx_hal_rcc_ex.h | 2 +- .../Inc/stm32wbaxx_hal_rtc_ex.h | 4 +- .../Inc/stm32wbaxx_hal_spi_ex.h | 4 +- .../Inc/stm32wbaxx_ll_adc.h | 8 +- .../Inc/stm32wbaxx_ll_bus.h | 34 --- .../Inc/stm32wbaxx_ll_comp.h | 12 +- .../Inc/stm32wbaxx_ll_dma.h | 10 +- .../Inc/stm32wbaxx_ll_exti.h | 52 +++- .../Inc/stm32wbaxx_ll_gpio.h | 1 - .../Inc/stm32wbaxx_ll_i2c.h | 2 +- .../Inc/stm32wbaxx_ll_lptim.h | 12 +- .../Inc/stm32wbaxx_ll_pwr.h | 44 ++-- .../Inc/stm32wbaxx_ll_rtc.h | 1 + .../Inc/stm32wbaxx_ll_utils.h | 4 + .../STM32WBAxx_HAL_Driver/Release_Notes.html | 231 ++++++++++++++---- .../Src/stm32wbaxx_hal_dma.c | 5 +- .../Src/stm32wbaxx_hal_dma_ex.c | 12 +- .../Src/stm32wbaxx_hal_flash_ex.c | 7 +- .../Src/stm32wbaxx_hal_gtzc.c | 20 +- .../Src/stm32wbaxx_hal_i2c.c | 67 +++-- .../Src/stm32wbaxx_hal_pka.c | 152 +++++++----- .../Src/stm32wbaxx_hal_pwr.c | 11 +- .../Src/stm32wbaxx_hal_pwr_ex.c | 16 +- .../Src/stm32wbaxx_hal_ramcfg.c | 4 +- .../Src/stm32wbaxx_hal_rcc.c | 8 + .../Src/stm32wbaxx_hal_rng.c | 11 +- .../Src/stm32wbaxx_hal_uart.c | 1 - .../Src/stm32wbaxx_ll_comp.c | 12 +- .../Src/stm32wbaxx_ll_dma.c | 17 +- .../Src/stm32wbaxx_ll_gpio.c | 2 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 47 files changed, 753 insertions(+), 385 deletions(-) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 3e06f51918..12ad24635c 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -875,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -1012,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -3931,7 +3946,7 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4225,6 +4240,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h index 61c21bc63f..ad03cc0417 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h @@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @brief STM32WBAxx HAL Driver version number */ #define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBAxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32WBAxx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_comp.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_comp.h index 8403ffa5d7..6a7b0f3d42 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_comp.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_comp.h @@ -228,8 +228,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Note: For the characteristics of comparator power modes */ /* (propagation delay and power consumption), */ /* refer to device datasheet. */ -#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */ -#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ +#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High speed */ +#define COMP_POWERMODE_INTERMSPEED (COMP_CSR_PWRMODE_0) /*!< Intermediate speed */ +#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_1) /*!< Medium speed */ +#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< Ultra-low power */ /** * @} */ @@ -418,16 +420,16 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ } while(0) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ } while(0) @@ -514,17 +516,17 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ } while(0) @@ -662,18 +664,20 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH) ) #define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ - ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) ) + ((__POWERMODE__) == COMP_POWERMODE_INTERMSPEED) || \ + ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \ + ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) ) #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) /* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ +/* compatibility with other STM32 series. */ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)) #define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \ @@ -685,14 +689,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__POL__) == COMP_OUTPUTPOL_INVERTED)) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ + ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)))) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h index 4f8c0988be..a9baaa8ba7 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h @@ -95,7 +95,9 @@ extern "C" { */ #if !defined (LSI_VALUE) #define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may vary depending on the variations in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations in voltage + and temperature.*/ #if defined (RCC_LSI2_SUPPORT) #if !defined (LSI2_VALUE) @@ -158,8 +160,8 @@ extern "C" { #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ #define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ #define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ @@ -191,12 +193,10 @@ extern "C" { #define USE_HAL_HASH_SUSPEND_RESUME 0U - /* Includes ------------------------------------------------------------------*/ /** * @brief Include module's header file */ - #ifdef HAL_DMA_MODULE_ENABLED #include "stm32wbaxx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_def.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_def.h index 45b7a00a65..427ec7826f 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_def.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_def.h @@ -113,14 +113,16 @@ typedef enum }while (0) #endif /* USE_RTOS */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + /* ARM Compiler V6 */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ #ifndef __packed #define __packed __attribute__((packed)) #endif /* __packed */ -#elif defined (__GNUC__) /* GNU Compiler */ +#elif defined (__GNUC__) + /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -148,11 +150,14 @@ typedef enum #endif /* __ARMCC_VERSION || __GNUC__ */ /* Macro to get variable aligned on 32-bytes, needed for cache maintenance purpose */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + /* ARM Compiler V6 */ #define ALIGN_32BYTES(buf) __ALIGNED(32) buf -#elif defined (__ICCARM__) /* IAR Compiler */ +#elif defined (__ICCARM__) + /* IAR Compiler */ #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf -#elif defined (__GNUC__) /* GNU Compiler */ +#elif defined (__GNUC__) + /* GNU Compiler */ #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) #endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h index d8c9946e31..58b3d100bf 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h @@ -412,6 +412,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ #define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ + /** * @} */ @@ -463,7 +464,6 @@ typedef struct __DMA_HandleTypeDef */ - /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h index e880d3556f..2d0832faba 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h @@ -190,6 +190,7 @@ typedef struct __DMA_QListTypeDef => Packed at the destination data width */ #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width => Unpacked at the destination data width */ + /** * @} */ @@ -281,6 +282,7 @@ typedef struct __DMA_QListTypeDef * @{ */ #define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ + /** * @} */ @@ -418,6 +420,7 @@ HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); * @{ */ uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); + /** * @} */ @@ -457,9 +460,10 @@ typedef struct * @brief DMAEx Private Constants * @{ */ -#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ +#define DMA_LINKEDLIST (0x0080U ) /* DMA channel linked-list mode */ #define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ +#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ #define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ #define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ @@ -511,14 +515,6 @@ typedef struct #define IS_DMA_REPEAT_COUNT(COUNT) \ (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) -#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ - (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ - ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) - -#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ - (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ - ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) - #define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h index e05609fcc6..d5615283bd 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h @@ -99,8 +99,8 @@ typedef struct This parameter must be a value between 0x0 and 0xFFFFFF00 */ uint32_t RDPKeyType; /*!< Configuration of the RDP OEM keys (used for OPTIONBYTE_RDPKEY). This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */ - uint32_t RDPKey1; /*!< Value of the RDP OEM key 1 (used for OPTIONBYTE_RDPKEY) */ - uint32_t RDPKey2; /*!< Value of the RDP OEM key 2 (used for OPTIONBYTE_RDPKEY) */ + uint32_t RDPKey1; /*!< Value of the RDP OEM key - bits[0:31] (used for OPTIONBYTE_RDPKEY) */ + uint32_t RDPKey2; /*!< Value of the RDP OEM key - bits[32:63] (used for OPTIONBYTE_RDPKEY) */ } FLASH_OBProgramInitTypeDef; /** @@ -241,8 +241,8 @@ typedef struct #define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR1_PG | FLASH_SECCR1_BWR) /*!< Program a burst (8xquad-word) at a specified secure address */ #define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR1_PG | FLASH_NSCR1_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst (8xquad-word) at a specified non-secure address */ #else -#define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR1_PG /*!AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ @@ -573,7 +572,6 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ UNUSED(tmpreg); \ } while(0) -#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -627,9 +625,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) -#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) @@ -676,6 +672,7 @@ typedef struct } while(0) + #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ @@ -1078,9 +1075,7 @@ typedef struct * @brief Check whether the AHB1 peripheral clock is enabled or not. * @{ */ -#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) -#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) @@ -1204,16 +1199,12 @@ typedef struct * @{ */ #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) -#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) -#endif /* GPDMA1 */ #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) -#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) -#endif /* GPDMA1 */ #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) /** @@ -1402,9 +1393,7 @@ typedef struct * is enabled only when a peripheral requests AHB clock. * @{ */ -#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) -#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) @@ -1415,9 +1404,7 @@ typedef struct #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) -#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) -#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) @@ -1625,9 +1612,7 @@ typedef struct * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) is enabled or not. * @{ */ -#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) != 0U) -#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) @@ -2174,6 +2159,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_CSS HSE32 Clock Security System Interrupt * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) #if defined(RCC_CCIPR2_ASSEL) * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) @@ -2201,6 +2187,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_CSS HSE32 Clock Security System Interrupt * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) #if defined(RCC_CCIPR2_ASSEL) * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) @@ -2228,6 +2215,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_CSS HSE32 Clock Security System Interrupt * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) #if defined(RCC_CCIPR2_ASSEL) * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) @@ -2253,6 +2241,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_CSS HSE32 Clock Security System Interrupt * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) #if defined(RCC_CCIPR2_ASSEL) * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h index 2742a0feb6..b29a1c54b5 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h @@ -844,7 +844,7 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); * @{ */ /* Define used for IS_RCC_* macros below */ -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined(STM32WBA5Mxx) #if !defined (STM32WBAXX_SI_CUT1_0) #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h index bf7e6fa2bb..3ff0e43461 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h @@ -612,6 +612,7 @@ typedef struct #define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ /** * @} */ @@ -1742,7 +1743,8 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_ ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_16) || \ ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_32) || \ ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_64) || \ - ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_128)) + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_128) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_2048)) #define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h index 21cd5a75f8..7537de2d39 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h @@ -46,7 +46,7 @@ extern "C" { typedef struct { uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value - of @ref FunctionalState */ + of @ref SPI_AutonomousMode_State */ uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter can be a value of @ref SPI_AutonomousMode_TriggerSelection */ @@ -66,7 +66,7 @@ typedef struct * @{ */ -/** @defgroup FunctionalState SPI Autonomous Mode State +/** @defgroup SPI_AutonomousMode_State SPI Autonomous Mode State * @{ */ #define SPI_AUTO_MODE_DISABLE (0x00000000UL) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h index 50878a41dd..6ce70f66e0 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h @@ -63,7 +63,6 @@ extern "C" { #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ - /* Internal mask for ADC group regular trigger: */ /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ @@ -93,7 +92,6 @@ extern "C" { #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ - /* Internal mask for ADC channel: */ /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ /* - channel identifier defined by number */ @@ -219,7 +217,6 @@ extern "C" { #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL) - /* ADC registers bits positions */ #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ @@ -1814,7 +1811,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t (void)(Register); /* Retrieve address of register DR */ - return (uint32_t) & (ADCx->DR); + return (uint32_t) &(ADCx->DR); } /** @@ -4361,8 +4358,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *A /** * @brief Get ADC group regular conversion data, range fit for * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). + * features extending data width (oversampling, data shift,...). * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h index 7da948247d..de7f7862e1 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h @@ -70,9 +70,7 @@ extern "C" { * @{ */ #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#if defined(GPDMA1) #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN -#endif #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN @@ -213,9 +211,7 @@ extern "C" { */ /** * @brief Enable AHB1 peripherals clock. -#if defined(GPDMA1) * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n -#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n @@ -225,9 +221,7 @@ extern "C" { * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH -#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) -#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG @@ -248,9 +242,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if AHB1 peripheral clock is enabled or not -#if defined(GPDMA1) * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock -#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n @@ -259,9 +251,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL -#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) -#endif * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) @@ -279,9 +269,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable AHB1 peripherals clock. -#if defined(GPDMA1) * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock -#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n @@ -291,9 +279,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH -#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) -#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG @@ -310,17 +296,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) /** * @brief Force AHB1 peripherals reset. -#if defined(GPDMA1) * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n -#endif * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL -#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) -#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) @@ -334,17 +316,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) /** * @brief Release AHB1 peripherals reset. -#if defined(GPDMA1) * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n -#endif * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL -#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) -#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) @@ -358,9 +336,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes -#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n -#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n @@ -369,9 +345,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL -#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) -#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC @@ -394,9 +368,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) /** * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not -#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n -#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n @@ -405,9 +377,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL -#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) -#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC @@ -426,9 +396,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) /** * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes -#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n -#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n @@ -437,9 +405,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL -#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) -#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h index 8124b00ac6..081cf9da75 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h @@ -169,7 +169,9 @@ typedef struct * @{ */ #define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< COMP power mode to high speed */ -#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */ +#define LL_COMP_POWERMODE_INTERMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to intermediate speed */ +#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_1) /*!< COMP power mode to medium speed */ +#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */ /** * @} */ @@ -324,8 +326,8 @@ typedef struct * @{ */ -/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: - * common to several COMP instances +/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration + * of COMP hierarchical scope: common to several COMP instances * @{ */ @@ -461,7 +463,9 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(const COMP_Common_TypeDef * @param COMPx Comparator instance * @param PowerMode This parameter can be one of the following values: * @arg @ref LL_COMP_POWERMODE_HIGHSPEED + * @arg @ref LL_COMP_POWERMODE_INTERMSPEED * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED + * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER * @retval None */ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode) @@ -475,7 +479,9 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @param COMPx Comparator instance * @retval Returned value can be one of the following values: * @arg @ref LL_COMP_POWERMODE_HIGHSPEED + * @arg @ref LL_COMP_POWERMODE_INTERMSPEED * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED + * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER */ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h index 03654564ea..d6f86e9adc 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h @@ -836,7 +836,6 @@ typedef struct #define LL_GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */ #define LL_GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */ #endif /* LPTIM2 */ - /** * @} */ @@ -1875,7 +1874,6 @@ __STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Cha uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc); } - /** * @brief Get destination increment mode. * @note This API is used for all available DMA channels. @@ -2296,7 +2294,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, ui * @brief Set trigger polarity. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -2323,7 +2321,7 @@ __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t * @brief Get trigger polarity. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -2348,7 +2346,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint * @brief Set trigger Mode. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -4531,7 +4529,7 @@ uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); -uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h index 005670cd90..a51c81b5d9 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h @@ -103,8 +103,8 @@ typedef struct #define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ #if defined(EXTI_IMR1_IM16) #define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#endif /* EXTI_IMR_IM16 */ #if defined(EXTI_IMR1_IM17) -#endif /* EXTI_IMR_IM17 */ #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ #endif /* LL_EXTI_LINE_17 */ #if defined(EXTI_IMR1_IM18) @@ -252,6 +252,8 @@ typedef struct * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -287,6 +289,8 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -322,6 +326,8 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -362,6 +368,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -395,6 +403,8 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -427,6 +437,8 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -475,6 +487,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -513,6 +527,8 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -545,6 +561,8 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -591,6 +609,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -628,6 +648,8 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -659,6 +681,8 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -703,6 +727,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -744,6 +770,8 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -777,6 +805,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval @note This bit is set when the selected edge event arrives on the interrupt */ @@ -810,6 +840,8 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -843,6 +875,8 @@ __STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -876,6 +910,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval @note This bit is set when the selected edge event arrives on the interrupt */ @@ -909,6 +945,8 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1051,6 +1089,8 @@ __STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1083,6 +1123,8 @@ __STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1115,6 +1157,8 @@ __STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -1157,6 +1201,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1189,6 +1235,8 @@ __STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1221,6 +1269,8 @@ __STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h index ad2afbee3c..04d4907158 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h @@ -954,7 +954,6 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); } - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h index fec55e8434..6c87e85166 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h @@ -360,7 +360,7 @@ typedef struct #endif /* I2C1 */ #define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ -#if defined(I2C_TRIG_GRP1) +#if defined(LL_I2C_TRIG_GRP1) #define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ #define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h index 61df87976d..ee641e53ae 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h @@ -401,10 +401,12 @@ typedef struct * @{ */ #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */ -#if defined(COMP1) && defined(COMP2) +#if defined(COMP1) #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */ +#endif /* COMP1 */ +#if defined(COMP2) #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */ -#endif /* COMP1 && COMP2 */ +#endif /* COMP2 */ /** * @} */ @@ -423,10 +425,12 @@ typedef struct * @{ */ #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */ -#if defined(COMP1) && defined(COMP2) +#if defined(COMP1) #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */ +#endif /* COMP1 */ +#if defined(COMP2) #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */ -#endif /* COMP1 && COMP2 */ +#endif /* COMP2 */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h index 23eac9fdda..f708de97cf 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (PWR) +#if defined(PWR) /** @defgroup PWR_LL PWR * @{ @@ -92,9 +92,9 @@ extern "C" { /** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELECTION Low Power Mode Selection * @{ */ -#define LL_PWR_MODE_STOP0 0U /*!< Stop 0 mode */ -#define LL_PWR_MODE_STOP1 PWR_CR1_LPMS_0 /*!< Stop 1 mode */ -#define LL_PWR_MODE_STANDBY PWR_CR1_LPMS_2 /*!< Standby mode */ +#define LL_PWR_MODE_STOP0 0U /*!< Stop 0 mode */ +#define LL_PWR_MODE_STOP1 PWR_CR1_LPMS_0 /*!< Stop 1 mode */ +#define LL_PWR_MODE_STANDBY PWR_CR1_LPMS_2 /*!< Standby mode */ /** * @} */ @@ -102,7 +102,7 @@ extern "C" { /** @defgroup PWR_LL_EC_SRAM1_SB_RETENTION PWR SRAM1 Retention in Standby Mode * @{ */ -#define LL_PWR_SRAM1_SB_NO_RETENTION 0U /*!< SRAM1 no retention in Standby mode */ +#define LL_PWR_SRAM1_SB_NO_RETENTION 0U /*!< SRAM1 no retention in Standby mode */ #define LL_PWR_SRAM1_SB_FULL_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 all pages retention in Standby mode */ /** * @} @@ -111,12 +111,13 @@ extern "C" { /** @defgroup PWR_LL_EC_SRAM2_SB_RETENTION PWR SRAM2 Retention in Standby Mode * @{ */ -#define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Standby mode */ -#define LL_PWR_SRAM2_SB_FULL_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 all pages retention in Standby mode */ +#define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Standby mode */ +#define LL_PWR_SRAM2_SB_FULL_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 all pages retention in Standby mode */ /** * @} */ + /** @defgroup PWR_LL_EC_RADIO_SB_RETENTION PWR RADIO SRAMs and Sleep Clock Retention in Standby Mode * @{ */ @@ -138,8 +139,8 @@ extern "C" { /** @defgroup PWR_LL_EC_SRAM2_STOP_RETENTION PWR SRAM2 Retention in Stop Mode * @{ */ -#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode */ -#define LL_PWR_SRAM2_STOP_FULL_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 all pages retention in Stop mode */ +#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode */ +#define LL_PWR_SRAM2_STOP_FULL_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 all pages retention in Stop mode */ /** * @} */ @@ -202,8 +203,8 @@ extern "C" { /** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection * @{ */ -#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 (highest frequency) */ -#define LL_PWR_REGU_VOLTAGE_SCALE2 0U /*!< Voltage scaling range 2 (lowest power) */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 (highest frequency) */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 0U /*!< Voltage scaling range 2 (lowest power) */ /** * @} */ @@ -568,8 +569,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void) */ __STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICRAMPageRetention) { - MODIFY_REG(PWR->CR2, PWR_CR2_ICRAMPDS, - ((~ICRAMPageRetention) & PWR_CR2_ICRAMPDS)); + MODIFY_REG(PWR->CR2, PWR_CR2_ICRAMPDS, ((~ICRAMPageRetention) & PWR_CR2_ICRAMPDS)); } /** @@ -1551,7 +1551,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) { WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); } -#endif /* PWR_WUSCR_CWUF2 */ +#endif /* defined(PWR_WUSCR_CWUF2) */ /** * @brief Clear wake up flag 3. @@ -1583,7 +1583,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) { WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); } -#endif /* PWR_WUSCR_CWUF5 */ +#endif /* defined(PWR_WUSCR_CWUF5) */ /** * @brief Clear wake up flag 6. @@ -1665,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void) } #endif /* PWR_PRIVCFGR_NSPRIV */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Enable privileged mode for secure items. * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege @@ -1685,7 +1685,7 @@ __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void) { CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined(PWR_PRIVCFGR_NSPRIV) /** @@ -1699,7 +1699,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void) } #endif /* PWR_PRIVCFGR_NSPRIV */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Configure secure attribute mode. * @note This API can be executed only by CPU in secure mode. @@ -1765,12 +1765,12 @@ __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void) { return (READ_REG(PWR->SECCFGR)); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ -#if defined (USE_FULL_LL_DRIVER) +#if defined(USE_FULL_LL_DRIVER) /** @defgroup PWR_LL_EF_Init De-initialization function * @{ */ @@ -1778,7 +1778,7 @@ ErrorStatus LL_PWR_DeInit(void); /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* defined(USE_FULL_LL_DRIVER) */ /** @@ -1789,7 +1789,7 @@ ErrorStatus LL_PWR_DeInit(void); * @} */ -#endif /* defined (PWR) */ +#endif /* defined(PWR) */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h index 8307da7fb2..876a3faa3b 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h @@ -621,6 +621,7 @@ typedef struct #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ #define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h index db35bbb41a..e03d562351 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h @@ -157,11 +157,13 @@ typedef struct /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE * @{ */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) #define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000000U /*!< UFQFPN32 package type */ #define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000002U /*!< UFQFPN48 package type */ #define LL_UTILS_PACKAGETYPE_WLCSP41_SMPS 0x00000009U /*!< WLCSP41 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS 0x0000000AU /*!< UFQFPN48 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFBGA59 0x0000000BU /*!< UFBGA59 package type */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ /** * @} */ @@ -222,11 +224,13 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) /** * @brief Get Package type * @retval Returned value can be one of the following values: +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP41_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA59 +#endif */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html index 822e47089f..e3943b7be0 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html @@ -40,17 +40,17 @@

                                                    Purpose

                                                    Update History

                                                    - +

                                                    Main Changes

                                                    -

                                                    Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

                                                    +

                                                    Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and STM32WBA5Mxx devices

                                                    Contents

                                                    Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                    • HAL/LL Drivers are available for all peripherals:
                                                      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
                                                        • -
                                                      • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
                                                        • +
                                                      • LL: ADC, BUS, COMP, CORTEX, CRC, DMA, EXTI, GPIO, HSEM, I2C, ICACHE, IWDG, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, SYSTEM, TIM, USART, UTILS, WWDG
                                                    • Update HAL/LL drivers to include latest corrections
                                                    @@ -58,6 +58,145 @@

                                                    Official Release

                                                    HAL Drivers updates

                                                      +
                                                    • HAL COMP driver +
                                                        +
                                                      • Add power modes intermediate and ultra low power
                                                        • +
                                                      • +
                                                    • HAL DMA driver +
                                                        +
                                                      • Add a reset of a node of a linked list
                                                        • +
                                                      • Remove unused code related to 2D addressing as no 2D addressing in this family
                                                        • +
                                                      • +
                                                    • HAL GPIO driver +
                                                        +
                                                      • Add WBA5M device
                                                        • +
                                                      • +
                                                    • HAL GTZC driver +
                                                        +
                                                      • Add WBA5M device
                                                        • +
                                                      • +
                                                    • HAL I2C driver +
                                                        +
                                                      • Move variable tmp declaration at the beginning in I2C_TransferCofig function
                                                        • +
                                                      • Update function HAL_I2C_IsDeviceReady() to take into account the number of trials
                                                        • +
                                                      • +
                                                    • HAL LPTIM driver +
                                                        +
                                                      • Removed duplicated macro
                                                        • +
                                                      • Fix compilation switch (COMP1/COMP2)
                                                        • +
                                                      • +
                                                    • HAL PKA driver +
                                                        +
                                                      • SAES decryption fails after PKA deinitialization
                                                        • +
                                                      • Remove static global variables and add them to PKA handle to be compliant with HAL coding rules
                                                        • +
                                                      • Add check for MontgomeryParam not equal to null
                                                        • +
                                                      • +
                                                    • HAL PWR driver +
                                                        +
                                                      • Reorganization of IS_PWR_WAKEUP_PIN macro in order to ease maintenance and declaration conditionned on CMSIS
                                                        • +
                                                      • Add WBA5M device
                                                        • +
                                                      • Guidance added for HAL_PWR_ConfigAttributes() API calls
                                                        • +
                                                      • +
                                                    • HAL RAMCFG driver +
                                                        +
                                                      • Add WBA5M device
                                                        • +
                                                      • +
                                                    • HAL RCC driver +
                                                        +
                                                      • Add WBA5M device
                                                        • +
                                                      • Guidance added for HAL_RCC_ConfigAttributes() API calls
                                                        • +
                                                      • Add missing @arg for RCC_IT_CSS function headers
                                                        • +
                                                      • +
                                                    • HAL RNG driver +
                                                        +
                                                      • Fix issue NIST parameters ​​not taken
                                                        • +
                                                      • +
                                                    • HAL RTC driver +
                                                        +
                                                      • Additional TAMP register bit ATCKSEL[3] inside TAMP_ATCR1
                                                        • +
                                                      • +
                                                    • HAL UART driver +
                                                        +
                                                      • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode
                                                        • +
                                                      • +
                                                    +


                                                    +

                                                    +

                                                    LL Drivers updates

                                                    +
                                                      +
                                                    • LL ADC driver +
                                                        +
                                                      • Update description of LL_ADC_REG_ReadConversionData32()
                                                        • +
                                                      • +
                                                    • LL COMP driver +
                                                        +
                                                      • Add power modes intermediate and ultra low power
                                                        • +
                                                      • +
                                                    • LL DMA driver +
                                                        +
                                                      • Misra-C:2012 Rule-8.13 update
                                                        • +
                                                      • +
                                                    • LL I2C driver +
                                                        +
                                                      • Update defined trigger for I2C autonomous mode.
                                                        • +
                                                      • +
                                                    • LL LPTIM driver +
                                                        +
                                                      • Fix compilation switch (COMP1/COMP2)
                                                        • +
                                                      • +
                                                    • LL RTC driver +
                                                        +
                                                      • Additional TAMP register bit ATCKSEL[3] inside TAMP_ATCR1
                                                        • +
                                                      • +
                                                    • LL UTILS driver +
                                                        +
                                                      • Add WBA5M device
                                                        • +
                                                      • +
                                                    +


                                                    +

                                                    +

                                                    Supported Devices and boards

                                                    +
                                                      +
                                                    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and STM32WBA5Mxx devices
                                                      • +
                                                    • NUCLEO-WBA55CG, STM32WBA55G-DK1 and b-WBA5M-WPAN boards
                                                      • +
                                                    +

                                                    Backward compatibility

                                                    +
                                                      +
                                                    • Not applicable
                                                      • +
                                                    +

                                                    Known Limitations

                                                    +
                                                      +
                                                    • None
                                                      • +
                                                    +

                                                    Dependencies

                                                    +
                                                      +
                                                    • None
                                                      • +
                                                    +

                                                    Notes

                                                    +
                                                      +
                                                    • None
                                                      • +
                                                    +
                                                    +
                                                    +
                                                    + +
                                                    +

                                                    Main Changes

                                                    +

                                                    Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

                                                    +

                                                    Contents

                                                    +

                                                    Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                    +
                                                      +
                                                    • HAL/LL Drivers are available for all peripherals: +
                                                        +
                                                      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
                                                        • +
                                                      • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
                                                        • +
                                                      • +
                                                    • Update HAL/LL drivers to include latest corrections
                                                      • +
                                                    +


                                                    +

                                                    +

                                                    HAL Drivers updates

                                                    +
                                                    • HAL CORTEX driver
                                                      • Add how to use MPU attributes
                                                        • @@ -96,7 +235,7 @@

                                                        HAL Drivers updates


                                                      -

                                                      LL Drivers updates

                                                      +

                                                      LL Drivers updates

                                                      • LL CORTEX driver
                                                          @@ -124,24 +263,24 @@

                                                          LL Drivers updates


                                                        -

                                                        Supported Devices and boards

                                                        +

                                                        Supported Devices and boards

                                                        • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices
                                                        • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
                                                        -

                                                        Backward compatibility

                                                        +

                                                        Backward compatibility

                                                        • Not applicable
                                                        -

                                                        Known Limitations

                                                        +

                                                        Known Limitations

                                                        • None
                                                        -

                                                        Dependencies

                                                        +

                                                        Dependencies

                                                        • None
                                                        -

                                                        Notes

                                                        +

                                                        Notes

                                                        • None
                                                        @@ -150,10 +289,10 @@

                                                        Notes

                                                        -

                                                        Main Changes

                                                        +

                                                        Main Changes

                                                        Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

                                                        -

                                                        Contents

                                                        -

                                                        Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                        +

                                                        Contents

                                                        +

                                                        Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                        • HAL/LL Drivers are available for all peripherals:
                                                            @@ -164,7 +303,7 @@

                                                            Official Relea


                                                          -

                                                          HAL Drivers updates

                                                          +

                                                          HAL Drivers updates

                                                          • HAL CORTEX driver
                                                              @@ -195,7 +334,7 @@

                                                              HAL Drivers updates


                                                            -

                                                            LL Drivers updates

                                                            +

                                                            LL Drivers updates

                                                            • LL LPUART driver
                                                                @@ -204,24 +343,24 @@

                                                                LL Drivers updates


                                                              -

                                                              Supported Devices and boards

                                                              +

                                                              Supported Devices and boards

                                                              • STM32WBA52xx and STM32WBA55xx devices
                                                              • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
                                                              -

                                                              Backward compatibility

                                                              +

                                                              Backward compatibility

                                                              • Not applicable
                                                              -

                                                              Known Limitations

                                                              +

                                                              Known Limitations

                                                              • None
                                                              -

                                                              Dependencies

                                                              +

                                                              Dependencies

                                                              • None
                                                              -

                                                              Notes

                                                              +

                                                              Notes

                                                              • None
                                                              @@ -230,10 +369,10 @@

                                                              Notes

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

                                                              -

                                                              Contents

                                                              -

                                                              Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                              +

                                                              Contents

                                                              +

                                                              Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                              • HAL/LL Drivers are available for all peripherals:
                                                                  @@ -249,7 +388,7 @@

                                                                  Official Relea


                                                                -

                                                                HAL Drivers updates

                                                                +

                                                                HAL Drivers updates

                                                                • HAL CORTEX driver
                                                                    @@ -336,7 +475,7 @@

                                                                    HAL Drivers updates


                                                                  -

                                                                  LL Drivers updates

                                                                  +

                                                                  LL Drivers updates

                                                                  • LL GPIO driver
                                                                      @@ -361,24 +500,24 @@

                                                                      LL Drivers updates


                                                                    -

                                                                    Supported Devices and boards

                                                                    +

                                                                    Supported Devices and boards

                                                                    • STM32WBA52xx and STM32WBA55xx devices
                                                                    • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
                                                                    -

                                                                    Backward compatibility

                                                                    +

                                                                    Backward compatibility

                                                                    • Not applicable
                                                                    -

                                                                    Known Limitations

                                                                    +

                                                                    Known Limitations

                                                                    • None
                                                                    -

                                                                    Dependencies

                                                                    +

                                                                    Dependencies

                                                                    • None
                                                                    -

                                                                    Notes

                                                                    +

                                                                    Notes

                                                                    • None
                                                                    @@ -387,10 +526,10 @@

                                                                    Notes

                                                                    -

                                                                    Main Changes

                                                                    +

                                                                    Main Changes

                                                                    Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

                                                                    -

                                                                    Contents

                                                                    -

                                                                    Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                                    +

                                                                    Contents

                                                                    +

                                                                    Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                                    • HAL/LL Drivers are available for all peripherals:
                                                                        @@ -400,7 +539,7 @@

                                                                        Official Relea


                                                                      -

                                                                      HAL Drivers updates

                                                                      +

                                                                      HAL Drivers updates

                                                                      • HAL CORTEX driver
                                                                          @@ -461,7 +600,7 @@

                                                                          HAL Drivers updates


                                                                        -

                                                                        LL Drivers updates

                                                                        +

                                                                        LL Drivers updates

                                                                        • LL DMA driver
                                                                            @@ -483,24 +622,24 @@

                                                                            LL Drivers updates


                                                                          -

                                                                          Supported Devices and boards

                                                                          +

                                                                          Supported Devices and boards

                                                                          • STM32WBA52xx devices
                                                                          • NUCLEO-WBA52CG board
                                                                          -

                                                                          Backward compatibility

                                                                          +

                                                                          Backward compatibility

                                                                          • Not applicable
                                                                          -

                                                                          Known Limitations

                                                                          +

                                                                          Known Limitations

                                                                          • None
                                                                          -

                                                                          Dependencies

                                                                          +

                                                                          Dependencies

                                                                          • None
                                                                          -

                                                                          Notes

                                                                          +

                                                                          Notes

                                                                          • None
                                                                          @@ -509,9 +648,9 @@

                                                                          Notes

                                                                          -

                                                                          Main Changes

                                                                          +

                                                                          Main Changes

                                                                          First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

                                                                          -

                                                                          Contents

                                                                          +

                                                                          Contents

                                                                          First Official Release of HAL/LL Drivers for STM32WBAxx serie

                                                                          • HAL/LL Drivers are available for all peripherals: @@ -522,24 +661,24 @@

                                                                            First Offi


                                                                          -

                                                                          Supported Devices and boards

                                                                          +

                                                                          Supported Devices and boards

                                                                          • STM32WBA52xx devices
                                                                          • NUCLEO-WBA52CG board
                                                                          -

                                                                          Backward compatibility

                                                                          +

                                                                          Backward compatibility

                                                                          • Not applicable
                                                                          -

                                                                          Known Limitations

                                                                          +

                                                                          Known Limitations

                                                                          • None
                                                                          -

                                                                          Dependencies

                                                                          +

                                                                          Dependencies

                                                                          • None
                                                                          -

                                                                          Notes

                                                                          +

                                                                          Notes

                                                                          • None
                                                                          diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma.c index a4e3e243df..37c483f682 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma.c @@ -238,6 +238,7 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma); */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) { + /* Get tick number */ uint32_t tickstart = HAL_GetTick(); @@ -270,6 +271,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort)); } + /* Allocate lock resource */ __HAL_UNLOCK(hdma); @@ -1524,7 +1526,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h */ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) { - DMA_TypeDef *p_dma_instance; + const DMA_TypeDef *p_dma_instance; uint32_t channel_idx; /* Check the DMA peripheral handle and lock state parameters */ @@ -1648,7 +1650,6 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma) MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM | DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_REQSEL), tmpreg); - /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/ WRITE_REG(hdma->Instance->CBR1, 0U); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma_ex.c index 4a02639bb7..fe23e92ece 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma_ex.c @@ -637,7 +637,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Get DMA instance */ DMA_TypeDef *p_dma_instance; #endif /* DMA_PRIVCFGR_PRIV0 */ - /* Get tick number */ uint32_t tickstart = HAL_GetTick(); @@ -654,7 +653,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Get DMA instance */ p_dma_instance = GET_DMA_INSTANCE(hdma); #endif /* DMA_PRIVCFGR_PRIV0 */ - /* Disable the selected DMA Channel */ __HAL_DMA_DISABLE(hdma); @@ -3199,6 +3197,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, { MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange)); + } else { @@ -3452,6 +3451,7 @@ uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma) { return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); } + /** * @} */ @@ -3560,7 +3560,6 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, /* Check for memory to peripheral transfer */ if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH) { - /* Check for GPDMA */ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) { pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ; @@ -3603,6 +3602,10 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress; /*********************************************************************************** CDAR register value is updated */ + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ /* Update node information value ************************************************************************************/ /* Set node information */ @@ -3641,6 +3644,7 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, (DMA_CTR1_SAP | DMA_CTR1_DAP); pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX); + pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) @@ -4071,7 +4075,7 @@ static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, uint32_t contextnode_reg_counter = 0U; uint32_t cllr_idx; uint32_t cllr_mask; - DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, DMA_CLLR_UDA, DMA_CLLR_ULL diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c index 9f95483992..f69e4acff0 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c @@ -582,8 +582,10 @@ void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks) SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP_ACCDIS); } + #endif /* __ARM_FEATURE_CMSE */ + /** * @} */ @@ -1116,8 +1118,8 @@ static void FLASH_OB_RDPConfig(uint32_t RDPLevel) * This parameter can be one of the following values: * @arg @ref OB_RDP_KEY_OEM1 OEM1 key * @arg @ref OB_RDP_KEY_OEM2 OEM2 key - * @param RDPKey1 Specifies the RDP key 1. - * @param RDPKey2 Specifies the RDP key 2. + * @param RDPKey1 Specifies the RDP key bits[0:31]. + * @param RDPKey2 Specifies the RDP key bits[32:63]. * @retval None */ static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2) @@ -1289,6 +1291,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) } + #if defined(FLASH_OPTR_TZEN) if ((UserType & OB_USER_TZEN) != 0U) { diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c index c0cf9910fe..0231d33878 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c @@ -113,7 +113,7 @@ /* Definitions for GTZC TZSC & TZIC ALL register values */ /* TZSC1 / TZIC1 instances */ -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined(STM32WBA5Mxx) #define TZSC1_SECCFGR1_ALL (0x000222C3UL) #define TZSC1_SECCFGR2_ALL (0x018F00EBUL) #define TZSC1_SECCFGR3_ALL (0x01C17858UL) @@ -123,7 +123,7 @@ #define TZSC1_SECCFGR2_ALL (0x010F006BUL) #define TZSC1_SECCFGR3_ALL (0x00C17858UL) #define TZIC1_IER4_ALL (0xC3C0EF87UL) -#endif /* STM32WBA54xx || STM32WBA55xx */ +#endif /* STM32WBA54xx || STM32WBA55xx || STM32WBA5Mxx */ #define TZSC1_PRIVCFGR1_ALL TZSC1_SECCFGR1_ALL #define TZSC1_PRIVCFGR2_ALL TZSC1_SECCFGR2_ALL @@ -560,14 +560,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } -#if defined(GTZC_MPCBB6) else { /* Here MemBaseAddress is inside SRAM6 (parameter already checked) */ mpcbb_ptr = GTZC_MPCBB6; mem_size = GTZC_MEM_SIZE(SRAM6); } -#endif /* GTZC_MPCBB6 */ /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); @@ -633,13 +631,11 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } -#if defined(GTZC_MPCBB6) else { mpcbb_ptr = GTZC_MPCBB6; mem_size = GTZC_MEM_SIZE(SRAM6); } -#endif /* GTZC_MPCBB6 */ /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); @@ -729,7 +725,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, base_address = SRAM2_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#if defined(GTZC_MPCBB6) else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U) { @@ -744,7 +739,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, base_address = SRAM6_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -876,7 +870,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, base_address = SRAM2_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM6, end_address))) { @@ -891,7 +884,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, base_address = SRAM6_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -971,7 +963,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCK; } -#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) && (IS_ADDRESS_IN(SRAM6, (MemAddress + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) @@ -981,7 +972,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCK; } -#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1066,7 +1056,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = GTZC_MPCBB2_S->CFGLOCK; } -#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) && (IS_ADDRESS_IN(SRAM6, (MemAddress + (NbSuperBlocks @@ -1077,7 +1066,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = GTZC_MPCBB6_S->CFGLOCK; } -#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1114,12 +1102,10 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) { SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } -#if defined(GTZC_MPCBB6) else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) { SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } -#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1146,12 +1132,10 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, { *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } -#if defined(GTZC_MPCBB6) else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) { *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } -#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c index 1f67b9d949..4c9b7a5df3 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c @@ -3458,6 +3458,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3515,37 +3517,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -7624,15 +7653,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pka.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pka.c index 961b4b300b..2acc1915ba 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pka.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pka.c @@ -276,6 +276,7 @@ * @{ */ #define PKA_RAM_SIZE 1334U +#define PKA_RAM_ERASE_TIMEOUT 1000U /* Private macro -------------------------------------------------------------*/ #define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \ @@ -287,9 +288,6 @@ */ /* Private variables ---------------------------------------------------------*/ -static uint32_t primeordersize; -static uint32_t opsize; -static uint32_t modulussize; /* Private function prototypes -----------------------------------------------*/ /** @defgroup PKA_Private_Functions PKA Private Functions * @{ @@ -399,8 +397,22 @@ HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka) /* Set the state to busy */ hpka->State = HAL_PKA_STATE_BUSY; - /* Reset the control register and enable the PKA */ - hpka->Instance->CR = PKA_CR_EN; + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Reset the control register and enable the PKA (wait the end of PKA RAM erase) */ + while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) + { + hpka->Instance->CR = PKA_CR_EN; + + /* Check the Timeout */ + if ((HAL_GetTick() - tickstart) > PKA_RAM_ERASE_TIMEOUT) + { + /* Set timeout status */ + err = HAL_TIMEOUT; + break; + } + } /* Get current tick */ tickstart = HAL_GetTick(); @@ -502,12 +514,50 @@ __weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka) */ __weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpka); - - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, the HAL_PKA_MspDeInit can be implemented in the user file + user should take into consideration PKA RAM erase when resetting PKA */ + uint32_t tickstart = HAL_GetTick(); + + /* Enable PKA reset state */ + __HAL_RCC_PKA_FORCE_RESET(); + + /* Release PKA from reset state */ + __HAL_RCC_PKA_RELEASE_RESET(); + + /* Wait the INITOK flag Setting */ + while (hpka->Instance->CR != PKA_CR_EN) + { + hpka->Instance->CR = PKA_CR_EN; + + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PKA_RAM_ERASE_TIMEOUT) + { + /* update the state */ + hpka->State = HAL_PKA_STATE_ERROR; + } + } + + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Wait the INITOK flag Setting */ + if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, PKA_RAM_ERASE_TIMEOUT) != HAL_OK) + { + /* update the state */ + hpka->State = HAL_PKA_STATE_ERROR; + } + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* PKA Periph clock disable */ + hpka->Instance->CR = 0; + __HAL_RCC_PKA_CLK_DISABLE(); + + /* PKA Periph IRQ disable */ + HAL_NVIC_DisableIRQ(PKA_IRQn); } #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) @@ -811,9 +861,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); } @@ -828,9 +876,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); } @@ -846,9 +892,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); } @@ -863,9 +907,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); } @@ -883,9 +925,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); } @@ -900,9 +940,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - - opsize = in->OpSize; - + hpka->opsize = in->OpSize; return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } @@ -918,7 +956,7 @@ void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) uint32_t size; /* Get output result size */ - size = opsize; + size = hpka->opsize; /* Move the result to appropriate location (indicated in out parameter) */ PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); @@ -935,9 +973,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - - primeordersize = in->primeOrderSize; - + hpka->primeordersize = in->primeOrderSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); } @@ -952,9 +988,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - - primeordersize = in->primeOrderSize; - + hpka->primeordersize = in->primeOrderSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); } @@ -971,7 +1005,7 @@ void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDe uint32_t size; /* Get output result size */ - size = primeordersize; + size = hpka->primeordersize; if (out != NULL) @@ -1087,11 +1121,18 @@ void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) */ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + } + else + { + return HAL_ERROR; + } } /** @@ -1102,11 +1143,18 @@ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTy */ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + } + else + { + return HAL_ERROR; + } } /** @@ -1132,9 +1180,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - - modulussize = in->modulusSize; - + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1149,9 +1195,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - - modulussize = in->modulusSize; - + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1166,9 +1210,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDe { /* Set input parameter in PKA RAM */ PKA_ECCMulEx_Set(hpka, in); - - modulussize = in->modulusSize; - + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1183,9 +1225,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTyp { /* Set input parameter in PKA RAM */ PKA_ECCMulEx_Set(hpka, in); - - modulussize = in->modulusSize; - + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1200,7 +1240,7 @@ void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out uint32_t size; /* Get output result size */ - size = modulussize; + size = hpka->modulussize; /* If a destination buffer is provided */ if (out != NULL) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr.c index 0bb4c5bfb0..ab11a8af5a 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr.c @@ -491,8 +491,8 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) * @arg @ref PWR_WAKEUP_PIN2 * @arg @ref PWR_WAKEUP_PIN3 * @arg @ref PWR_WAKEUP_PIN4 - * @arg @ref PWR_WAKEUP_PIN6 * @arg @ref PWR_WAKEUP_PIN5 + * @arg @ref PWR_WAKEUP_PIN6 * @arg @ref PWR_WAKEUP_PIN7 * @arg @ref PWR_WAKEUP_PIN8 * @retval None @@ -514,8 +514,8 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) * @arg @ref PWR_WAKEUP_PIN2 * @arg @ref PWR_WAKEUP_PIN3 * @arg @ref PWR_WAKEUP_PIN4 - * @arg @ref PWR_WAKEUP_PIN6 * @arg @ref PWR_WAKEUP_PIN5 + * @arg @ref PWR_WAKEUP_PIN6 * @arg @ref PWR_WAKEUP_PIN7 * @arg @ref PWR_WAKEUP_PIN8 */ @@ -1026,6 +1026,13 @@ __weak void HAL_PWR_WKUP8_Callback(void) * privileged access. * @note Privilege attribute for nsecure items can be managed by a secure * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). * @param Item : Specifies the item(s) to set attributes on. * This parameter can be a combination of PWR_ITEMS. * @param Attributes : Specifies the available attribute(s). diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c index c9183a4517..44d3161dce 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c @@ -109,7 +109,7 @@ /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines * @{ */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) #define PWR_PORTA_AVAILABLE_PINS (0x0FFFFU) #define PWR_PORTB_AVAILABLE_PINS (0x0FFFFU) #define PWR_PORTC_AVAILABLE_PINS (0x0E000U) @@ -119,7 +119,7 @@ #define PWR_PORTB_AVAILABLE_PINS (0x09318U) #define PWR_PORTC_AVAILABLE_PINS (0x0C000U) #define PWR_PORTH_AVAILABLE_PINS (0x00008U) -#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ /*!< Time out value of flags setting */ #define PWR_VOSF_SETTING_DELAY_VALUE (0x32U) /*!< Time out value for VOSF flag setting */ #define PWR_MODE_CHANGE_DELAY_VALUE (0x32U) /*!< Time out for step down converter operating mode */ @@ -532,9 +532,9 @@ void HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void) * stop modes otherwise an hard fault may occur when waking up from stop modes. * @param RAMSelection: Specifies RAMs content to be retained in Stop mode. * This parameter can be one or a combination of the values: - * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention . - * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention. - * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention. + * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention. + * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention. + * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention. * @retval None. */ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) @@ -552,9 +552,9 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) * powered down in Stop mode. (Consumption is optimized) * @param RAMSelection: Specifies RAMs content to be lost in Stop mode. * This parameter can be one or a combination of the values: - * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention . - * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention. - * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention. + * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention. + * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention. + * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention. * @retval None. */ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c index 66d7e8071e..d5cd69e12b 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c @@ -31,12 +31,12 @@ [..] (+) Each SRAM is managed by a RAMCFG instance. (++) SRAM1 placed in Core Domain. - (+++) Size = 64 kB (STM32WBA54xx, STM32WBA55xx) + (+++) Size = 64 kB (STM32WBA54xx, STM32WBA55xx, STM32WBA5Mxx) (+++) Size = 16 kB (STM32WBA50xx) (+++) Base Address = 0x20000000. (++) SRAM2 placed in Core Domain. - (+++) Size = 64 kB (STM32WBA54xx, STM32WBA55xx) + (+++) Size = 64 kB (STM32WBA54xx, STM32WBA55xx, STM32WBA5Mxx) (+++) Size = 48 kB (STM32WBA50xx) (+++) Base Address = 0x20010000. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc.c index d9e342f11a..e3de60ef44 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc.c @@ -1634,6 +1634,14 @@ uint32_t HAL_RCC_GetResetSource(void) /** * @brief Configure the RCC item attribute(s). * @note Available attributes are to secure items and set RCC as privileged. + * @note As the privileged attributes concern either all secure or all + * non-secure RCC resources accesses and not each RCC individual items + * access attribute, the application must ensure that the privilege + * access attribute configurations are coherent amongst the security + * level set on RCC individual items so not to overwrite a previous + * more restricted access rule (consider either all secure and/or all + * non-secure RCC resources accesses by privileged-only transactions or + * privileged and unprivileged transactions). * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref RCC_items * @param Attributes specifies the RCC secure/privilege attributes. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c index cbaa165f72..dd490bc154 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c @@ -197,17 +197,18 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST | RNG_CR_RNG_CONFIG2, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST | (1U << RNG_CR_RNG_CONFIG2_Pos)); -#if defined(RNG_CR_NIST_VALUE) - /* Recommended value for NIST compliance, refer to application note AN4230 */ - WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE); -#endif /* defined(RNG_CR_NIST_VALUE) */ +#endif /* RNG_CR_NIST_VALUE */ #if defined(RNG_HTCR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); -#endif /* defined(RNG_HTCR_NIST_VALUE) */ +#endif /* RNG_HTCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c index ce8899a170..17ee716eec 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c @@ -3949,7 +3949,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_comp.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_comp.c index 45afaeb9bf..bde489b511 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_comp.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_comp.c @@ -88,14 +88,14 @@ #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ ((((__COMP_INSTANCE__) == COMP1) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ || \ (((__COMP_INSTANCE__) == COMP2) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2))) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2))) \ ) /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_dma.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_dma.c index 1f13c6cdcd..52dbc539f1 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_dma.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_dma.c @@ -52,7 +52,6 @@ */ #if defined (GPDMA1) - /** @addtogroup DMA_LL * @{ */ @@ -137,12 +136,14 @@ #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_ADC4_AWD1) #endif /* TIM3 */ + #if defined (LPTIM2) #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM2_UE) #else #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM1_UE) #endif /* LPTIM2 */ + #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \ ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \ ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \ @@ -191,7 +192,8 @@ #define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U)) -#define IS_LL_DMA_LINK_NODETYPE(__VALUE__) ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE) +#define IS_LL_DMA_LINK_NODETYPE(TYPE) \ + ((TYPE) == LL_DMA_GPDMA_LINEAR_NODE) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \ @@ -424,7 +426,6 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength, DMA_InitStruct->DestBurstLength); } - /*-------------------------- DMAx CTR2 Configuration ------------------------- * Configure the channel transfer parameter : * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits @@ -603,7 +604,6 @@ uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinked LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \ DMA_InitLinkedListStruct->LinkAllocatedPort | \ DMA_InitLinkedListStruct->LinkStepMode); - /*-------------------------- DMAx CTR2 Configuration ------------------------- * Configure the channel transfer parameter : * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits @@ -666,7 +666,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) * LL_DMA_LinkNodeTypeDef parameters. * @retval None */ -uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode) +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode) { uint32_t reg_counter = 0U; @@ -746,6 +746,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM DMA_InitNodeStruct->SrcSecure); #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + /* Update CTR1 register fields */ pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \ DMA_InitNodeStruct->DestHWordExchange | \ @@ -836,7 +837,6 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM } - /* Check if CLLR register update is enabled */ if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR) { @@ -854,6 +854,11 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM DMA_CLLR_UDA | DMA_CLLR_ULL))); } + else + { + /* Reset of the CLLR of the node being created */ + pNode->LinkRegisters[reg_counter] = 0U; + } return (uint32_t)SUCCESS; } diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_gpio.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_gpio.c index 8661f1a656..baa3a7bccd 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_gpio.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_gpio.c @@ -30,7 +30,7 @@ * @{ */ -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) /** @addtogroup GPIO_LL * @{ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index a81cc7785e..0f8b0e5a07 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -19,7 +19,7 @@ * STM32U0: 1.2.0 * STM32U5: 1.6.0 * STM32WB: 1.14.3 - * STM32WBA: 1.4.0 + * STM32WBA: 1.5.0 * STM32WL: 1.3.0 Release notes of each STM32YYxx HAL Drivers available here: From de522b467158b688b54d079c4ef33c985927b08b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Jan 2025 09:29:22 +0100 Subject: [PATCH 062/141] system(WBA): update STM32WBAxx CMSIS Drivers to v1.5.0 Included in STM32CubeWBA FW v1.5.0 Signed-off-by: Frederic Pillon --- .../Templates/partition_stm32wba5mxx.h | 593 + .../STM32WBAxx/Include/partition_stm32wbaxx.h | 2 + .../ST/STM32WBAxx/Include/stm32wba50xx.h | 5 +- .../ST/STM32WBAxx/Include/stm32wba52xx.h | 10 +- .../ST/STM32WBAxx/Include/stm32wba54xx.h | 10 +- .../ST/STM32WBAxx/Include/stm32wba55xx.h | 10 +- .../ST/STM32WBAxx/Include/stm32wba5mxx.h | 15835 ++++++++++++++++ .../Device/ST/STM32WBAxx/Include/stm32wbaxx.h | 8 +- .../Device/ST/STM32WBAxx/Release_Notes.html | 82 +- .../gcc/linker/STM32WBA5Mxx_FLASH.ld | 187 + .../gcc/linker/STM32WBA5Mxx_FLASH_ns.ld | 187 + .../gcc/linker/STM32WBA5Mxx_FLASH_s.ld | 195 + .../Templates/gcc/linker/STM32WBA5Mxx_RAM.ld | 187 + .../gcc/linker/STM32WBA5Mxx_RAM_ns.ld | 187 + .../gcc/linker/STM32WBA5Mxx_RAM_s.ld | 195 + .../Templates/gcc/startup_stm32wba5mxx.s | 474 + .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 17 files changed, 18127 insertions(+), 42 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba5mxx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba5mxx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba5mxx.s diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba5mxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba5mxx.h new file mode 100644 index 0000000000..8c9eae96e7 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba5mxx.h @@ -0,0 +1,593 @@ +/** + ****************************************************************************** + * @file partition_stm32wba5mxx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA5Mxx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE V5.4.0 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2024 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32WBA5MXX_H +#define PARTITION_STM32WBA5MXX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x08080000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x080FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF88000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BF97FFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C07E000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C07FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x40000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x4FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// RADIO_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_S_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_S_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_AUDIOSYNC_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + +} + +#endif /* PARTITION_STM32WBA5MXX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h index cd6c267c5b..1888424f00 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h @@ -48,6 +48,8 @@ #include "partition_stm32wba54xx.h" #elif defined(STM32WBA55xx) #include "partition_stm32wba55xx.h" +#elif defined(STM32WBA5Mxx) + #include "partition_stm32wba5mxx.h" #else #error "Please select first the target STM32WBAxx device used in your application (in stm32wbaxx.h file)" #endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h index 24a1a72994..ed95f6c6fd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h @@ -158,7 +158,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ @@ -7790,11 +7790,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h index b51658ff98..affb76a31a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h @@ -172,7 +172,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ @@ -1211,12 +1211,13 @@ typedef struct * Vector table. The function does not return on successful execution. * @param HdpArea notifies which hdp area to close, can be a combination of * hdpa area 1 and hdp area 2 - * @param pointer on the vector table containing the reset handler the function + * @param VectorTableAddr pointer on the vector table containing the reset handler the function * jumps to. * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + /** * @brief RSSLib non-secure callable function pointer structure */ @@ -1231,7 +1232,7 @@ typedef struct typedef struct { __IM uint32_t Reserved2[2]; - __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Close and exit HDP Address offset: 0x28 */ }S_pFuncTypeDef; /** @@ -11855,11 +11856,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h index ec33cd994b..f3ab2b5768 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h @@ -175,7 +175,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ @@ -1287,12 +1287,13 @@ typedef struct * Vector table. The function does not return on successful execution. * @param HdpArea notifies which hdp area to close, can be a combination of * hdpa area 1 and hdp area 2 - * @param pointer on the vector table containing the reset handler the function + * @param VectorTableAddr pointer on the vector table containing the reset handler the function * jumps to. * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + /** * @brief RSSLib non-secure callable function pointer structure */ @@ -1307,7 +1308,7 @@ typedef struct typedef struct { __IM uint32_t Reserved2[2]; - __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Close and exit HDP Address offset: 0x28 */ }S_pFuncTypeDef; /** @@ -12563,11 +12564,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h index 05890e1b2a..45dc9038c2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h @@ -175,7 +175,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ @@ -1287,12 +1287,13 @@ typedef struct * Vector table. The function does not return on successful execution. * @param HdpArea notifies which hdp area to close, can be a combination of * hdpa area 1 and hdp area 2 - * @param pointer on the vector table containing the reset handler the function + * @param VectorTableAddr pointer on the vector table containing the reset handler the function * jumps to. * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + /** * @brief RSSLib non-secure callable function pointer structure */ @@ -1307,7 +1308,7 @@ typedef struct typedef struct { __IM uint32_t Reserved2[2]; - __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Close and exit HDP Address offset: 0x28 */ }S_pFuncTypeDef; /** @@ -12581,11 +12582,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba5mxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba5mxx.h new file mode 100644 index 0000000000..d31d7db309 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba5mxx.h @@ -0,0 +1,15835 @@ +/** + ****************************************************************************** + * @file stm32wba5mxx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA5Mxx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STM32WBA5Mxx_H +#define STM32WBA5Mxx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + +/** @addtogroup STM32WBA5Mxx + * @{ + */ + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32WBA5Mxx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + TIM1_BRK_IRQn = 37, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 38, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 39, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 40, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 41, /*!< TIM2 global interrupt */ + TIM3_IRQn = 42, /*!< TIM3 global interrupt */ + I2C1_EV_IRQn = 43, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 44, /*!< I2C1 Error interrupt */ + SPI1_IRQn = 45, /*!< SPI1 global interrupt */ + USART1_IRQn = 46, /*!< USART1 global interrupt */ + USART2_IRQn = 47, /*!< USART2 global interrupt */ + LPUART1_IRQn = 48, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 49, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 50, /*!< LPTIM2 global interrupt */ + TIM16_IRQn = 51, /*!< TIM16 global interrupt */ + TIM17_IRQn = 52, /*!< TIM17 global interrupt */ + COMP_IRQn = 53, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + I2C3_EV_IRQn = 54, /*!< I2C3 Event interrupt */ + I2C3_ER_IRQn = 55, /*!< I2C3 Error interrupt */ + SAI1_IRQn = 56, /*!< Serial Audio Interface 1 global interrupt */ + TSC_IRQn = 57, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 58, /*!< AES global interrupt */ + RNG_IRQn = 59, /*!< RNG global interrupt */ + FPU_IRQn = 60, /*!< FPU global interrupt */ + HASH_IRQn = 61, /*!< HASH global interrupt */ + PKA_IRQn = 62, /*!< PKA global interrupt */ + SPI3_IRQn = 63, /*!< SPI3 global interrupt */ + ICACHE_IRQn = 64, /*!< Instruction cache global interrupt */ + ADC4_IRQn = 65, /*!< ADC4 global interrupt */ + RADIO_IRQn = 66, /*!< 2.4GHz RADIO global interrupt */ + WKUP_IRQn = 67, /*!< PWR global WKUP pin interrupt */ + HSEM_IRQn = 68, /*!< HSEM non-secure global interrupt */ + HSEM_S_IRQn = 69, /*!< HSEM secure global interrupt */ + WKUP_S_IRQn = 70, /*!< PWR secure global WKUP pin interrupt */ + RCC_AUDIOSYNC_IRQn = 71, /*!< RCC audio synchronization interrupt */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the STM32WBAxx System On Chip ------ */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter (ADC) + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x02C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x30-0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED2[22];/*!< Reserved, Address offset: 0x48-0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED3[7]; /*!< Reserved, Address offset: 0xA8-0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xC4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief Analog comparators (COMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA secure and privilege lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< RESERVED1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x14 */ + __IO uint32_t PDKEYR; /*!< FLASH Bank power-down key register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR1; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR1; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + __IO uint32_t NSCR2; /*!< FLASH non-secure control register, Address offset: 0x38 */ + __IO uint32_t SECCR2; /*!< FLASH secure control register, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWMR1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWMR2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRPAR; /*!< FLASH WRP area A address register, Address offset: 0x58 */ + __IO uint32_t WRPBR; /*!< FLASH WRP area B address register, Address offset: 0x5C */ + uint32_t RESERVED3[4]; /*!< Reserved3, Address offset: 0x60-0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBBR1; /*!< FLASH secure block-based bank register 1, Address offset: 0x80 */ + __IO uint32_t SECBBR2; /*!< FLASH secure block-based bank register 2, Address offset: 0x84 */ + __IO uint32_t SECBBR3; /*!< FLASH secure block-based bank register 3, Address offset: 0x88 */ + __IO uint32_t SECBBR4; /*!< FLASH secure block-based bank register 4, Address offset: 0x8C */ + uint32_t RESERVED4[12]; /*!< Reserved4, Address offset: 0x90-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBBR1; /*!< FLASH privilege block-based bank register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBBR2; /*!< FLASH privilege block-based bank register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBBR3; /*!< FLASH privilege block-based bank register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBBR4; /*!< FLASH privilege block-based bank register 4, Address offset: 0xDC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCK; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[4]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x10C */ + uint32_t RESERVED3[60]; /*!< Reserved3, Address offset: 0x110-0x1FC */ + __IO uint32_t PRIVCFGR[4]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x20C */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED0[52]; /*!< Reserved, Address offset: 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ + uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ + __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ + uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 100h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 104h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 108h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: 10Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 110h-17Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 180h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 184h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 188h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 18Ch */ + uint32_t Reserved4[28]; /*!< Reserved Address offset: 190h-1FCh */ + __IO uint32_t SECCFGR; /*!< HSEM security configuration register, Address offset: 200h */ + uint32_t Reserved5[3]; /*!< Reserved Address offset: 204h-20Ch */ + __IO uint32_t PRIVCFGR; /*!< HSEM privilege configuration register, Address offset: 210h */ + uint32_t Reserved6[7]; /*!< Reserved Address offset: 214h-22Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register, Address offset: 230h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register, Address offset: 234h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 10h-7Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 80h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 84h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 88h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 8Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief PTACONV + */ +typedef struct +{ + __IO uint32_t ACTCR; /*!< PTACONV active control register, Address offset: 0x00 */ + __IO uint32_t PRICR; /*!< PTACONV priority control register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< PTACONV control register, Address offset: 0x08 */ +} PTACONV_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t IORETENRA; /*!< PWR Port A IO retention in Standby register, Address offset: 0x50 */ + __IO uint32_t IORETRA; /*!< PWR Port A IO retention status in Standby register, Address offset: 0x54 */ + __IO uint32_t IORETENRB; /*!< PWR Port B IO retention in Standby register, Address offset: 0x58 */ + __IO uint32_t IORETRB; /*!< PWR Port B IO retention status in Standby register, Address offset: 0x5C */ + __IO uint32_t IORETENRC; /*!< PWR Port C IO retention in Standby register, Address offset: 0x60 */ + __IO uint32_t IORETRC; /*!< PWR Port C IO retention status in Standby register, Address offset: 0x64 */ + uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x68 -- 0x84 */ + __IO uint32_t IORETENRH; /*!< PWR Port H IO retention in Standby register, Address offset: 0x88 */ + __IO uint32_t IORETRH; /*!< PWR Port H IO retention status in Standby register, Address offset: 0x8C */ + uint32_t RESERVED4[28]; /*!< Reserved, Address offset: 0x90 -- 0xFC */ + __IO uint32_t RADIOSCR; /*!< PWR 2.4 GHZ radio status and control register, Address offset: 0x100 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved 0x004 -- 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved 0x014 -- 0x018 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x024 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x028 */ + uint32_t RESERVED2[2]; /*!< Reserved 0x02C -- 0x030 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x034 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved 0x03C -- 0x04C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x060 */ + __IO uint32_t AHB2RSTR; /*!< AHB2 Peripherals Reset Register Address offset: 0x064 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x068 */ + __IO uint32_t AHB4RSTR; /*!< AHB4 Peripherals Reset Register Address offset: 0x06C */ + __IO uint32_t AHB5RSTR; /*!< AHB5 Peripherals Reset Register Address offset: 0x070 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Low Register Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset High Register Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB7RSTR; /*!< APB7 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x088 */ + __IO uint32_t AHB2ENR; /*!< AHB2 Peripherals Clock Enable Register Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x090 */ + __IO uint32_t AHB4ENR; /*!< AHB4 Peripherals Clock Enable Register Address offset: 0x094 */ + __IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Low Register Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable High Register Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB7ENR; /*!< APB7 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Low Power Enable Register Address offset: 0x0B0 */ + __IO uint32_t AHB2SMENR; /*!< AHB2 Peripherals Clock Low Power Enable Register Address offset: 0x0B4 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0B8 */ + __IO uint32_t AHB4SMENR; /*!< AHB4 Peripherals Clock Low Power Enable Register Address offset: 0x0BC */ + __IO uint32_t AHB5SMENR; /*!< AHB5 Peripherals Clock Low Power Enable Register Address offset: 0x0C0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Low Power Enable Low Register Address offset: 0x0C4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Low Power Enable High Register Address offset: 0x0C8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Low Power Enable Register Address offset: 0x0CC */ + __IO uint32_t APB7SMENR; /*!< APB7 Peripherals Clock Low Power Enable Register Address offset: 0x0D0 */ + uint32_t RESERVED10[3]; /*!< Reserved 0x0D4 -- 0x0DC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0x0E0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0x0E4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0x0E8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0EC */ + __IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address offset: 0x0F0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0x0F4 */ + __IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address offset: 0x0F8 */ + uint32_t RESERVED12[5]; /*!< Reserved 0x0FC -- 0x010C */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +#if !defined (STM32WBAXX_SI_CUT1_0) + uint32_t RESERVED13[42]; /*!< Reserved 0x118 -- 0x1BC */ + __IO uint32_t ASCR; /*!< RCC privilege configuration register Address offset: 0x1C0 */ + __IO uint32_t ASIER; /*!< RCC privilege configuration register Address offset: 0x1C4 */ + __IO uint32_t ASSR; /*!< RCC privilege configuration register Address offset: 0x1C8 */ + __IO uint32_t ASCNTR; /*!< RCC privilege configuration register Address offset: 0x1CC */ + __IO uint32_t ASARR; /*!< RCC privilege configuration register Address offset: 0x1D0 */ + __IO uint32_t ASCAR; /*!< RCC privilege configuration register Address offset: 0x1D4 */ + __IO uint32_t ASCOR; /*!< RCC privilege configuration register Address offset: 0x1D8 */ + uint32_t RESERVED14[9]; /*!< Reserved 0x1DC -- 0x1FC */ +#else + uint32_t RESERVED13[58]; /*!< Reserved 0x118 -- 0x1FC */ +#endif + __IO uint32_t CFGR4; /*!< RCC clock configuration register 4 Address offset: 0x200 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0x204 */ + __IO uint32_t RADIOENR; /*!< RCC RADIO peripheral clock enable register Address offset: 0x208 */ + uint32_t RESERVED16; /*!< Reserved Address offset: 0x20C */ + __IO uint32_t ECSCR1; /*!< RCC external clock sources calibration register 1 Address offset: 0x210 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_BACKUP_NB RTC_BKP_NB + +#define RTC_TAMP_NB 6U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED2[4];/*!< Reserved, Address offset: 0x44 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x68-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief TSC + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC Control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC Interrupt Enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC Interrupt Control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC Interrupt Status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register, Address offset: 0x34-48 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32WBA5Mxx_Peripherals */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_peripheralAddr + * @{ + */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF88000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20010000UL /*!< SRAM2 non-secure base address */ +#define SRAM6_BASE_NS 0x48028000UL /*!< 2.4 GHz RADIO TXRX SRAM non-secure base address */ +#define SEQSRAM_BASE_NS 0x48021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define DBGMCU_BASE 0xE0044000UL /*!< Debug MCU registers base address */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x100000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x100000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/* Internal SRAMs size */ +#define SRAM1_SIZE 0x00010000UL /*!< SRAM1 = 64 Kbytes */ +#define SRAM2_SIZE 0x00010000UL /*!< SRAM2 = 64 Kbytes */ +#define SRAM6_SIZE 0x00004000UL /*!< 2.4 GHz RADIO TXRX SRAM 16 Kbytes */ +#define SEQSRAM_SIZE 0x00000200UL /*!< SRAM Sequence / retention 512 bytes */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00008000UL) +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ + +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00008500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB7PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS APB1PERIPH_BASE_NS +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define GTZC_TZSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x14000UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS AHB2PERIPH_BASE_NS +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define HSEM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA1C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB7 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB7PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB7PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB7PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB7PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB7PERIPH_BASE_NS + 0x4400UL) +#define COMP12_BASE_NS (APB7PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define RTC_BASE_NS (APB7PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB7PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB4 Non secure peripherals */ +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB4PERIPH_BASE_NS + 0x1308UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB5 Non secure peripherals */ +#define RADIO_BASE_NS AHB5PERIPH_BASE_NS +#define PTACONV_BASE_NS (AHB5PERIPH_BASE_NS + 0x18000UL) + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ +#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ +#define SRAM2_BASE_S 0x30010000UL /*!< SRAM2 secure base address */ +#define SRAM6_BASE_S 0x58028000UL /*!< 2.4 GHz RADIO TXRX SRAM secure base address */ +#define SEQSRAM_BASE_S 0x58021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB7PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S APB1PERIPH_BASE_S +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define GTZC_TZSC_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x14000UL) + +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0140UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S AHB2PERIPH_BASE_S +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define HSEM_BASE_S (AHB2PERIPH_BASE_S + 0xA1C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB7 Secure peripherals */ +#define SYSCFG_BASE_S (APB7PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB7PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB7PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB7PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB7PERIPH_BASE_S + 0x4400UL) +#define COMP12_BASE_S (APB7PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define RTC_BASE_S (APB7PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB7PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB4 Secure peripherals */ +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB4PERIPH_BASE_S + 0x1308UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x2000UL) + +/*!< AHB5 Secure peripherals */ +#define RADIO_BASE_S AHB5PERIPH_BASE_S +#define PTACONV_BASE_S (AHB5PERIPH_BASE_S + 0x18000UL) +#endif + +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (SYSTEM_FLASH_BASE_NS + 0x00007E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (SYSTEM_FLASH_BASE_NS + 0x00007E6BUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR 0xF5F5F5F5UL +#define RSSLIB_SUCCESS 0xEAEAEAEAUL + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x1UL << RSSLIB_HDP_AREA_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param VectorTableAddr pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32WBAxx_Peripheral_peripheralAddr */ +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_declaration + * @{ + */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GTZC_TZSC_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HSEM_NS ((HSEM_TypeDef *) HSEM_BASE_NS) +#define HSEM_COMMON_NS ((HSEM_Common_TypeDef *) (HSEM_BASE_NS + 0x100U)) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PTACONV_NS ((PTACONV_TypeDef *) PTACONV_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GTZC_TZIC_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_S) +#define GTZC_TZSC_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HSEM_S ((HSEM_TypeDef *) HSEM_BASE_S) +#define HSEM_COMMON_S ((HSEM_Common_TypeDef *) (HSEM_BASE_S + 0x100U)) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PTACONV_S ((PTACONV_TypeDef *) PTACONV_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) + + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define SEQSRAM_BASE SEQSRAM_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S +#define AES AES_S +#define AES_BASE AES_BASE_S +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S +#define COMP12_COMMON COMP12_COMMON_S +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S +#define GTZC_TZIC GTZC_TZIC_S +#define GTZC_TZIC_BASE GTZC_TZIC_BASE_S +#define GTZC_TZSC GTZC_TZSC_S +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_S +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S +#define HSEM HSEM_S +#define HSEM_BASE HSEM_BASE_S +#define HSEM_COMMON HSEM_COMMON_S +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S +#define PTACONV_BASE PTACONV_BASE_S +#define PTACONV PTACONV_S +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S +#define RADIO_BASE RADIO_BASE_S +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define SEQSRAM_BASE SEQSRAM_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS +#define AES AES_NS +#define AES_BASE AES_BASE_NS +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS +#define COMP12_COMMON COMP12_COMMON_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS +#define GTZC_TZSC GTZC_TZSC_NS +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define HSEM HSEM_NS +#define HSEM_BASE HSEM_BASE_NS +#define HSEM_COMMON HSEM_COMMON_NS +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS +#define PTACONV_BASE PTACONV_BASE_NS +#define PTACONV PTACONV_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RADIO_BASE RADIO_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS +#endif + + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_SCANDIR_Pos (4U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_PWRR register ******************/ +#define ADC_PWRR_AUTOFF_Pos (0U) +#define ADC_PWRR_AUTOFF_Msk (0x1UL << ADC_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC_PWRR_AUTOFF ADC_PWRR_AUTOFF_Msk /*!< ADC auto-off mode */ +#define ADC_PWRR_DPD_Pos (1U) +#define ADC_PWRR_DPD_Msk (0x1UL << ADC_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC_PWRR_DPD ADC_PWRR_DPD_Msk /*!< ADC deep power down mode */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000300 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ + +#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_WINOUT_Pos (14U) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ + +#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CSR_BLANKSEL_Pos (20U) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_KEYPROT_Pos (19U) +#define AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) /*!< 0x00080000 */ +#define AES_CR_KEYPROT AES_CR_KEYPROT_Msk /*!< Key protection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_KSHAREID_Pos (26U) +#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define AES_CR_KEYSEL_Pos (28U) +#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key Selection */ +#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ + + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key Valid Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************* Bit definition for AES_IER register ******************/ +#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3U) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< SAES Rng error interrupt enable */ + +/******************* Bit definition for AES_ISR register ******************/ +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3U) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< SAES Rng error interrupt flag */ + +/******************* Bit definition for AES_ICR register ******************/ +#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3U) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< SAES Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register *************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBGMCU_SCR register *****************/ +#define DBGMCU_SCR_DBG_STOP_Pos (1U) +#define DBGMCU_SCR_DBG_STOP_Msk (0x1UL << DBGMCU_SCR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_SCR_DBG_STOP DBGMCU_SCR_DBG_STOP_Msk +#define DBGMCU_SCR_DBG_STANDBY_Pos (2U) +#define DBGMCU_SCR_DBG_STANDBY_Msk (0x1UL << DBGMCU_SCR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_SCR_DBG_STANDBY DBGMCU_SCR_DBG_STANDBY_Msk +#define DBGMCU_SCR_DBG_LPMS_Pos (16U) +#define DBGMCU_SCR_DBG_LPMS_Msk (0x7UL << DBGMCU_SCR_DBG_LPMS_Pos) /*!< 0x00070000 */ +#define DBGMCU_SCR_DBG_LPMS DBGMCU_SCR_DBG_LPMS_Msk +#define DBGMCU_SCR_DBG_LPMS_0 (0x1UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_1 (0x2UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_2 (0x4UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_STOPF_Pos (19U) +#define DBGMCU_SCR_DBG_STOPF_Msk (0x1UL << DBGMCU_SCR_DBG_STOPF_Pos) /*!< 0x00080000 */ +#define DBGMCU_SCR_DBG_STOPF DBGMCU_SCR_DBG_STOPF_Msk +#define DBGMCU_SCR_DBG_SBF_Pos (20U) +#define DBGMCU_SCR_DBG_SBF_Msk (0x1UL << DBGMCU_SCR_DBG_SBF_Pos) /*!< 0x00100000 */ +#define DBGMCU_SCR_DBG_SBF DBGMCU_SCR_DBG_SBF_Msk +#define DBGMCU_SCR_DBG_CS_Pos (24U) +#define DBGMCU_SCR_DBG_CS_Msk (0x1UL << DBGMCU_SCR_DBG_CS_Pos) /*!< 0x01000000 */ +#define DBGMCU_SCR_DBG_CS DBGMCU_SCR_DBG_CS_Msk +#define DBGMCU_SCR_DBG_CDS_Pos (25U) +#define DBGMCU_SCR_DBG_CDS_Msk (0x1UL << DBGMCU_SCR_DBG_CDS_Pos) /*!< 0x02000000 */ +#define DBGMCU_SCR_DBG_CDS DBGMCU_SCR_DBG_CDS_Msk + +/******************** Bit definition for DBGMCU_APB1LFZR register ***********/ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk + +/******************** Bit definition for DBGMCU_APB1HFZR register ***********/ +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos (5U) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk + +/******************** Bit definition for DBGMCU_APB2FZR register ***********/ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk + +/******************** Bit definition for DBGMCU_APB7FZR register ***********/ +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos (10U) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_RTC_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP_Msk + +/******************** Bit definition for DBGMCU_AHB1FZR register ***********/ +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk + + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_SECCFGR register ****************/ +#define DMA_SECCFGR_SEC0_Pos (0U) +#define DMA_SECCFGR_SEC0_Msk (0x1UL << DMA_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define DMA_SECCFGR_SEC0 DMA_SECCFGR_SEC0_Msk /*!< Secure State of Channel 0 */ +#define DMA_SECCFGR_SEC1_Pos (1U) +#define DMA_SECCFGR_SEC1_Msk (0x1UL << DMA_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define DMA_SECCFGR_SEC1 DMA_SECCFGR_SEC1_Msk /*!< Secure State of Channel 1 */ +#define DMA_SECCFGR_SEC2_Pos (2U) +#define DMA_SECCFGR_SEC2_Msk (0x1UL << DMA_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define DMA_SECCFGR_SEC2 DMA_SECCFGR_SEC2_Msk /*!< Secure State of Channel 2 */ +#define DMA_SECCFGR_SEC3_Pos (3U) +#define DMA_SECCFGR_SEC3_Msk (0x1UL << DMA_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define DMA_SECCFGR_SEC3 DMA_SECCFGR_SEC3_Msk /*!< Secure State of Channel 3 */ +#define DMA_SECCFGR_SEC4_Pos (4U) +#define DMA_SECCFGR_SEC4_Msk (0x1UL << DMA_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define DMA_SECCFGR_SEC4 DMA_SECCFGR_SEC4_Msk /*!< Secure State of Channel 4 */ +#define DMA_SECCFGR_SEC5_Pos (5U) +#define DMA_SECCFGR_SEC5_Msk (0x1UL << DMA_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define DMA_SECCFGR_SEC5 DMA_SECCFGR_SEC5_Msk /*!< Secure State of Channel 5 */ +#define DMA_SECCFGR_SEC6_Pos (6U) +#define DMA_SECCFGR_SEC6_Msk (0x1UL << DMA_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define DMA_SECCFGR_SEC6 DMA_SECCFGR_SEC6_Msk /*!< Secure State of Channel 6 */ +#define DMA_SECCFGR_SEC7_Pos (7U) +#define DMA_SECCFGR_SEC7_Msk (0x1UL << DMA_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define DMA_SECCFGR_SEC7 DMA_SECCFGR_SEC7_Msk /*!< Secure State of Channel 7 */ + +/******************* Bit definition for DMA_PRIVCFGR register ****************/ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of Channel 7 */ + +/******************* Bit definition for DMA_RCFGLOCKR register ****************/ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Privileged and Secure State Lock of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Privileged and Secure State Lock of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Privileged and Secure State Lock of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Privileged and Secure State Lock of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Privileged and Secure State Lock of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Privileged and Secure State Lock of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Privileged and Secure State Lock of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Privileged and Secure State Lock of Channel 7 */ + +/******************* Bit definition for DMA_MISR register ****************/ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */ + +/******************* Bit definition for DMA_SMISR register ****************/ +#define DMA_SMISR_MIS0_Pos (0U) +#define DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk /*!< Masked Interrupt State of Secure Channel 0 */ +#define DMA_SMISR_MIS1_Pos (1U) +#define DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk /*!< Masked Interrupt State of Secure Channel 1 */ +#define DMA_SMISR_MIS2_Pos (2U) +#define DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk /*!< Masked Interrupt State of Secure Channel 2 */ +#define DMA_SMISR_MIS3_Pos (3U) +#define DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk /*!< Masked Interrupt State of Secure Channel 3 */ +#define DMA_SMISR_MIS4_Pos (4U) +#define DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk /*!< Masked Interrupt State of Secure Channel 4 */ +#define DMA_SMISR_MIS5_Pos (5U) +#define DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk /*!< Masked Interrupt State of Secure Channel 5 */ +#define DMA_SMISR_MIS6_Pos (6U) +#define DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk /*!< Masked Interrupt State of Secure Channel 6 */ +#define DMA_SMISR_MIS7_Pos (7U) +#define DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk /*!< Masked Interrupt State of Secure Channel 7 */ + +/******************* Bit definition for DMA_CLBAR register ****************/ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address of DMA channel x */ + +/******************* Bit definition for DMA_CFCR register *******************/ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun flag clear */ + +/******************* Bit definition for DMA_CSR register *******************/ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun event flag */ +#define DMA_CSR_FIFOL_Pos (16U) +#define DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) /*!< 0x00FF0000 */ +#define DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk /*!< Monitored FIFO level in bytes */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_LAP_Pos (17U) +#define DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) /*!< 0x00020000 */ +#define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-list allocated port */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for DMA_CTR1 register *******************/ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_SBL_1_Pos (4U) +#define DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) /*!< 0x000003F0 */ +#define DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk /*!< Source burst length minus 1 */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */ +#define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SBX_Pos (13U) +#define DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) /*!< 0x00002000 */ +#define DMA_CTR1_SBX DMA_CTR1_SBX_Msk /*!< Source byte exchange within the unaligned half-word of each source word */ +#define DMA_CTR1_SAP_Pos (14U) +#define DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) /*!< 0x00004000 */ +#define DMA_CTR1_SAP DMA_CTR1_SAP_Msk /*!< Source allocated port */ +#define DMA_CTR1_SSEC_Pos (15U) +#define DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) /*!< 0x00008000 */ +#define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security attribute of the DMA transfer from the source */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the destination data width of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing burst */ +#define DMA_CTR1_DBL_1_Pos (20U) +#define DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) /*!< 0x03F00000 */ +#define DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk /*!< Destination burst length minus 1 */ +#define DMA_CTR1_DBX_Pos (26U) +#define DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) /*!< 0x04000000 */ +#define DMA_CTR1_DBX DMA_CTR1_DBX_Msk /*!< Destination byte exchange */ +#define DMA_CTR1_DHX_Pos (27U) +#define DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) /*!< 0x08000000 */ +#define DMA_CTR1_DHX DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */ +#define DMA_CTR1_DAP_Pos (30U) +#define DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) /*!< 0x40000000 */ +#define DMA_CTR1_DAP DMA_CTR1_DAP_Msk /*!< Destination allocated port */ +#define DMA_CTR1_DSEC_Pos (31U) +#define DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) /*!< 0x80000000 */ +#define DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk /*!< Security attribute of the DMA transfer from the destination */ + +/****************** Bit definition for DMA_CTR2 register *******************/ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x3FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000003F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_DREQ_Pos (10U) +#define DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk /*!< Destination hardware request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/****************** Bit definition for DMA_CBR1 register *******************/ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes to transfer from the source */ + +/****************** Bit definition for DMA_CSAR register ********************/ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/****************** Bit definition for DMA_CDAR register *******************/ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/****************** Bit definition for DMA_CLLR register *******************/ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger configuration for input line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger configuration for input line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */ +#define EXTI_RPR1_RPIF17_Pos (17U) +#define EXTI_RPR1_RPIF17_Msk (0x1UL << EXTI_RPR1_RPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_RPR1_RPIF17 EXTI_RPR1_RPIF17_Msk /*!< Rising Pending Interrupt Flag on line 17 */ +#define EXTI_RPR1_RPIF18_Pos (18U) +#define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */ +#define EXTI_FPR1_FPIF17_Pos (17U) +#define EXTI_FPR1_FPIF17_Msk (0x1UL << EXTI_FPR1_FPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_FPR1_FPIF17 EXTI_FPR1_FPIF17_Msk /*!< Falling Pending Interrupt Flag on line 17 */ +#define EXTI_FPR1_FPIF18_Pos (18U) +#define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_SECCFGR1 register ******************/ +#define EXTI_SECCFGR1_SEC0_Pos (0U) +#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */ +#define EXTI_SECCFGR1_SEC1_Pos (1U) +#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */ +#define EXTI_SECCFGR1_SEC2_Pos (2U) +#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */ +#define EXTI_SECCFGR1_SEC3_Pos (3U) +#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */ +#define EXTI_SECCFGR1_SEC4_Pos (4U) +#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */ +#define EXTI_SECCFGR1_SEC5_Pos (5U) +#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */ +#define EXTI_SECCFGR1_SEC6_Pos (6U) +#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */ +#define EXTI_SECCFGR1_SEC7_Pos (7U) +#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */ +#define EXTI_SECCFGR1_SEC8_Pos (8U) +#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */ +#define EXTI_SECCFGR1_SEC9_Pos (9U) +#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */ +#define EXTI_SECCFGR1_SEC10_Pos (10U) +#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */ +#define EXTI_SECCFGR1_SEC11_Pos (11U) +#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */ +#define EXTI_SECCFGR1_SEC12_Pos (12U) +#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */ +#define EXTI_SECCFGR1_SEC13_Pos (13U) +#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */ +#define EXTI_SECCFGR1_SEC14_Pos (14U) +#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */ +#define EXTI_SECCFGR1_SEC15_Pos (15U) +#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */ +#define EXTI_SECCFGR1_SEC16_Pos (16U) +#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on line 16 */ +#define EXTI_SECCFGR1_SEC17_Pos (17U) +#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */ +#define EXTI_SECCFGR1_SEC18_Pos (18U) +#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */ + +/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on line 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI0_4 (0x10UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR1_EXTI0_5 (0x20UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR1_EXTI0_6 (0x40UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR1_EXTI0_7 (0x80UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI1_4 (0x10UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR1_EXTI1_5 (0x20UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR1_EXTI1_6 (0x40UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR1_EXTI1_7 (0x80UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI2_4 (0x10UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR1_EXTI2_5 (0x20UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR1_EXTI2_6 (0x40UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR1_EXTI2_7 (0x80UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR1_EXTI3_4 (0x10UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR1_EXTI3_5 (0x20UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR1_EXTI3_6 (0x40UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR1_EXTI3_7 (0x80UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI4_4 (0x10UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR2_EXTI4_5 (0x20UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR2_EXTI4_6 (0x40UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR2_EXTI4_7 (0x80UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI5_4 (0x10UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR2_EXTI5_5 (0x20UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR2_EXTI5_6 (0x40UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR2_EXTI5_7 (0x80UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI6_4 (0x10UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR2_EXTI6_5 (0x20UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR2_EXTI6_6 (0x40UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR2_EXTI6_7 (0x80UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR2_EXTI7_4 (0x10UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR2_EXTI7_5 (0x20UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR2_EXTI7_6 (0x40UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR2_EXTI7_7 (0x80UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI8_4 (0x10UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR3_EXTI8_5 (0x20UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR3_EXTI8_6 (0x40UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR3_EXTI8_7 (0x80UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI9_4 (0x10UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR3_EXTI9_5 (0x20UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR3_EXTI9_6 (0x40UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR3_EXTI9_7 (0x80UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI10_4 (0x10UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR3_EXTI10_5 (0x20UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR3_EXTI10_6 (0x40UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR3_EXTI10_7 (0x80UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR3_EXTI11_4 (0x10UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR3_EXTI11_5 (0x20UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR3_EXTI11_6 (0x40UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR3_EXTI11_7 (0x80UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI12_4 (0x10UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR4_EXTI12_5 (0x20UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR4_EXTI12_6 (0x40UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR4_EXTI12_7 (0x80UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI13_4 (0x10UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR4_EXTI13_5 (0x20UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR4_EXTI13_6 (0x40UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR4_EXTI13_7 (0x80UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI14_4 (0x10UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR4_EXTI14_5 (0x20UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR4_EXTI14_6 (0x40UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR4_EXTI14_7 (0x80UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR4_EXTI15_4 (0x10UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR4_EXTI15_5 (0x20UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR4_EXTI15_6 (0x40UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR4_EXTI15_7 (0x80UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for EXTI_LOCKR register ******************/ +#define EXTI_LOCKR_LOCK_Pos (0U) +#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */ +#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Security and privilege configuration lock */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0 /* FLASH Latency 1 Wait State */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_LATENCY_3 (0x8UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ_Pos (12U) +#define FLASH_ACR_PDREQ_Msk (0x1UL << FLASH_ACR_PDREQ_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ FLASH_ACR_PDREQ_Msk /*!< Flash power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSKEYR register *****************/ +#define FLASH_NSKEYR_NSKEY_Pos (0U) +#define FLASH_NSKEYR_NSKEY_Msk (0xFFFFFFFFUL << FLASH_NSKEYR_NSKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_NSKEYR_NSKEY FLASH_NSKEYR_NSKEY_Msk /*!< Flash memory non-secure key */ + +/****************** Bits definition for FLASH_SECKEYR register *****************/ +#define FLASH_SECKEYR_SECKEY_Pos (0U) +#define FLASH_SECKEYR_SECKEY_Msk (0xFFFFFFFFUL << FLASH_SECKEYR_SECKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_SECKEYR_SECKEY FLASH_SECKEYR_SECKEY_Msk /*!< Flash memory secure key */ + +/****************** Bits definition for FLASH_OPTKEYR register *****************/ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< Option byte key */ + +/****************** Bits definition for FLASH_PDKEYR register *****************/ +#define FLASH_PDKEYR_PDKEY_Pos (0U) +#define FLASH_PDKEYR_PDKEY_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_PDKEYR_PDKEY FLASH_PDKEYR_PDKEY_Msk /*!< Flash power-down key */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD_Pos (20U) +#define FLASH_NSSR_PD_Msk (0x1UL << FLASH_NSSR_PD_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD FLASH_NSSR_PD_Msk /*!< Flash in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR1 register *****************/ +#define FLASH_NSCR1_PG_Pos (0U) +#define FLASH_NSCR1_PG_Msk (0x1UL << FLASH_NSCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR1_PG FLASH_NSCR1_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR1_PER_Pos (1U) +#define FLASH_NSCR1_PER_Msk (0x1UL << FLASH_NSCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR1_PER FLASH_NSCR1_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR1_MER_Pos (2U) +#define FLASH_NSCR1_MER_Msk (0x1UL << FLASH_NSCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR1_MER FLASH_NSCR1_MER_Msk /*!< Non-secure Mass Erase */ +#define FLASH_NSCR1_PNB_Pos (3U) +#define FLASH_NSCR1_PNB_Msk (0x7FUL << FLASH_NSCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_NSCR1_PNB FLASH_NSCR1_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR1_BWR_Pos (14U) +#define FLASH_NSCR1_BWR_Msk (0x1UL << FLASH_NSCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR1_BWR FLASH_NSCR1_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR1_STRT_Pos (16U) +#define FLASH_NSCR1_STRT_Msk (0x1UL << FLASH_NSCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR1_STRT FLASH_NSCR1_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR1_OPTSTRT_Pos (17U) +#define FLASH_NSCR1_OPTSTRT_Msk (0x1UL << FLASH_NSCR1_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR1_OPTSTRT FLASH_NSCR1_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR1_EOPIE_Pos (24U) +#define FLASH_NSCR1_EOPIE_Msk (0x1UL << FLASH_NSCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR1_EOPIE FLASH_NSCR1_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR1_ERRIE_Pos (25U) +#define FLASH_NSCR1_ERRIE_Msk (0x1UL << FLASH_NSCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR1_ERRIE FLASH_NSCR1_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR1_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR1_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR1_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR1_OBL_LAUNCH FLASH_NSCR1_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR1_OPTLOCK_Pos (30U) +#define FLASH_NSCR1_OPTLOCK_Msk (0x1UL << FLASH_NSCR1_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR1_OPTLOCK FLASH_NSCR1_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR1_LOCK_Pos (31U) +#define FLASH_NSCR1_LOCK_Msk (0x1UL << FLASH_NSCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR1_LOCK FLASH_NSCR1_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR1 register ****************/ +#define FLASH_SECCR1_PG_Pos (0U) +#define FLASH_SECCR1_PG_Msk (0x1UL << FLASH_SECCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR1_PG FLASH_SECCR1_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR1_PER_Pos (1U) +#define FLASH_SECCR1_PER_Msk (0x1UL << FLASH_SECCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR1_PER FLASH_SECCR1_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR1_MER_Pos (2U) +#define FLASH_SECCR1_MER_Msk (0x1UL << FLASH_SECCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR1_MER FLASH_SECCR1_MER_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR1_PNB_Pos (3U) +#define FLASH_SECCR1_PNB_Msk (0x7FUL << FLASH_SECCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_SECCR1_PNB FLASH_SECCR1_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR1_BWR_Pos (14U) +#define FLASH_SECCR1_BWR_Msk (0x1UL << FLASH_SECCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR1_BWR FLASH_SECCR1_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR1_STRT_Pos (16U) +#define FLASH_SECCR1_STRT_Msk (0x1UL << FLASH_SECCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR1_STRT FLASH_SECCR1_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR1_EOPIE_Pos (24U) +#define FLASH_SECCR1_EOPIE_Msk (0x1UL << FLASH_SECCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR1_EOPIE FLASH_SECCR1_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR1_ERRIE_Pos (25U) +#define FLASH_SECCR1_ERRIE_Msk (0x1UL << FLASH_SECCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR1_ERRIE FLASH_SECCR1_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR1_INV_Pos (29U) +#define FLASH_SECCR1_INV_Msk (0x1UL << FLASH_SECCR1_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR1_INV FLASH_SECCR1_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR1_LOCK_Pos (31U) +#define FLASH_SECCR1_LOCK_Msk (0x1UL << FLASH_SECCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR1_LOCK FLASH_SECCR1_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in system Flash memory interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x07000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x02000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x04000000 */ + +/******************* Bits definition for FLASH_NSCR2 register ***************/ +#define FLASH_NSCR2_PS_Pos (0U) +#define FLASH_NSCR2_PS_Msk (0x1UL << FLASH_NSCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR2_PS FLASH_NSCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_NSCR2_ES_Pos (1U) +#define FLASH_NSCR2_ES_Msk (0x1UL << FLASH_NSCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR2_ES FLASH_NSCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_SECCR2 register ***************/ +#define FLASH_SECCR2_PS_Pos (0U) +#define FLASH_SECCR2_PS_Msk (0x1UL << FLASH_SECCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR2_PS FLASH_SECCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_SECCR2_ES_Pos (1U) +#define FLASH_SECCR2_ES_Msk (0x1UL << FLASH_SECCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR2_ES FLASH_SECCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_SRAM1_RST_Pos (15U) +#define FLASH_OPTR_SRAM1_RST_Msk (0x1UL << FLASH_OPTR_SRAM1_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM1_RST FLASH_OPTR_SRAM1_RST_Msk /*!< SRAM1 erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SRAM2_PE_Pos (24U) +#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWMR1 register **************/ +#define FLASH_SECWMR1_SECWM_PSTRT_Pos (0U) +#define FLASH_SECWMR1_SECWM_PSTRT_Msk (0x7FUL << FLASH_SECWMR1_SECWM_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWMR1_SECWM_PSTRT FLASH_SECWMR1_SECWM_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWMR1_SECWM_PEND_Pos (16U) +#define FLASH_SECWMR1_SECWM_PEND_Msk (0x7FUL << FLASH_SECWMR1_SECWM_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR1_SECWM_PEND FLASH_SECWMR1_SECWM_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWMR2 register **************/ +#define FLASH_SECWMR2_HDP_PEND_Pos (16U) +#define FLASH_SECWMR2_HDP_PEND_Msk (0x7FUL << FLASH_SECWMR2_HDP_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR2_HDP_PEND FLASH_SECWMR2_HDP_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWMR2_HDPEN_Pos (31U) +#define FLASH_SECWMR2_HDPEN_Msk (0x1UL << FLASH_SECWMR2_HDPEN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWMR2_HDPEN FLASH_SECWMR2_HDPEN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRPAR register ***************/ +#define FLASH_WRPAR_WRPA_PSTRT_Pos (0U) +#define FLASH_WRPAR_WRPA_PSTRT_Msk (0x7FUL << FLASH_WRPAR_WRPA_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRPAR_WRPA_PSTRT FLASH_WRPAR_WRPA_PSTRT_Msk /*!< WPR first area A start page */ +#define FLASH_WRPAR_WRPA_PEND_Pos (16U) +#define FLASH_WRPAR_WRPA_PEND_Msk (0x7FUL << FLASH_WRPAR_WRPA_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRPAR_WRPA_PEND FLASH_WRPAR_WRPA_PEND_Msk /*!< WPR first area A end page */ +#define FLASH_WRPAR_UNLOCK_Pos (31U) +#define FLASH_WRPAR_UNLOCK_Msk (0x1UL << FLASH_WRPAR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPAR_UNLOCK FLASH_WRPAR_UNLOCK_Msk /*!< WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRPBR register ***************/ +#define FLASH_WRPBR_WRPB_PSTRT_Pos (0U) +#define FLASH_WRPBR_WRPB_PSTRT_Msk (0x7FUL << FLASH_WRPBR_WRPB_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRPBR_WRPB_PSTRT FLASH_WRPBR_WRPB_PSTRT_Msk /*!< WPR second area B start page */ +#define FLASH_WRPBR_WRPB_PEND_Pos (16U) +#define FLASH_WRPBR_WRPB_PEND_Msk (0x7FUL << FLASH_WRPBR_WRPB_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRPBR_WRPB_PEND FLASH_WRPBR_WRPB_PEND_Msk /*!< WPR second area B end page */ +#define FLASH_WRPBR_UNLOCK_Pos (31U) +#define FLASH_WRPBR_UNLOCK_Msk (0x1UL << FLASH_WRPBR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPBR_UNLOCK FLASH_WRPBR_UNLOCK_Msk /*!< WPR first area B unlock */ + +/****************** Bits definition for FLASH_OEM1KEYR1 register *****************/ +#define FLASH_OEM1KEYR1_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR1_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR1_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR1_OEM1KEY FLASH_OEM1KEYR1_OEM1KEY_Msk /*!< OEM1 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM1KEYR2 register *****************/ +#define FLASH_OEM1KEYR2_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR2_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR2_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR2_OEM1KEY FLASH_OEM1KEYR2_OEM1KEY_Msk /*!< OEM1 most significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR1 register *****************/ +#define FLASH_OEM2KEYR1_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR1_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR1_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR1_OEM2KEY FLASH_OEM2KEYR1_OEM2KEY_Msk /*!< OEM2 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR2 register *****************/ +#define FLASH_OEM2KEYR2_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR2_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR2_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR2_OEM2KEY FLASH_OEM2KEYR2_OEM2KEY_Msk /*!< OEM2 most significant bytes key */ + +/******************* Bit definition for FLASH_SECBBR1 register ******************/ +#define FLASH_SECBBR1_SECBB0_Pos (0U) +#define FLASH_SECBBR1_SECBB0_Msk (0x1UL << FLASH_SECBBR1_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR1_SECBB0 FLASH_SECBBR1_SECBB0_Msk /*!< Page 0 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB1_Pos (1U) +#define FLASH_SECBBR1_SECBB1_Msk (0x1UL << FLASH_SECBBR1_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR1_SECBB1 FLASH_SECBBR1_SECBB1_Msk /*!< Page 1 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB2_Pos (2U) +#define FLASH_SECBBR1_SECBB2_Msk (0x1UL << FLASH_SECBBR1_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR1_SECBB2 FLASH_SECBBR1_SECBB2_Msk /*!< Page 2 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB3_Pos (3U) +#define FLASH_SECBBR1_SECBB3_Msk (0x1UL << FLASH_SECBBR1_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR1_SECBB3 FLASH_SECBBR1_SECBB3_Msk /*!< Page 3 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB4_Pos (4U) +#define FLASH_SECBBR1_SECBB4_Msk (0x1UL << FLASH_SECBBR1_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR1_SECBB4 FLASH_SECBBR1_SECBB4_Msk /*!< Page 4 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB5_Pos (5U) +#define FLASH_SECBBR1_SECBB5_Msk (0x1UL << FLASH_SECBBR1_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR1_SECBB5 FLASH_SECBBR1_SECBB5_Msk /*!< Page 5 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB6_Pos (6U) +#define FLASH_SECBBR1_SECBB6_Msk (0x1UL << FLASH_SECBBR1_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR1_SECBB6 FLASH_SECBBR1_SECBB6_Msk /*!< Page 6 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB7_Pos (7U) +#define FLASH_SECBBR1_SECBB7_Msk (0x1UL << FLASH_SECBBR1_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR1_SECBB7 FLASH_SECBBR1_SECBB7_Msk /*!< Page 7 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB8_Pos (8U) +#define FLASH_SECBBR1_SECBB8_Msk (0x1UL << FLASH_SECBBR1_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR1_SECBB8 FLASH_SECBBR1_SECBB8_Msk /*!< Page 8 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB9_Pos (9U) +#define FLASH_SECBBR1_SECBB9_Msk (0x1UL << FLASH_SECBBR1_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR1_SECBB9 FLASH_SECBBR1_SECBB9_Msk /*!< Page 9 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB10_Pos (10U) +#define FLASH_SECBBR1_SECBB10_Msk (0x1UL << FLASH_SECBBR1_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR1_SECBB10 FLASH_SECBBR1_SECBB10_Msk /*!< Page 10 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB11_Pos (11U) +#define FLASH_SECBBR1_SECBB11_Msk (0x1UL << FLASH_SECBBR1_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR1_SECBB11 FLASH_SECBBR1_SECBB11_Msk /*!< Page 11 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB12_Pos (12U) +#define FLASH_SECBBR1_SECBB12_Msk (0x1UL << FLASH_SECBBR1_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR1_SECBB12 FLASH_SECBBR1_SECBB12_Msk /*!< Page 12 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB13_Pos (13U) +#define FLASH_SECBBR1_SECBB13_Msk (0x1UL << FLASH_SECBBR1_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR1_SECBB13 FLASH_SECBBR1_SECBB13_Msk /*!< Page 13 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB14_Pos (14U) +#define FLASH_SECBBR1_SECBB14_Msk (0x1UL << FLASH_SECBBR1_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR1_SECBB14 FLASH_SECBBR1_SECBB14_Msk /*!< Page 14 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB15_Pos (15U) +#define FLASH_SECBBR1_SECBB15_Msk (0x1UL << FLASH_SECBBR1_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR1_SECBB15 FLASH_SECBBR1_SECBB15_Msk /*!< Page 15 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB16_Pos (16U) +#define FLASH_SECBBR1_SECBB16_Msk (0x1UL << FLASH_SECBBR1_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR1_SECBB16 FLASH_SECBBR1_SECBB16_Msk /*!< Page 16 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB17_Pos (17U) +#define FLASH_SECBBR1_SECBB17_Msk (0x1UL << FLASH_SECBBR1_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR1_SECBB17 FLASH_SECBBR1_SECBB17_Msk /*!< Page 17 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB18_Pos (18U) +#define FLASH_SECBBR1_SECBB18_Msk (0x1UL << FLASH_SECBBR1_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR1_SECBB18 FLASH_SECBBR1_SECBB18_Msk /*!< Page 18 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB19_Pos (19U) +#define FLASH_SECBBR1_SECBB19_Msk (0x1UL << FLASH_SECBBR1_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR1_SECBB19 FLASH_SECBBR1_SECBB19_Msk /*!< Page 19 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB20_Pos (20U) +#define FLASH_SECBBR1_SECBB20_Msk (0x1UL << FLASH_SECBBR1_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR1_SECBB20 FLASH_SECBBR1_SECBB20_Msk /*!< Page 20 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB21_Pos (21U) +#define FLASH_SECBBR1_SECBB21_Msk (0x1UL << FLASH_SECBBR1_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR1_SECBB21 FLASH_SECBBR1_SECBB21_Msk /*!< Page 21 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB22_Pos (22U) +#define FLASH_SECBBR1_SECBB22_Msk (0x1UL << FLASH_SECBBR1_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR1_SECBB22 FLASH_SECBBR1_SECBB22_Msk /*!< Page 22 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB23_Pos (23U) +#define FLASH_SECBBR1_SECBB23_Msk (0x1UL << FLASH_SECBBR1_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR1_SECBB23 FLASH_SECBBR1_SECBB23_Msk /*!< Page 23 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB24_Pos (24U) +#define FLASH_SECBBR1_SECBB24_Msk (0x1UL << FLASH_SECBBR1_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR1_SECBB24 FLASH_SECBBR1_SECBB24_Msk /*!< Page 24 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB25_Pos (25U) +#define FLASH_SECBBR1_SECBB25_Msk (0x1UL << FLASH_SECBBR1_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR1_SECBB25 FLASH_SECBBR1_SECBB25_Msk /*!< Page 25 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB26_Pos (26U) +#define FLASH_SECBBR1_SECBB26_Msk (0x1UL << FLASH_SECBBR1_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR1_SECBB26 FLASH_SECBBR1_SECBB26_Msk /*!< Page 26 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB27_Pos (27U) +#define FLASH_SECBBR1_SECBB27_Msk (0x1UL << FLASH_SECBBR1_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR1_SECBB27 FLASH_SECBBR1_SECBB27_Msk /*!< Page 27 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB28_Pos (28U) +#define FLASH_SECBBR1_SECBB28_Msk (0x1UL << FLASH_SECBBR1_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR1_SECBB28 FLASH_SECBBR1_SECBB28_Msk /*!< Page 28 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB29_Pos (29U) +#define FLASH_SECBBR1_SECBB29_Msk (0x1UL << FLASH_SECBBR1_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR1_SECBB29 FLASH_SECBBR1_SECBB29_Msk /*!< Page 29 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB30_Pos (30U) +#define FLASH_SECBBR1_SECBB30_Msk (0x1UL << FLASH_SECBBR1_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR1_SECBB30 FLASH_SECBBR1_SECBB30_Msk /*!< Page 30 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB31_Pos (31U) +#define FLASH_SECBBR1_SECBB31_Msk (0x1UL << FLASH_SECBBR1_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR1_SECBB31 FLASH_SECBBR1_SECBB31_Msk /*!< Page 31 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR2 register ******************/ +#define FLASH_SECBBR2_SECBB0_Pos (0U) +#define FLASH_SECBBR2_SECBB0_Msk (0x1UL << FLASH_SECBBR2_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR2_SECBB0 FLASH_SECBBR2_SECBB0_Msk /*!< Page 32 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB1_Pos (1U) +#define FLASH_SECBBR2_SECBB1_Msk (0x1UL << FLASH_SECBBR2_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR2_SECBB1 FLASH_SECBBR2_SECBB1_Msk /*!< Page 33 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB2_Pos (2U) +#define FLASH_SECBBR2_SECBB2_Msk (0x1UL << FLASH_SECBBR2_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR2_SECBB2 FLASH_SECBBR2_SECBB2_Msk /*!< Page 34 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB3_Pos (3U) +#define FLASH_SECBBR2_SECBB3_Msk (0x1UL << FLASH_SECBBR2_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR2_SECBB3 FLASH_SECBBR2_SECBB3_Msk /*!< Page 35 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB4_Pos (4U) +#define FLASH_SECBBR2_SECBB4_Msk (0x1UL << FLASH_SECBBR2_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR2_SECBB4 FLASH_SECBBR2_SECBB4_Msk /*!< Page 36 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB5_Pos (5U) +#define FLASH_SECBBR2_SECBB5_Msk (0x1UL << FLASH_SECBBR2_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR2_SECBB5 FLASH_SECBBR2_SECBB5_Msk /*!< Page 37 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB6_Pos (6U) +#define FLASH_SECBBR2_SECBB6_Msk (0x1UL << FLASH_SECBBR2_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR2_SECBB6 FLASH_SECBBR2_SECBB6_Msk /*!< Page 38 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB7_Pos (7U) +#define FLASH_SECBBR2_SECBB7_Msk (0x1UL << FLASH_SECBBR2_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR2_SECBB7 FLASH_SECBBR2_SECBB7_Msk /*!< Page 39 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB8_Pos (8U) +#define FLASH_SECBBR2_SECBB8_Msk (0x1UL << FLASH_SECBBR2_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR2_SECBB8 FLASH_SECBBR2_SECBB8_Msk /*!< Page 40 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB9_Pos (9U) +#define FLASH_SECBBR2_SECBB9_Msk (0x1UL << FLASH_SECBBR2_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR2_SECBB9 FLASH_SECBBR2_SECBB9_Msk /*!< Page 41 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB10_Pos (10U) +#define FLASH_SECBBR2_SECBB10_Msk (0x1UL << FLASH_SECBBR2_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR2_SECBB10 FLASH_SECBBR2_SECBB10_Msk /*!< Page 42 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB11_Pos (11U) +#define FLASH_SECBBR2_SECBB11_Msk (0x1UL << FLASH_SECBBR2_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR2_SECBB11 FLASH_SECBBR2_SECBB11_Msk /*!< Page 43 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB12_Pos (12U) +#define FLASH_SECBBR2_SECBB12_Msk (0x1UL << FLASH_SECBBR2_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR2_SECBB12 FLASH_SECBBR2_SECBB12_Msk /*!< Page 44 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB13_Pos (13U) +#define FLASH_SECBBR2_SECBB13_Msk (0x1UL << FLASH_SECBBR2_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR2_SECBB13 FLASH_SECBBR2_SECBB13_Msk /*!< Page 45 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB14_Pos (14U) +#define FLASH_SECBBR2_SECBB14_Msk (0x1UL << FLASH_SECBBR2_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR2_SECBB14 FLASH_SECBBR2_SECBB14_Msk /*!< Page 46 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB15_Pos (15U) +#define FLASH_SECBBR2_SECBB15_Msk (0x1UL << FLASH_SECBBR2_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR2_SECBB15 FLASH_SECBBR2_SECBB15_Msk /*!< Page 47 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB16_Pos (16U) +#define FLASH_SECBBR2_SECBB16_Msk (0x1UL << FLASH_SECBBR2_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR2_SECBB16 FLASH_SECBBR2_SECBB16_Msk /*!< Page 48 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB17_Pos (17U) +#define FLASH_SECBBR2_SECBB17_Msk (0x1UL << FLASH_SECBBR2_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR2_SECBB17 FLASH_SECBBR2_SECBB17_Msk /*!< Page 49 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB18_Pos (18U) +#define FLASH_SECBBR2_SECBB18_Msk (0x1UL << FLASH_SECBBR2_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR2_SECBB18 FLASH_SECBBR2_SECBB18_Msk /*!< Page 50 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB19_Pos (19U) +#define FLASH_SECBBR2_SECBB19_Msk (0x1UL << FLASH_SECBBR2_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR2_SECBB19 FLASH_SECBBR2_SECBB19_Msk /*!< Page 51 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB20_Pos (20U) +#define FLASH_SECBBR2_SECBB20_Msk (0x1UL << FLASH_SECBBR2_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR2_SECBB20 FLASH_SECBBR2_SECBB20_Msk /*!< Page 52 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB21_Pos (21U) +#define FLASH_SECBBR2_SECBB21_Msk (0x1UL << FLASH_SECBBR2_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR2_SECBB21 FLASH_SECBBR2_SECBB21_Msk /*!< Page 53 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB22_Pos (22U) +#define FLASH_SECBBR2_SECBB22_Msk (0x1UL << FLASH_SECBBR2_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR2_SECBB22 FLASH_SECBBR2_SECBB22_Msk /*!< Page 54 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB23_Pos (23U) +#define FLASH_SECBBR2_SECBB23_Msk (0x1UL << FLASH_SECBBR2_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR2_SECBB23 FLASH_SECBBR2_SECBB23_Msk /*!< Page 55 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB24_Pos (24U) +#define FLASH_SECBBR2_SECBB24_Msk (0x1UL << FLASH_SECBBR2_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR2_SECBB24 FLASH_SECBBR2_SECBB24_Msk /*!< Page 56 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB25_Pos (25U) +#define FLASH_SECBBR2_SECBB25_Msk (0x1UL << FLASH_SECBBR2_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR2_SECBB25 FLASH_SECBBR2_SECBB25_Msk /*!< Page 57 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB26_Pos (26U) +#define FLASH_SECBBR2_SECBB26_Msk (0x1UL << FLASH_SECBBR2_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR2_SECBB26 FLASH_SECBBR2_SECBB26_Msk /*!< Page 58 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB27_Pos (27U) +#define FLASH_SECBBR2_SECBB27_Msk (0x1UL << FLASH_SECBBR2_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR2_SECBB27 FLASH_SECBBR2_SECBB27_Msk /*!< Page 59 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB28_Pos (28U) +#define FLASH_SECBBR2_SECBB28_Msk (0x1UL << FLASH_SECBBR2_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR2_SECBB28 FLASH_SECBBR2_SECBB28_Msk /*!< Page 60 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB29_Pos (29U) +#define FLASH_SECBBR2_SECBB29_Msk (0x1UL << FLASH_SECBBR2_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR2_SECBB29 FLASH_SECBBR2_SECBB29_Msk /*!< Page 61 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB30_Pos (30U) +#define FLASH_SECBBR2_SECBB30_Msk (0x1UL << FLASH_SECBBR2_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR2_SECBB30 FLASH_SECBBR2_SECBB30_Msk /*!< Page 62 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB31_Pos (31U) +#define FLASH_SECBBR2_SECBB31_Msk (0x1UL << FLASH_SECBBR2_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR2_SECBB31 FLASH_SECBBR2_SECBB31_Msk /*!< Page 63 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR3 register ******************/ +#define FLASH_SECBBR3_SECBB0_Pos (0U) +#define FLASH_SECBBR3_SECBB0_Msk (0x1UL << FLASH_SECBBR3_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR3_SECBB0 FLASH_SECBBR3_SECBB0_Msk /*!< Page 64 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB1_Pos (1U) +#define FLASH_SECBBR3_SECBB1_Msk (0x1UL << FLASH_SECBBR3_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR3_SECBB1 FLASH_SECBBR3_SECBB1_Msk /*!< Page 65 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB2_Pos (2U) +#define FLASH_SECBBR3_SECBB2_Msk (0x1UL << FLASH_SECBBR3_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR3_SECBB2 FLASH_SECBBR3_SECBB2_Msk /*!< Page 66 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB3_Pos (3U) +#define FLASH_SECBBR3_SECBB3_Msk (0x1UL << FLASH_SECBBR3_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR3_SECBB3 FLASH_SECBBR3_SECBB3_Msk /*!< Page 67 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB4_Pos (4U) +#define FLASH_SECBBR3_SECBB4_Msk (0x1UL << FLASH_SECBBR3_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR3_SECBB4 FLASH_SECBBR3_SECBB4_Msk /*!< Page 68 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB5_Pos (5U) +#define FLASH_SECBBR3_SECBB5_Msk (0x1UL << FLASH_SECBBR3_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR3_SECBB5 FLASH_SECBBR3_SECBB5_Msk /*!< Page 69 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB6_Pos (6U) +#define FLASH_SECBBR3_SECBB6_Msk (0x1UL << FLASH_SECBBR3_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR3_SECBB6 FLASH_SECBBR3_SECBB6_Msk /*!< Page 70 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB7_Pos (7U) +#define FLASH_SECBBR3_SECBB7_Msk (0x1UL << FLASH_SECBBR3_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR3_SECBB7 FLASH_SECBBR3_SECBB7_Msk /*!< Page 71 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB8_Pos (8U) +#define FLASH_SECBBR3_SECBB8_Msk (0x1UL << FLASH_SECBBR3_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR3_SECBB8 FLASH_SECBBR3_SECBB8_Msk /*!< Page 72 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB9_Pos (9U) +#define FLASH_SECBBR3_SECBB9_Msk (0x1UL << FLASH_SECBBR3_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR3_SECBB9 FLASH_SECBBR3_SECBB9_Msk /*!< Page 73 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB10_Pos (10U) +#define FLASH_SECBBR3_SECBB10_Msk (0x1UL << FLASH_SECBBR3_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR3_SECBB10 FLASH_SECBBR3_SECBB10_Msk /*!< Page 74 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB11_Pos (11U) +#define FLASH_SECBBR3_SECBB11_Msk (0x1UL << FLASH_SECBBR3_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR3_SECBB11 FLASH_SECBBR3_SECBB11_Msk /*!< Page 75 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB12_Pos (12U) +#define FLASH_SECBBR3_SECBB12_Msk (0x1UL << FLASH_SECBBR3_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR3_SECBB12 FLASH_SECBBR3_SECBB12_Msk /*!< Page 76 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB13_Pos (13U) +#define FLASH_SECBBR3_SECBB13_Msk (0x1UL << FLASH_SECBBR3_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR3_SECBB13 FLASH_SECBBR3_SECBB13_Msk /*!< Page 77 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB14_Pos (14U) +#define FLASH_SECBBR3_SECBB14_Msk (0x1UL << FLASH_SECBBR3_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR3_SECBB14 FLASH_SECBBR3_SECBB14_Msk /*!< Page 78 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB15_Pos (15U) +#define FLASH_SECBBR3_SECBB15_Msk (0x1UL << FLASH_SECBBR3_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR3_SECBB15 FLASH_SECBBR3_SECBB15_Msk /*!< Page 79 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB16_Pos (16U) +#define FLASH_SECBBR3_SECBB16_Msk (0x1UL << FLASH_SECBBR3_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR3_SECBB16 FLASH_SECBBR3_SECBB16_Msk /*!< Page 80 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB17_Pos (17U) +#define FLASH_SECBBR3_SECBB17_Msk (0x1UL << FLASH_SECBBR3_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR3_SECBB17 FLASH_SECBBR3_SECBB17_Msk /*!< Page 81 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB18_Pos (18U) +#define FLASH_SECBBR3_SECBB18_Msk (0x1UL << FLASH_SECBBR3_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR3_SECBB18 FLASH_SECBBR3_SECBB18_Msk /*!< Page 82 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB19_Pos (19U) +#define FLASH_SECBBR3_SECBB19_Msk (0x1UL << FLASH_SECBBR3_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR3_SECBB19 FLASH_SECBBR3_SECBB19_Msk /*!< Page 83 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB20_Pos (20U) +#define FLASH_SECBBR3_SECBB20_Msk (0x1UL << FLASH_SECBBR3_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR3_SECBB20 FLASH_SECBBR3_SECBB20_Msk /*!< Page 84 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB21_Pos (21U) +#define FLASH_SECBBR3_SECBB21_Msk (0x1UL << FLASH_SECBBR3_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR3_SECBB21 FLASH_SECBBR3_SECBB21_Msk /*!< Page 85 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB22_Pos (22U) +#define FLASH_SECBBR3_SECBB22_Msk (0x1UL << FLASH_SECBBR3_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR3_SECBB22 FLASH_SECBBR3_SECBB22_Msk /*!< Page 86 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB23_Pos (23U) +#define FLASH_SECBBR3_SECBB23_Msk (0x1UL << FLASH_SECBBR3_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR3_SECBB23 FLASH_SECBBR3_SECBB23_Msk /*!< Page 87 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB24_Pos (24U) +#define FLASH_SECBBR3_SECBB24_Msk (0x1UL << FLASH_SECBBR3_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR3_SECBB24 FLASH_SECBBR3_SECBB24_Msk /*!< Page 88 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB25_Pos (25U) +#define FLASH_SECBBR3_SECBB25_Msk (0x1UL << FLASH_SECBBR3_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR3_SECBB25 FLASH_SECBBR3_SECBB25_Msk /*!< Page 89 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB26_Pos (26U) +#define FLASH_SECBBR3_SECBB26_Msk (0x1UL << FLASH_SECBBR3_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR3_SECBB26 FLASH_SECBBR3_SECBB26_Msk /*!< Page 90 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB27_Pos (27U) +#define FLASH_SECBBR3_SECBB27_Msk (0x1UL << FLASH_SECBBR3_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR3_SECBB27 FLASH_SECBBR3_SECBB27_Msk /*!< Page 91 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB28_Pos (28U) +#define FLASH_SECBBR3_SECBB28_Msk (0x1UL << FLASH_SECBBR3_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR3_SECBB28 FLASH_SECBBR3_SECBB28_Msk /*!< Page 92 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB29_Pos (29U) +#define FLASH_SECBBR3_SECBB29_Msk (0x1UL << FLASH_SECBBR3_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR3_SECBB29 FLASH_SECBBR3_SECBB29_Msk /*!< Page 93 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB30_Pos (30U) +#define FLASH_SECBBR3_SECBB30_Msk (0x1UL << FLASH_SECBBR3_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR3_SECBB30 FLASH_SECBBR3_SECBB30_Msk /*!< Page 94 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB31_Pos (31U) +#define FLASH_SECBBR3_SECBB31_Msk (0x1UL << FLASH_SECBBR3_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR3_SECBB31 FLASH_SECBBR3_SECBB31_Msk /*!< Page 95 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR4 register ******************/ +#define FLASH_SECBBR4_SECBB0_Pos (0U) +#define FLASH_SECBBR4_SECBB0_Msk (0x1UL << FLASH_SECBBR4_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR4_SECBB0 FLASH_SECBBR4_SECBB0_Msk /*!< Page 96 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB1_Pos (1U) +#define FLASH_SECBBR4_SECBB1_Msk (0x1UL << FLASH_SECBBR4_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR4_SECBB1 FLASH_SECBBR4_SECBB1_Msk /*!< Page 97 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB2_Pos (2U) +#define FLASH_SECBBR4_SECBB2_Msk (0x1UL << FLASH_SECBBR4_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR4_SECBB2 FLASH_SECBBR4_SECBB2_Msk /*!< Page 98 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB3_Pos (3U) +#define FLASH_SECBBR4_SECBB3_Msk (0x1UL << FLASH_SECBBR4_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR4_SECBB3 FLASH_SECBBR4_SECBB3_Msk /*!< Page 99 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB4_Pos (4U) +#define FLASH_SECBBR4_SECBB4_Msk (0x1UL << FLASH_SECBBR4_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR4_SECBB4 FLASH_SECBBR4_SECBB4_Msk /*!< Page 100 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB5_Pos (5U) +#define FLASH_SECBBR4_SECBB5_Msk (0x1UL << FLASH_SECBBR4_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR4_SECBB5 FLASH_SECBBR4_SECBB5_Msk /*!< Page 101 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB6_Pos (6U) +#define FLASH_SECBBR4_SECBB6_Msk (0x1UL << FLASH_SECBBR4_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR4_SECBB6 FLASH_SECBBR4_SECBB6_Msk /*!< Page 102 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB7_Pos (7U) +#define FLASH_SECBBR4_SECBB7_Msk (0x1UL << FLASH_SECBBR4_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR4_SECBB7 FLASH_SECBBR4_SECBB7_Msk /*!< Page 103 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB8_Pos (8U) +#define FLASH_SECBBR4_SECBB8_Msk (0x1UL << FLASH_SECBBR4_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR4_SECBB8 FLASH_SECBBR4_SECBB8_Msk /*!< Page 104 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB9_Pos (9U) +#define FLASH_SECBBR4_SECBB9_Msk (0x1UL << FLASH_SECBBR4_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR4_SECBB9 FLASH_SECBBR4_SECBB9_Msk /*!< Page 105 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB10_Pos (10U) +#define FLASH_SECBBR4_SECBB10_Msk (0x1UL << FLASH_SECBBR4_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR4_SECBB10 FLASH_SECBBR4_SECBB10_Msk /*!< Page 106 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB11_Pos (11U) +#define FLASH_SECBBR4_SECBB11_Msk (0x1UL << FLASH_SECBBR4_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR4_SECBB11 FLASH_SECBBR4_SECBB11_Msk /*!< Page 107 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB12_Pos (12U) +#define FLASH_SECBBR4_SECBB12_Msk (0x1UL << FLASH_SECBBR4_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR4_SECBB12 FLASH_SECBBR4_SECBB12_Msk /*!< Page 108 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB13_Pos (13U) +#define FLASH_SECBBR4_SECBB13_Msk (0x1UL << FLASH_SECBBR4_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR4_SECBB13 FLASH_SECBBR4_SECBB13_Msk /*!< Page 109 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB14_Pos (14U) +#define FLASH_SECBBR4_SECBB14_Msk (0x1UL << FLASH_SECBBR4_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR4_SECBB14 FLASH_SECBBR4_SECBB14_Msk /*!< Page 110 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB15_Pos (15U) +#define FLASH_SECBBR4_SECBB15_Msk (0x1UL << FLASH_SECBBR4_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR4_SECBB15 FLASH_SECBBR4_SECBB15_Msk /*!< Page 111 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB16_Pos (16U) +#define FLASH_SECBBR4_SECBB16_Msk (0x1UL << FLASH_SECBBR4_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR4_SECBB16 FLASH_SECBBR4_SECBB16_Msk /*!< Page 112 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB17_Pos (17U) +#define FLASH_SECBBR4_SECBB17_Msk (0x1UL << FLASH_SECBBR4_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR4_SECBB17 FLASH_SECBBR4_SECBB17_Msk /*!< Page 113 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB18_Pos (18U) +#define FLASH_SECBBR4_SECBB18_Msk (0x1UL << FLASH_SECBBR4_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR4_SECBB18 FLASH_SECBBR4_SECBB18_Msk /*!< Page 114 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB19_Pos (19U) +#define FLASH_SECBBR4_SECBB19_Msk (0x1UL << FLASH_SECBBR4_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR4_SECBB19 FLASH_SECBBR4_SECBB19_Msk /*!< Page 115 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB20_Pos (20U) +#define FLASH_SECBBR4_SECBB20_Msk (0x1UL << FLASH_SECBBR4_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR4_SECBB20 FLASH_SECBBR4_SECBB20_Msk /*!< Page 116 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB21_Pos (21U) +#define FLASH_SECBBR4_SECBB21_Msk (0x1UL << FLASH_SECBBR4_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR4_SECBB21 FLASH_SECBBR4_SECBB21_Msk /*!< Page 117 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB22_Pos (22U) +#define FLASH_SECBBR4_SECBB22_Msk (0x1UL << FLASH_SECBBR4_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR4_SECBB22 FLASH_SECBBR4_SECBB22_Msk /*!< Page 118 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB23_Pos (23U) +#define FLASH_SECBBR4_SECBB23_Msk (0x1UL << FLASH_SECBBR4_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR4_SECBB23 FLASH_SECBBR4_SECBB23_Msk /*!< Page 119 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB24_Pos (24U) +#define FLASH_SECBBR4_SECBB24_Msk (0x1UL << FLASH_SECBBR4_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR4_SECBB24 FLASH_SECBBR4_SECBB24_Msk /*!< Page 120 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB25_Pos (25U) +#define FLASH_SECBBR4_SECBB25_Msk (0x1UL << FLASH_SECBBR4_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR4_SECBB25 FLASH_SECBBR4_SECBB25_Msk /*!< Page 121 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB26_Pos (26U) +#define FLASH_SECBBR4_SECBB26_Msk (0x1UL << FLASH_SECBBR4_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR4_SECBB26 FLASH_SECBBR4_SECBB26_Msk /*!< Page 122 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB27_Pos (27U) +#define FLASH_SECBBR4_SECBB27_Msk (0x1UL << FLASH_SECBBR4_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR4_SECBB27 FLASH_SECBBR4_SECBB27_Msk /*!< Page 123 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB28_Pos (28U) +#define FLASH_SECBBR4_SECBB28_Msk (0x1UL << FLASH_SECBBR4_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR4_SECBB28 FLASH_SECBBR4_SECBB28_Msk /*!< Page 124 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB29_Pos (29U) +#define FLASH_SECBBR4_SECBB29_Msk (0x1UL << FLASH_SECBBR4_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR4_SECBB29 FLASH_SECBBR4_SECBB29_Msk /*!< Page 125 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB30_Pos (30U) +#define FLASH_SECBBR4_SECBB30_Msk (0x1UL << FLASH_SECBBR4_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR4_SECBB30 FLASH_SECBBR4_SECBB30_Msk /*!< Page 126 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB31_Pos (31U) +#define FLASH_SECBBR4_SECBB31_Msk (0x1UL << FLASH_SECBBR4_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR4_SECBB31 FLASH_SECBBR4_SECBB31_Msk /*!< Page 127 in Flash block-based secure */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP_ACCDIS FLASH_SECHDPCR_HDP_ACCDIS_Msk /*!< HDP area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************* Bit definition for FLASH_PRIVBBR1 register ******************/ +#define FLASH_PRIVBBR1_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR1_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR1_PRIVBB0 FLASH_PRIVBBR1_PRIVBB0_Msk /*!< Page 0 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR1_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR1_PRIVBB1 FLASH_PRIVBBR1_PRIVBB1_Msk /*!< Page 1 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR1_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR1_PRIVBB2 FLASH_PRIVBBR1_PRIVBB2_Msk /*!< Page 2 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR1_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR1_PRIVBB3 FLASH_PRIVBBR1_PRIVBB3_Msk /*!< Page 3 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR1_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR1_PRIVBB4 FLASH_PRIVBBR1_PRIVBB4_Msk /*!< Page 4 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR1_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR1_PRIVBB5 FLASH_PRIVBBR1_PRIVBB5_Msk /*!< Page 5 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR1_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR1_PRIVBB6 FLASH_PRIVBBR1_PRIVBB6_Msk /*!< Page 6 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR1_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR1_PRIVBB7 FLASH_PRIVBBR1_PRIVBB7_Msk /*!< Page 7 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR1_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR1_PRIVBB8 FLASH_PRIVBBR1_PRIVBB8_Msk /*!< Page 8 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR1_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR1_PRIVBB9 FLASH_PRIVBBR1_PRIVBB9_Msk /*!< Page 9 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR1_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR1_PRIVBB10 FLASH_PRIVBBR1_PRIVBB10_Msk /*!< Page 10 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR1_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR1_PRIVBB11 FLASH_PRIVBBR1_PRIVBB11_Msk /*!< Page 11 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR1_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR1_PRIVBB12 FLASH_PRIVBBR1_PRIVBB12_Msk /*!< Page 12 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR1_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR1_PRIVBB13 FLASH_PRIVBBR1_PRIVBB13_Msk /*!< Page 13 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR1_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR1_PRIVBB14 FLASH_PRIVBBR1_PRIVBB14_Msk /*!< Page 14 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR1_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR1_PRIVBB15 FLASH_PRIVBBR1_PRIVBB15_Msk /*!< Page 15 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR1_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR1_PRIVBB16 FLASH_PRIVBBR1_PRIVBB16_Msk /*!< Page 16 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR1_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR1_PRIVBB17 FLASH_PRIVBBR1_PRIVBB17_Msk /*!< Page 17 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR1_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR1_PRIVBB18 FLASH_PRIVBBR1_PRIVBB18_Msk /*!< Page 18 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR1_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR1_PRIVBB19 FLASH_PRIVBBR1_PRIVBB19_Msk /*!< Page 19 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR1_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR1_PRIVBB20 FLASH_PRIVBBR1_PRIVBB20_Msk /*!< Page 20 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR1_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR1_PRIVBB21 FLASH_PRIVBBR1_PRIVBB21_Msk /*!< Page 21 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR1_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR1_PRIVBB22 FLASH_PRIVBBR1_PRIVBB22_Msk /*!< Page 22 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR1_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR1_PRIVBB23 FLASH_PRIVBBR1_PRIVBB23_Msk /*!< Page 23 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR1_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR1_PRIVBB24 FLASH_PRIVBBR1_PRIVBB24_Msk /*!< Page 24 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR1_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR1_PRIVBB25 FLASH_PRIVBBR1_PRIVBB25_Msk /*!< Page 25 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR1_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR1_PRIVBB26 FLASH_PRIVBBR1_PRIVBB26_Msk /*!< Page 26 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR1_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR1_PRIVBB27 FLASH_PRIVBBR1_PRIVBB27_Msk /*!< Page 27 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR1_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR1_PRIVBB28 FLASH_PRIVBBR1_PRIVBB28_Msk /*!< Page 28 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR1_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR1_PRIVBB29 FLASH_PRIVBBR1_PRIVBB29_Msk /*!< Page 29 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR1_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR1_PRIVBB30 FLASH_PRIVBBR1_PRIVBB30_Msk /*!< Page 30 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR1_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR1_PRIVBB31 FLASH_PRIVBBR1_PRIVBB31_Msk /*!< Page 31 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR2 register ******************/ +#define FLASH_PRIVBBR2_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR2_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR2_PRIVBB0 FLASH_PRIVBBR2_PRIVBB0_Msk /*!< Page 32 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR2_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR2_PRIVBB1 FLASH_PRIVBBR2_PRIVBB1_Msk /*!< Page 33 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR2_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR2_PRIVBB2 FLASH_PRIVBBR2_PRIVBB2_Msk /*!< Page 34 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR2_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR2_PRIVBB3 FLASH_PRIVBBR2_PRIVBB3_Msk /*!< Page 35 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR2_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR2_PRIVBB4 FLASH_PRIVBBR2_PRIVBB4_Msk /*!< Page 36 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR2_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR2_PRIVBB5 FLASH_PRIVBBR2_PRIVBB5_Msk /*!< Page 37 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR2_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR2_PRIVBB6 FLASH_PRIVBBR2_PRIVBB6_Msk /*!< Page 38 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR2_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR2_PRIVBB7 FLASH_PRIVBBR2_PRIVBB7_Msk /*!< Page 39 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR2_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR2_PRIVBB8 FLASH_PRIVBBR2_PRIVBB8_Msk /*!< Page 40 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR2_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR2_PRIVBB9 FLASH_PRIVBBR2_PRIVBB9_Msk /*!< Page 41 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR2_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR2_PRIVBB10 FLASH_PRIVBBR2_PRIVBB10_Msk /*!< Page 42 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR2_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR2_PRIVBB11 FLASH_PRIVBBR2_PRIVBB11_Msk /*!< Page 43 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR2_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR2_PRIVBB12 FLASH_PRIVBBR2_PRIVBB12_Msk /*!< Page 44 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR2_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR2_PRIVBB13 FLASH_PRIVBBR2_PRIVBB13_Msk /*!< Page 45 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR2_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR2_PRIVBB14 FLASH_PRIVBBR2_PRIVBB14_Msk /*!< Page 46 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR2_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR2_PRIVBB15 FLASH_PRIVBBR2_PRIVBB15_Msk /*!< Page 47 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR2_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR2_PRIVBB16 FLASH_PRIVBBR2_PRIVBB16_Msk /*!< Page 48 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR2_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR2_PRIVBB17 FLASH_PRIVBBR2_PRIVBB17_Msk /*!< Page 49 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR2_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR2_PRIVBB18 FLASH_PRIVBBR2_PRIVBB18_Msk /*!< Page 50 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR2_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR2_PRIVBB19 FLASH_PRIVBBR2_PRIVBB19_Msk /*!< Page 51 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR2_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR2_PRIVBB20 FLASH_PRIVBBR2_PRIVBB20_Msk /*!< Page 52 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR2_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR2_PRIVBB21 FLASH_PRIVBBR2_PRIVBB21_Msk /*!< Page 53 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR2_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR2_PRIVBB22 FLASH_PRIVBBR2_PRIVBB22_Msk /*!< Page 54 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR2_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR2_PRIVBB23 FLASH_PRIVBBR2_PRIVBB23_Msk /*!< Page 55 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR2_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR2_PRIVBB24 FLASH_PRIVBBR2_PRIVBB24_Msk /*!< Page 56 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR2_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR2_PRIVBB25 FLASH_PRIVBBR2_PRIVBB25_Msk /*!< Page 57 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR2_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR2_PRIVBB26 FLASH_PRIVBBR2_PRIVBB26_Msk /*!< Page 58 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR2_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR2_PRIVBB27 FLASH_PRIVBBR2_PRIVBB27_Msk /*!< Page 59 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR2_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR2_PRIVBB28 FLASH_PRIVBBR2_PRIVBB28_Msk /*!< Page 60 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR2_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR2_PRIVBB29 FLASH_PRIVBBR2_PRIVBB29_Msk /*!< Page 61 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR2_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR2_PRIVBB30 FLASH_PRIVBBR2_PRIVBB30_Msk /*!< Page 62 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR2_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR2_PRIVBB31 FLASH_PRIVBBR2_PRIVBB31_Msk /*!< Page 63 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR3 register ******************/ +#define FLASH_PRIVBBR3_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR3_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR3_PRIVBB0 FLASH_PRIVBBR3_PRIVBB0_Msk /*!< Page 64 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR3_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR3_PRIVBB1 FLASH_PRIVBBR3_PRIVBB1_Msk /*!< Page 65 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR3_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR3_PRIVBB2 FLASH_PRIVBBR3_PRIVBB2_Msk /*!< Page 66 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR3_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR3_PRIVBB3 FLASH_PRIVBBR3_PRIVBB3_Msk /*!< Page 67 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR3_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR3_PRIVBB4 FLASH_PRIVBBR3_PRIVBB4_Msk /*!< Page 68 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR3_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR3_PRIVBB5 FLASH_PRIVBBR3_PRIVBB5_Msk /*!< Page 69 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR3_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR3_PRIVBB6 FLASH_PRIVBBR3_PRIVBB6_Msk /*!< Page 70 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR3_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR3_PRIVBB7 FLASH_PRIVBBR3_PRIVBB7_Msk /*!< Page 71 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR3_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR3_PRIVBB8 FLASH_PRIVBBR3_PRIVBB8_Msk /*!< Page 72 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR3_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR3_PRIVBB9 FLASH_PRIVBBR3_PRIVBB9_Msk /*!< Page 73 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR3_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR3_PRIVBB10 FLASH_PRIVBBR3_PRIVBB10_Msk /*!< Page 74 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR3_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR3_PRIVBB11 FLASH_PRIVBBR3_PRIVBB11_Msk /*!< Page 75 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR3_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR3_PRIVBB12 FLASH_PRIVBBR3_PRIVBB12_Msk /*!< Page 76 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR3_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR3_PRIVBB13 FLASH_PRIVBBR3_PRIVBB13_Msk /*!< Page 77 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR3_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR3_PRIVBB14 FLASH_PRIVBBR3_PRIVBB14_Msk /*!< Page 78 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR3_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR3_PRIVBB15 FLASH_PRIVBBR3_PRIVBB15_Msk /*!< Page 79 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR3_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR3_PRIVBB16 FLASH_PRIVBBR3_PRIVBB16_Msk /*!< Page 80 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR3_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR3_PRIVBB17 FLASH_PRIVBBR3_PRIVBB17_Msk /*!< Page 81 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR3_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR3_PRIVBB18 FLASH_PRIVBBR3_PRIVBB18_Msk /*!< Page 82 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR3_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR3_PRIVBB19 FLASH_PRIVBBR3_PRIVBB19_Msk /*!< Page 83 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR3_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR3_PRIVBB20 FLASH_PRIVBBR3_PRIVBB20_Msk /*!< Page 84 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR3_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR3_PRIVBB21 FLASH_PRIVBBR3_PRIVBB21_Msk /*!< Page 85 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR3_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR3_PRIVBB22 FLASH_PRIVBBR3_PRIVBB22_Msk /*!< Page 86 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR3_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR3_PRIVBB23 FLASH_PRIVBBR3_PRIVBB23_Msk /*!< Page 87 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR3_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR3_PRIVBB24 FLASH_PRIVBBR3_PRIVBB24_Msk /*!< Page 88 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR3_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR3_PRIVBB25 FLASH_PRIVBBR3_PRIVBB25_Msk /*!< Page 89 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR3_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR3_PRIVBB26 FLASH_PRIVBBR3_PRIVBB26_Msk /*!< Page 90 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR3_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR3_PRIVBB27 FLASH_PRIVBBR3_PRIVBB27_Msk /*!< Page 91 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR3_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR3_PRIVBB28 FLASH_PRIVBBR3_PRIVBB28_Msk /*!< Page 92 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR3_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR3_PRIVBB29 FLASH_PRIVBBR3_PRIVBB29_Msk /*!< Page 93 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR3_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR3_PRIVBB30 FLASH_PRIVBBR3_PRIVBB30_Msk /*!< Page 94 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR3_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR3_PRIVBB31 FLASH_PRIVBBR3_PRIVBB31_Msk /*!< Page 95 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR4 register ******************/ +#define FLASH_PRIVBBR4_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR4_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR4_PRIVBB0 FLASH_PRIVBBR4_PRIVBB0_Msk /*!< Page 96 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR4_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR4_PRIVBB1 FLASH_PRIVBBR4_PRIVBB1_Msk /*!< Page 97 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR4_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR4_PRIVBB2 FLASH_PRIVBBR4_PRIVBB2_Msk /*!< Page 98 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR4_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR4_PRIVBB3 FLASH_PRIVBBR4_PRIVBB3_Msk /*!< Page 99 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR4_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR4_PRIVBB4 FLASH_PRIVBBR4_PRIVBB4_Msk /*!< Page 100 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR4_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR4_PRIVBB5 FLASH_PRIVBBR4_PRIVBB5_Msk /*!< Page 101 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR4_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR4_PRIVBB6 FLASH_PRIVBBR4_PRIVBB6_Msk /*!< Page 102 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR4_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR4_PRIVBB7 FLASH_PRIVBBR4_PRIVBB7_Msk /*!< Page 103 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR4_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR4_PRIVBB8 FLASH_PRIVBBR4_PRIVBB8_Msk /*!< Page 104 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR4_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR4_PRIVBB9 FLASH_PRIVBBR4_PRIVBB9_Msk /*!< Page 105 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR4_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR4_PRIVBB10 FLASH_PRIVBBR4_PRIVBB10_Msk /*!< Page 106 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR4_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR4_PRIVBB11 FLASH_PRIVBBR4_PRIVBB11_Msk /*!< Page 107 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR4_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR4_PRIVBB12 FLASH_PRIVBBR4_PRIVBB12_Msk /*!< Page 108 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR4_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR4_PRIVBB13 FLASH_PRIVBBR4_PRIVBB13_Msk /*!< Page 109 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR4_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR4_PRIVBB14 FLASH_PRIVBBR4_PRIVBB14_Msk /*!< Page 110 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR4_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR4_PRIVBB15 FLASH_PRIVBBR4_PRIVBB15_Msk /*!< Page 111 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR4_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR4_PRIVBB16 FLASH_PRIVBBR4_PRIVBB16_Msk /*!< Page 112 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR4_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR4_PRIVBB17 FLASH_PRIVBBR4_PRIVBB17_Msk /*!< Page 113 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR4_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR4_PRIVBB18 FLASH_PRIVBBR4_PRIVBB18_Msk /*!< Page 114 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR4_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR4_PRIVBB19 FLASH_PRIVBBR4_PRIVBB19_Msk /*!< Page 115 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR4_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR4_PRIVBB20 FLASH_PRIVBBR4_PRIVBB20_Msk /*!< Page 116 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR4_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR4_PRIVBB21 FLASH_PRIVBBR4_PRIVBB21_Msk /*!< Page 117 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR4_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR4_PRIVBB22 FLASH_PRIVBBR4_PRIVBB22_Msk /*!< Page 118 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR4_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR4_PRIVBB23 FLASH_PRIVBBR4_PRIVBB23_Msk /*!< Page 119 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR4_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR4_PRIVBB24 FLASH_PRIVBBR4_PRIVBB24_Msk /*!< Page 120 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR4_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR4_PRIVBB25 FLASH_PRIVBBR4_PRIVBB25_Msk /*!< Page 121 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR4_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR4_PRIVBB26 FLASH_PRIVBBR4_PRIVBB26_Msk /*!< Page 122 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR4_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR4_PRIVBB27 FLASH_PRIVBBR4_PRIVBB27_Msk /*!< Page 123 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR4_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR4_PRIVBB28 FLASH_PRIVBBR4_PRIVBB28_Msk /*!< Page 124 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR4_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR4_PRIVBB29 FLASH_PRIVBBR4_PRIVBB29_Msk /*!< Page 125 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR4_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR4_PRIVBB30 FLASH_PRIVBBR4_PRIVBB30_Msk /*!< Page 126 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR4_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR4_PRIVBB31 FLASH_PRIVBBR4_PRIVBB31_Msk /*!< Page 127 in Flash only accessible by privileged access */ + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8U) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9U) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10U) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11U) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12U) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13U) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14U) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15U) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ +#define GTZC_TZSC_CR_LCK GTZC_TZSC_CR_LCK_Msk /*!< GTZC Secure and privilege configurations lock */ + +/******* Bits definition for GTZC_TZSC_SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for GTZC_TZIC_IERx/_SRx/_IFCRx registers ********/ + +/******************* Bits definition for GTZC_TZSC_SECCFGR1 register ***************/ +#define GTZC_CFGR1_TIM2_Pos GTZC_TZSC_SECCFGR1_TIM2SEC_Pos +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos GTZC_TZSC_SECCFGR1_TIM3SEC_Pos +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_WWDG_Pos GTZC_TZSC_SECCFGR1_WWDGSEC_Pos +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos GTZC_TZSC_SECCFGR1_IWDGSEC_Pos +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_USART2_Pos GTZC_TZSC_SECCFGR1_USART2SEC_Pos +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_I2C1_Pos GTZC_TZSC_SECCFGR1_I2C1SEC_Pos +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_LPTIM2_Pos GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_CFGR2_TIM1_Pos GTZC_TZSC_SECCFGR2_TIM1SEC_Pos +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_USART1_Pos GTZC_TZSC_SECCFGR2_USART1SEC_Pos +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM16_Pos GTZC_TZSC_SECCFGR2_TIM16SEC_Pos +#define GTZC_CFGR2_TIM16_Msk (0x01UL << GTZC_CFGR2_TIM16_Pos) +#define GTZC_CFGR2_TIM17_Pos GTZC_TZSC_SECCFGR2_TIM17SEC_Pos +#define GTZC_CFGR2_TIM17_Msk (0x01UL << GTZC_CFGR2_TIM17_Pos) +#define GTZC_CFGR2_SAI1_Pos GTZC_TZSC_SECCFGR2_SAI1SEC_Pos +#define GTZC_CFGR2_SAI1_Msk (0x01UL << GTZC_CFGR2_SAI1_Pos) +#define GTZC_CFGR2_SPI3_Pos GTZC_TZSC_SECCFGR2_SPI3SEC_Pos +#define GTZC_CFGR2_SPI3_Msk (0x01UL << GTZC_CFGR2_SPI3_Pos) +#define GTZC_CFGR2_LPUART1_Pos GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos GTZC_TZSC_SECCFGR2_I2C3SEC_Pos +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) +#define GTZC_CFGR2_COMP_Pos GTZC_TZSC_SECCFGR2_COMPSEC_Pos +#define GTZC_CFGR2_COMP_Msk (0x01UL << GTZC_CFGR2_COMP_Pos) +#define GTZC_CFGR2_ADC4_Pos GTZC_TZSC_SECCFGR2_ADC4SEC_Pos +#define GTZC_CFGR2_ADC4_Msk (0x01UL << GTZC_CFGR2_ADC4_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_CFGR3_CRC_Pos GTZC_TZSC_SECCFGR3_CRCSEC_Pos +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_TSC_Pos GTZC_TZSC_SECCFGR3_TSCSEC_Pos +#define GTZC_CFGR3_TSC_Msk (0x01UL << GTZC_CFGR3_TSC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_AES_Pos GTZC_TZSC_SECCFGR3_AESSEC_Pos +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos GTZC_TZSC_SECCFGR3_HASHSEC_Pos +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos GTZC_TZSC_SECCFGR3_RNGSEC_Pos +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos GTZC_TZSC_SECCFGR3_SAESSEC_Pos +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_HSEM_Pos GTZC_TZIC_IER3_HSEMIE_Pos +#define GTZC_CFGR3_HSEM_Msk (0x01UL << GTZC_CFGR3_HSEM_Pos) +#define GTZC_CFGR3_PKA_Pos GTZC_TZSC_SECCFGR3_PKASEC_Pos +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_RAMCFG_Pos GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) +#define GTZC_CFGR3_RADIO_Pos GTZC_TZSC_SECCFGR3_RADIOSEC_Pos +#define GTZC_CFGR3_RADIO_Msk (0x01UL << GTZC_CFGR3_RADIO_Pos) +#define GTZC_CFGR3_PTACONV_Pos GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos +#define GTZC_CFGR3_PTACONV_Msk (0x01UL << GTZC_CFGR3_PTACONV_Pos) + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_CFGR4_GPDMA1_Pos GTZC_TZIC_IER4_GPDMA1IE_Pos +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_FLASH_Pos GTZC_TZIC_IER4_FLASHIE_Pos +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos GTZC_TZIC_IER4_FLASH_REGIE_Pos +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) +#define GTZC_CFGR4_TZSC_Pos GTZC_TZIC_IER4_TZSCIE_Pos +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos GTZC_TZIC_IER4_TZICIE_Pos +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_SYSCFG_Pos GTZC_TZIC_IER4_SYSCFGIE_Pos +#define GTZC_CFGR4_SYSCFG_Msk (0x01UL << GTZC_CFGR4_SYSCFG_Pos) +#define GTZC_CFGR4_RTC_Pos GTZC_TZIC_IER4_RTCIE_Pos +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos GTZC_TZIC_IER4_TAMPIE_Pos +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos GTZC_TZIC_IER4_PWRIE_Pos +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos GTZC_TZIC_IER4_RCCIE_Pos +#define GTZC_CFGR4_RCC_sk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos GTZC_TZIC_IER4_EXTIIE_Pos +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_SRAM1_Pos GTZC_TZIC_IER4_SRAM1IE_Pos +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos GTZC_TZIC_IER4_MPCBB1IE_Pos +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos GTZC_TZIC_IER4_SRAM2IE_Pos +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos GTZC_TZIC_IER4_MPCBB2IE_Pos +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM6_Pos GTZC_TZIC_IER4_SRAM6IE_Pos +#define GTZC_CFGR4_SRAM6_Msk (0x01UL << GTZC_CFGR4_SRAM6_Pos) +#define GTZC_CFGR4_MPCBB6_REG_Pos GTZC_TZIC_IER4_MPCBB6IE_Pos +#define GTZC_CFGR4_MPCBB6_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB6_REG_Pos) + +/*************** Bits definition for register x=1 (GTZC_TZSC_SECCFGR1) *************/ +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Pos (0U) +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM2SEC GTZC_TZSC_SECCFGR1_TIM2SEC_Msk /*!< secure access mode for TIM2 */ +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Pos (1U) +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM3SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM3SEC GTZC_TZSC_SECCFGR1_TIM3SEC_Msk /*!< secure access mode for TIM3 */ +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Pos (6U) +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_WWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_WWDGSEC GTZC_TZSC_SECCFGR1_WWDGSEC_Msk /*!< secure access mode for WWDG */ +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Pos (7U) +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_IWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_IWDGSEC GTZC_TZSC_SECCFGR1_IWDGSEC_Msk /*!< secure access mode for IWDG */ +#define GTZC_TZSC_SECCFGR1_USART2SEC_Pos (9U) +#define GTZC_TZSC_SECCFGR1_USART2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_USART2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_USART2SEC GTZC_TZSC_SECCFGR1_USART2SEC_Msk /*!< secure access mode for USART2 */ +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Pos (13U) +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_I2C1SEC_Pos) +#define GTZC_TZSC_SECCFGR1_I2C1SEC GTZC_TZSC_SECCFGR1_I2C1SEC_Msk /*!< secure access mode for I2C1 */ +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos (17U) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk /*!< secure access mode for LPTIM2 */ + +/*************** Bits definition for register x=2 (GTZC_TZSC_SECCFGR2) *************/ +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Pos (0U) +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM1SEC GTZC_TZSC_SECCFGR2_TIM1SEC_Msk /*!< secure access mode for TIM1 */ +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Pos (1U) +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI1SEC GTZC_TZSC_SECCFGR2_SPI1SEC_Msk /*!< secure access mode for SPI1 */ +#define GTZC_TZSC_SECCFGR2_USART1SEC_Pos (3U) +#define GTZC_TZSC_SECCFGR2_USART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_USART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_USART1SEC GTZC_TZSC_SECCFGR2_USART1SEC_Msk /*!< secure access mode for USART1 */ +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Pos (5U) +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM16SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM16SEC GTZC_TZSC_SECCFGR2_TIM16SEC_Msk /*!< secure access mode for TIM16 */ +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Pos (6U) +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM17SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM17SEC GTZC_TZSC_SECCFGR2_TIM17SEC_Msk /*!< secure access mode for TIM17 */ +#define GTZC_TZSC_SECCFGR2_SAI1SEC_Pos (7U) +#define GTZC_TZSC_SECCFGR2_SAI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SAI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SAI1SEC GTZC_TZSC_SECCFGR2_SAI1SEC_Msk /*!< secure access mode for SAI1 */ +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Pos (16U) +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI3SEC GTZC_TZSC_SECCFGR2_SPI3SEC_Msk /*!< secure access mode for SPI3 */ +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos (17U) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk /*!< secure access mode for LPUART1 */ +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Pos (18U) +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_I2C3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_I2C3SEC GTZC_TZSC_SECCFGR2_I2C3SEC_Msk /*!< secure access mode for I2C3 */ +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos (19U) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk /*!< secure access mode for LPTIM1 */ +#define GTZC_TZSC_SECCFGR2_COMPSEC_Pos (23U) +#define GTZC_TZSC_SECCFGR2_COMPSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_COMPSEC_Pos) +#define GTZC_TZSC_SECCFGR2_COMPSEC GTZC_TZSC_SECCFGR2_COMPSEC_Msk /*!< secure access mode for COMP */ +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Pos (24U) +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_ADC4SEC_Pos) +#define GTZC_TZSC_SECCFGR2_ADC4SEC GTZC_TZSC_SECCFGR2_ADC4SEC_Msk /*!< secure access mode for ADC4 */ + +/*************** Bits definition for register x=3 (GTZC_TZSC_SECCFGR3) *************/ +#define GTZC_TZSC_SECCFGR3_CRCSEC_Pos (3U) +#define GTZC_TZSC_SECCFGR3_CRCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_CRCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_CRCSEC GTZC_TZSC_SECCFGR3_CRCSEC_Msk /*!< secure access mode for CRC */ +#define GTZC_TZSC_SECCFGR3_TSCSEC_Pos (4U) +#define GTZC_TZSC_SECCFGR3_TSCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_TSCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_TSCSEC GTZC_TZSC_SECCFGR3_TSCSEC_Msk /*!< secure access mode for TSC */ +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos (6U) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk /*!< secure access mode for ICACHE_REG */ +#define GTZC_TZSC_SECCFGR3_AESSEC_Pos (11U) +#define GTZC_TZSC_SECCFGR3_AESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_AESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_AESSEC GTZC_TZSC_SECCFGR3_AESSEC_Msk /*!< secure access mode for AES */ +#define GTZC_TZSC_SECCFGR3_HASHSEC_Pos (12U) +#define GTZC_TZSC_SECCFGR3_HASHSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_HASHSEC_Pos) +#define GTZC_TZSC_SECCFGR3_HASHSEC GTZC_TZSC_SECCFGR3_HASHSEC_Msk /*!< secure access mode for HASH */ +#define GTZC_TZSC_SECCFGR3_RNGSEC_Pos (13U) +#define GTZC_TZSC_SECCFGR3_RNGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RNGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RNGSEC GTZC_TZSC_SECCFGR3_RNGSEC_Msk /*!< secure access mode for RNG */ +#define GTZC_TZSC_SECCFGR3_SAESSEC_Pos (14U) +#define GTZC_TZSC_SECCFGR3_SAESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_SAESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_SAESSEC GTZC_TZSC_SECCFGR3_SAESSEC_Msk /*!< secure access mode for SAES */ +#define GTZC_TZSC_SECCFGR3_PKASEC_Pos (16U) +#define GTZC_TZSC_SECCFGR3_PKASEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PKASEC_Pos) +#define GTZC_TZSC_SECCFGR3_PKASEC GTZC_TZSC_SECCFGR3_PKASEC_Msk /*!< secure access mode for PKA */ +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos (22U) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk /*!< secure access mode for RAMCFG */ +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Pos (23U) +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RADIOSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RADIOSEC GTZC_TZSC_SECCFGR3_RADIOSEC_Msk /*!< secure access mode for 2.4 GHz RADIO */ +#define GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos (24U) +#define GTZC_TZSC_SECCFGR3_PTACONVSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos) +#define GTZC_TZSC_SECCFGR3_PTACONVSEC GTZC_TZSC_SECCFGR3_PTACONVSEC_Msk /*!< secure access mode for PTACONV */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos (0U) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk /*!< privileged access mode for TIM2 */ +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos (1U) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk /*!< privileged access mode for TIM3 */ +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk /*!< privileged access mode for WWDG */ +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos (7U) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk /*!< privileged access mode for IWDG */ +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos (9U) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk /*!< privileged access mode for USART2 */ +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos (13U) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk /*!< privileged access mode for I2C1 */ +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos (17U) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk /*!< privileged access mode for LPTIM2 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos (0U) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk /*!< privileged access mode for TIM1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos (1U) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk /*!< privileged access mode for SPI1 */ +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos (3U) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk /*!< privileged access mode for USART1 */ +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos (5U) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk /*!< privileged access mode for TIM16 */ +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk /*!< privileged access mode for TIM17 */ +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos (7U) +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk /*!< privileged access mode for SAI1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos (16U) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk /*!< privileged access mode for SPI3 */ +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos (17U) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk /*!< privileged access mode for LPUART1 */ +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos (18U) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk /*!< privileged access mode for I2C3 */ +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos (19U) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk /*!< privileged access mode for LPTIM1 */ +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV_Pos (23U) +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_COMPPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV GTZC_TZSC_PRIVCFGR2_COMPPRIV_Msk /*!< privileged access mode for COMP */ +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos (24U) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk /*!< privileged access mode for ADC4 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos (3U) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk /*!< privileged access mode for CRC */ +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos (4U) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk /*!< privileged access mode for TSC */ +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk /*!< privileged access mode for ICACHE_REG */ +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos (11U) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk /*!< privileged access mode for AES */ +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos (12U) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk /*!< privileged access mode for HASH */ +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos (13U) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk /*!< privileged access mode for RNG */ +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos (14U) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk /*!< privileged access mode for SAES */ +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos (16U) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk /*!< privileged access mode for PKA */ +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos (22U) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk /*!< privileged access mode for RAMCFG */ +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos (23U) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk /*!< privileged access mode for 2.4 GHz RADIO */ +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Pos (24U) +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Msk /*!< privileged access mode for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC_IER1_TIM2IE_Pos (0U) +#define GTZC_TZIC_IER1_TIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM2IE_Pos) +#define GTZC_TZIC_IER1_TIM2IE GTZC_TZIC_IER1_TIM2IE_Msk /*!< illegal access interrupt enable for TIM2 */ +#define GTZC_TZIC_IER1_TIM3IE_Pos (1U) +#define GTZC_TZIC_IER1_TIM3IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM3IE_Pos) +#define GTZC_TZIC_IER1_TIM3IE GTZC_TZIC_IER1_TIM3IE_Msk /*!< illegal access interrupt enable for TIM3 */ +#define GTZC_TZIC_IER1_WWDGIE_Pos (6U) +#define GTZC_TZIC_IER1_WWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_WWDGIE_Pos) +#define GTZC_TZIC_IER1_WWDGIE GTZC_TZIC_IER1_WWDGIE_Msk /*!< illegal access interrupt enable for WWDG */ +#define GTZC_TZIC_IER1_IWDGIE_Pos (7U) +#define GTZC_TZIC_IER1_IWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_IWDGIE_Pos) +#define GTZC_TZIC_IER1_IWDGIE GTZC_TZIC_IER1_IWDGIE_Msk /*!< illegal access interrupt enable for IWDG */ +#define GTZC_TZIC_IER1_USART2IE_Pos (9U) +#define GTZC_TZIC_IER1_USART2IE_Msk (0x01UL << GTZC_TZIC_IER1_USART2IE_Pos) +#define GTZC_TZIC_IER1_USART2IE GTZC_TZIC_IER1_USART2IE_Msk /*!< illegal access interrupt enable for USART2 */ +#define GTZC_TZIC_IER1_I2C1IE_Pos (13U) +#define GTZC_TZIC_IER1_I2C1IE_Msk (0x01UL << GTZC_TZIC_IER1_I2C1IE_Pos) +#define GTZC_TZIC_IER1_I2C1IE GTZC_TZIC_IER1_I2C1IE_Msk /*!< illegal access interrupt enable for I2C1 */ +#define GTZC_TZIC_IER1_LPTIM2IE_Pos (17U) +#define GTZC_TZIC_IER1_LPTIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_LPTIM2IE_Pos) +#define GTZC_TZIC_IER1_LPTIM2IE GTZC_TZIC_IER1_LPTIM2IE_Msk /*!< illegal access interrupt enable for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC_IER2_TIM1IE_Pos (0U) +#define GTZC_TZIC_IER2_TIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM1IE_Pos) +#define GTZC_TZIC_IER2_TIM1IE GTZC_TZIC_IER2_TIM1IE_Msk /*!< illegal access interrupt enable for TIM1 */ +#define GTZC_TZIC_IER2_SPI1IE_Pos (1U) +#define GTZC_TZIC_IER2_SPI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI1IE_Pos) +#define GTZC_TZIC_IER2_SPI1IE GTZC_TZIC_IER2_SPI1IE_Msk /*!< illegal access interrupt enable for SPI1 */ +#define GTZC_TZIC_IER2_USART1IE_Pos (3U) +#define GTZC_TZIC_IER2_USART1IE_Msk (0x01UL << GTZC_TZIC_IER2_USART1IE_Pos) +#define GTZC_TZIC_IER2_USART1IE GTZC_TZIC_IER2_USART1IE_Msk /*!< illegal access interrupt enable for USART1 */ +#define GTZC_TZIC_IER2_TIM16IE_Pos (5U) +#define GTZC_TZIC_IER2_TIM16IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM16IE_Pos) +#define GTZC_TZIC_IER2_TIM16IE GTZC_TZIC_IER2_TIM16IE_Msk /*!< illegal access interrupt enable for TIM16 */ +#define GTZC_TZIC_IER2_TIM17IE_Pos (6U) +#define GTZC_TZIC_IER2_TIM17IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM17IE_Pos) +#define GTZC_TZIC_IER2_TIM17IE GTZC_TZIC_IER2_TIM17IE_Msk /*!< illegal access interrupt enable for TIM17 */ +#define GTZC_TZIC_IER2_SAI1IE_Pos (7U) +#define GTZC_TZIC_IER2_SAI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SAI1IE_Pos) +#define GTZC_TZIC_IER2_SAI1IE GTZC_TZIC_IER2_SAI1IE_Msk /*!< illegal access interrupt enable for SAI1 */ +#define GTZC_TZIC_IER2_SPI3IE_Pos (16U) +#define GTZC_TZIC_IER2_SPI3IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI3IE_Pos) +#define GTZC_TZIC_IER2_SPI3IE GTZC_TZIC_IER2_SPI3IE_Msk /*!< illegal access interrupt enable for SPI3 */ +#define GTZC_TZIC_IER2_LPUART1IE_Pos (17U) +#define GTZC_TZIC_IER2_LPUART1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPUART1IE_Pos) +#define GTZC_TZIC_IER2_LPUART1IE GTZC_TZIC_IER2_LPUART1IE_Msk /*!< illegal access interrupt enable for LPUART1 */ +#define GTZC_TZIC_IER2_I2C3IE_Pos (18U) +#define GTZC_TZIC_IER2_I2C3IE_Msk (0x01UL << GTZC_TZIC_IER2_I2C3IE_Pos) +#define GTZC_TZIC_IER2_I2C3IE GTZC_TZIC_IER2_I2C3IE_Msk /*!< illegal access interrupt enable for I2C3 */ +#define GTZC_TZIC_IER2_LPTIM1IE_Pos (19U) +#define GTZC_TZIC_IER2_LPTIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPTIM1IE_Pos) +#define GTZC_TZIC_IER2_LPTIM1IE GTZC_TZIC_IER2_LPTIM1IE_Msk /*!< illegal access interrupt enable for LPTIM1 */ +#define GTZC_TZIC_IER2_COMPIE_Pos (23U) +#define GTZC_TZIC_IER2_COMPIE_Msk (0x01UL << GTZC_TZIC_IER2_COMPIE_Pos) +#define GTZC_TZIC_IER2_COMPIE GTZC_TZIC_IER2_COMPIE_Msk /*!< illegal access interrupt enable for COMP */ +#define GTZC_TZIC_IER2_ADC4IE_Pos (24U) +#define GTZC_TZIC_IER2_ADC4IE_Msk (0x01UL << GTZC_TZIC_IER2_ADC4IE_Pos) +#define GTZC_TZIC_IER2_ADC4IE GTZC_TZIC_IER2_ADC4IE_Msk /*!< illegal access interrupt enable for ADC4 */ + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC_IER3_CRCIE_Pos (3U) +#define GTZC_TZIC_IER3_CRCIE_Msk (0x01UL << GTZC_TZIC_IER3_CRCIE_Pos) +#define GTZC_TZIC_IER3_CRCIE GTZC_TZIC_IER3_CRCIE_Msk /*!< illegal access interrupt enable for CRC */ +#define GTZC_TZIC_IER3_TSCIE_Pos (4U) +#define GTZC_TZIC_IER3_TSCIE_Msk (0x01UL << GTZC_TZIC_IER3_TSCIE_Pos) +#define GTZC_TZIC_IER3_TSCIE GTZC_TZIC_IER3_TSCIE_Msk /*!< illegal access interrupt enable for TSC */ +#define GTZC_TZIC_IER3_ICACHE_REGIE_Pos (6U) +#define GTZC_TZIC_IER3_ICACHE_REGIE_Msk (0x01UL << GTZC_TZIC_IER3_ICACHE_REGIE_Pos) +#define GTZC_TZIC_IER3_ICACHE_REGIE GTZC_TZIC_IER3_ICACHE_REGIE_Msk /*!< illegal access interrupt enable for ICACHE_REG */ +#define GTZC_TZIC_IER3_AESIE_Pos (11U) +#define GTZC_TZIC_IER3_AESIE_Msk (0x01UL << GTZC_TZIC_IER3_AESIE_Pos) +#define GTZC_TZIC_IER3_AESIE GTZC_TZIC_IER3_AESIE_Msk /*!< illegal access interrupt enable for AES */ +#define GTZC_TZIC_IER3_HASHIE_Pos (12U) +#define GTZC_TZIC_IER3_HASHIE_Msk (0x01UL << GTZC_TZIC_IER3_HASHIE_Pos) +#define GTZC_TZIC_IER3_HASHIE GTZC_TZIC_IER3_HASHIE_Msk /*!< illegal access interrupt enable for HASH */ +#define GTZC_TZIC_IER3_RNGIE_Pos (13U) +#define GTZC_TZIC_IER3_RNGIE_Msk (0x01UL << GTZC_TZIC_IER3_RNGIE_Pos) +#define GTZC_TZIC_IER3_RNGIE GTZC_TZIC_IER3_RNGIE_Msk /*!< illegal access interrupt enable for RNG */ +#define GTZC_TZIC_IER3_SAESIE_Pos (14U) +#define GTZC_TZIC_IER3_SAESIE_Msk (0x01UL << GTZC_TZIC_IER3_SAESIE_Pos) +#define GTZC_TZIC_IER3_SAESIE GTZC_TZIC_IER3_SAESIE_Msk /*!< illegal access interrupt enable for SAES */ +#define GTZC_TZIC_IER3_HSEMIE_Pos (15U) +#define GTZC_TZIC_IER3_HSEMIE_Msk (0x01UL << GTZC_TZIC_IER3_HSEMIE_Pos) +#define GTZC_TZIC_IER3_HSEMIE GTZC_TZIC_IER3_HSEMIE_Msk /*!< illegal access interrupt enable for HSEM */ +#define GTZC_TZIC_IER3_PKAIE_Pos (16U) +#define GTZC_TZIC_IER3_PKAIE_Msk (0x01UL << GTZC_TZIC_IER3_PKAIE_Pos) +#define GTZC_TZIC_IER3_PKAIE GTZC_TZIC_IER3_PKAIE_Msk /*!< illegal access interrupt enable for PKA */ +#define GTZC_TZIC_IER3_RAMCFGIE_Pos (22U) +#define GTZC_TZIC_IER3_RAMCFGIE_Msk (0x01UL << GTZC_TZIC_IER3_RAMCFGIE_Pos) +#define GTZC_TZIC_IER3_RAMCFGIE GTZC_TZIC_IER3_RAMCFGIE_Msk /*!< illegal access interrupt enable for RAMCFG */ +#define GTZC_TZIC_IER3_RADIOIE_Pos (23U) +#define GTZC_TZIC_IER3_RADIOIE_Msk (0x01UL << GTZC_TZIC_IER3_RADIOIE_Pos) +#define GTZC_TZIC_IER3_RADIOIE GTZC_TZIC_IER3_RADIOIE_Msk /*!< illegal access interrupt enable for 2.4 GHz RADIO */ +#define GTZC_TZIC_IER3_PTACONVIE_Pos (24U) +#define GTZC_TZIC_IER3_PTACONVIE_Msk (0x01UL << GTZC_TZIC_IER3_PTACONVIE_Pos) +#define GTZC_TZIC_IER3_PTACONVIE GTZC_TZIC_IER3_PTACONVIE_Msk /*!< illegal access interrupt enable for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC_IER4_GPDMA1IE_Pos (0U) +#define GTZC_TZIC_IER4_GPDMA1IE_Msk (0x01UL << GTZC_TZIC_IER4_GPDMA1IE_Pos) +#define GTZC_TZIC_IER4_GPDMA1IE GTZC_TZIC_IER4_GPDMA1IE_Msk /*!< illegal access interrupt enable for GPDMA1 */ +#define GTZC_TZIC_IER4_FLASHIE_Pos (1U) +#define GTZC_TZIC_IER4_FLASHIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASHIE_Pos) +#define GTZC_TZIC_IER4_FLASHIE GTZC_TZIC_IER4_FLASHIE_Msk /*!< illegal access interrupt enable for FLASH memory */ +#define GTZC_TZIC_IER4_FLASH_REGIE_Pos (2U) +#define GTZC_TZIC_IER4_FLASH_REGIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASH_REGIE_Pos) +#define GTZC_TZIC_IER4_FLASH_REGIE GTZC_TZIC_IER4_FLASH_REGIE_Msk /*!< illegal access interrupt enable for FLASH interface */ +#define GTZC_TZIC_IER4_SYSCFGIE_Pos (7U) +#define GTZC_TZIC_IER4_SYSCFGIE_Msk (0x01UL << GTZC_TZIC_IER4_SYSCFGIE_Pos) +#define GTZC_TZIC_IER4_SYSCFGIE GTZC_TZIC_IER4_SYSCFGIE_Msk /*!< illegal access interrupt enable for SYSCFG interface */ +#define GTZC_TZIC_IER4_RTCIE_Pos (8U) +#define GTZC_TZIC_IER4_RTCIE_Msk (0x01UL << GTZC_TZIC_IER4_RTCIE_Pos) +#define GTZC_TZIC_IER4_RTCIE GTZC_TZIC_IER4_RTCIE_Msk /*!< illegal access interrupt enable for RTC interface */ +#define GTZC_TZIC_IER4_TAMPIE_Pos (9U) +#define GTZC_TZIC_IER4_TAMPIE_Msk (0x01UL << GTZC_TZIC_IER4_TAMPIE_Pos) +#define GTZC_TZIC_IER4_TAMPIE GTZC_TZIC_IER4_TAMPIE_Msk /*!< illegal access interrupt enable for TAMP interface */ +#define GTZC_TZIC_IER4_PWRIE_Pos (10U) +#define GTZC_TZIC_IER4_PWRIE_Msk (0x01UL << GTZC_TZIC_IER4_PWRIE_Pos) +#define GTZC_TZIC_IER4_PWRIE GTZC_TZIC_IER4_PWRIE_Msk /*!< illegal access interrupt enable for PWR interface */ +#define GTZC_TZIC_IER4_RCCIE_Pos (11U) +#define GTZC_TZIC_IER4_RCCIE_Msk (0x01UL << GTZC_TZIC_IER4_RCCIE_Pos) +#define GTZC_TZIC_IER4_RCCIE GTZC_TZIC_IER4_RCCIE_Msk /*!< illegal access interrupt enable for RCC interface */ +#define GTZC_TZIC_IER4_EXTIIE_Pos (13U) +#define GTZC_TZIC_IER4_EXTIIE_Msk (0x01UL << GTZC_TZIC_IER4_EXTIIE_Pos) +#define GTZC_TZIC_IER4_EXTIIE GTZC_TZIC_IER4_EXTIIE_Msk /*!< illegal access interrupt enable for EXTI interface */ +#define GTZC_TZIC_IER4_TZSCIE_Pos (14U) +#define GTZC_TZIC_IER4_TZSCIE_Msk (0x01UL << GTZC_TZIC_IER4_TZSCIE_Pos) +#define GTZC_TZIC_IER4_TZSCIE GTZC_TZIC_IER4_TZSCIE_Msk /*!< illegal access interrupt enable for GTZC TZSC */ +#define GTZC_TZIC_IER4_TZICIE_Pos (15U) +#define GTZC_TZIC_IER4_TZICIE_Msk (0x01UL << GTZC_TZIC_IER4_TZICIE_Pos) +#define GTZC_TZIC_IER4_TZICIE GTZC_TZIC_IER4_TZICIE_Msk /*!< illegal access interrupt enable for GTZC TZIC */ +#define GTZC_TZIC_IER4_SRAM1IE_Pos (22U) +#define GTZC_TZIC_IER4_SRAM1IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM1IE_Pos) +#define GTZC_TZIC_IER4_SRAM1IE GTZC_TZIC_IER4_SRAM1IE_Msk /*!< illegal access interrupt enable for SRAM1 memory */ +#define GTZC_TZIC_IER4_MPCBB1IE_Pos (23U) +#define GTZC_TZIC_IER4_MPCBB1IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB1IE_Pos) +#define GTZC_TZIC_IER4_MPCBB1IE GTZC_TZIC_IER4_MPCBB1IE_Msk /*!< illegal access interrupt enable for MPCBB1 */ +#define GTZC_TZIC_IER4_SRAM2IE_Pos (24U) +#define GTZC_TZIC_IER4_SRAM2IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM2IE_Pos) +#define GTZC_TZIC_IER4_SRAM2IE GTZC_TZIC_IER4_SRAM2IE_Msk /*!< illegal access interrupt enable for SRAM2 memory */ +#define GTZC_TZIC_IER4_MPCBB2IE_Pos (25U) +#define GTZC_TZIC_IER4_MPCBB2IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB2IE_Pos) +#define GTZC_TZIC_IER4_MPCBB2IE GTZC_TZIC_IER4_MPCBB2IE_Msk /*!< illegal access interrupt enable for MPCBB2 */ +#define GTZC_TZIC_IER4_SRAM6IE_Pos (30U) +#define GTZC_TZIC_IER4_SRAM6IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM6IE_Pos) +#define GTZC_TZIC_IER4_SRAM6IE GTZC_TZIC_IER4_SRAM6IE_Msk /*!< illegal access interrupt enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_IER4_MPCBB6IE_Pos (31U) +#define GTZC_TZIC_IER4_MPCBB6IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB6IE_Pos) +#define GTZC_TZIC_IER4_MPCBB6IE GTZC_TZIC_IER4_MPCBB6IE_Msk /*!< illegal access interrupt enable for MPCBB6 */ + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC_SR1_TIM2F_Pos (0U) +#define GTZC_TZIC_SR1_TIM2F_Msk (0x01UL << GTZC_TZIC_SR1_TIM2F_Pos) +#define GTZC_TZIC_SR1_TIM2F GTZC_TZIC_SR1_TIM2F_Msk /*!< illegal access flag for TIM2 */ +#define GTZC_TZIC_SR1_TIM3F_Pos (1U) +#define GTZC_TZIC_SR1_TIM3F_Msk (0x01UL << GTZC_TZIC_SR1_TIM3F_Pos) +#define GTZC_TZIC_SR1_TIM3F GTZC_TZIC_SR1_TIM3F_Msk /*!< illegal access flag for TIM3 */ +#define GTZC_TZIC_SR1_WWDGF_Pos (6U) +#define GTZC_TZIC_SR1_WWDGF_Msk (0x01UL << GTZC_TZIC_SR1_WWDGF_Pos) +#define GTZC_TZIC_SR1_WWDGF GTZC_TZIC_SR1_WWDGF_Msk /*!< illegal access flag for WWDG */ +#define GTZC_TZIC_SR1_IWDGF_Pos (7U) +#define GTZC_TZIC_SR1_IWDGF_Msk (0x01UL << GTZC_TZIC_SR1_IWDGF_Pos) +#define GTZC_TZIC_SR1_IWDGF GTZC_TZIC_SR1_IWDGF_Msk /*!< illegal access flag for IWDG */ +#define GTZC_TZIC_SR1_USART2F_Pos (9U) +#define GTZC_TZIC_SR1_USART2F_Msk (0x01UL << GTZC_TZIC_SR1_USART2F_Pos) +#define GTZC_TZIC_SR1_USART2F GTZC_TZIC_SR1_USART2F_Msk /*!< illegal access flag for USART2 */ +#define GTZC_TZIC_SR1_I2C1F_Pos (13U) +#define GTZC_TZIC_SR1_I2C1F_Msk (0x01UL << GTZC_TZIC_SR1_I2C1F_Pos) +#define GTZC_TZIC_SR1_I2C1F GTZC_TZIC_SR1_I2C1F_Msk /*!< illegal access flag for I2C1 */ +#define GTZC_TZIC_SR1_LPTIM2F_Pos (17U) +#define GTZC_TZIC_SR1_LPTIM2F_Msk (0x01UL << GTZC_TZIC_SR1_LPTIM2F_Pos) +#define GTZC_TZIC_SR1_LPTIM2F GTZC_TZIC_SR1_LPTIM2F_Msk /*!< illegal access flag for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC_SR2_TIM1F_Pos (0U) +#define GTZC_TZIC_SR2_TIM1F_Msk (0x01UL << GTZC_TZIC_SR2_TIM1F_Pos) +#define GTZC_TZIC_SR2_TIM1F GTZC_TZIC_SR2_TIM1F_Msk /*!< illegal access flag for TIM1 */ +#define GTZC_TZIC_SR2_SPI1F_Pos (1U) +#define GTZC_TZIC_SR2_SPI1F_Msk (0x01UL << GTZC_TZIC_SR2_SPI1F_Pos) +#define GTZC_TZIC_SR2_SPI1F GTZC_TZIC_SR2_SPI1F_Msk /*!< illegal access flag for SPI1 */ +#define GTZC_TZIC_SR2_USART1F_Pos (3U) +#define GTZC_TZIC_SR2_USART1F_Msk (0x01UL << GTZC_TZIC_SR2_USART1F_Pos) +#define GTZC_TZIC_SR2_USART1F GTZC_TZIC_SR2_USART1F_Msk /*!< illegal access flag for USART1 */ +#define GTZC_TZIC_SR2_TIM16F_Pos (5U) +#define GTZC_TZIC_SR2_TIM16F_Msk (0x01UL << GTZC_TZIC_SR2_TIM16F_Pos) +#define GTZC_TZIC_SR2_TIM16F GTZC_TZIC_SR2_TIM16F_Msk /*!< illegal access flag for TIM16 */ +#define GTZC_TZIC_SR2_TIM17F_Pos (6U) +#define GTZC_TZIC_SR2_TIM17F_Msk (0x01UL << GTZC_TZIC_SR2_TIM17F_Pos) +#define GTZC_TZIC_SR2_TIM17F GTZC_TZIC_SR2_TIM17F_Msk /*!< illegal access flag for TIM17 */ +#define GTZC_TZIC_SR2_SAI1F_Pos (7U) +#define GTZC_TZIC_SR2_SAI1F_Msk (0x01UL << GTZC_TZIC_SR2_SAI1F_Pos) +#define GTZC_TZIC_SR2_SAI1F GTZC_TZIC_SR2_SAI1F_Msk /*!< illegal access flag for SAI1 */ +#define GTZC_TZIC_SR2_SPI3F_Pos (16U) +#define GTZC_TZIC_SR2_SPI3F_Msk (0x01UL << GTZC_TZIC_SR2_SPI3F_Pos) +#define GTZC_TZIC_SR2_SPI3F GTZC_TZIC_SR2_SPI3F_Msk /*!< illegal access flag for SPI3 */ +#define GTZC_TZIC_SR2_LPUART1F_Pos (17U) +#define GTZC_TZIC_SR2_LPUART1F_Msk (0x01UL << GTZC_TZIC_SR2_LPUART1F_Pos) +#define GTZC_TZIC_SR2_LPUART1F GTZC_TZIC_SR2_LPUART1F_Msk /*!< illegal access flag for LPUART1 */ +#define GTZC_TZIC_SR2_I2C3F_Pos (18U) +#define GTZC_TZIC_SR2_I2C3F_Msk (0x01UL << GTZC_TZIC_SR2_I2C3F_Pos) +#define GTZC_TZIC_SR2_I2C3F GTZC_TZIC_SR2_I2C3F_Msk /*!< illegal access flag for I2C3 */ +#define GTZC_TZIC_SR2_LPTIM1F_Pos (19U) +#define GTZC_TZIC_SR2_LPTIM1F_Msk (0x01UL << GTZC_TZIC_SR2_LPTIM1F_Pos) +#define GTZC_TZIC_SR2_LPTIM1F GTZC_TZIC_SR2_LPTIM1F_Msk /*!< illegal access flag for LPTIM1 */ +#define GTZC_TZIC_SR2_COMPF_Pos (23U) +#define GTZC_TZIC_SR2_COMPF_Msk (0x01UL << GTZC_TZIC_SR2_COMPF_Pos) +#define GTZC_TZIC_SR2_COMPF GTZC_TZIC_SR2_COMPF_Msk /*!< illegal access flag for COMP */ +#define GTZC_TZIC_SR2_ADC4F_Pos (24U) +#define GTZC_TZIC_SR2_ADC4F_Msk (0x01UL << GTZC_TZIC_SR2_ADC4F_Pos) +#define GTZC_TZIC_SR2_ADC4F GTZC_TZIC_SR2_ADC4F_Msk /*!< illegal access flag for ADC4 */ + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC_SR3_CRCF_Pos (3U) +#define GTZC_TZIC_SR3_CRCF_Msk (0x01UL << GTZC_TZIC_SR3_CRCF_Pos) +#define GTZC_TZIC_SR3_CRCF GTZC_TZIC_SR3_CRCF_Msk /*!< illegal access flag for CRC */ +#define GTZC_TZIC_SR3_TSCF_Pos (4U) +#define GTZC_TZIC_SR3_TSCF_Msk (0x01UL << GTZC_TZIC_SR3_TSCF_Pos) +#define GTZC_TZIC_SR3_TSCF GTZC_TZIC_SR3_TSCF_Msk /*!< illegal access flag for TSC */ +#define GTZC_TZIC_SR3_ICACHE_REGF_Pos (6U) +#define GTZC_TZIC_SR3_ICACHE_REGF_Msk (0x01UL << GTZC_TZIC_SR3_ICACHE_REGF_Pos) +#define GTZC_TZIC_SR3_ICACHE_REGF GTZC_TZIC_SR3_ICACHE_REGF_Msk /*!< illegal access flag for ICACHE_REG */ +#define GTZC_TZIC_SR3_AESF_Pos (11U) +#define GTZC_TZIC_SR3_AESF_Msk (0x01UL << GTZC_TZIC_SR3_AESF_Pos) +#define GTZC_TZIC_SR3_AESF GTZC_TZIC_SR3_AESF_Msk /*!< illegal access flag for AES */ +#define GTZC_TZIC_SR3_HASHF_Pos (12U) +#define GTZC_TZIC_SR3_HASHF_Msk (0x01UL << GTZC_TZIC_SR3_HASHF_Pos) +#define GTZC_TZIC_SR3_HASHF GTZC_TZIC_SR3_HASHF_Msk /*!< illegal access flag for HASH */ +#define GTZC_TZIC_SR3_RNGF_Pos (13U) +#define GTZC_TZIC_SR3_RNGF_Msk (0x01UL << GTZC_TZIC_SR3_RNGF_Pos) +#define GTZC_TZIC_SR3_RNGF GTZC_TZIC_SR3_RNGF_Msk /*!< illegal access flag for RNG */ +#define GTZC_TZIC_SR3_SAESF_Pos (14U) +#define GTZC_TZIC_SR3_SAESF_Msk (0x01UL << GTZC_TZIC_SR3_SAESF_Pos) +#define GTZC_TZIC_SR3_SAESF GTZC_TZIC_SR3_SAESF_Msk /*!< illegal access flag for SAES */ +#define GTZC_TZIC_SR3_HSEMF_Pos (15U) +#define GTZC_TZIC_SR3_HSEMF_Msk (0x01UL << GTZC_TZIC_SR3_HSEMF_Pos) +#define GTZC_TZIC_SR3_HSEMF GTZC_TZIC_SR3_HSEMF_Msk /*!< illegal access flag for HSEM */ +#define GTZC_TZIC_SR3_PKAF_Pos (16U) +#define GTZC_TZIC_SR3_PKAF_Msk (0x01UL << GTZC_TZIC_SR3_PKAF_Pos) +#define GTZC_TZIC_SR3_PKAF GTZC_TZIC_SR3_PKAF_Msk /*!< illegal access flag for PKA */ +#define GTZC_TZIC_SR3_RAMCFGF_Pos (22U) +#define GTZC_TZIC_SR3_RAMCFGF_Msk (0x01UL << GTZC_TZIC_SR3_RAMCFGF_Pos) +#define GTZC_TZIC_SR3_RAMCFGF GTZC_TZIC_SR3_RAMCFGF_Msk /*!< illegal access flag for RAMCFG */ +#define GTZC_TZIC_SR3_RADIOF_Pos (23U) +#define GTZC_TZIC_SR3_RADIOF_Msk (0x01UL << GTZC_TZIC_SR3_RADIOF_Pos) +#define GTZC_TZIC_SR3_RADIOF GTZC_TZIC_SR3_RADIOF_Msk /*!< illegal access flag for 2.4 GHz RADIO */ +#define GTZC_TZIC_SR3_PTACONVF_Pos (24U) +#define GTZC_TZIC_SR3_PTACONVF_Msk (0x01UL << GTZC_TZIC_SR3_PTACONVF_Pos) +#define GTZC_TZIC_SR3_PTACONVF GTZC_TZIC_SR3_PTACONVF_Msk /*!< illegal access flag for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC_SR4_GPDMA1F_Pos (0U) +#define GTZC_TZIC_SR4_GPDMA1F_Msk (0x01UL << GTZC_TZIC_SR4_GPDMA1F_Pos) +#define GTZC_TZIC_SR4_GPDMA1F GTZC_TZIC_SR4_GPDMA1F_Msk /*!< illegal access flag for GPDMA1 */ +#define GTZC_TZIC_SR4_FLASHF_Pos (1U) +#define GTZC_TZIC_SR4_FLASHF_Msk (0x01UL << GTZC_TZIC_SR4_FLASHF_Pos) +#define GTZC_TZIC_SR4_FLASHF GTZC_TZIC_SR4_FLASHF_Msk /*!< illegal access flag for FLASH memory */ +#define GTZC_TZIC_SR4_FLASH_REGF_Pos (2U) +#define GTZC_TZIC_SR4_FLASH_REGF_Msk (0x01UL << GTZC_TZIC_SR4_FLASH_REGF_Pos) +#define GTZC_TZIC_SR4_FLASH_REGF GTZC_TZIC_SR4_FLASH_REGF_Msk /*!< illegal access flag for FLASH interface */ +#define GTZC_TZIC_SR4_SYSCFGF_Pos (7U) +#define GTZC_TZIC_SR4_SYSCFGF_Msk (0x01UL << GTZC_TZIC_SR4_SYSCFGF_Pos) +#define GTZC_TZIC_SR4_SYSCFGF GTZC_TZIC_SR4_SYSCFGF_Msk /*!< illegal access flag for SYSCFG interface */ +#define GTZC_TZIC_SR4_RTCF_Pos (8U) +#define GTZC_TZIC_SR4_RTCF_Msk (0x01UL << GTZC_TZIC_SR4_RTCF_Pos) +#define GTZC_TZIC_SR4_RTCF GTZC_TZIC_SR4_RTCF_Msk /*!< illegal access flag for RTC interface */ +#define GTZC_TZIC_SR4_TAMPF_Pos (9U) +#define GTZC_TZIC_SR4_TAMPF_Msk (0x01UL << GTZC_TZIC_SR4_TAMPF_Pos) +#define GTZC_TZIC_SR4_TAMPF GTZC_TZIC_SR4_TAMPF_Msk /*!< illegal access flag for TAMP interface */ +#define GTZC_TZIC_SR4_PWRF_Pos (10U) +#define GTZC_TZIC_SR4_PWRF_Msk (0x01UL << GTZC_TZIC_SR4_PWRF_Pos) +#define GTZC_TZIC_SR4_PWRF GTZC_TZIC_SR4_PWRF_Msk /*!< illegal access flag for PWR interface */ +#define GTZC_TZIC_SR4_RCCF_Pos (11U) +#define GTZC_TZIC_SR4_RCCF_Msk (0x01UL << GTZC_TZIC_SR4_RCCF_Pos) +#define GTZC_TZIC_SR4_RCCF GTZC_TZIC_SR4_RCCF_Msk /*!< illegal access flag for RCC interface */ +#define GTZC_TZIC_SR4_EXTIF_Pos (13U) +#define GTZC_TZIC_SR4_EXTIF_Msk (0x01UL << GTZC_TZIC_SR4_EXTIF_Pos) +#define GTZC_TZIC_SR4_EXTIF GTZC_TZIC_SR4_EXTIF_Msk /*!< illegal access flag for EXTI interface */ +#define GTZC_TZIC_SR4_TZSCF_Pos (14U) +#define GTZC_TZIC_SR4_TZSCF_Msk (0x01UL << GTZC_TZIC_SR4_TZSCF_Pos) +#define GTZC_TZIC_SR4_TZSCF GTZC_TZIC_SR4_TZSCF_Msk /*!< illegal access flag for GTZC TZSC */ +#define GTZC_TZIC_SR4_TZICF_Pos (15U) +#define GTZC_TZIC_SR4_TZICF_Msk (0x01UL << GTZC_TZIC_SR4_TZICF_Pos) +#define GTZC_TZIC_SR4_TZICF GTZC_TZIC_SR4_TZICF_Msk /*!< illegal access flag for GTZC TZIC */ +#define GTZC_TZIC_SR4_SRAM1F_Pos (22U) +#define GTZC_TZIC_SR4_SRAM1F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM1F_Pos) +#define GTZC_TZIC_SR4_SRAM1F GTZC_TZIC_SR4_SRAM1F_Msk /*!< illegal access flag for SRAM1 memory */ +#define GTZC_TZIC_SR4_MPCBB1F_Pos (23U) +#define GTZC_TZIC_SR4_MPCBB1F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB1F_Pos) +#define GTZC_TZIC_SR4_MPCBB1F GTZC_TZIC_SR4_MPCBB1F_Msk /*!< illegal access flag for MPCBB1 */ +#define GTZC_TZIC_SR4_SRAM2F_Pos (24U) +#define GTZC_TZIC_SR4_SRAM2F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM2F_Pos) +#define GTZC_TZIC_SR4_SRAM2F GTZC_TZIC_SR4_SRAM2F_Msk /*!< illegal access flag for SRAM2 memory */ +#define GTZC_TZIC_SR4_MPCBB2F_Pos (25U) +#define GTZC_TZIC_SR4_MPCBB2F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB2F_Pos) +#define GTZC_TZIC_SR4_MPCBB2F GTZC_TZIC_SR4_MPCBB2F_Msk /*!< illegal access flag for MPCBB2 */ +#define GTZC_TZIC_SR4_SRAM6F_Pos (30U) +#define GTZC_TZIC_SR4_SRAM6F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM6F_Pos) +#define GTZC_TZIC_SR4_SRAM6F GTZC_TZIC_SR4_SRAM6F_Msk /*!< illegal access flag for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_SR4_MPCBB6F_Pos (31U) +#define GTZC_TZIC_SR4_MPCBB6F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB6F_Pos) +#define GTZC_TZIC_SR4_MPCBB6F GTZC_TZIC_SR4_MPCBB6F_Msk /*!< illegal access flag for MPCBB6 */ + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC_FCR1_CTIM2F_Pos (0U) +#define GTZC_TZIC_FCR1_CTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM2F_Pos) +#define GTZC_TZIC_FCR1_CTIM2F GTZC_TZIC_FCR1_CTIM2F_Msk /*!< clear the illegal access flag for TIM2 */ +#define GTZC_TZIC_FCR1_CTIM3F_Pos (1U) +#define GTZC_TZIC_FCR1_CTIM3F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM3F_Pos) +#define GTZC_TZIC_FCR1_CTIM3F GTZC_TZIC_FCR1_CTIM3F_Msk /*!< clear the illegal access flag for TIM3 */ +#define GTZC_TZIC_FCR1_CWWDGF_Pos (6U) +#define GTZC_TZIC_FCR1_CWWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CWWDGF_Pos) +#define GTZC_TZIC_FCR1_CWWDGF GTZC_TZIC_FCR1_CWWDGF_Msk /*!< clear the illegal access flag for WWDG */ +#define GTZC_TZIC_FCR1_CIWDGF_Pos (7U) +#define GTZC_TZIC_FCR1_CIWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CIWDGF_Pos) +#define GTZC_TZIC_FCR1_CIWDGF GTZC_TZIC_FCR1_CIWDGF_Msk /*!< clear the illegal access flag for IWDG */ +#define GTZC_TZIC_FCR1_CUSART2F_Pos (9U) +#define GTZC_TZIC_FCR1_CUSART2F_Msk (0x01UL << GTZC_TZIC_FCR1_CUSART2F_Pos) +#define GTZC_TZIC_FCR1_CUSART2F GTZC_TZIC_FCR1_CUSART2F_Msk /*!< clear the illegal access flag for USART2 */ +#define GTZC_TZIC_FCR1_CI2C1F_Pos (13U) +#define GTZC_TZIC_FCR1_CI2C1F_Msk (0x01UL << GTZC_TZIC_FCR1_CI2C1F_Pos) +#define GTZC_TZIC_FCR1_CI2C1F GTZC_TZIC_FCR1_CI2C1F_Msk /*!< clear the illegal access flag for I2C1 */ +#define GTZC_TZIC_FCR1_CLPTIM2F_Pos (17U) +#define GTZC_TZIC_FCR1_CLPTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CLPTIM2F_Pos) +#define GTZC_TZIC_FCR1_CLPTIM2F GTZC_TZIC_FCR1_CLPTIM2F_Msk /*!< clear the illegal access flag for LPTIM2 */ + +/****************** Bits definition for GTZC_TZIC_FCR2 register ****************/ +#define GTZC_TZIC_FCR2_CTIM1F_Pos (0U) +#define GTZC_TZIC_FCR2_CTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM1F_Pos) +#define GTZC_TZIC_FCR2_CTIM1F GTZC_TZIC_FCR2_CTIM1F_Msk /*!< clear the illegal access flag for TIM1 */ +#define GTZC_TZIC_FCR2_CSPI1F_Pos (1U) +#define GTZC_TZIC_FCR2_CSPI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI1F_Pos) +#define GTZC_TZIC_FCR2_CSPI1F GTZC_TZIC_FCR2_CSPI1F_Msk /*!< clear the illegal access flag for SPI1 */ +#define GTZC_TZIC_FCR2_CUSART1F_Pos (3U) +#define GTZC_TZIC_FCR2_CUSART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CUSART1F_Pos) +#define GTZC_TZIC_FCR2_CUSART1F GTZC_TZIC_FCR2_CUSART1F_Msk /*!< clear the illegal access flag for USART1 */ +#define GTZC_TZIC_FCR2_CTIM16F_Pos (5U) +#define GTZC_TZIC_FCR2_CTIM16F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM16F_Pos) +#define GTZC_TZIC_FCR2_CTIM16F GTZC_TZIC_FCR2_CTIM16F_Msk /*!< clear the illegal access flag for TIM16 */ +#define GTZC_TZIC_FCR2_CTIM17F_Pos (6U) +#define GTZC_TZIC_FCR2_CTIM17F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM17F_Pos) +#define GTZC_TZIC_FCR2_CTIM17F GTZC_TZIC_FCR2_CTIM17F_Msk /*!< clear the illegal access flag for TIM17 */ +#define GTZC_TZIC_FCR2_CSAI1F_Pos (7U) +#define GTZC_TZIC_FCR2_CSAI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSAI1F_Pos) +#define GTZC_TZIC_FCR2_CSAI1F GTZC_TZIC_FCR2_CSAI1F_Msk /*!< clear the illegal access flag for SAI1 */ +#define GTZC_TZIC_FCR2_CSPI3F_Pos (16U) +#define GTZC_TZIC_FCR2_CSPI3F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI3F_Pos) +#define GTZC_TZIC_FCR2_CSPI3F GTZC_TZIC_FCR2_CSPI3F_Msk /*!< clear the illegal access flag for SPI3 */ +#define GTZC_TZIC_FCR2_CLPUART1F_Pos (17U) +#define GTZC_TZIC_FCR2_CLPUART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPUART1F_Pos) +#define GTZC_TZIC_FCR2_CLPUART1F GTZC_TZIC_FCR2_CLPUART1F_Msk /*!< clear the illegal access flag for LPUART1 */ +#define GTZC_TZIC_FCR2_CI2C3F_Pos (18U) +#define GTZC_TZIC_FCR2_CI2C3F_Msk (0x01UL << GTZC_TZIC_FCR2_CI2C3F_Pos) +#define GTZC_TZIC_FCR2_CI2C3F GTZC_TZIC_FCR2_CI2C3F_Msk /*!< clear the illegal access flag for I2C3 */ +#define GTZC_TZIC_FCR2_CLPTIM1F_Pos (19U) +#define GTZC_TZIC_FCR2_CLPTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPTIM1F_Pos) +#define GTZC_TZIC_FCR2_CLPTIM1F GTZC_TZIC_FCR2_CLPTIM1F_Msk /*!< clear the illegal access flag for LPTIM1 */ +#define GTZC_TZIC_FCR2_CCOMPF_Pos (23U) +#define GTZC_TZIC_FCR2_CCOMPF_Msk (0x01UL << GTZC_TZIC_FCR2_CCOMPF_Pos) +#define GTZC_TZIC_FCR2_CCOMPF GTZC_TZIC_FCR2_CCOMPF_Msk /*!< clear the illegal access flag for COMP */ +#define GTZC_TZIC_FCR2_CADC4F_Pos (24U) +#define GTZC_TZIC_FCR2_CADC4F_Msk (0x01UL << GTZC_TZIC_FCR2_CADC4F_Pos) +#define GTZC_TZIC_FCR2_CADC4F GTZC_TZIC_FCR2_CADC4F_Msk /*!< clear the illegal access flag for ADC4 */ + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC_FCR3_CCRCF_Pos (3U) +#define GTZC_TZIC_FCR3_CCRCF_Msk (0x01UL << GTZC_TZIC_FCR3_CCRCF_Pos) +#define GTZC_TZIC_FCR3_CCRCF GTZC_TZIC_FCR3_CCRCF_Msk /*!< clear the illegal access flag enable for CRC */ +#define GTZC_TZIC_FCR3_CTSCF_Pos (4U) +#define GTZC_TZIC_FCR3_CTSCF_Msk (0x01UL << GTZC_TZIC_FCR3_CTSCF_Pos) +#define GTZC_TZIC_FCR3_CTSCF GTZC_TZIC_FCR3_CTSCF_Msk /*!< clear the illegal access flag enable for TSC */ +#define GTZC_TZIC_FCR3_CICACHE_REGF_Pos (6U) +#define GTZC_TZIC_FCR3_CICACHE_REGF_Msk (0x01UL << GTZC_TZIC_FCR3_CICACHE_REGF_Pos) +#define GTZC_TZIC_FCR3_CICACHE_REGF GTZC_TZIC_FCR3_CICACHE_REGF_Msk /*!< clear the illegal access flag enable for ICACHE_REG */ +#define GTZC_TZIC_FCR3_CAESF_Pos (11U) +#define GTZC_TZIC_FCR3_CAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CAESF_Pos) +#define GTZC_TZIC_FCR3_CAESF GTZC_TZIC_FCR3_CAESF_Msk /*!< clear the illegal access flag enable for AES */ +#define GTZC_TZIC_FCR3_CHASHF_Pos (12U) +#define GTZC_TZIC_FCR3_CHASHF_Msk (0x01UL << GTZC_TZIC_FCR3_CHASHF_Pos) +#define GTZC_TZIC_FCR3_CHASHF GTZC_TZIC_FCR3_CHASHF_Msk /*!< clear the illegal access flag enable for HASH */ +#define GTZC_TZIC_FCR3_CRNGF_Pos (13U) +#define GTZC_TZIC_FCR3_CRNGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRNGF_Pos) +#define GTZC_TZIC_FCR3_CRNGF GTZC_TZIC_FCR3_CRNGF_Msk /*!< clear the illegal access flag enable for RNG */ +#define GTZC_TZIC_FCR3_CSAESF_Pos (14U) +#define GTZC_TZIC_FCR3_CSAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CSAESF_Pos) +#define GTZC_TZIC_FCR3_CSAESF GTZC_TZIC_FCR3_CSAESF_Msk /*!< clear the illegal access flag enable for SAES */ +#define GTZC_TZIC_FCR3_CHSEMF_Pos (15U) +#define GTZC_TZIC_FCR3_CHSEMF_Msk (0x01UL << GTZC_TZIC_FCR3_CHSEMF_Pos) +#define GTZC_TZIC_FCR3_CHSEMF GTZC_TZIC_FCR3_CHSEMF_Msk /*!< clear the illegal access flag enable for HSEM */ +#define GTZC_TZIC_FCR3_CPKAF_Pos (16U) +#define GTZC_TZIC_FCR3_CPKAF_Msk (0x01UL << GTZC_TZIC_FCR3_CPKAF_Pos) +#define GTZC_TZIC_FCR3_CPKAF GTZC_TZIC_FCR3_CPKAF_Msk /*!< clear the illegal access flag enable for PKA */ +#define GTZC_TZIC_FCR3_CRAMCFGF_Pos (22U) +#define GTZC_TZIC_FCR3_CRAMCFGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRAMCFGF_Pos) +#define GTZC_TZIC_FCR3_CRAMCFGF GTZC_TZIC_FCR3_CRAMCFGF_Msk /*!< clear the illegal access flag enable for RAMCFG */ +#define GTZC_TZIC_FCR3_CRADIOF_Pos (23U) +#define GTZC_TZIC_FCR3_CRADIOF_Msk (0x01UL << GTZC_TZIC_FCR3_CRADIOF_Pos) +#define GTZC_TZIC_FCR3_CRADIOF GTZC_TZIC_FCR3_CRADIOF_Msk /*!< clear the illegal access flag enable for 2.4 GHz RADIO */ +#define GTZC_TZIC_FCR3_CPTACONVF_Pos (24U) +#define GTZC_TZIC_FCR3_CPTACONVF_Msk (0x01UL << GTZC_TZIC_FCR3_CPTACONVF_Pos) +#define GTZC_TZIC_FCR3_CPTACONVF GTZC_TZIC_FCR3_CPTACONVF_Msk /*!< clear the illegal access flag enable for PTACONV */ + +/****************** Bits definition for GTZC_TZIC_FCR4 register ****************/ +#define GTZC_TZIC_FCR4_CGPDMA1F_Pos (0U) +#define GTZC_TZIC_FCR4_CGPDMA1F_Msk (0x01UL << GTZC_TZIC_FCR4_CGPDMA1F_Pos) +#define GTZC_TZIC_FCR4_CGPDMA1F GTZC_TZIC_FCR4_CGPDMA1F_Msk /*!< clear the illegal access flag enable for GPDMA1 */ +#define GTZC_TZIC_FCR4_CFLASHF_Pos (1U) +#define GTZC_TZIC_FCR4_CFLASHF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASHF_Pos) +#define GTZC_TZIC_FCR4_CFLASHF GTZC_TZIC_FCR4_CFLASHF_Msk /*!< clear the illegal access flag enable for FLASH memory */ +#define GTZC_TZIC_FCR4_CFLASH_REGF_Pos (2U) +#define GTZC_TZIC_FCR4_CFLASH_REGF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASH_REGF_Pos) +#define GTZC_TZIC_FCR4_CFLASH_REGF GTZC_TZIC_FCR4_CFLASH_REGF_Msk /*!< clear the illegal access flag enable for FLASH interface */ +#define GTZC_TZIC_FCR4_CSYSCFGF_Pos (7U) +#define GTZC_TZIC_FCR4_CSYSCFGF_Msk (0x01UL << GTZC_TZIC_FCR4_CSYSCFGF_Pos) +#define GTZC_TZIC_FCR4_CSYSCFGF GTZC_TZIC_FCR4_CSYSCFGF_Msk /*!< clear the illegal access flag enable for SYSCFG interface */ +#define GTZC_TZIC_FCR4_CRTCF_Pos (8U) +#define GTZC_TZIC_FCR4_CRTCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRTCF_Pos) +#define GTZC_TZIC_FCR4_CRTCF GTZC_TZIC_FCR4_CRTCF_Msk /*!< clear the illegal access flag enable for RTC interface */ +#define GTZC_TZIC_FCR4_CTAMPF_Pos (9U) +#define GTZC_TZIC_FCR4_CTAMPF_Msk (0x01UL << GTZC_TZIC_FCR4_CTAMPF_Pos) +#define GTZC_TZIC_FCR4_CTAMPF GTZC_TZIC_FCR4_CTAMPF_Msk /*!< clear the illegal access flag enable for TAMP interface */ +#define GTZC_TZIC_FCR4_CPWRF_Pos (10U) +#define GTZC_TZIC_FCR4_CPWRF_Msk (0x01UL << GTZC_TZIC_FCR4_CPWRF_Pos) +#define GTZC_TZIC_FCR4_CPWRF GTZC_TZIC_FCR4_CPWRF_Msk /*!< clear the illegal access flag enable for PWR interface */ +#define GTZC_TZIC_FCR4_CRCCF_Pos (11U) +#define GTZC_TZIC_FCR4_CRCCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRCCF_Pos) +#define GTZC_TZIC_FCR4_CRCCF GTZC_TZIC_FCR4_CRCCF_Msk /*!< clear the illegal access flag enable for RCC interface */ +#define GTZC_TZIC_FCR4_CEXTIF_Pos (13U) +#define GTZC_TZIC_FCR4_CEXTIF_Msk (0x01UL << GTZC_TZIC_FCR4_CEXTIF_Pos) +#define GTZC_TZIC_FCR4_CEXTIF GTZC_TZIC_FCR4_CEXTIF_Msk /*!< clear the illegal access flag enable for EXTI interface */ +#define GTZC_TZIC_FCR4_CTZSCF_Pos (14U) +#define GTZC_TZIC_FCR4_CTZSCF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZSCF_Pos) +#define GTZC_TZIC_FCR4_CTZSCF GTZC_TZIC_FCR4_CTZSCF_Msk /*!< clear the illegal access flag enable for GTZC TZSC */ +#define GTZC_TZIC_FCR4_CTZICF_Pos (15U) +#define GTZC_TZIC_FCR4_CTZICF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZICF_Pos) +#define GTZC_TZIC_FCR4_CTZICF GTZC_TZIC_FCR4_CTZICF_Msk /*!< clear the illegal access flag enable for GTZC TZIC */ +#define GTZC_TZIC_FCR4_CSRAM1F_Pos (22U) +#define GTZC_TZIC_FCR4_CSRAM1F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM1F_Pos) +#define GTZC_TZIC_FCR4_CSRAM1F GTZC_TZIC_FCR4_CSRAM1F_Msk /*!< clear the illegal access flag enable for SRAM1 memory */ +#define GTZC_TZIC_FCR4_CMPCBB1F_Pos (23U) +#define GTZC_TZIC_FCR4_CMPCBB1F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB1F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB1F GTZC_TZIC_FCR4_CMPCBB1F_Msk /*!< clear the illegal access flag enable for MPCBB1 */ +#define GTZC_TZIC_FCR4_CSRAM2F_Pos (24U) +#define GTZC_TZIC_FCR4_CSRAM2F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM2F_Pos) +#define GTZC_TZIC_FCR4_CSRAM2F GTZC_TZIC_FCR4_CSRAM2F_Msk /*!< clear the illegal access flag enable for SRAM2 memory */ +#define GTZC_TZIC_FCR4_CMPCBB2F_Pos (25U) +#define GTZC_TZIC_FCR4_CMPCBB2F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB2F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB2F GTZC_TZIC_FCR4_CMPCBB2F_Msk /*!< clear the illegal access flag enable for MPCBB2 */ +#define GTZC_TZIC_FCR4_CSRAM6F_Pos (30U) +#define GTZC_TZIC_FCR4_CSRAM6F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM6F_Pos) +#define GTZC_TZIC_FCR4_CSRAM6F GTZC_TZIC_FCR4_CSRAM6F_Msk /*!< clear the illegal access flag enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_FCR4_CMPCBB6F_Pos (31U) +#define GTZC_TZIC_FCR4_CMPCBB6F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB6F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB6F GTZC_TZIC_FCR4_CMPCBB6F_Msk /*!< clear the illegal access flag enable for MPCBB6 */ + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_GLOCK GTZC_MPCBB_CR_GLOCK_Msk /*!< lock the control register of the MPCBB until next reset */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_INVSECSTATE GTZC_MPCBB_CR_INVSECSTATE_Msk /*!< SRAM clocks security state */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_CR_SRWILADIS GTZC_MPCBB_CR_SRWILADIS_Msk /*!< secure read/write illegal access disable */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCK register ************/ +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK0 GTZC_MPCBB_CFGLOCK_SPLCK0_Msk /*!< Security/privilege configuration lock super-block 0 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1 GTZC_MPCBB_CFGLOCK_SPLCK1_Msk /*!< Security/privilege configuration lock super-block 1 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2 GTZC_MPCBB_CFGLOCK_SPLCK2_Msk /*!< Security/privilege configuration lock super-block 2 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3 GTZC_MPCBB_CFGLOCK_SPLCK3_Msk /*!< Security/privilege configuration lock super-block 3 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR0 register ************/ +#define GTZC_MPCBB_SECCFGR0_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR0_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR0_SEC0 GTZC_MPCBB_SECCFGR0_SEC0_Msk /*!< Security configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR0_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR0_SEC1 GTZC_MPCBB_SECCFGR0_SEC1_Msk /*!< Security configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR0_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR0_SEC2 GTZC_MPCBB_SECCFGR0_SEC2_Msk /*!< Security configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR0_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR0_SEC3 GTZC_MPCBB_SECCFGR0_SEC3_Msk /*!< Security configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR0_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR0_SEC4 GTZC_MPCBB_SECCFGR0_SEC4_Msk /*!< Security configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR0_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR0_SEC5 GTZC_MPCBB_SECCFGR0_SEC5_Msk /*!< Security configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR0_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR0_SEC6 GTZC_MPCBB_SECCFGR0_SEC6_Msk /*!< Security configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR0_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR0_SEC7 GTZC_MPCBB_SECCFGR0_SEC7_Msk /*!< Security configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR0_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR0_SEC8 GTZC_MPCBB_SECCFGR0_SEC8_Msk /*!< Security configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR0_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR0_SEC9 GTZC_MPCBB_SECCFGR0_SEC9_Msk /*!< Security configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR0_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR0_SEC10 GTZC_MPCBB_SECCFGR0_SEC10_Msk /*!< Security configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR0_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR0_SEC11 GTZC_MPCBB_SECCFGR0_SEC11_Msk /*!< Security configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR0_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR0_SEC12 GTZC_MPCBB_SECCFGR0_SEC12_Msk /*!< Security configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR0_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR0_SEC13 GTZC_MPCBB_SECCFGR0_SEC13_Msk /*!< Security configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR0_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR0_SEC14 GTZC_MPCBB_SECCFGR0_SEC14_Msk /*!< Security configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR0_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR0_SEC15 GTZC_MPCBB_SECCFGR0_SEC15_Msk /*!< Security configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR0_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR0_SEC16 GTZC_MPCBB_SECCFGR0_SEC16_Msk /*!< Security configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR0_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR0_SEC17 GTZC_MPCBB_SECCFGR0_SEC17_Msk /*!< Security configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR0_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR0_SEC18 GTZC_MPCBB_SECCFGR0_SEC18_Msk /*!< Security configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR0_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR0_SEC19 GTZC_MPCBB_SECCFGR0_SEC19_Msk /*!< Security configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR0_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR0_SEC20 GTZC_MPCBB_SECCFGR0_SEC20_Msk /*!< Security configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR0_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR0_SEC21 GTZC_MPCBB_SECCFGR0_SEC21_Msk /*!< Security configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR0_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR0_SEC22 GTZC_MPCBB_SECCFGR0_SEC22_Msk /*!< Security configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR0_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR0_SEC23 GTZC_MPCBB_SECCFGR0_SEC23_Msk /*!< Security configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR0_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC24 GTZC_MPCBB_SECCFGR0_SEC24_Msk /*!< Security configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR0_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC25 GTZC_MPCBB_SECCFGR0_SEC25_Msk /*!< Security configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR0_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC26 GTZC_MPCBB_SECCFGR0_SEC26_Msk /*!< Security configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR0_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC27 GTZC_MPCBB_SECCFGR0_SEC27_Msk /*!< Security configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR0_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC28 GTZC_MPCBB_SECCFGR0_SEC28_Msk /*!< Security configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR0_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC29 GTZC_MPCBB_SECCFGR0_SEC29_Msk /*!< Security configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR0_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC30 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR0_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC31 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR1 register ************/ +#define GTZC_MPCBB_SECCFGR1_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR1_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR1_SEC0 GTZC_MPCBB_SECCFGR1_SEC0_Msk /*!< Security configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR1_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR1_SEC1 GTZC_MPCBB_SECCFGR1_SEC1_Msk /*!< Security configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR1_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR1_SEC2 GTZC_MPCBB_SECCFGR1_SEC2_Msk /*!< Security configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR1_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR1_SEC3 GTZC_MPCBB_SECCFGR1_SEC3_Msk /*!< Security configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR1_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR1_SEC4 GTZC_MPCBB_SECCFGR1_SEC4_Msk /*!< Security configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR1_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR1_SEC5 GTZC_MPCBB_SECCFGR1_SEC5_Msk /*!< Security configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR1_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR1_SEC6 GTZC_MPCBB_SECCFGR1_SEC6_Msk /*!< Security configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR1_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR1_SEC7 GTZC_MPCBB_SECCFGR1_SEC7_Msk /*!< Security configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR1_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR1_SEC8 GTZC_MPCBB_SECCFGR1_SEC8_Msk /*!< Security configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR1_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR1_SEC9 GTZC_MPCBB_SECCFGR1_SEC9_Msk /*!< Security configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR1_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR1_SEC10 GTZC_MPCBB_SECCFGR1_SEC10_Msk /*!< Security configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR1_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR1_SEC11 GTZC_MPCBB_SECCFGR1_SEC11_Msk /*!< Security configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR1_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR1_SEC12 GTZC_MPCBB_SECCFGR1_SEC12_Msk /*!< Security configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR1_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR1_SEC13 GTZC_MPCBB_SECCFGR1_SEC13_Msk /*!< Security configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR1_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR1_SEC14 GTZC_MPCBB_SECCFGR1_SEC14_Msk /*!< Security configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR1_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR1_SEC15 GTZC_MPCBB_SECCFGR1_SEC15_Msk /*!< Security configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR1_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR1_SEC16 GTZC_MPCBB_SECCFGR1_SEC16_Msk /*!< Security configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR1_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR1_SEC17 GTZC_MPCBB_SECCFGR1_SEC17_Msk /*!< Security configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR1_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR1_SEC18 GTZC_MPCBB_SECCFGR1_SEC18_Msk /*!< Security configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR1_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR1_SEC19 GTZC_MPCBB_SECCFGR1_SEC19_Msk /*!< Security configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR1_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR1_SEC20 GTZC_MPCBB_SECCFGR1_SEC20_Msk /*!< Security configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR1_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR1_SEC21 GTZC_MPCBB_SECCFGR1_SEC21_Msk /*!< Security configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR1_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR1_SEC22 GTZC_MPCBB_SECCFGR1_SEC22_Msk /*!< Security configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR1_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR1_SEC23 GTZC_MPCBB_SECCFGR1_SEC23_Msk /*!< Security configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR1_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC24 GTZC_MPCBB_SECCFGR1_SEC24_Msk /*!< Security configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR1_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC25 GTZC_MPCBB_SECCFGR1_SEC25_Msk /*!< Security configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR1_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC26 GTZC_MPCBB_SECCFGR1_SEC26_Msk /*!< Security configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR1_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC27 GTZC_MPCBB_SECCFGR1_SEC27_Msk /*!< Security configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR1_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC28 GTZC_MPCBB_SECCFGR1_SEC28_Msk /*!< Security configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR1_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC29 GTZC_MPCBB_SECCFGR1_SEC29_Msk /*!< Security configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR1_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC30 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR1_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC31 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR2 register ************/ +#define GTZC_MPCBB_SECCFGR2_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR2_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR2_SEC0 GTZC_MPCBB_SECCFGR2_SEC0_Msk /*!< Security configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR2_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR2_SEC1 GTZC_MPCBB_SECCFGR2_SEC1_Msk /*!< Security configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR2_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR2_SEC2 GTZC_MPCBB_SECCFGR2_SEC2_Msk /*!< Security configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR2_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR2_SEC3 GTZC_MPCBB_SECCFGR2_SEC3_Msk /*!< Security configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR2_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR2_SEC4 GTZC_MPCBB_SECCFGR2_SEC4_Msk /*!< Security configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR2_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR2_SEC5 GTZC_MPCBB_SECCFGR2_SEC5_Msk /*!< Security configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR2_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR2_SEC6 GTZC_MPCBB_SECCFGR2_SEC6_Msk /*!< Security configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR2_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR2_SEC7 GTZC_MPCBB_SECCFGR2_SEC7_Msk /*!< Security configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR2_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR2_SEC8 GTZC_MPCBB_SECCFGR2_SEC8_Msk /*!< Security configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR2_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR2_SEC9 GTZC_MPCBB_SECCFGR2_SEC9_Msk /*!< Security configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR2_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR2_SEC10 GTZC_MPCBB_SECCFGR2_SEC10_Msk /*!< Security configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR2_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR2_SEC11 GTZC_MPCBB_SECCFGR2_SEC11_Msk /*!< Security configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR2_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR2_SEC12 GTZC_MPCBB_SECCFGR2_SEC12_Msk /*!< Security configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR2_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR2_SEC13 GTZC_MPCBB_SECCFGR2_SEC13_Msk /*!< Security configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR2_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR2_SEC14 GTZC_MPCBB_SECCFGR2_SEC14_Msk /*!< Security configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR2_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR2_SEC15 GTZC_MPCBB_SECCFGR2_SEC15_Msk /*!< Security configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR2_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR2_SEC16 GTZC_MPCBB_SECCFGR2_SEC16_Msk /*!< Security configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR2_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR2_SEC17 GTZC_MPCBB_SECCFGR2_SEC17_Msk /*!< Security configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR2_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR2_SEC18 GTZC_MPCBB_SECCFGR2_SEC18_Msk /*!< Security configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR2_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR2_SEC19 GTZC_MPCBB_SECCFGR2_SEC19_Msk /*!< Security configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR2_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR2_SEC20 GTZC_MPCBB_SECCFGR2_SEC20_Msk /*!< Security configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR2_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR2_SEC21 GTZC_MPCBB_SECCFGR2_SEC21_Msk /*!< Security configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR2_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR2_SEC22 GTZC_MPCBB_SECCFGR2_SEC22_Msk /*!< Security configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR2_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR2_SEC23 GTZC_MPCBB_SECCFGR2_SEC23_Msk /*!< Security configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR2_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC24 GTZC_MPCBB_SECCFGR2_SEC24_Msk /*!< Security configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR2_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC25 GTZC_MPCBB_SECCFGR2_SEC25_Msk /*!< Security configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR2_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC26 GTZC_MPCBB_SECCFGR2_SEC26_Msk /*!< Security configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR2_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC27 GTZC_MPCBB_SECCFGR2_SEC27_Msk /*!< Security configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR2_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC28 GTZC_MPCBB_SECCFGR2_SEC28_Msk /*!< Security configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR2_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC29 GTZC_MPCBB_SECCFGR2_SEC29_Msk /*!< Security configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR2_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC30 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR2_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC31 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR3 register ************/ +#define GTZC_MPCBB_SECCFGR3_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR3_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR3_SEC0 GTZC_MPCBB_SECCFGR3_SEC0_Msk /*!< Security configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR3_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR3_SEC1 GTZC_MPCBB_SECCFGR3_SEC1_Msk /*!< Security configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR3_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR3_SEC2 GTZC_MPCBB_SECCFGR3_SEC2_Msk /*!< Security configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR3_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR3_SEC3 GTZC_MPCBB_SECCFGR3_SEC3_Msk /*!< Security configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR3_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR3_SEC4 GTZC_MPCBB_SECCFGR3_SEC4_Msk /*!< Security configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR3_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR3_SEC5 GTZC_MPCBB_SECCFGR3_SEC5_Msk /*!< Security configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR3_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR3_SEC6 GTZC_MPCBB_SECCFGR3_SEC6_Msk /*!< Security configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR3_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR3_SEC7 GTZC_MPCBB_SECCFGR3_SEC7_Msk /*!< Security configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR3_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR3_SEC8 GTZC_MPCBB_SECCFGR3_SEC8_Msk /*!< Security configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR3_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR3_SEC9 GTZC_MPCBB_SECCFGR3_SEC9_Msk /*!< Security configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR3_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR3_SEC10 GTZC_MPCBB_SECCFGR3_SEC10_Msk /*!< Security configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR3_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR3_SEC11 GTZC_MPCBB_SECCFGR3_SEC11_Msk /*!< Security configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR3_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR3_SEC12 GTZC_MPCBB_SECCFGR3_SEC12_Msk /*!< Security configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR3_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR3_SEC13 GTZC_MPCBB_SECCFGR3_SEC13_Msk /*!< Security configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR3_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR3_SEC14 GTZC_MPCBB_SECCFGR3_SEC14_Msk /*!< Security configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR3_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR3_SEC15 GTZC_MPCBB_SECCFGR3_SEC15_Msk /*!< Security configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR3_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR3_SEC16 GTZC_MPCBB_SECCFGR3_SEC16_Msk /*!< Security configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR3_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR3_SEC17 GTZC_MPCBB_SECCFGR3_SEC17_Msk /*!< Security configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR3_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR3_SEC18 GTZC_MPCBB_SECCFGR3_SEC18_Msk /*!< Security configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR3_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR3_SEC19 GTZC_MPCBB_SECCFGR3_SEC19_Msk /*!< Security configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR3_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR3_SEC20 GTZC_MPCBB_SECCFGR3_SEC20_Msk /*!< Security configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR3_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR3_SEC21 GTZC_MPCBB_SECCFGR3_SEC21_Msk /*!< Security configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR3_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR3_SEC22 GTZC_MPCBB_SECCFGR3_SEC22_Msk /*!< Security configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR3_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR3_SEC23 GTZC_MPCBB_SECCFGR3_SEC23_Msk /*!< Security configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR3_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC24 GTZC_MPCBB_SECCFGR3_SEC24_Msk /*!< Security configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR3_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC25 GTZC_MPCBB_SECCFGR3_SEC25_Msk /*!< Security configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR3_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC26 GTZC_MPCBB_SECCFGR3_SEC26_Msk /*!< Security configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR3_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC27 GTZC_MPCBB_SECCFGR3_SEC27_Msk /*!< Security configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR3_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC28 GTZC_MPCBB_SECCFGR3_SEC28_Msk /*!< Security configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR3_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC29 GTZC_MPCBB_SECCFGR3_SEC29_Msk /*!< Security configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR3_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC30 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR3_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC31 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 31 in super block 3 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR0 register ************/ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0 GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1 GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2 GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3 GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4 GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5 GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6 GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7 GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8 GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9 GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10 GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11 GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12 GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13 GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14 GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15 GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16 GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17 GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18 GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19 GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20 GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21 GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22 GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23 GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24 GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25 GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26 GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27 GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28 GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29 GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR1 register ************/ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0 GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1 GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2 GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3 GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4 GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5 GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6 GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7 GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8 GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9 GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10 GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11 GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12 GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13 GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14 GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15 GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16 GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17 GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18 GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19 GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20 GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21 GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22 GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23 GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24 GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25 GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26 GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27 GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28 GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29 GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR2 register ************/ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0 GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1 GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2 GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3 GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4 GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5 GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6 GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7 GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8 GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9 GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10 GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11 GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12 GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13 GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14 GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15 GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16 GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17 GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18 GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19 GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20 GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21 GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22 GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23 GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24 GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25 GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26 GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27 GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28 GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29 GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR3 register ************/ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0 GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1 GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2 GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3 GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4 GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5 GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6 GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7 GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8 GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9 GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10 GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11 GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12 GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13 GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14 GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15 GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16 GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17 GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18 GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19 GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20 GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21 GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22 GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23 GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24 GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25 GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26 GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27 GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28 GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29 GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 3 */ + + +/******************************************************************************/ +/* */ +/* HASH */ +/* */ +/******************************************************************************/ +/****************** Bits definition for HASH_CR register ********************/ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/****************** Bits definition for HASH_STR register *******************/ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk +#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk + +/****************** Bits definition for HASH_IMR register *******************/ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk + +/****************** Bits definition for HASH_SR register ********************/ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk +#define HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk +#define HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) /*!< 0x000O0200 */ +#define HASH_SR_NBWP_1 (0x02UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ + + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* PTA Converter */ +/* */ +/******************************************************************************/ +/****************** Bit definition for PTACONV_ACTCR register ***************/ +#define PTACONV_ACTCR_TACTIVE_Pos (0U) +#define PTACONV_ACTCR_TACTIVE_Msk (0xFFUL << PTACONV_ACTCR_TACTIVE_Pos) /*!< 0x000000FF */ +#define PTACONV_ACTCR_TACTIVE PTACONV_ACTCR_TACTIVE_Msk /*!< PTA_ACTIVE setup time in us */ +#define PTACONV_ACTCR_ACTPOL_Pos (15U) +#define PTACONV_ACTCR_ACTPOL_Msk (0x1UL << PTACONV_ACTCR_ACTPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_ACTCR_ACTPOL PTACONV_ACTCR_ACTPOL_Msk /*!< PTA_ACTIVE polarity */ +#define PTACONV_ACTCR_TABORT_Pos (16U) +#define PTACONV_ACTCR_TABORT_Msk (0xFUL << PTACONV_ACTCR_TABORT_Pos) /*!< 0x000F0000 */ +#define PTACONV_ACTCR_TABORT PTACONV_ACTCR_TABORT_Msk /*!< PTA_ACTIVE delay to cease an ongoing transmission in us */ +#define PTACONV_ACTCR_ABORTDIS_Pos (20U) +#define PTACONV_ACTCR_ABORTDIS_Msk (0x1UL << PTACONV_ACTCR_ABORTDIS_Pos) /*!< 0x00100000 */ +#define PTACONV_ACTCR_ABORTDIS PTACONV_ACTCR_ABORTDIS_Msk /*!< Disable PTA_ACTIVE deny to abort an ongoing transmission */ + +/****************** Bit definition for PTACONV_PRICR register ***************/ +#define PTACONV_PRICR_TPRIORITY_Pos (0U) +#define PTACONV_PRICR_TPRIORITY_Msk (0x1FUL << PTACONV_PRICR_TPRIORITY_Pos) /*!< 0x0000001F */ +#define PTACONV_PRICR_TPRIORITY PTACONV_PRICR_TPRIORITY_Msk /*!< Priority valid time in us */ +#define PTACONV_PRICR_PRIPOL_Pos (15U) +#define PTACONV_PRICR_PRIPOL_Msk (0x1UL << PTACONV_PRICR_PRIPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_PRICR_PRIPOL PTACONV_PRICR_PRIPOL_Msk /*!< Priority polarity */ + +/****************** Bit definition for PTACONV_CR register ******************/ +#define PTACONV_CR_TXRXPOL_Pos (15U) +#define PTACONV_CR_TXRXPOL_Msk (0x1UL << PTACONV_CR_TXRXPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_CR_TXRXPOL PTACONV_CR_TXRXPOL_Msk /*!< PTA_STATUS transmit and receive polarity */ +#define PTACONV_CR_GRANTPOL_Pos (31U) +#define PTACONV_CR_GRANTPOL_Msk (0x1UL << PTACONV_CR_GRANTPOL_Pos) /*!< 0x80000000 */ +#define PTACONV_CR_GRANTPOL PTACONV_CR_GRANTPOL_Msk /*!< PTA_GRANT polarity */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_LPMS_Pos (0U) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< LPMS[2:0] Low-power mode selection field */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ +#define PWR_CR1_R2RSB1_Pos (5U) +#define PWR_CR1_R2RSB1_Msk (0x1UL << PWR_CR1_R2RSB1_Pos) /*!< 0x00000020 */ +#define PWR_CR1_R2RSB1 PWR_CR1_R2RSB1_Msk /*!< SRAM2 Retention in Standby */ +#define PWR_CR1_ULPMEN_Pos (7U) +#define PWR_CR1_ULPMEN_Msk (0x1UL << PWR_CR1_ULPMEN_Pos) /*!< 0x00000080 */ +#define PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk /*!< BOR ultra-low power mode in Standby/Shutdown */ +#define PWR_CR1_RADIORSB_Pos (9U) +#define PWR_CR1_RADIORSB_Msk (0x1UL << PWR_CR1_RADIORSB_Pos) /*!< 0x00000200 */ +#define PWR_CR1_RADIORSB PWR_CR1_RADIORSB_Msk /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) and Sleep clock retention in Standby mode */ +#define PWR_CR1_R1RSB1_Pos (12U) +#define PWR_CR1_R1RSB1_Msk (0x1UL << PWR_CR1_R1RSB1_Pos) /*!< 0x00001000 */ +#define PWR_CR1_R1RSB1 PWR_CR1_R1RSB1_Msk /*!< SRAM1 Page 1 Retention in Standby */ + +/******************** Bit definition for PWR_CR2 register *******************/ +#define PWR_CR2_SRAM1PDS1_Pos (0U) +#define PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) /*!< 0x00000001 */ +#define PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 Page 1 power-down in Stop modes */ +#define PWR_CR2_SRAM2PDS1_Pos (4U) +#define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010 */ +#define PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 power-down in Stop modes */ +#define PWR_CR2_ICRAMPDS_Pos (8U) +#define PWR_CR2_ICRAMPDS_Msk (0x1UL << PWR_CR2_ICRAMPDS_Pos) /*!< 0x00000100 */ +#define PWR_CR2_ICRAMPDS PWR_CR2_ICRAMPDS_Msk /*!< ICACHE SRAM power-down in Stop modes */ +#define PWR_CR2_FLASHFWU_Pos (14U) +#define PWR_CR2_FLASHFWU_Msk (0x1UL << PWR_CR2_FLASHFWU_Pos) /*!< 0x00004000 */ +#define PWR_CR2_FLASHFWU PWR_CR2_FLASHFWU_Msk /*!< Flash low-power mode in Stop modes */ +#define PWR_CR2_FPWM_Pos (30U) +#define PWR_CR2_FPWM_Msk (0x1UL << PWR_CR2_FPWM_Pos) /*!< 0x40000000 */ +#define PWR_CR2_FPWM PWR_CR2_FPWM_Msk /*!< SMPS PWM mode */ + +/******************** Bit definition for PWR_CR3 register *******************/ +#define PWR_CR3_REGSEL_Pos (1U) +#define PWR_CR3_REGSEL_Msk (0x1UL << PWR_CR3_REGSEL_Pos) /*!< 0x00000002 */ +#define PWR_CR3_REGSEL PWR_CR3_REGSEL_Msk /*!< Regulator selection */ +#define PWR_CR3_FSTEN_Pos (2U) +#define PWR_CR3_FSTEN_Msk (0x1UL << PWR_CR3_FSTEN_Pos) /*!< 0x00000004 */ +#define PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk /*!< Fast soft start */ + +/******************* Bit definition for PWR_VOSR register *******************/ +#define PWR_VOSR_VOSRDY_Pos (15U) +#define PWR_VOSR_VOSRDY_Msk (0x1UL << PWR_VOSR_VOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_VOSR_VOSRDY PWR_VOSR_VOSRDY_Msk /*!< Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSR_VOS_Pos (16U) +#define PWR_VOSR_VOS_Msk (0x1UL << PWR_VOSR_VOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSR_VOS PWR_VOSR_VOS_Msk /*!< Voltage scaling range selection */ + +/******************* Bit definition for PWR_SVMCR register ******************/ +#define PWR_SVMCR_PVDE_Pos (4U) +#define PWR_SVMCR_PVDE_Msk (0x1UL << PWR_SVMCR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR_PVDE PWR_SVMCR_PVDE_Msk /*!< Power voltage detector enable */ +#define PWR_SVMCR_PVDLS_Pos (5U) +#define PWR_SVMCR_PVDLS_Msk (0x7UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x000000E0 */ +#define PWR_SVMCR_PVDLS PWR_SVMCR_PVDLS_Msk /*!< PVDLS[2:0] Power voltage detector level selection field */ +#define PWR_SVMCR_PVDLS_0 (0x1UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000020 */ +#define PWR_SVMCR_PVDLS_1 (0x2UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000040 */ +#define PWR_SVMCR_PVDLS_2 (0x4UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for PWR_WUCR1 register ******************/ +#define PWR_WUCR1_WUPEN1_Pos (0U) +#define PWR_WUCR1_WUPEN1_Msk (0x1UL << PWR_WUCR1_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR1_WUPEN1 PWR_WUCR1_WUPEN1_Msk /*!< Wakeup pin WKUP1 enable */ +#define PWR_WUCR1_WUPEN2_Pos (1U) +#define PWR_WUCR1_WUPEN2_Msk (0x1UL << PWR_WUCR1_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR1_WUPEN2 PWR_WUCR1_WUPEN2_Msk /*!< Wakeup pin WKUP2 enable */ +#define PWR_WUCR1_WUPEN3_Pos (2U) +#define PWR_WUCR1_WUPEN3_Msk (0x1UL << PWR_WUCR1_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR1_WUPEN3 PWR_WUCR1_WUPEN3_Msk /*!< Wakeup pin WKUP3 enable */ +#define PWR_WUCR1_WUPEN4_Pos (3U) +#define PWR_WUCR1_WUPEN4_Msk (0x1UL << PWR_WUCR1_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR1_WUPEN4 PWR_WUCR1_WUPEN4_Msk /*!< Wakeup pin WKUP4 enable */ +#define PWR_WUCR1_WUPEN5_Pos (4U) +#define PWR_WUCR1_WUPEN5_Msk (0x1UL << PWR_WUCR1_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR1_WUPEN5 PWR_WUCR1_WUPEN5_Msk /*!< Wakeup pin WKUP5 enable */ +#define PWR_WUCR1_WUPEN6_Pos (5U) +#define PWR_WUCR1_WUPEN6_Msk (0x1UL << PWR_WUCR1_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR1_WUPEN6 PWR_WUCR1_WUPEN6_Msk /*!< Wakeup pin WKUP6 enable */ +#define PWR_WUCR1_WUPEN7_Pos (6U) +#define PWR_WUCR1_WUPEN7_Msk (0x1UL << PWR_WUCR1_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR1_WUPEN7 PWR_WUCR1_WUPEN7_Msk /*!< Wakeup pin WKUP7 enable */ +#define PWR_WUCR1_WUPEN8_Pos (7U) +#define PWR_WUCR1_WUPEN8_Msk (0x1UL << PWR_WUCR1_WUPEN8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR1_WUPEN8 PWR_WUCR1_WUPEN8_Msk /*!< Wakeup pin WKUP8 enable */ + +/******************* Bit definition for PWR_WUCR2 register ******************/ +#define PWR_WUCR2_WUPP1_Pos (0U) +#define PWR_WUCR2_WUPP1_Msk (0x1UL << PWR_WUCR2_WUPP1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR2_WUPP1 PWR_WUCR2_WUPP1_Msk /*!< Wakeup pin WKUP1 polarity */ +#define PWR_WUCR2_WUPP2_Pos (1U) +#define PWR_WUCR2_WUPP2_Msk (0x1UL << PWR_WUCR2_WUPP2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR2_WUPP2 PWR_WUCR2_WUPP2_Msk /*!< Wakeup pin WKUP2 polarity */ +#define PWR_WUCR2_WUPP3_Pos (2U) +#define PWR_WUCR2_WUPP3_Msk (0x1UL << PWR_WUCR2_WUPP3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR2_WUPP3 PWR_WUCR2_WUPP3_Msk /*!< Wakeup pin WKUP3 polarity */ +#define PWR_WUCR2_WUPP4_Pos (3U) +#define PWR_WUCR2_WUPP4_Msk (0x1UL << PWR_WUCR2_WUPP4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR2_WUPP4 PWR_WUCR2_WUPP4_Msk /*!< Wakeup pin WKUP4 polarity */ +#define PWR_WUCR2_WUPP5_Pos (4U) +#define PWR_WUCR2_WUPP5_Msk (0x1UL << PWR_WUCR2_WUPP5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR2_WUPP5 PWR_WUCR2_WUPP5_Msk /*!< Wakeup pin WKUP5 polarity */ +#define PWR_WUCR2_WUPP6_Pos (5U) +#define PWR_WUCR2_WUPP6_Msk (0x1UL << PWR_WUCR2_WUPP6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR2_WUPP6 PWR_WUCR2_WUPP6_Msk /*!< Wakeup pin WKUP6 polarity */ +#define PWR_WUCR2_WUPP7_Pos (6U) +#define PWR_WUCR2_WUPP7_Msk (0x1UL << PWR_WUCR2_WUPP7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR2_WUPP7 PWR_WUCR2_WUPP7_Msk /*!< Wakeup pin WKUP7 polarity */ +#define PWR_WUCR2_WUPP8_Pos (7U) +#define PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk /*!< Wakeup pin WKUP8 polarity */ + +/******************* Bit definition for PWR_WUCR3 register ******************/ +#define PWR_WUCR3_WUSEL1_Pos (0U) +#define PWR_WUCR3_WUSEL1_Msk (0x3UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000003 */ +#define PWR_WUCR3_WUSEL1 PWR_WUCR3_WUSEL1_Msk /*!< Wakeup pin WKUP1 selection field */ +#define PWR_WUCR3_WUSEL1_0 (0x1UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR3_WUSEL1_1 (0x2UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000002 */ +#define PWR_WUCR3_WUSEL2_Pos (2U) +#define PWR_WUCR3_WUSEL2_Msk (0x3UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x0000000C */ +#define PWR_WUCR3_WUSEL2 PWR_WUCR3_WUSEL2_Msk /*!< Wakeup pin WKUP2 selection field */ +#define PWR_WUCR3_WUSEL2_0 (0x1UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000004 */ +#define PWR_WUCR3_WUSEL2_1 (0x2UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000008 */ +#define PWR_WUCR3_WUSEL3_Pos (4U) +#define PWR_WUCR3_WUSEL3_Msk (0x3UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000030 */ +#define PWR_WUCR3_WUSEL3 PWR_WUCR3_WUSEL3_Msk /*!< Wakeup pin WKUP3 selection field */ +#define PWR_WUCR3_WUSEL3_0 (0x1UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000010 */ +#define PWR_WUCR3_WUSEL3_1 (0x2UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000020 */ +#define PWR_WUCR3_WUSEL4_Pos (6U) +#define PWR_WUCR3_WUSEL4_Msk (0x3UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x000000C0 */ +#define PWR_WUCR3_WUSEL4 PWR_WUCR3_WUSEL4_Msk /*!< Wakeup pin WKUP4 selection field */ +#define PWR_WUCR3_WUSEL4_0 (0x1UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000040 */ +#define PWR_WUCR3_WUSEL4_1 (0x2UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000080 */ +#define PWR_WUCR3_WUSEL5_Pos (8U) +#define PWR_WUCR3_WUSEL5_Msk (0x3UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000300 */ +#define PWR_WUCR3_WUSEL5 PWR_WUCR3_WUSEL5_Msk /*!< Wakeup pin WKUP5 selection field */ +#define PWR_WUCR3_WUSEL5_0 (0x1UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000100 */ +#define PWR_WUCR3_WUSEL5_1 (0x2UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000200 */ +#define PWR_WUCR3_WUSEL6_Pos (10U) +#define PWR_WUCR3_WUSEL6_Msk (0x3UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000C00 */ +#define PWR_WUCR3_WUSEL6 PWR_WUCR3_WUSEL6_Msk /*!< Wakeup pin WKUP6 selection field */ +#define PWR_WUCR3_WUSEL6_0 (0x1UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000400 */ +#define PWR_WUCR3_WUSEL6_1 (0x2UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000800 */ +#define PWR_WUCR3_WUSEL7_Pos (12U) +#define PWR_WUCR3_WUSEL7_Msk (0x3UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00003000 */ +#define PWR_WUCR3_WUSEL7 PWR_WUCR3_WUSEL7_Msk /*!< Wakeup pin WKUP7 selection field */ +#define PWR_WUCR3_WUSEL7_0 (0x1UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00001000 */ +#define PWR_WUCR3_WUSEL7_1 (0x2UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00002000 */ +#define PWR_WUCR3_WUSEL8_Pos (14U) +#define PWR_WUCR3_WUSEL8_Msk (0x3UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x0000C000 */ +#define PWR_WUCR3_WUSEL8 PWR_WUCR3_WUSEL8_Msk /*!< Wakeup pin WKUP8 selection field */ +#define PWR_WUCR3_WUSEL8_0 (0x1UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00004000 */ +#define PWR_WUCR3_WUSEL8_1 (0x2UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_DBPR register ******************/ +#define PWR_DBPR_DBP_Pos (0U) +#define PWR_DBPR_DBP_Msk (0x1UL << PWR_DBPR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPR_DBP PWR_DBPR_DBP_Msk /*!< Disable backup domain write protection */ + +/******************* Bit definition for PWR_SECCFGR register ****************/ +#define PWR_SECCFGR_WUP1SEC_Pos (0U) +#define PWR_SECCFGR_WUP1SEC_Msk (0x1UL << PWR_SECCFGR_WUP1SEC_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_WUP1SEC PWR_SECCFGR_WUP1SEC_Msk /*!< WUP1 secure protection */ +#define PWR_SECCFGR_WUP2SEC_Pos (1U) +#define PWR_SECCFGR_WUP2SEC_Msk (0x1UL << PWR_SECCFGR_WUP2SEC_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_WUP2SEC PWR_SECCFGR_WUP2SEC_Msk /*!< WUP2 secure protection */ +#define PWR_SECCFGR_WUP3SEC_Pos (2U) +#define PWR_SECCFGR_WUP3SEC_Msk (0x1UL << PWR_SECCFGR_WUP3SEC_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_WUP3SEC PWR_SECCFGR_WUP3SEC_Msk /*!< WUP3 secure protection */ +#define PWR_SECCFGR_WUP4SEC_Pos (3U) +#define PWR_SECCFGR_WUP4SEC_Msk (0x1UL << PWR_SECCFGR_WUP4SEC_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_WUP4SEC PWR_SECCFGR_WUP4SEC_Msk /*!< WUP4 secure protection */ +#define PWR_SECCFGR_WUP5SEC_Pos (4U) +#define PWR_SECCFGR_WUP5SEC_Msk (0x1UL << PWR_SECCFGR_WUP5SEC_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_WUP5SEC PWR_SECCFGR_WUP5SEC_Msk /*!< WUP5 secure protection */ +#define PWR_SECCFGR_WUP6SEC_Pos (5U) +#define PWR_SECCFGR_WUP6SEC_Msk (0x1UL << PWR_SECCFGR_WUP6SEC_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_WUP6SEC PWR_SECCFGR_WUP6SEC_Msk /*!< WUP6 secure protection */ +#define PWR_SECCFGR_WUP7SEC_Pos (6U) +#define PWR_SECCFGR_WUP7SEC_Msk (0x1UL << PWR_SECCFGR_WUP7SEC_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_WUP7SEC PWR_SECCFGR_WUP7SEC_Msk /*!< WUP7 secure protection */ +#define PWR_SECCFGR_WUP8SEC_Pos (7U) +#define PWR_SECCFGR_WUP8SEC_Msk (0x1UL << PWR_SECCFGR_WUP8SEC_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_WUP8SEC PWR_SECCFGR_WUP8SEC_Msk /*!< WUP8 secure protection */ +#define PWR_SECCFGR_LPMSEC_Pos (12U) +#define PWR_SECCFGR_LPMSEC_Msk (0x1UL << PWR_SECCFGR_LPMSEC_Pos) /*!< 0x00001000 */ +#define PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk /*!< Low-power modes secure protection */ +#define PWR_SECCFGR_VDMSEC_Pos (13U) +#define PWR_SECCFGR_VDMSEC_Msk (0x1UL << PWR_SECCFGR_VDMSEC_Pos) /*!< 0x00002000 */ +#define PWR_SECCFGR_VDMSEC PWR_SECCFGR_VDMSEC_Msk /*!< Voltage detection and monitoring secure protection */ +#define PWR_SECCFGR_VBSEC_Pos (14U) +#define PWR_SECCFGR_VBSEC_Msk (0x1UL << PWR_SECCFGR_VBSEC_Pos) /*!< 0x00004000 */ +#define PWR_SECCFGR_VBSEC PWR_SECCFGR_VBSEC_Msk /*!< Backup domain secure protection */ + +/******************* Bit definition for PWR_PRIVCFGR register ***************/ +#define PWR_PRIVCFGR_SPRIV_Pos (0U) +#define PWR_PRIVCFGR_SPRIV_Msk (0x1UL << PWR_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_SPRIV PWR_PRIVCFGR_SPRIV_Msk /*!< RCC secure functions privilege configuration */ +#define PWR_PRIVCFGR_NSPRIV_Pos (1U) +#define PWR_PRIVCFGR_NSPRIV_Msk (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_NSPRIV PWR_PRIVCFGR_NSPRIV_Msk /*!< RCC non-secure functions privilege configuration */ + +/********************** Bit definition for PWR_SR register ******************/ +#define PWR_SR_CSSF_Pos (0U) +#define PWR_SR_CSSF_Msk (0x1UL << PWR_SR_CSSF_Pos) /*!< 0x00000001 */ +#define PWR_SR_CSSF PWR_SR_CSSF_Msk /*!< Clear Stop and Standby/Shutdown flags */ +#define PWR_SR_STOPF_Pos (1U) +#define PWR_SR_STOPF_Msk (0x1UL << PWR_SR_STOPF_Pos) /*!< 0x00000002 */ +#define PWR_SR_STOPF PWR_SR_STOPF_Msk /*!< Stop flag */ +#define PWR_SR_SBF_Pos (2U) +#define PWR_SR_SBF_Msk (0x1UL << PWR_SR_SBF_Pos) /*!< 0x00000004 */ +#define PWR_SR_SBF PWR_SR_SBF_Msk /*!< Standby/Shutdown flag */ + +/******************** Bit definition for PWR_SVMSR register *****************/ +#define PWR_SVMSR_REGS_Pos (1U) +#define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002 */ +#define PWR_SVMSR_REGS PWR_SVMSR_REGS_Msk /*!< Regulator status */ +#define PWR_SVMSR_PVDO_Pos (4U) +#define PWR_SVMSR_PVDO_Msk (0x1UL << PWR_SVMSR_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SVMSR_PVDO PWR_SVMSR_PVDO_Msk /*!< VDD voltage detector output */ +#define PWR_SVMSR_ACTVOSRDY_Pos (15U) +#define PWR_SVMSR_ACTVOSRDY_Msk (0x1UL << PWR_SVMSR_ACTVOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_SVMSR_ACTVOSRDY PWR_SVMSR_ACTVOSRDY_Msk /*!< Voltage level ready for currently used VOS */ +#define PWR_SVMSR_ACTVOS_Pos (16U) +#define PWR_SVMSR_ACTVOS_Msk (0x1UL << PWR_SVMSR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_SVMSR_ACTVOS PWR_SVMSR_ACTVOS_Msk /*!< Voltage Output Scaling currently applied to VCORE */ + +/********************* Bit definition for PWR_WUSR register *****************/ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< Wakeup flag 1 */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< Wakeup flag 2 */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< Wakeup flag 3 */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< Wakeup flag 4 */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< Wakeup flag 5 */ +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< Wakeup flag 6 */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< Wakeup flag 7 */ +#define PWR_WUSR_WUF8_Pos (7U) +#define PWR_WUSR_WUF8_Msk (0x1UL << PWR_WUSR_WUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSR_WUF8 PWR_WUSR_WUF8_Msk /*!< Wakeup flag 8 */ +#define PWR_WUSR_WUF_Pos (0U) +#define PWR_WUSR_WUF_Msk (0xFFUL << PWR_WUSR_WUF_Pos) /*!< 0x000000FF */ +#define PWR_WUSR_WUF PWR_WUSR_WUF_Msk /*!< all Wakeup flag */ + +/********************* Bit definition for PWR_WUSCR register ****************/ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001*/ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< Wakeup clear flag 1 */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< Wakeup clear flag 2 */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< Wakeup clear flag 3 */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< Wakeup clear flag 4 */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< Wakeup clear flag 5 */ +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< Wakeup clear flag 6 */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< Wakeup clear flag 7 */ +#define PWR_WUSCR_CWUF8_Pos (7U) +#define PWR_WUSCR_CWUF8_Msk (0x1UL << PWR_WUSCR_CWUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8_Msk /*!< Wakeup clear flag 8 */ +#define PWR_WUSCR_CWUF_Pos (0U) +#define PWR_WUSCR_CWUF_Msk (0xFFUL << PWR_WUSCR_CWUF1_Pos) /*!< 0x000000FF */ +#define PWR_WUSCR_CWUF PWR_WUSCR_CWUF_Msk /*!< all Wakeup clear flag */ + +/******************** Bit definition for PWR_IORETENRA register *****************/ +#define PWR_IORETENRA_EN0_Pos (0U) +#define PWR_IORETENRA_EN0_Msk (0x1UL << PWR_IORETENRA_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRA_EN0 PWR_IORETENRA_EN0_Msk /*!< Standby GPIO retention enable for PA0 */ +#define PWR_IORETENRA_EN1_Pos (1U) +#define PWR_IORETENRA_EN1_Msk (0x1UL << PWR_IORETENRA_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRA_EN1 PWR_IORETENRA_EN1_Msk /*!< Standby GPIO retention enable for PA1 */ +#define PWR_IORETENRA_EN2_Pos (2U) +#define PWR_IORETENRA_EN2_Msk (0x1UL << PWR_IORETENRA_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRA_EN2 PWR_IORETENRA_EN2_Msk /*!< Standby GPIO retention enable for PA2 */ +#define PWR_IORETENRA_EN3_Pos (3U) +#define PWR_IORETENRA_EN3_Msk (0x1UL << PWR_IORETENRA_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRA_EN3 PWR_IORETENRA_EN3_Msk /*!< Standby GPIO retention enable for PA3 */ +#define PWR_IORETENRA_EN4_Pos (4U) +#define PWR_IORETENRA_EN4_Msk (0x1UL << PWR_IORETENRA_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRA_EN4 PWR_IORETENRA_EN4_Msk /*!< Standby GPIO retention enable for PA4 */ +#define PWR_IORETENRA_EN5_Pos (5U) +#define PWR_IORETENRA_EN5_Msk (0x1UL << PWR_IORETENRA_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRA_EN5 PWR_IORETENRA_EN5_Msk /*!< Standby GPIO retention enable for PA5 */ +#define PWR_IORETENRA_EN6_Pos (6U) +#define PWR_IORETENRA_EN6_Msk (0x1UL << PWR_IORETENRA_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRA_EN6 PWR_IORETENRA_EN6_Msk /*!< Standby GPIO retention enable for PA6 */ +#define PWR_IORETENRA_EN7_Pos (7U) +#define PWR_IORETENRA_EN7_Msk (0x1UL << PWR_IORETENRA_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRA_EN7 PWR_IORETENRA_EN7_Msk /*!< Standby GPIO retention enable for PA7 */ +#define PWR_IORETENRA_EN8_Pos (8U) +#define PWR_IORETENRA_EN8_Msk (0x1UL << PWR_IORETENRA_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRA_EN8 PWR_IORETENRA_EN8_Msk /*!< Standby GPIO retention enable for PA8 */ +#define PWR_IORETENRA_EN9_Pos (9U) +#define PWR_IORETENRA_EN9_Msk (0x1UL << PWR_IORETENRA_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRA_EN9 PWR_IORETENRA_EN9_Msk /*!< Standby GPIO retention enable for PA9 */ +#define PWR_IORETENRA_EN10_Pos (10U) +#define PWR_IORETENRA_EN10_Msk (0x1UL << PWR_IORETENRA_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRA_EN10 PWR_IORETENRA_EN10_Msk /*!< Standby GPIO retention enable for PA10 */ +#define PWR_IORETENRA_EN11_Pos (11U) +#define PWR_IORETENRA_EN11_Msk (0x1UL << PWR_IORETENRA_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRA_EN11 PWR_IORETENRA_EN11_Msk /*!< Standby GPIO retention enable for PA11 */ +#define PWR_IORETENRA_EN12_Pos (12U) +#define PWR_IORETENRA_EN12_Msk (0x1UL << PWR_IORETENRA_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRA_EN12 PWR_IORETENRA_EN12_Msk /*!< Standby GPIO retention enable for PA12 */ +#define PWR_IORETENRA_EN13_Pos (13U) +#define PWR_IORETENRA_EN13_Msk (0x1UL << PWR_IORETENRA_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRA_EN13 PWR_IORETENRA_EN13_Msk /*!< Standby GPIO retention enable for PA13 */ +#define PWR_IORETENRA_EN14_Pos (14U) +#define PWR_IORETENRA_EN14_Msk (0x1UL << PWR_IORETENRA_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRA_EN14 PWR_IORETENRA_EN14_Msk /*!< Standby GPIO retention enable for PA14 */ +#define PWR_IORETENRA_EN15_Pos (15U) +#define PWR_IORETENRA_EN15_Msk (0x1UL << PWR_IORETENRA_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRA_EN15 PWR_IORETENRA_EN15_Msk /*!< Standby GPIO retention enable for PA15 */ + +/******************** Bit definition for PWR_IORETRA register *****************/ +#define PWR_IORETRA_RET0_Pos (0U) +#define PWR_IORETRA_RET0_Msk (0x1UL << PWR_IORETRA_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRA_RET0 PWR_IORETRA_RET0_Msk /*!< Standby GPIO retention status for PA0 */ +#define PWR_IORETRA_RET1_Pos (1U) +#define PWR_IORETRA_RET1_Msk (0x1UL << PWR_IORETRA_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRA_RET1 PWR_IORETRA_RET1_Msk /*!< Standby GPIO retention status for PA1 */ +#define PWR_IORETRA_RET2_Pos (2U) +#define PWR_IORETRA_RET2_Msk (0x1UL << PWR_IORETRA_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRA_RET2 PWR_IORETRA_RET2_Msk /*!< Standby GPIO retention status for PA2 */ +#define PWR_IORETRA_RET3_Pos (3U) +#define PWR_IORETRA_RET3_Msk (0x1UL << PWR_IORETRA_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRA_RET3 PWR_IORETRA_RET3_Msk /*!< Standby GPIO retention status for PA3 */ +#define PWR_IORETRA_RET4_Pos (4U) +#define PWR_IORETRA_RET4_Msk (0x1UL << PWR_IORETRA_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRA_RET4 PWR_IORETRA_RET4_Msk /*!< Standby GPIO retention status for PA4 */ +#define PWR_IORETRA_RET5_Pos (5U) +#define PWR_IORETRA_RET5_Msk (0x1UL << PWR_IORETRA_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRA_RET5 PWR_IORETRA_RET5_Msk /*!< Standby GPIO retention status for PA5 */ +#define PWR_IORETRA_RET6_Pos (6U) +#define PWR_IORETRA_RET6_Msk (0x1UL << PWR_IORETRA_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRA_RET6 PWR_IORETRA_RET6_Msk /*!< Standby GPIO retention status for PA6 */ +#define PWR_IORETRA_RET7_Pos (7U) +#define PWR_IORETRA_RET7_Msk (0x1UL << PWR_IORETRA_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRA_RET7 PWR_IORETRA_RET7_Msk /*!< Standby GPIO retention status for PA7 */ +#define PWR_IORETRA_RET8_Pos (8U) +#define PWR_IORETRA_RET8_Msk (0x1UL << PWR_IORETRA_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRA_RET8 PWR_IORETRA_RET8_Msk /*!< Standby GPIO retention status for PA8 */ +#define PWR_IORETRA_RET9_Pos (9U) +#define PWR_IORETRA_RET9_Msk (0x1UL << PWR_IORETRA_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRA_RET9 PWR_IORETRA_RET9_Msk /*!< Standby GPIO retention status for PA9 */ +#define PWR_IORETRA_RET10_Pos (10U) +#define PWR_IORETRA_RET10_Msk (0x1UL << PWR_IORETRA_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRA_RET10 PWR_IORETRA_RET10_Msk /*!< Standby GPIO retention status for PA10 */ +#define PWR_IORETRA_RET11_Pos (11U) +#define PWR_IORETRA_RET11_Msk (0x1UL << PWR_IORETRA_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRA_RET11 PWR_IORETRA_RET11_Msk /*!< Standby GPIO retention status for PA11 */ +#define PWR_IORETRA_RET12_Pos (12U) +#define PWR_IORETRA_RET12_Msk (0x1UL << PWR_IORETRA_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRA_RET12 PWR_IORETRA_RET12_Msk /*!< Standby GPIO retention status for PA12 */ +#define PWR_IORETRA_RET13_Pos (13U) +#define PWR_IORETRA_RET13_Msk (0x1UL << PWR_IORETRA_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRA_RET13 PWR_IORETRA_RET13_Msk /*!< Standby GPIO retention status for PA13 */ +#define PWR_IORETRA_RET14_Pos (14U) +#define PWR_IORETRA_RET14_Msk (0x1UL << PWR_IORETRA_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRA_RET14 PWR_IORETRA_RET14_Msk /*!< Standby GPIO retention status for PA14 */ +#define PWR_IORETRA_RET15_Pos (15U) +#define PWR_IORETRA_RET15_Msk (0x1UL << PWR_IORETRA_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRA_RET15 PWR_IORETRA_RET15_Msk /*!< Standby GPIO retention status for PA15 */ + +/******************** Bit definition for PWR_IORETENRB register *****************/ +#define PWR_IORETENRB_EN0_Pos (0U) +#define PWR_IORETENRB_EN0_Msk (0x1UL << PWR_IORETENRB_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRB_EN0 PWR_IORETENRB_EN0_Msk /*!< Standby GPIO retention enable for PB0 */ +#define PWR_IORETENRB_EN1_Pos (1U) +#define PWR_IORETENRB_EN1_Msk (0x1UL << PWR_IORETENRB_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRB_EN1 PWR_IORETENRB_EN1_Msk /*!< Standby GPIO retention enable for PB1 */ +#define PWR_IORETENRB_EN2_Pos (2U) +#define PWR_IORETENRB_EN2_Msk (0x1UL << PWR_IORETENRB_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRB_EN2 PWR_IORETENRB_EN2_Msk /*!< Standby GPIO retention enable for PB2 */ +#define PWR_IORETENRB_EN3_Pos (3U) +#define PWR_IORETENRB_EN3_Msk (0x1UL << PWR_IORETENRB_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRB_EN3 PWR_IORETENRB_EN3_Msk /*!< Standby GPIO retention enable for PB3 */ +#define PWR_IORETENRB_EN4_Pos (4U) +#define PWR_IORETENRB_EN4_Msk (0x1UL << PWR_IORETENRB_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRB_EN4 PWR_IORETENRB_EN4_Msk /*!< Standby GPIO retention enable for PB4 */ +#define PWR_IORETENRB_EN5_Pos (5U) +#define PWR_IORETENRB_EN5_Msk (0x1UL << PWR_IORETENRB_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRB_EN5 PWR_IORETENRB_EN5_Msk /*!< Standby GPIO retention enable for PB5 */ +#define PWR_IORETENRB_EN6_Pos (6U) +#define PWR_IORETENRB_EN6_Msk (0x1UL << PWR_IORETENRB_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRB_EN6 PWR_IORETENRB_EN6_Msk /*!< Standby GPIO retention enable for PB6 */ +#define PWR_IORETENRB_EN7_Pos (7U) +#define PWR_IORETENRB_EN7_Msk (0x1UL << PWR_IORETENRB_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRB_EN7 PWR_IORETENRB_EN7_Msk /*!< Standby GPIO retention enable for PB7 */ +#define PWR_IORETENRB_EN8_Pos (8U) +#define PWR_IORETENRB_EN8_Msk (0x1UL << PWR_IORETENRB_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRB_EN8 PWR_IORETENRB_EN8_Msk /*!< Standby GPIO retention enable for PB8 */ +#define PWR_IORETENRB_EN9_Pos (9U) +#define PWR_IORETENRB_EN9_Msk (0x1UL << PWR_IORETENRB_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRB_EN9 PWR_IORETENRB_EN9_Msk /*!< Standby GPIO retention enable for PB9 */ +#define PWR_IORETENRB_EN10_Pos (10U) +#define PWR_IORETENRB_EN10_Msk (0x1UL << PWR_IORETENRB_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRB_EN10 PWR_IORETENRB_EN10_Msk /*!< Standby GPIO retention enable for PB10 */ +#define PWR_IORETENRB_EN11_Pos (11U) +#define PWR_IORETENRB_EN11_Msk (0x1UL << PWR_IORETENRB_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRB_EN11 PWR_IORETENRB_EN11_Msk /*!< Standby GPIO retention enable for PB11 */ +#define PWR_IORETENRB_EN12_Pos (12U) +#define PWR_IORETENRB_EN12_Msk (0x1UL << PWR_IORETENRB_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRB_EN12 PWR_IORETENRB_EN12_Msk /*!< Standby GPIO retention enable for PB12 */ +#define PWR_IORETENRB_EN13_Pos (13U) +#define PWR_IORETENRB_EN13_Msk (0x1UL << PWR_IORETENRB_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRB_EN13 PWR_IORETENRB_EN13_Msk /*!< Standby GPIO retention enable for PB13 */ +#define PWR_IORETENRB_EN14_Pos (14U) +#define PWR_IORETENRB_EN14_Msk (0x1UL << PWR_IORETENRB_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRB_EN14 PWR_IORETENRB_EN14_Msk /*!< Standby GPIO retention enable for PB14 */ +#define PWR_IORETENRB_EN15_Pos (15U) +#define PWR_IORETENRB_EN15_Msk (0x1UL << PWR_IORETENRB_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRB_EN15 PWR_IORETENRB_EN15_Msk /*!< Standby GPIO retention enable for PB15 */ + +/******************** Bit definition for PWR_IORETRB register *****************/ +#define PWR_IORETRB_RET0_Pos (0U) +#define PWR_IORETRB_RET0_Msk (0x1UL << PWR_IORETRB_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRB_RET0 PWR_IORETRB_RET0_Msk /*!< Standby GPIO retention status for PB0 */ +#define PWR_IORETRB_RET1_Pos (1U) +#define PWR_IORETRB_RET1_Msk (0x1UL << PWR_IORETRB_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRB_RET1 PWR_IORETRB_RET1_Msk /*!< Standby GPIO retention status for PB1 */ +#define PWR_IORETRB_RET2_Pos (2U) +#define PWR_IORETRB_RET2_Msk (0x1UL << PWR_IORETRB_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRB_RET2 PWR_IORETRB_RET2_Msk /*!< Standby GPIO retention status for PB2 */ +#define PWR_IORETRB_RET3_Pos (3U) +#define PWR_IORETRB_RET3_Msk (0x1UL << PWR_IORETRB_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRB_RET3 PWR_IORETRB_RET3_Msk /*!< Standby GPIO retention status for PB3 */ +#define PWR_IORETRB_RET4_Pos (4U) +#define PWR_IORETRB_RET4_Msk (0x1UL << PWR_IORETRB_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRB_RET4 PWR_IORETRB_RET4_Msk /*!< Standby GPIO retention status for PB4 */ +#define PWR_IORETRB_RET5_Pos (5U) +#define PWR_IORETRB_RET5_Msk (0x1UL << PWR_IORETRB_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRB_RET5 PWR_IORETRB_RET5_Msk /*!< Standby GPIO retention status for PB5 */ +#define PWR_IORETRB_RET6_Pos (6U) +#define PWR_IORETRB_RET6_Msk (0x1UL << PWR_IORETRB_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRB_RET6 PWR_IORETRB_RET6_Msk /*!< Standby GPIO retention status for PB6 */ +#define PWR_IORETRB_RET7_Pos (7U) +#define PWR_IORETRB_RET7_Msk (0x1UL << PWR_IORETRB_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRB_RET7 PWR_IORETRB_RET7_Msk /*!< Standby GPIO retention status for PB7 */ +#define PWR_IORETRB_RET8_Pos (8U) +#define PWR_IORETRB_RET8_Msk (0x1UL << PWR_IORETRB_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRB_RET8 PWR_IORETRB_RET8_Msk /*!< Standby GPIO retention status for PB8 */ +#define PWR_IORETRB_RET9_Pos (9U) +#define PWR_IORETRB_RET9_Msk (0x1UL << PWR_IORETRB_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRB_RET9 PWR_IORETRB_RET9_Msk /*!< Standby GPIO retention status for PB9 */ +#define PWR_IORETRB_RET10_Pos (10U) +#define PWR_IORETRB_RET10_Msk (0x1UL << PWR_IORETRB_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRB_RET10 PWR_IORETRB_RET10_Msk /*!< Standby GPIO retention status for PB10 */ +#define PWR_IORETRB_RET11_Pos (11U) +#define PWR_IORETRB_RET11_Msk (0x1UL << PWR_IORETRB_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRB_RET11 PWR_IORETRB_RET11_Msk /*!< Standby GPIO retention status for PB11 */ +#define PWR_IORETRB_RET12_Pos (12U) +#define PWR_IORETRB_RET12_Msk (0x1UL << PWR_IORETRB_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRB_RET12 PWR_IORETRB_RET12_Msk /*!< Standby GPIO retention status for PB12 */ +#define PWR_IORETRB_RET13_Pos (13U) +#define PWR_IORETRB_RET13_Msk (0x1UL << PWR_IORETRB_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRB_RET13 PWR_IORETRB_RET13_Msk /*!< Standby GPIO retention status for PB13 */ +#define PWR_IORETRB_RET14_Pos (14U) +#define PWR_IORETRB_RET14_Msk (0x1UL << PWR_IORETRB_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRB_RET14 PWR_IORETRB_RET14_Msk /*!< Standby GPIO retention status for PB14 */ +#define PWR_IORETRB_RET15_Pos (15U) +#define PWR_IORETRB_RET15_Msk (0x1UL << PWR_IORETRB_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRB_RET15 PWR_IORETRB_RET15_Msk /*!< Standby GPIO retention status for PB15 */ + +/******************** Bit definition for PWR_IORETENRC register *****************/ +#define PWR_IORETENRC_EN13_Pos (13U) +#define PWR_IORETENRC_EN13_Msk (0x1UL << PWR_IORETENRC_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRC_EN13 PWR_IORETENRC_EN13_Msk /*!< Standby GPIO retention enable for PC13 */ +#define PWR_IORETENRC_EN14_Pos (14U) +#define PWR_IORETENRC_EN14_Msk (0x1UL << PWR_IORETENRC_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRC_EN14 PWR_IORETENRC_EN14_Msk /*!< Standby GPIO retention enable for PC14 */ +#define PWR_IORETENRC_EN15_Pos (15U) +#define PWR_IORETENRC_EN15_Msk (0x1UL << PWR_IORETENRC_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRC_EN15 PWR_IORETENRC_EN15_Msk /*!< Standby GPIO retention enable for PC15 */ + +/******************** Bit definition for PWR_IORETRC register *****************/ +#define PWR_IORETRC_RET13_Pos (13U) +#define PWR_IORETRC_RET13_Msk (0x1UL << PWR_IORETRC_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRC_RET13 PWR_IORETRC_RET13_Msk /*!< Standby GPIO retention status for PC13 */ +#define PWR_IORETRC_RET14_Pos (14U) +#define PWR_IORETRC_RET14_Msk (0x1UL << PWR_IORETRC_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRC_RET14 PWR_IORETRC_RET14_Msk /*!< Standby GPIO retention status for PC14 */ +#define PWR_IORETRC_RET15_Pos (15U) +#define PWR_IORETRC_RET15_Msk (0x1UL << PWR_IORETRC_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRC_RET15 PWR_IORETRC_RET15_Msk /*!< Standby GPIO retention status for PC15 */ + +/******************** Bit definition for PWR_IORETENRH register *****************/ +#define PWR_IORETENRH_EN3_Pos (3U) +#define PWR_IORETENRH_EN3_Msk (0x1UL << PWR_IORETENRH_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRH_EN3 PWR_IORETENRH_EN3_Msk /*!< Standby GPIO retention enable for PH3 */ + +/******************** Bit definition for PWR_IORETRH register *****************/ +#define PWR_IORETRH_RET3_Pos (3U) +#define PWR_IORETRH_RET3_Msk (0x1UL << PWR_IORETRH_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRH_RET3 PWR_IORETRH_RET3_Msk /*!< Standby GPIO retention status for PH3 */ + +/******************** Bit definition for PWR_RADIOSCR register *****************/ +#define PWR_RADIOSCR_MODE_Pos (0U) +#define PWR_RADIOSCR_MODE_Msk (0x3UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000003 */ +#define PWR_RADIOSCR_MODE PWR_RADIOSCR_MODE_Msk /*!< 2.4 GHz RADIO operating mode */ +#define PWR_RADIOSCR_MODE_0 (0x1UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000001 */ +#define PWR_RADIOSCR_MODE_1 (0x2UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000002 */ +#define PWR_RADIOSCR_PHYMODE_Pos (2U) +#define PWR_RADIOSCR_PHYMODE_Msk (0x1UL << PWR_RADIOSCR_PHYMODE_Pos) /*!< 0x00000004 */ +#define PWR_RADIOSCR_PHYMODE PWR_RADIOSCR_PHYMODE_Msk /*!< 2.4 GHz RADIO PHY operating mode */ +#define PWR_RADIOSCR_ENCMODE_Pos (3U) +#define PWR_RADIOSCR_ENCMODE_Msk (0x1UL << PWR_RADIOSCR_ENCMODE_Pos) /*!< 0x00000008 */ +#define PWR_RADIOSCR_ENCMODE PWR_RADIOSCR_ENCMODE_Msk /*!< 2.4 GHz RADIO encryption function operating mode */ +#define PWR_RADIOSCR_RFVDDHPA_Pos (8U) +#define PWR_RADIOSCR_RFVDDHPA_Msk (0x1FUL << PWR_RADIOSCR_RFVDDHPA_Pos) /*!< 0x00001F00 */ +#define PWR_RADIOSCR_RFVDDHPA PWR_RADIOSCR_RFVDDHPA_Msk /*!< 2.4 GHz RADIO VDDHPA control word */ +#define PWR_RADIOSCR_REGPARDYV11_Pos (14U) +#define PWR_RADIOSCR_REGPARDYV11_Msk (0x1UL << PWR_RADIOSCR_REGPARDYV11_Pos) /*!< 0x00004000 */ +#define PWR_RADIOSCR_REGPARDYV11 PWR_RADIOSCR_REGPARDYV11_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Pos (15U) +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Msk (0x1UL << PWR_RADIOSCR_REGPARDYVDDRFPA_Pos) /*!< 0x00008000 */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA PWR_RADIOSCR_REGPARDYVDDRFPA_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ +#define PWR_RADIOSCR_REGPASEL_Pos (23U) +#define PWR_RADIOSCR_REGPASEL_Msk (0x1UL << PWR_RADIOSCR_REGPASEL_Pos) /*!< 0x00800000 */ +#define PWR_RADIOSCR_REGPASEL PWR_RADIOSCR_REGPASEL_Msk /*!< Regulator REG_VDDHPA input supply selection */ +#define PWR_RADIOSCR_REGPABYPEN_Pos (24U) +#define PWR_RADIOSCR_REGPABYPEN_Msk (0x1UL << PWR_RADIOSCR_REGPABYPEN_Pos) /*!< 0x01000000 */ +#define PWR_RADIOSCR_REGPABYPEN PWR_RADIOSCR_REGPABYPEN_Msk /*!< Regulator REG_VDDHPA bypass enable.*/ + + +/******************************************************************************/ +/* */ +/* SRAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_MxCR register ******************/ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_WSC_Pos (16U) +#define RAMCFG_CR_WSC_Msk (0x7UL << RAMCFG_CR_WSC_Pos) /*!< 0x00070000 */ +#define RAMCFG_CR_WSC RAMCFG_CR_WSC_Msk /*!< WSC[18:16] Wait State Configuration field */ +#define RAMCFG_CR_WSC_0 (0x1UL << RAMCFG_CR_WSC_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_WSC_1 (0x2UL << RAMCFG_CR_WSC_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_WSC_2 (0x4UL << RAMCFG_CR_WSC_Pos) /*!< 0x00040000 */ + +/******************* Bit definition for RAMCFG_MxISR register ******************/ +#define RAMCFG_ISR_PED_Pos (1U) +#define RAMCFG_ISR_PED_Msk (0x1UL << RAMCFG_ISR_PED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_PED RAMCFG_ISR_PED_Msk /*!< Parity error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/***************** Bit definition for RAMCFG_MxERKEYR register ***************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/******************* Bit definition for RAMCFG_MxIER register ******************/ +#define RAMCFG_IER_PEIE_Pos (1U) +#define RAMCFG_IER_PEIE_Msk (0x1UL << RAMCFG_IER_PEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_PEIE RAMCFG_IER_PEIE_Msk /*!< Parity error interrupt enable */ +#define RAMCFG_IER_PENMI_Pos (3U) +#define RAMCFG_IER_PENMI_Msk (0x1UL << RAMCFG_IER_PENMI_Pos) /*!< 0x00000004 */ +#define RAMCFG_IER_PENMI RAMCFG_IER_PENMI_Msk /*!< Parity error NMI */ + +/******************* Bit definition for RAMCFG_MxPEAR register ******************/ +#define RAMCFG_PEAR_PEA_Pos (0U) +#define RAMCFG_PEAR_PEA_Msk (0xFFFFUL << RAMCFG_PEAR_PEA_Pos) /*!< 0x0000FFFF */ +#define RAMCFG_PEAR_PEA RAMCFG_PEAR_PEA_Msk /*!< Parity error SRAM word aligned address offset */ +#define RAMCFG_PEAR_ID_Pos (24U) +#define RAMCFG_PEAR_ID_Msk (0xFUL << RAMCFG_PEAR_ID_Pos) /*!< 0x0F000000 */ +#define RAMCFG_PEAR_ID RAMCFG_PEAR_ID_Msk /*!< Parity error AHB bus master ID */ +#define RAMCFG_PEAR_BYTE_Pos (28U) +#define RAMCFG_PEAR_BYTE_Msk (0xFUL << RAMCFG_PEAR_BYTE_Pos) /*!< 0xF0000000 */ +#define RAMCFG_PEAR_BYTE RAMCFG_PEAR_BYTE_Msk /*!< Byte parity error flag */ + +/******************* Bit definition for RAMCFG_MxICR register *****************/ +#define RAMCFG_ICR_CPED_Pos (1U) +#define RAMCFG_ICR_CPED_Msk (0x1UL << RAMCFG_ICR_CPED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CPED RAMCFG_ICR_CPED_Msk /*!< Clear parity error detect bit */ + +/****************** Bit definition for RAMCFG_MxWPR1 register *****************/ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/****************** Bit definition for RAMCFG_MxWPR2 register ****************/ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +#define RCC_LSI2_SUPPORT + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (8U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ +#define RCC_CR_HSIKERON_Pos (9U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ +#define RCC_CR_HSECSSON_Pos (19U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< External High Speed oscillator (HSE) clock security system enable */ +#define RCC_CR_HSEPRE_Pos (20U) +#define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< External High Speed oscillator (HSE) clock for sysclk prescaler */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */ + +/******************** Bit definition for RCC_ICSCR3 register ***************/ +#define RCC_ICSCR3_HSICAL_Pos (0U) +#define RCC_ICSCR3_HSICAL_Msk (0xFFFUL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_ICSCR3_HSICAL RCC_ICSCR3_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_ICSCR3_HSICAL_0 (0x01UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_ICSCR3_HSICAL_1 (0x002UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_ICSCR3_HSICAL_2 (0x004UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_ICSCR3_HSICAL_3 (0x008UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_ICSCR3_HSICAL_4 (0x010UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_ICSCR3_HSICAL_5 (0x020UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_ICSCR3_HSICAL_6 (0x040UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_ICSCR3_HSICAL_7 (0x080UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_ICSCR3_HSICAL_8 (0x100UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_ICSCR3_HSICAL_9 (0x200UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_ICSCR3_HSICAL_10 (0x400UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_ICSCR3_HSICAL_11 (0x800UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000800 */ +#define RCC_ICSCR3_HSITRIM_Pos (16U) +#define RCC_ICSCR3_HSITRIM_Msk (0x1FUL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_ICSCR3_HSITRIM RCC_ICSCR3_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR3_HSITRIM_0 (0x01UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00010000 */ +#define RCC_ICSCR3_HSITRIM_1 (0x02UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00020000 */ +#define RCC_ICSCR3_HSITRIM_2 (0x04UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00040000 */ +#define RCC_ICSCR3_HSITRIM_3 (0x08UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00080000 */ +#define RCC_ICSCR3_HSITRIM_4 (0x10UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00100000 */ + +/******************** Bit definition for RCC_CFGR1 register *****************/ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (2U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_MCOSEL_Pos (24U) +#define RCC_CFGR1_MCOSEL_Msk (0xFUL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR1_MCOSEL RCC_CFGR1_MCOSEL_Msk /*!< MCOSEL[3:0] bits (Clock output selection) */ +#define RCC_CFGR1_MCOSEL_0 (0x1UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCOSEL_1 (0x2UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCOSEL_2 (0x4UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCOSEL_3 (0x8UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCOPRE_Pos (28U) +#define RCC_CFGR1_MCOPRE_Msk (0x7UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR1_MCOPRE RCC_CFGR1_MCOPRE_Msk /*!< MCO[220] (Prescaler) */ +#define RCC_CFGR1_MCOPRE_0 (0x1UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCOPRE_1 (0x2UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCOPRE_2 (0x4UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CFGR2 register ******************/ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< HPRE[2:0] bits (AHB prescaler) */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< PPRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< PPRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_CFGR3 register ******************/ +#define RCC_CFGR3_PPRE7_Pos (4U) +#define RCC_CFGR3_PPRE7_Msk (0x7UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000070 */ +#define RCC_CFGR3_PPRE7 RCC_CFGR3_PPRE7_Msk /*!< PPRE7[2:0] bits (APB7 prescaler) */ +#define RCC_CFGR3_PPRE7_0 (0x1UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000010 */ +#define RCC_CFGR3_PPRE7_1 (0x2UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000020 */ +#define RCC_CFGR3_PPRE7_2 (0x4UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for RCC_PLL1CFGR register ***************/ +#define RCC_PLL1CFGR_PLL1SRC_Pos (0U) +#define RCC_PLL1CFGR_PLL1SRC_Msk (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000003 */ +#define RCC_PLL1CFGR_PLL1SRC RCC_PLL1CFGR_PLL1SRC_Msk +#define RCC_PLL1CFGR_PLL1SRC_0 (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR_PLL1SRC_1 (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR_PLL1RGE_Pos (2U) +#define RCC_PLL1CFGR_PLL1RGE_Msk (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x0000000C */ +#define RCC_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_Msk +#define RCC_PLL1CFGR_PLL1RGE_0 (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR_PLL1RGE_1 (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR_PLL1FRACEN_Pos (4U) +#define RCC_PLL1CFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN_Msk +#define RCC_PLL1CFGR_PLL1M_Pos (8U) +#define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700 */ +#define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk +#define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR_PLL1PEN_Pos (16U) +#define RCC_PLL1CFGR_PLL1PEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR_PLL1PEN RCC_PLL1CFGR_PLL1PEN_Msk +#define RCC_PLL1CFGR_PLL1QEN_Pos (17U) +#define RCC_PLL1CFGR_PLL1QEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR_PLL1QEN RCC_PLL1CFGR_PLL1QEN_Msk +#define RCC_PLL1CFGR_PLL1REN_Pos (18U) +#define RCC_PLL1CFGR_PLL1REN_Msk (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRE_Pos (20U) +#define RCC_PLL1CFGR_PLL1RCLKPRE_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRE_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRE RCC_PLL1CFGR_PLL1RCLKPRE_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos (21U) +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos (22U) +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRERDY RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk + +/******************** Bit definition for RCC_PLL1DIVR register ***************/ +#define RCC_PLL1DIVR_PLL1N_Pos (0U) +#define RCC_PLL1DIVR_PLL1N_Msk (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N_Msk +#define RCC_PLL1DIVR_PLL1N_0 (0x001UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR_PLL1N_1 (0x002UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR_PLL1N_2 (0x004UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR_PLL1N_3 (0x008UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR_PLL1N_4 (0x010UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR_PLL1N_5 (0x020UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR_PLL1N_6 (0x040UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR_PLL1N_7 (0x080UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR_PLL1N_8 (0x100UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000100 */ +#define RCC_PLL1DIVR_PLL1P_Pos (9U) +#define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P_Msk +#define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000 */ +#define RCC_PLL1DIVR_PLL1Q_Pos (16U) +#define RCC_PLL1DIVR_PLL1Q_Msk (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR_PLL1Q RCC_PLL1DIVR_PLL1Q_Msk +#define RCC_PLL1DIVR_PLL1Q_0 (0x01UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR_PLL1Q_1 (0x02UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR_PLL1Q_2 (0x04UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR_PLL1Q_3 (0x08UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR_PLL1Q_4 (0x10UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR_PLL1Q_5 (0x20UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00200020 */ +#define RCC_PLL1DIVR_PLL1Q_6 (0x40UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00400000 */ +#define RCC_PLL1DIVR_PLL1R_Pos (24U) +#define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R_Msk +#define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register ***************/ +#define RCC_PLL1FRACR_PLL1FRACN_Pos (3U) +#define RCC_PLL1FRACR_PLL1FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_PLL1FRACN RCC_PLL1FRACR_PLL1FRACN_Msk + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSI1RDYIE_Pos (0U) +#define RCC_CIER_LSI1RDYIE_Msk (0x1UL << RCC_CIER_LSI1RDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_LSI2RDYIE_Pos (16U) +#define RCC_CIER_LSI2RDYIE_Msk (0x1UL << RCC_CIER_LSI2RDYIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE_Msk + +/******************** Bit definition for RCC_CIFR register ****************/ +#define RCC_CIFR_LSI1RDYF_Pos (0U) +#define RCC_CIFR_LSI1RDYF_Msk (0x1UL << RCC_CIFR_LSI1RDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk +#define RCC_CIFR_LSI2RDYF_Pos (16U) +#define RCC_CIFR_LSI2RDYF_Msk (0x1UL << RCC_CIFR_LSI2RDYF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF_Msk + +/******************** Bit definition for RCC_CICR register ****************/ +#define RCC_CICR_LSI1RDYC_Pos (0U) +#define RCC_CICR_LSI1RDYC_Msk (0x1UL << RCC_CICR_LSI1RDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk +#define RCC_CICR_LSI2RDYC_Pos (16U) +#define RCC_CICR_LSI2RDYC_Msk (0x1UL << RCC_CICR_LSI2RDYC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk +#define RCC_AHB1RSTR_TSCRST_Pos (16U) +#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk +#define RCC_AHB2RSTR_AESRST_Pos (16U) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk +#define RCC_AHB2RSTR_SAESRST_Pos (19U) +#define RCC_AHB2RSTR_SAESRST_Msk (0x1UL << RCC_AHB2RSTR_SAESRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB2RSTR_SAESRST RCC_AHB2RSTR_SAESRST_Msk +#define RCC_AHB2RSTR_HSEMRST_Pos (20U) +#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk +#define RCC_AHB2RSTR_PKARST_Pos (21U) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00200000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_ADC4RST_Pos (5U) +#define RCC_AHB4RSTR_ADC4RST_Msk (0x1UL << RCC_AHB4RSTR_ADC4RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_ADC4RST RCC_AHB4RSTR_ADC4RST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_RADIORST_Pos (0U) +#define RCC_AHB5RSTR_RADIORST_Msk (0x1UL << RCC_AHB5RSTR_RADIORST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_RADIORST RCC_AHB5RSTR_RADIORST_Msk +#define RCC_AHB5RSTR_PTACONVRST_Pos (1U) +#define RCC_AHB5RSTR_PTACONVRST_Msk (0x1UL << RCC_AHB5RSTR_PTACONVRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_PTACONVRST RCC_AHB5RSTR_PTACONVRST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register **************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_I2C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register **************/ +#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) +#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (21U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk + +/******************** Bit definition for RCC_APB7RSTR register **************/ +#define RCC_APB7RSTR_SYSCFGRST_Pos (1U) +#define RCC_APB7RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB7RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */ +#define RCC_APB7RSTR_SYSCFGRST RCC_APB7RSTR_SYSCFGRST_Msk +#define RCC_APB7RSTR_SPI3RST_Pos (5U) +#define RCC_APB7RSTR_SPI3RST_Msk (0x1UL << RCC_APB7RSTR_SPI3RST_Pos) /*!< 0x00000020 */ +#define RCC_APB7RSTR_SPI3RST RCC_APB7RSTR_SPI3RST_Msk +#define RCC_APB7RSTR_LPUART1RST_Pos (6U) +#define RCC_APB7RSTR_LPUART1RST_Msk (0x1UL << RCC_APB7RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB7RSTR_LPUART1RST RCC_APB7RSTR_LPUART1RST_Msk +#define RCC_APB7RSTR_I2C3RST_Pos (7U) +#define RCC_APB7RSTR_I2C3RST_Msk (0x1UL << RCC_APB7RSTR_I2C3RST_Pos) /*!< 0x00000080 */ +#define RCC_APB7RSTR_I2C3RST RCC_APB7RSTR_I2C3RST_Msk +#define RCC_APB7RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB7RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB7RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB7RSTR_LPTIM1RST RCC_APB7RSTR_LPTIM1RST_Msk +#define RCC_APB7RSTR_COMPRST_Pos (15U) +#define RCC_APB7RSTR_COMPRST_Msk (0x1UL << RCC_APB7RSTR_COMPRST_Pos) /*!< 0x00008000 */ +#define RCC_APB7RSTR_COMPRST RCC_APB7RSTR_COMPRST_Msk + +/******************** Bit definition for RCC_AHB1ENR register **************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk +#define RCC_AHB1ENR_TSCEN_Pos (16U) +#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk +#define RCC_AHB1ENR_GTZC1EN_Pos (24U) +#define RCC_AHB1ENR_GTZC1EN_Msk (0x1UL << RCC_AHB1ENR_GTZC1EN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1ENR_GTZC1EN RCC_AHB1ENR_GTZC1EN_Msk +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register **************/ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk +#define RCC_AHB2ENR_AESEN_Pos (16U) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk +#define RCC_AHB2ENR_SAESEN_Pos (19U) +#define RCC_AHB2ENR_SAESEN_Msk (0x1UL << RCC_AHB2ENR_SAESEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2ENR_SAESEN RCC_AHB2ENR_SAESEN_Msk +#define RCC_AHB2ENR_HSEMEN_Pos (20U) +#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk +#define RCC_AHB2ENR_PKAEN_Pos (21U) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB4ENR register **************/ +#define RCC_AHB4ENR_PWREN_Pos (2U) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk +#define RCC_AHB4ENR_ADC4EN_Pos (5U) +#define RCC_AHB4ENR_ADC4EN_Msk (0x1UL << RCC_AHB4ENR_ADC4EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_ADC4EN RCC_AHB4ENR_ADC4EN_Msk + +/******************** Bit definition for RCC_AHB5ENR register **************/ +#define RCC_AHB5ENR_RADIOEN_Pos (0U) +#define RCC_AHB5ENR_RADIOEN_Msk (0x1UL << RCC_AHB5ENR_RADIOEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_RADIOEN RCC_AHB5ENR_RADIOEN_Msk +#define RCC_AHB5ENR_PTACONVEN_Pos (1U) +#define RCC_AHB5ENR_PTACONVEN_Msk (0x1UL << RCC_AHB5ENR_PTACONVEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_PTACONVEN RCC_AHB5ENR_PTACONVEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_I2C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_LPTIM2EN_Pos (5U) +#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk + +/******************** Bit definition for RCC_APB2ENR register **************/ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (21U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk + +/******************** Bit definition for RCC_APB7ENR register **************/ +#define RCC_APB7ENR_SYSCFGEN_Pos (1U) +#define RCC_APB7ENR_SYSCFGEN_Msk (0x1UL << RCC_APB7ENR_SYSCFGEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7ENR_SYSCFGEN RCC_APB7ENR_SYSCFGEN_Msk +#define RCC_APB7ENR_SPI3EN_Pos (5U) +#define RCC_APB7ENR_SPI3EN_Msk (0x1UL << RCC_APB7ENR_SPI3EN_Pos) /*!< 0x00000020 */ +#define RCC_APB7ENR_SPI3EN RCC_APB7ENR_SPI3EN_Msk +#define RCC_APB7ENR_LPUART1EN_Pos (6U) +#define RCC_APB7ENR_LPUART1EN_Msk (0x1UL << RCC_APB7ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB7ENR_LPUART1EN RCC_APB7ENR_LPUART1EN_Msk +#define RCC_APB7ENR_I2C3EN_Pos (7U) +#define RCC_APB7ENR_I2C3EN_Msk (0x1UL << RCC_APB7ENR_I2C3EN_Pos) /*!< 0x00000080 */ +#define RCC_APB7ENR_I2C3EN RCC_APB7ENR_I2C3EN_Msk +#define RCC_APB7ENR_LPTIM1EN_Pos (11U) +#define RCC_APB7ENR_LPTIM1EN_Msk (0x1UL << RCC_APB7ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB7ENR_LPTIM1EN RCC_APB7ENR_LPTIM1EN_Msk +#define RCC_APB7ENR_COMPEN_Pos (15U) +#define RCC_APB7ENR_COMPEN_Msk (0x1UL << RCC_APB7ENR_COMPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB7ENR_COMPEN RCC_APB7ENR_COMPEN_Msk +#define RCC_APB7ENR_RTCAPBEN_Pos (21U) +#define RCC_APB7ENR_RTCAPBEN_Msk (0x1UL << RCC_APB7ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7ENR_RTCAPBEN RCC_APB7ENR_RTCAPBEN_Msk + +/******************** Bit definition for RCC_AHB1SMENR register **************/ +#define RCC_AHB1SMENR_GPDMA1SMEN_Pos (0U) +#define RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) /*!< 0x00000000*/ +#define RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk +#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U) +#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk +#define RCC_AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk +#define RCC_AHB1SMENR_TSCSMEN_Pos (16U) +#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk +#define RCC_AHB1SMENR_RAMCFGSMEN_Pos (17U) +#define RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk +#define RCC_AHB1SMENR_GTZC1SMEN_Pos (24U) +#define RCC_AHB1SMENR_GTZC1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1SMENR_GTZC1SMEN RCC_AHB1SMENR_GTZC1SMEN_Msk +#define RCC_AHB1SMENR_ICACHESMEN_Pos (29U) +#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk +#define RCC_AHB1SMENR_SRAM1SMEN_Pos (31U) +#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk + +/******************** Bit definition for RCC_AHB2SMENR register **************/ +#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk +#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk +#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk +#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk +#define RCC_AHB2SMENR_AESSMEN_Pos (16U) +#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk +#define RCC_AHB2SMENR_HASHSMEN_Pos (17U) +#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR_HASHSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk +#define RCC_AHB2SMENR_RNGSMEN_Pos (18U) +#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk +#define RCC_AHB2SMENR_SAESSMEN_Pos (19U) +#define RCC_AHB2SMENR_SAESSMEN_Msk (0x1UL << RCC_AHB2SMENR_SAESSMEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2SMENR_SAESSMEN RCC_AHB2SMENR_SAESSMEN_Msk +#define RCC_AHB2SMENR_PKASMEN_Pos (21U) +#define RCC_AHB2SMENR_PKASMEN_Msk (0x1UL << RCC_AHB2SMENR_PKASMEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2SMENR_PKASMEN RCC_AHB2SMENR_PKASMEN_Msk +#define RCC_AHB2SMENR_SRAM2SMEN_Pos (30U) +#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk + +/******************** Bit definition for RCC_AHB4SMENR register **************/ +#define RCC_AHB4SMENR_PWRSMEN_Pos (2U) +#define RCC_AHB4SMENR_PWRSMEN_Msk (0x1UL << RCC_AHB4SMENR_PWRSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4SMENR_PWRSMEN RCC_AHB4SMENR_PWRSMEN_Msk +#define RCC_AHB4SMENR_ADC4SMEN_Pos (5U) +#define RCC_AHB4SMENR_ADC4SMEN_Msk (0x1UL << RCC_AHB4SMENR_ADC4SMEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4SMENR_ADC4SMEN RCC_AHB4SMENR_ADC4SMEN_Msk + +/******************** Bit definition for RCC_AHB5SMENR register **************/ +#define RCC_AHB5SMENR_RADIOSMEN_Pos (0U) +#define RCC_AHB5SMENR_RADIOSMEN_Msk (0x1UL << RCC_AHB5SMENR_RADIOSMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5SMENR_RADIOSMEN RCC_AHB5SMENR_RADIOSMEN_Msk +#define RCC_AHB5SMENR_PTACONVSMEN_Pos (1U) +#define RCC_AHB5SMENR_PTACONVSMEN_Msk (0x1UL << RCC_AHB5SMENR_PTACONVSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5SMENR_PTACONVSMEN RCC_AHB5SMENR_PTACONVSMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR1 register **************/ +#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk +#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U) +#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk +#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk +#define RCC_APB1SMENR1_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk +#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR2 register **************/ +#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) +#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk + +/******************** Bit definition for RCC_APB2SMENR register **************/ +#define RCC_APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk +#define RCC_APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk +#define RCC_APB2SMENR_TIM17SMEN_Pos (18U) +#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk +#define RCC_APB2SMENR_SAI1SMEN_Pos (21U) +#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk + +/******************** Bit definition for RCC_APB7SMENR register **************/ +#define RCC_APB7SMENR_SYSCFGSMEN_Pos (1U) +#define RCC_APB7SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB7SMENR_SYSCFGSMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7SMENR_SYSCFGSMEN RCC_APB7SMENR_SYSCFGSMEN_Msk +#define RCC_APB7SMENR_SPI3SMEN_Pos (5U) +#define RCC_APB7SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB7SMENR_SPI3SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB7SMENR_SPI3SMEN RCC_APB7SMENR_SPI3SMEN_Msk +#define RCC_APB7SMENR_LPUART1SMEN_Pos (6U) +#define RCC_APB7SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPUART1SMEN_Pos) /*!< 0x00000040 */ +#define RCC_APB7SMENR_LPUART1SMEN RCC_APB7SMENR_LPUART1SMEN_Msk +#define RCC_APB7SMENR_I2C3SMEN_Pos (7U) +#define RCC_APB7SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB7SMENR_I2C3SMEN_Pos) /*!< 0x00000080 */ +#define RCC_APB7SMENR_I2C3SMEN RCC_APB7SMENR_I2C3SMEN_Msk +#define RCC_APB7SMENR_LPTIM1SMEN_Pos (11U) +#define RCC_APB7SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPTIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB7SMENR_LPTIM1SMEN RCC_APB7SMENR_LPTIM1SMEN_Msk +#define RCC_APB7SMENR_COMPSMEN_Pos (15U) +#define RCC_APB7SMENR_COMPSMEN_Msk (0x1UL << RCC_APB7SMENR_COMPSMEN_Pos) /*!< 0x00008000 */ +#define RCC_APB7SMENR_COMPSMEN RCC_APB7SMENR_COMPSMEN_Msk +#define RCC_APB7SMENR_RTCAPBSMEN_Pos (21U) +#define RCC_APB7SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB7SMENR_RTCAPBSMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7SMENR_RTCAPBSMEN RCC_APB7SMENR_RTCAPBSMEN_Msk + +/******************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_I2C1SEL_Pos (10U) +#define RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk +#define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_LPTIM2SEL_Pos (18U) +#define RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk +#define RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (20U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_SYSTICKSEL_Pos (22U) +#define RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk +#define RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00800000 */ +#define RCC_CCIPR1_TIMICSEL_Pos (31U) +#define RCC_CCIPR1_TIMICSEL_Msk (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x80000000 */ +#define RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk + +/******************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_SAI1SEL_Pos (5U) +#define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */ +#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk +#define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_RNGSEL_Pos (12U) +#define RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk +#define RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00200000 */ +#if !defined (STM32WBAXX_SI_CUT1_0) +#define RCC_CCIPR2_ASSEL_Pos (30U) +#define RCC_CCIPR2_ASSEL_Msk (0x1UL << RCC_CCIPR2_ASSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_ASSEL RCC_CCIPR2_ASSEL_Msk +#endif + +/******************** Bit definition for RCC_CCIPR3 register ***************/ +#define RCC_CCIPR3_LPUART1SEL_Pos (0U) +#define RCC_CCIPR3_LPUART1SEL_Msk (0x3UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk +#define RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_SPI3SEL_Pos (3U) +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ +#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk +#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_I2C3SEL_Pos (6U) +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR3_LPTIM1SEL_Pos (10U) +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR3_ADCSEL_Pos (12U) +#define RCC_CCIPR3_ADCSEL_Msk (0x7UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR3_ADCSEL RCC_CCIPR3_ADCSEL_Msk +#define RCC_CCIPR3_ADCSEL_0 (0x1UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCSEL_1 (0x2UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCSEL_2 (0x4UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_BDCR1 register ******************/ +#define RCC_BDCR1_LSEON_Pos (0U) +#define RCC_BDCR1_LSEON_Msk (0x1UL << RCC_BDCR1_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR1_LSEON RCC_BDCR1_LSEON_Msk +#define RCC_BDCR1_LSERDY_Pos (1U) +#define RCC_BDCR1_LSERDY_Msk (0x1UL << RCC_BDCR1_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR1_LSERDY RCC_BDCR1_LSERDY_Msk +#define RCC_BDCR1_LSEBYP_Pos (2U) +#define RCC_BDCR1_LSEBYP_Msk (0x1UL << RCC_BDCR1_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR1_LSEBYP RCC_BDCR1_LSEBYP_Msk +#define RCC_BDCR1_LSEDRV_Pos (3U) +#define RCC_BDCR1_LSEDRV_Msk (0x3UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR1_LSEDRV RCC_BDCR1_LSEDRV_Msk +#define RCC_BDCR1_LSEDRV_0 (0x1UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR1_LSEDRV_1 (0x2UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR1_LSECSSON_Pos (5U) +#define RCC_BDCR1_LSECSSON_Msk (0x1UL << RCC_BDCR1_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR1_LSECSSON RCC_BDCR1_LSECSSON_Msk +#define RCC_BDCR1_LSECSSD_Pos (6U) +#define RCC_BDCR1_LSECSSD_Msk (0x1UL << RCC_BDCR1_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR1_LSECSSD RCC_BDCR1_LSECSSD_Msk +#define RCC_BDCR1_LSESYSEN_Pos (7U) +#define RCC_BDCR1_LSESYSEN_Msk (0x1UL << RCC_BDCR1_LSESYSEN_Pos) /*!< 0x00000080 */ +#define RCC_BDCR1_LSESYSEN RCC_BDCR1_LSESYSEN_Msk +#define RCC_BDCR1_RTCSEL_Pos (8U) +#define RCC_BDCR1_RTCSEL_Msk (0x3UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR1_RTCSEL RCC_BDCR1_RTCSEL_Msk +#define RCC_BDCR1_RTCSEL_0 (0x1UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR1_RTCSEL_1 (0x2UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR1_LSESYSRDY_Pos (11U) +#define RCC_BDCR1_LSESYSRDY_Msk (0x1UL << RCC_BDCR1_LSESYSRDY_Pos) /*!< 0x00000800 */ +#define RCC_BDCR1_LSESYSRDY RCC_BDCR1_LSESYSRDY_Msk +#define RCC_BDCR1_LSEGFON_Pos (12U) +#define RCC_BDCR1_LSEGFON_Msk (0x1UL << RCC_BDCR1_LSEGFON_Pos) /*!< 0x00001000 */ +#define RCC_BDCR1_LSEGFON RCC_BDCR1_LSEGFON_Msk +#define RCC_BDCR1_LSETRIM_Pos (13U) +#define RCC_BDCR1_LSETRIM_Msk (0x3UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00006000 */ +#define RCC_BDCR1_LSETRIM RCC_BDCR1_LSETRIM_Msk +#define RCC_BDCR1_LSETRIM_0 (0x1UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00002000 */ +#define RCC_BDCR1_LSETRIM_1 (0x2UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00004000 */ +#define RCC_BDCR1_BDRST_Pos (16U) +#define RCC_BDCR1_BDRST_Msk (0x1UL << RCC_BDCR1_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR1_BDRST RCC_BDCR1_BDRST_Msk +#define RCC_BDCR1_RADIOSTSEL_Pos (18U) +#define RCC_BDCR1_RADIOSTSEL_Msk (0x3UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x000C0000 */ +#define RCC_BDCR1_RADIOSTSEL RCC_BDCR1_RADIOSTSEL_Msk +#define RCC_BDCR1_RADIOSTSEL_0 (0x1UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00040000 */ +#define RCC_BDCR1_RADIOSTSEL_1 (0x2UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00080000 */ +#define RCC_BDCR1_LSCOEN_Pos (24U) +#define RCC_BDCR1_LSCOEN_Msk (0x1UL << RCC_BDCR1_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR1_LSCOEN RCC_BDCR1_LSCOEN_Msk +#define RCC_BDCR1_LSCOSEL_Pos (25U) +#define RCC_BDCR1_LSCOSEL_Msk (0x1UL << RCC_BDCR1_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR1_LSCOSEL RCC_BDCR1_LSCOSEL_Msk +#define RCC_BDCR1_LSI1ON_Pos (26U) +#define RCC_BDCR1_LSI1ON_Msk (0x1UL << RCC_BDCR1_LSI1ON_Pos) /*!< 0x04000000 */ +#define RCC_BDCR1_LSI1ON RCC_BDCR1_LSI1ON_Msk +#define RCC_BDCR1_LSI1RDY_Pos (27U) +#define RCC_BDCR1_LSI1RDY_Msk (0x1UL << RCC_BDCR1_LSI1RDY_Pos) /*!< 0x08000000 */ +#define RCC_BDCR1_LSI1RDY RCC_BDCR1_LSI1RDY_Msk +#define RCC_BDCR1_LSI1PREDIV_Pos (28U) +#define RCC_BDCR1_LSI1PREDIV_Msk (0x1UL << RCC_BDCR1_LSI1PREDIV_Pos) /*!< 0x10000000 */ +#define RCC_BDCR1_LSI1PREDIV RCC_BDCR1_LSI1PREDIV_Msk +#define RCC_BDCR1_LSI2ON_Pos (29U) +#define RCC_BDCR1_LSI2ON_Msk (0x1UL << RCC_BDCR1_LSI2ON_Pos) /*!< 0x20000000 */ +#define RCC_BDCR1_LSI2ON RCC_BDCR1_LSI2ON_Msk +#define RCC_BDCR1_LSI2RDY_Pos (30U) +#define RCC_BDCR1_LSI2RDY_Msk (0x1UL << RCC_BDCR1_LSI2RDY_Pos) /*!< 0x40000000 */ +#define RCC_BDCR1_LSI2RDY RCC_BDCR1_LSI2RDY_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_BORRSTF_Pos (27U) +#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_BDCR2 register *******************/ +#define RCC_BDCR2_LSI2MODE_Pos (0U) +#define RCC_BDCR2_LSI2MODE_Msk (0x7UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000007 */ +#define RCC_BDCR2_LSI2MODE RCC_BDCR2_LSI2MODE_Msk +#define RCC_BDCR2_LSI2MODE_0 (0x1UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000001 */ +#define RCC_BDCR2_LSI2MODE_1 (0x2UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000002 */ +#define RCC_BDCR2_LSI2MODE_2 (0x4UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000004 */ +#define RCC_BDCR2_LSI2CFG_Pos (4U) +#define RCC_BDCR2_LSI2CFG_Msk (0xFUL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x000000F0 */ +#define RCC_BDCR2_LSI2CFG RCC_BDCR2_LSI2CFG_Msk +#define RCC_BDCR2_LSI2CFG_0 (0x1UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000010 */ +#define RCC_BDCR2_LSI2CFG_1 (0x2UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000020 */ +#define RCC_BDCR2_LSI2CFG_2 (0x4UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000040 */ +#define RCC_BDCR2_LSI2CFG_3 (0x8UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000080 */ + +/******************** Bit definition for RCC_SECCFGR register **************/ +#define RCC_SECCFGR_HSISEC_Pos (0U) +#define RCC_SECCFGR_HSISEC_Msk (0x1UL << RCC_SECCFGR_HSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR_HSISEC RCC_SECCFGR_HSISEC_Msk +#define RCC_SECCFGR_HSESEC_Pos (1U) +#define RCC_SECCFGR_HSESEC_Msk (0x1UL << RCC_SECCFGR_HSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR_HSESEC RCC_SECCFGR_HSESEC_Msk +#define RCC_SECCFGR_LSISEC_Pos (3U) +#define RCC_SECCFGR_LSISEC_Msk (0x1UL << RCC_SECCFGR_LSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR_LSISEC RCC_SECCFGR_LSISEC_Msk +#define RCC_SECCFGR_LSESEC_Pos (4U) +#define RCC_SECCFGR_LSESEC_Msk (0x1UL << RCC_SECCFGR_LSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR_LSESEC RCC_SECCFGR_LSESEC_Msk +#define RCC_SECCFGR_SYSCLKSEC_Pos (5U) +#define RCC_SECCFGR_SYSCLKSEC_Msk (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR_SYSCLKSEC RCC_SECCFGR_SYSCLKSEC_Msk +#define RCC_SECCFGR_PRESCSEC_Pos (6U) +#define RCC_SECCFGR_PRESCSEC_Msk (0x1UL << RCC_SECCFGR_PRESCSEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR_PRESCSEC RCC_SECCFGR_PRESCSEC_Msk +#define RCC_SECCFGR_PLL1SEC_Pos (7U) +#define RCC_SECCFGR_PLL1SEC_Msk (0x1UL << RCC_SECCFGR_PLL1SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR_PLL1SEC RCC_SECCFGR_PLL1SEC_Msk +#define RCC_SECCFGR_RMVFSEC_Pos (12U) +#define RCC_SECCFGR_RMVFSEC_Msk (0x1UL << RCC_SECCFGR_RMVFSEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR_RMVFSEC RCC_SECCFGR_RMVFSEC_Msk + +/******************** Bit definition for RCC_PRIVCFGR register **************/ +#define RCC_PRIVCFGR_SPRIV_Pos (0U) +#define RCC_PRIVCFGR_SPRIV_Msk (0x1UL << RCC_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR_SPRIV RCC_PRIVCFGR_SPRIV_Msk +#define RCC_PRIVCFGR_NSPRIV_Pos (1U) +#define RCC_PRIVCFGR_NSPRIV_Msk (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_NSPRIV RCC_PRIVCFGR_NSPRIV_Msk + +#if !defined (STM32WBAXX_SI_CUT1_0) +/******************** Bit definition for RCC_ASCR register **************/ +#define RCC_ASCR_CEN_Pos (0U) +#define RCC_ASCR_CEN RCC_ASCR_CEN_Msk +#define RCC_ASCR_CEN_Msk (0x1UL << RCC_ASCR_CEN_Pos) /*!< 0x00000001 */ +#define RCC_ASCR_PSC_Pos (8U) +#define RCC_ASCR_PSC_Msk (0x7FUL << RCC_ASCR_PSC_Pos) /*!< 0x00007F00 */ +#define RCC_ASCR_PSC RCC_ASCR_PSC_Msk +#define RCC_ASCR_CPS_Pos (16U) +#define RCC_ASCR_CPS_Msk (0x7FUL << RCC_ASCR_CPS_Pos) /*!< 0x007F0000 */ +#define RCC_ASCR_CPS RCC_ASCR_CPS_Msk + +/******************** Bit definition for RCC_ASIER register **************/ +#define RCC_ASIER_CAIE_Pos (0U) +#define RCC_ASIER_CAIE RCC_ASIER_CAIE_Msk +#define RCC_ASIER_CAIE_Msk (0x1UL << RCC_ASIER_CAIE_Pos) /*!< 0x00000001 */ +#define RCC_ASIER_COIE_Pos (1U) +#define RCC_ASIER_COIE_Msk (0x1UL << RCC_ASIER_COIE_Pos) /*!< 0x00000002 */ +#define RCC_ASIER_COIE RCC_ASIER_COIE_Msk +#define RCC_ASIER_CAEIE_Pos (2U) +#define RCC_ASIER_CAEIE_Msk (0x1UL << RCC_ASIER_CAEIE_Pos) /*!< 0x00000004 */ +#define RCC_ASIER_CAEIE RCC_ASIER_CAEIE_Msk + +/******************** Bit definition for RCC_ASSR register **************/ +#define RCC_ASSR_CAF_Pos (0U) +#define RCC_ASSR_CAF RCC_ASSR_CAF_Msk +#define RCC_ASSR_CAF_Msk (0x1UL << RCC_ASSR_CAF_Pos) /*!< 0x00000001 */ +#define RCC_ASSR_COF_Pos (1U) +#define RCC_ASSR_COF_Msk (0x1UL << RCC_ASSR_COF_Pos) /*!< 0x00000002 */ +#define RCC_ASSR_COF RCC_ASSR_COF_Msk +#define RCC_ASSR_CAEF_Pos (2U) +#define RCC_ASSR_CAEF_Msk (0x1UL << RCC_ASSR_CAEF_Pos) /*!< 0x00000004 */ +#define RCC_ASSR_CAEF RCC_ASSR_CAEF_Msk + +/******************** Bit definition for RCC_ASCNTR register **************/ +#define RCC_ASCNTR_CNT_Pos (0U) +#define RCC_ASCNTR_CNT RCC_ASCNTR_CNT_Msk +#define RCC_ASCNTR_CNT_Msk (0xFFFFFUL << RCC_ASCNTR_CNT_Pos) /*!< 0x000FFFFF */ + +/******************** Bit definition for RCC_ASARR register **************/ +#define RCC_ASARR_AR_Pos (0U) +#define RCC_ASARR_AR RCC_ASARR_AR_Msk +#define RCC_ASARR_AR_Msk (0xFFFFFUL << RCC_ASARR_AR_Pos) /*!< 0x000FFFFF */ + +/******************** Bit definition for RCC_ASCAR register **************/ +#define RCC_ASCAR_CA_Pos (0U) +#define RCC_ASCAR_CA RCC_ASCAR_CA_Msk +#define RCC_ASCAR_CA_Msk (0x7FFFFFFUL << RCC_ASCAR_CA_Pos) /*!< 0x07FFFFFF */ + +/******************** Bit definition for RCC_ASCOR register **************/ +#define RCC_ASCOR_CO_Pos (0U) +#define RCC_ASCOR_CO RCC_ASCOR_CO_Msk +#define RCC_ASCOR_CO_Msk (0xFFFFFUL << RCC_ASCOR_CO_Pos) /*!< 0x000FFFFF */ + +#endif +/******************** Bit definition for RCC_CFGR4 register *******************/ +#define RCC_CFGR4_HPRE5_Pos (0U) +#define RCC_CFGR4_HPRE5_Msk (0x7UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000007 */ +#define RCC_CFGR4_HPRE5 RCC_CFGR4_HPRE5_Msk +#define RCC_CFGR4_HPRE5_0 (0x1UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000001 */ +#define RCC_CFGR4_HPRE5_1 (0x2UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000002 */ +#define RCC_CFGR4_HPRE5_2 (0x4UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000004 */ +#define RCC_CFGR4_HDIV5_Pos (4U) +#define RCC_CFGR4_HDIV5_Msk (0x1UL << RCC_CFGR4_HDIV5_Pos) /*!< 0x00000080 */ +#define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk + +/******************** Bit definition for RCC_RADIOENR register **************/ +#define RCC_RADIOENR_BBCLKEN_Pos (1U) +#define RCC_RADIOENR_BBCLKEN_Msk (0x1UL << RCC_RADIOENR_BBCLKEN_Pos) /*!< 0x00000002 */ +#define RCC_RADIOENR_BBCLKEN RCC_RADIOENR_BBCLKEN_Msk +#define RCC_RADIOENR_STRADIOCLKON_Pos (16U) +#define RCC_RADIOENR_STRADIOCLKON_Msk (0x1UL << RCC_RADIOENR_STRADIOCLKON_Pos) /*!< 0x00010000 */ +#define RCC_RADIOENR_STRADIOCLKON RCC_RADIOENR_STRADIOCLKON_Msk +#define RCC_RADIOENR_RADIOCLKRDY_Pos (17U) +#define RCC_RADIOENR_RADIOCLKRDY_Msk (0x1UL << RCC_RADIOENR_RADIOCLKRDY_Pos) /*!< 0x00020000 */ +#define RCC_RADIOENR_RADIOCLKRDY RCC_RADIOENR_RADIOCLKRDY_Msk + +/******************** Bit definition for RCC_ECSCR1 register *******************/ +#define RCC_ECSCR1_HSETRIM_Pos (16U) +#define RCC_ECSCR1_HSETRIM_Msk (0x3FUL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x003F0000 */ +#define RCC_ECSCR1_HSETRIM RCC_ECSCR1_HSETRIM_Msk +#define RCC_ECSCR1_HSETRIM_0 (0x1UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00010000 */ +#define RCC_ECSCR1_HSETRIM_1 (0x2UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00020000 */ +#define RCC_ECSCR1_HSETRIM_2 (0x4UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00040000 */ +#define RCC_ECSCR1_HSETRIM_3 (0x8UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00080000 */ +#define RCC_ECSCR1_HSETRIM_4 (0x10UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00100000 */ +#define RCC_ECSCR1_HSETRIM_5 (0x20UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00200000 */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_DR register *******************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S)) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/* Instances allowed from Non-Secure state - only alias Non-Secure */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_NS) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_COMMON_NS) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_NS) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || \ + ((INSTANCE) == RAMCFG_SRAM6_NS)) + +/***************************** RAMCFG PED Instances *****************************/ +#define IS_RAMCFG_PED_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Erase Instances ********************************/ +#define IS_RAMCFG_ER_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \ + ((INSTANCE) == GPIOB_NS) || \ + ((INSTANCE) == GPIOC_NS) || \ + ((INSTANCE) == GPIOH_NS)) + +/******************************* GPIO AF Instances ****************************/ +/* On WBA, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On WBA, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** HSEM Lock Instances *****************************/ +#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM_NS) + +#define HSEM_CPU1_LOCKID (HSEM_CR_LOCKID_CURRENT >> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C3_NS)) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == I2C1_NS) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_B_NS)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C3_NS)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == I2C1_NS) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI3_NS)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1_NS) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == SPI1_NS) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + (((INSTANCE) == TIM2_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM3_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS) + +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** @} */ /* End of group STM32WBAxx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32WBA5Mxx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBA5Mxx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h index 5713869e8e..cb31dfac42 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h @@ -56,11 +56,13 @@ application */ -#if !defined(STM32WBA50xx) && !defined(STM32WBA52xx) && !defined(STM32WBA54xx) && !defined(STM32WBA55xx) +#if !defined(STM32WBA50xx) && !defined(STM32WBA52xx) && !defined(STM32WBA54xx) && !defined(STM32WBA55xx) && \ + !defined(STM32WBA5Mxx) /* #define STM32WBA50xx */ /*!< STM32WBA50xx Devices */ /* #define STM32WBA52xx */ /*!< STM32WBA52xx Devices */ /* #define STM32WBA54xx */ /*!< STM32WBA54xx Devices */ /* #define STM32WBA55xx */ /*!< STM32WBA55xx Devices */ + /* #define STM32WBA5Mxx */ /*!< STM32WBA5Mxx Devices */ #endif /* !STM32WBA50xx && !STM32WBA52xx ...*/ /* Tip: To avoid modifying this file each time you need to switch between these @@ -79,7 +81,7 @@ * @brief CMSIS Device version number */ #define __STM32WBA_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBA_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32WBA_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32WBA_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBA_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBA_CMSIS_VERSION ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\ @@ -103,6 +105,8 @@ #include "stm32wba54xx.h" #elif defined(STM32WBA55xx) #include "stm32wba55xx.h" +#elif defined(STM32WBA5Mxx) + #include "stm32wba5mxx.h" #else #error "Please select first the target STM32WBAxx device used in your application (in stm32wbaxx.h file)" #endif /* STM32WBA50xx */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html index 8f716ba1a6..4117e6ec00 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html @@ -34,6 +34,7 @@

                                                                          Purpose

                                                                        • STM32WBA52xx devices
                                                                        • STM32WBA54xx devices
                                                                        • STM32WBA55xx devices
                                                                          • +
                                                                        • STM32WBA5Mxx devices

                                                                        This driver is composed of the description of the registers under “Include†directory.

                                                                        Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

                                                                        @@ -46,11 +47,42 @@

                                                                        Purpose

                                                                        Update History

                                                                        - +

                                                                        Main Changes

                                                                        -

                                                                        Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

                                                                        +

                                                                        Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and STM32WBA5Mxx devices

                                                                        Contents

                                                                        +

                                                                        Official Release of CMSIS devices drivers supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and STM32WBA5Mxx devices

                                                                        +
                                                                          +
                                                                        • Update CMSIS device to add STM32WBA5Mxx devices
                                                                          • +
                                                                        • Update CMSIS device to include latest corrections +
                                                                            +
                                                                          • Additional TAMP register bit ATCKSEL[3] inside TAMP_ATCR1
                                                                            • +
                                                                          • Update to use #include "core_cm33.h" instead of #include <core_cm33.h> to force the first searches for the core_cm33.h file in the same directory as the file that contains the #include directive (Drivers\CMSIS\Core\Include)
                                                                            • +
                                                                          • +
                                                                        +


                                                                        +

                                                                        +

                                                                        Known Limitations

                                                                        +
                                                                          +
                                                                        • None
                                                                          • +
                                                                        +

                                                                        Dependencies

                                                                        +
                                                                          +
                                                                        • None
                                                                          • +
                                                                        +

                                                                        Notes

                                                                        +
                                                                          +
                                                                        • None
                                                                          • +
                                                                        +
                                                                        +
                                                                        +
                                                                        + +
                                                                        +

                                                                        Main Changes

                                                                        +

                                                                        Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

                                                                        +

                                                                        Contents

                                                                        Official Release of CMSIS devices drivers supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

                                                                        • Update CMSIS devices to include latest corrections @@ -62,15 +94,15 @@

                                                                          Known Limitations

                                                                          +

                                                                          Known Limitations

                                                                          • None
                                                                          -

                                                                          Dependencies

                                                                          +

                                                                          Dependencies

                                                                          • None
                                                                          -

                                                                          Notes

                                                                          +

                                                                          Notes

                                                                          • None
                                                                          @@ -79,9 +111,9 @@

                                                                          Notes

                                                                          -

                                                                          Main Changes

                                                                          +

                                                                          Main Changes

                                                                          Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

                                                                          -

                                                                          Contents

                                                                          +

                                                                          Contents

                                                                          Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

                                                                          • Update CMSIS devices to include latest corrections @@ -93,15 +125,15 @@

                                                                            Known Limitations

                                                                            +

                                                                            Known Limitations

                                                                            • None
                                                                            -

                                                                            Dependencies

                                                                            +

                                                                            Dependencies

                                                                            • None
                                                                            -

                                                                            Notes

                                                                            +

                                                                            Notes

                                                                            • None
                                                                            @@ -110,9 +142,9 @@

                                                                            Notes

                                                                            -

                                                                            Main Changes

                                                                            +

                                                                            Main Changes

                                                                            Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

                                                                            -

                                                                            Contents

                                                                            +

                                                                            Contents

                                                                            Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

                                                                            • Update CMSIS devices to include latest corrections @@ -124,15 +156,15 @@

                                                                              Known Limitations

                                                                              +

                                                                              Known Limitations

                                                                              • None
                                                                              -

                                                                              Dependencies

                                                                              +

                                                                              Dependencies

                                                                              • None
                                                                              -

                                                                              Notes

                                                                              +

                                                                              Notes

                                                                              • None
                                                                              @@ -141,9 +173,9 @@

                                                                              Notes

                                                                              -

                                                                              Main Changes

                                                                              +

                                                                              Main Changes

                                                                              Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

                                                                              -

                                                                              Contents

                                                                              +

                                                                              Contents

                                                                              Official Release of CMSIS devices drivers supporting STM32WBA52xx devices

                                                                              • Update CMSIS devices to include latest corrections @@ -153,15 +185,15 @@

                                                                                Known Limitations

                                                                                +

                                                                                Known Limitations

                                                                                • None
                                                                                -

                                                                                Dependencies

                                                                                +

                                                                                Dependencies

                                                                                • None
                                                                                -

                                                                                Notes

                                                                                +

                                                                                Notes

                                                                                • None
                                                                                @@ -170,24 +202,24 @@

                                                                                Notes

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

                                                                                -

                                                                                Contents

                                                                                +

                                                                                Contents

                                                                                • First official release of CMSIS devices drivers
                                                                                  • Support of STM32WBA52xx devices
                                                                                -

                                                                                Known Limitations

                                                                                +

                                                                                Known Limitations

                                                                                • None
                                                                                -

                                                                                Dependencies

                                                                                +

                                                                                Dependencies

                                                                                • None
                                                                                -

                                                                                Notes

                                                                                +

                                                                                Notes

                                                                                • None
                                                                                diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH.ld new file mode 100644 index 0000000000..bf2f31c061 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA5Mxx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH_ns.ld new file mode 100644 index 0000000000..09ad909d2c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH_ns.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA5Mxx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH_s.ld new file mode 100644 index 0000000000..8813efc730 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_FLASH_s.ld @@ -0,0 +1,195 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA5Mxx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K + FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM.ld new file mode 100644 index 0000000000..a7e1583d4c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA5Mxx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM_ns.ld new file mode 100644 index 0000000000..3a8673b11b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM_ns.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA5Mxx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20018000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x20010000, LENGTH = 32K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM_s.ld new file mode 100644 index 0000000000..9836fd00d1 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA5Mxx_RAM_s.ld @@ -0,0 +1,195 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA5Mxx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30008000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x30000000, LENGTH = 32256 + FLASH_NSC (rx) : ORIGIN = 0x30007E00, LENGTH = 512 +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba5mxx.s b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba5mxx.s new file mode 100644 index 0000000000..a4413b9e20 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba5mxx.s @@ -0,0 +1,474 @@ +/** + ****************************************************************************** + * @file startup_stm32wba5mxx.s + * @author MCD Application Team + * @brief STM32WBA5Mxx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M33. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word IWDG_IRQHandler + .word SAES_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word SPI1_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word COMP_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word TSC_IRQHandler + .word AES_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word SPI3_IRQHandler + .word ICACHE_IRQHandler + .word ADC4_IRQHandler + .word RADIO_IRQHandler + .word WKUP_IRQHandler + .word HSEM_IRQHandler + .word HSEM_S_IRQHandler + .word WKUP_S_IRQHandler + .word RCC_AUDIOSYNC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak RADIO_IRQHandler + .thumb_set RADIO_IRQHandler,Default_Handler + + .weak WKUP_IRQHandler + .thumb_set WKUP_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak HSEM_S_IRQHandler + .thumb_set HSEM_S_IRQHandler,Default_Handler + + .weak WKUP_S_IRQHandler + .thumb_set WKUP_S_IRQHandler,Default_Handler + + .weak RCC_AUDIOSYNC_IRQHandler + .thumb_set RCC_AUDIOSYNC_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index e7e12952c8..0e3e0ae7c6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -19,7 +19,7 @@ * STM32U0: 1.2.0 * STM32U5: 1.4.0 * STM32WB: 1.12.2 - * STM32WBA: 1.4.0 + * STM32WBA: 1.5.0 * STM32WL: 1.2.0 Release notes of each STM32YYxx CMSIS available here: From 7afbaac885acaa123cedee9b9a5eeccdb1fd3c51 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Jan 2025 09:29:23 +0100 Subject: [PATCH 063/141] core(WBA): update wrapped files Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def_build.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 179b810851..b89e327f20 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -478,6 +478,8 @@ #define CMSIS_STARTUP_FILE "startup_stm32wba54xx.s" #elif defined(STM32WBA55xx) #define CMSIS_STARTUP_FILE "startup_stm32wba55xx.s" + #elif defined(STM32WBA5Mxx) + #define CMSIS_STARTUP_FILE "startup_stm32wba5mxx.s" #elif defined(STM32WB10xx) #define CMSIS_STARTUP_FILE "startup_stm32wb10xx_cm4.s" #elif defined(STM32WB15xx) From 5050bc8f35d7e8531af73b581b4887addb96033d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Jan 2025 09:33:55 +0100 Subject: [PATCH 064/141] chore(wba): update variants after cube update Signed-off-by: Frederic Pillon --- variants/STM32WBAxx/WBA5MJGH/boards_entry.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variants/STM32WBAxx/WBA5MJGH/boards_entry.txt b/variants/STM32WBAxx/WBA5MJGH/boards_entry.txt index 638de3441c..30c96f2714 100644 --- a/variants/STM32WBAxx/WBA5MJGH/boards_entry.txt +++ b/variants/STM32WBAxx/WBA5MJGH/boards_entry.txt @@ -8,7 +8,7 @@ GenWBA.menu.pnum.GENERIC_WBA5MJGHX=Generic WBA5MJGHx GenWBA.menu.pnum.GENERIC_WBA5MJGHX.upload.maximum_size=1048576 GenWBA.menu.pnum.GENERIC_WBA5MJGHX.upload.maximum_data_size=131072 GenWBA.menu.pnum.GENERIC_WBA5MJGHX.build.board=GENERIC_WBA5MJGHX -GenWBA.menu.pnum.GENERIC_WBA5MJGHX.build.product_line= +GenWBA.menu.pnum.GENERIC_WBA5MJGHX.build.product_line=STM32WBA5Mxx GenWBA.menu.pnum.GENERIC_WBA5MJGHX.build.variant=STM32WBAxx/WBA5MJGH GenWBA.menu.pnum.GENERIC_WBA5MJGHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBAxx/STM32WBA55.svd From 95b529f712bc8add96a2eba750ce35fa3ad3ffb7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Jan 2025 09:36:40 +0100 Subject: [PATCH 065/141] system(wba): update STM32WBAxx hal default config Signed-off-by: Frederic Pillon --- system/STM32WBAxx/stm32wbaxx_hal_conf_default.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h index 75d96c6a62..9ca346f966 100644 --- a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h +++ b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h @@ -101,7 +101,9 @@ extern "C" { */ #if !defined (LSI_VALUE) #define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may vary depending on the variations in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations in voltage + and temperature.*/ #if defined (RCC_LSI2_SUPPORT) #if !defined (LSI2_VALUE) @@ -172,8 +174,8 @@ extern "C" { #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ #define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ #define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ @@ -205,12 +207,10 @@ extern "C" { #define USE_HAL_HASH_SUSPEND_RESUME 0U - /* Includes ------------------------------------------------------------------*/ /** * @brief Include module's header file */ - #ifdef HAL_DMA_MODULE_ENABLED #include "stm32wbaxx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ From b064aa2dd8a73449e355ea25e154128de14a25ad Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Jan 2025 14:27:23 +0100 Subject: [PATCH 066/141] system(WB) update STM32WBxx HAL Drivers to v1.14.4 Included in STM32CubeWB FW v1.21.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 63 ++- .../Inc/stm32wbxx_hal_pcd.h | 17 +- .../Inc/stm32wbxx_hal_pcd_ex.h | 1 - .../Inc/stm32wbxx_hal_spi.h | 46 +- .../Inc/stm32wbxx_ll_adc.h | 10 +- .../Inc/stm32wbxx_ll_spi.h | 119 +++--- .../STM32WBxx_HAL_Driver/Release_Notes.html | 182 +++++--- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c | 2 +- .../Src/stm32wbxx_hal_adc.c | 22 +- .../Src/stm32wbxx_hal_crc_ex.c | 2 - .../Src/stm32wbxx_hal_lptim.c | 47 --- .../Src/stm32wbxx_hal_pcd.c | 41 +- .../Src/stm32wbxx_hal_pcd_ex.c | 2 - .../Src/stm32wbxx_hal_pwr.c | 50 ++- .../Src/stm32wbxx_hal_qspi.c | 12 + .../Src/stm32wbxx_hal_spi.c | 399 +++++++++--------- .../Src/stm32wbxx_hal_uart.c | 1 - .../Src/stm32wbxx_ll_adc.c | 34 +- .../Src/stm32wbxx_ll_pwr.c | 50 ++- .../Src/stm32wbxx_ll_spi.c | 7 +- .../Src/stm32wbxx_ll_usb.c | 73 ++-- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 22 files changed, 659 insertions(+), 523 deletions(-) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index f7ec781bb3..2207fbdd32 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -875,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -1012,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1264,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1279,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -2014,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -3679,8 +3694,10 @@ extern "C" { #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK #endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3931,7 +3948,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4225,6 +4243,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h index b14b38d0e3..2f023a607f 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h @@ -806,20 +806,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); \ *(pdwReg) &= 0x3FFU; \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - *(pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd_ex.h index 0d4d78799a..d19fe513ee 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h index 4a30885d23..b50ce5cda5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h index 6b8b8d8868..d9eab2bd18 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h @@ -7204,7 +7204,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx) } #else -#endif /* ADC_SUPPORT_2_5_MSPS */ +#endif /** * @brief Get flag ADC group regular end of unitary conversion. * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC @@ -7359,7 +7359,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx) } #else -#endif /* ADC_SUPPORT_2_5_MSPS */ +#endif /** * @brief Clear flag ADC group regular end of unitary conversion. * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC @@ -7519,7 +7519,7 @@ __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx) } #else -#endif /* ADC_SUPPORT_2_5_MSPS */ +#endif /** * @brief Enable interruption ADC group regular end of unitary conversion. * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC @@ -7671,7 +7671,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx) } #else -#endif /* ADC_SUPPORT_2_5_MSPS */ +#endif /** * @brief Disable interruption ADC group regular end of unitary conversion. * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC @@ -7824,7 +7824,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx) } #else -#endif /* ADC_SUPPORT_2_5_MSPS */ +#endif /** * @brief Get state of interruption ADC group regular end of unitary conversion * (0: interrupt disabled, 1: interrupt enabled). diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h index 8c7e7a83e1..875eea997a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html index 7f617a7dd9..1a17999451 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html @@ -40,7 +40,7 @@

                                                                                Purpose

                                                                                Update History

                                                                                - +

                                                                                Main Changes

                                                                                  @@ -50,6 +50,60 @@

                                                                                  Main Changes

                                                                                  Contents

                                                                                  HAL Drivers updates

                                                                                    +
                                                                                  • HAL ADC driver +
                                                                                      +
                                                                                    • Fixed MISRA 20.6_b warnings
                                                                                      • +
                                                                                    • +
                                                                                  • HAL QSPI driver +
                                                                                      +
                                                                                    • Clear AR register after CCR to avoid new transfer when address is not needed
                                                                                      • +
                                                                                    • +
                                                                                  • HAL SPI driver +
                                                                                      +
                                                                                    • Check data size before changing state in reception API
                                                                                      • +
                                                                                    • Fix MISRA2012 Rule 8.13 errors
                                                                                      • +
                                                                                    • +
                                                                                  • HAL UART driver +
                                                                                      +
                                                                                    • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode
                                                                                      • +
                                                                                    • +
                                                                                  • HAL PCD driver +
                                                                                      +
                                                                                    • Fix added to support bulk transfer in double buffer mode
                                                                                      • +
                                                                                    • +
                                                                                  +

                                                                                  LL Drivers updates

                                                                                  +
                                                                                    +
                                                                                  • LL ADC driver +
                                                                                      +
                                                                                    • Fixed MISRA 20.6_b warnings.
                                                                                      • +
                                                                                    • +
                                                                                  • LL SPI driver +
                                                                                      +
                                                                                    • Add const qualifiers to be compliant with MISRA rule 8.13
                                                                                      • +
                                                                                    • +
                                                                                  • LL USB driver +
                                                                                      +
                                                                                    • Fix added to support bulk transfer in double buffer mode
                                                                                      • +
                                                                                    • +
                                                                                  +


                                                                                  +

                                                                                  +

                                                                                  Backward Compatibility

                                                                                  +

                                                                                  This release is compatible with the previous versions.

                                                                                  +
                                                                                +
                                                                                +
                                                                                + +
                                                                                +

                                                                                Main Changes

                                                                                +
                                                                                  +
                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                  • +
                                                                                • HAL/LL code quality enhancement
                                                                                  • +
                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                +
                                                                                • HAL CRYP driver
                                                                                  • Code quality enhancment MISRAC 2012 Rule-10.4
                                                                                    • @@ -78,7 +132,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL LPUART driver
                                                                                      @@ -91,20 +145,20 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                • HAL/LL code quality enhancement
                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL GPIO driver
                                                                                    @@ -144,7 +198,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL UTILS driver
                                                                                      @@ -153,20 +207,20 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                • HAL/LL code quality enhancement
                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL I2C driver
                                                                                    @@ -201,7 +255,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL I2C driver
                                                                                      @@ -219,20 +273,20 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                • HAL/LL code quality enhancement
                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL CRYP driver
                                                                                    @@ -271,7 +325,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL USB driver
                                                                                      @@ -280,20 +334,20 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                • HAL/LL code quality enhancement
                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL FLASH driver
                                                                                    @@ -324,20 +378,20 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  Backward Compatibility

                                                                                  +

                                                                                  Backward Compatibility

                                                                                  This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)
                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL ADC driver
                                                                                    @@ -384,7 +438,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL ADC driver
                                                                                      @@ -405,20 +459,20 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                • Correct English spelling errors and typos
                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL EXTI driver
                                                                                    @@ -494,7 +548,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL I2C driver
                                                                                      @@ -530,19 +584,19 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Patch release of HAL and Low Layer drivers
                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL COMP driver
                                                                                    @@ -551,7 +605,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL COMP driver
                                                                                      @@ -560,21 +614,21 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                • All source files: update disclaimer to add reference to the new license agreement
                                                                                • Correct English spelling errors and typos
                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL ADC driver
                                                                                    @@ -645,7 +699,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL ADC driver
                                                                                      @@ -660,14 +714,14 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                                • Update of HAL SMBUS driver to introduce fast mode and fast mode plus @@ -681,8 +735,8 @@

                                                                                  Main Changes


                                                                                -

                                                                                Contents

                                                                                -

                                                                                HAL Drivers updates

                                                                                +

                                                                                Contents

                                                                                +

                                                                                HAL Drivers updates

                                                                                • HAL CORTEX driver
                                                                                    @@ -758,7 +812,7 @@

                                                                                    HAL Drivers updates


                                                                                  -

                                                                                  LL Drivers updates

                                                                                  +

                                                                                  LL Drivers updates

                                                                                  • LL DMA driver
                                                                                      @@ -785,14 +839,14 @@

                                                                                      LL Drivers updates


                                                                                    -

                                                                                    Backward Compatibility

                                                                                    +

                                                                                    Backward Compatibility

                                                                                    This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                Add support for STM32WB15xx and STM32WB10xx

                                                                                @@ -928,14 +982,14 @@

                                                                                Add support for STM32WB15xx

                                                                                -

                                                                                Backward Compatibility

                                                                                +

                                                                                Backward Compatibility

                                                                                This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                Maitenance release

                                                                                All peripheral

                                                                                @@ -1008,14 +1062,14 @@

                                                                                Maitenance release

                                                                                -

                                                                                Backward Compatibility

                                                                                +

                                                                                Backward Compatibility

                                                                                This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                Maitenance release

                                                                                All peripheral

                                                                                @@ -1120,14 +1174,14 @@

                                                                                Maitenance release

                                                                                -

                                                                                Backward Compatibility

                                                                                +

                                                                                Backward Compatibility

                                                                                This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product

                                                                                This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

                                                                                Added features:

                                                                                @@ -1172,14 +1226,14 @@

                                                                                Introduct -

                                                                                Backward Compatibility

                                                                                +

                                                                                Backward Compatibility

                                                                                This release is compatible with the previous versions.

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                Maitenance release

                                                                                @@ -1223,7 +1277,7 @@

                                                                                Maitenance release

                                                                                -

                                                                                Backward Compatibility

                                                                                +

                                                                                Backward Compatibility

                                                                                This release is compatible with the previous versions.

                                                                                Dependencies

                                                                                This software release is compatible with:

                                                                                @@ -1233,7 +1287,7 @@

                                                                                Dependencies

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                Maitenance release

                                                                                @@ -1305,7 +1359,7 @@

                                                                                Maitenance release

                                                                                -

                                                                                Backward Compatibility

                                                                                +

                                                                                Backward Compatibility

                                                                                This release is compatible with the previous versions.

                                                                                Dependencies

                                                                                This software release is compatible with:

                                                                                @@ -1315,7 +1369,7 @@

                                                                                Dependencies

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                STM32WB50xx introduction and maintenance release

                                                                                First release for STM32WBxx HAL drivers introducing stm32wb50xx devices.

                                                                                @@ -1384,7 +1438,7 @@

                                                                                STM32WB50xx introducti

                                                                                -

                                                                                Backward Compatibility

                                                                                +

                                                                                Backward Compatibility

                                                                                This release is compatible with the previous versions.

                                                                                Dependencies

                                                                                This software release is compatible with:

                                                                                @@ -1394,7 +1448,7 @@

                                                                                Dependencies

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                Maintenance release

                                                                                Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.

                                                                                @@ -1448,7 +1502,7 @@

                                                                                Maintenance release

                                                                                -

                                                                                Backward Compatibility

                                                                                +

                                                                                Backward Compatibility

                                                                                This release is compatible with the previous versions.

                                                                                Dependencies

                                                                                This software release is compatible with:

                                                                                @@ -1458,7 +1512,7 @@

                                                                                Dependencies

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                First release

                                                                                First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.

                                                                                diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c index 2dcc929e61..8fcb2d2401 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c @@ -56,7 +56,7 @@ */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_HAL_VERSION_SUB1 (0x0EU) /*!< [23:16] sub1 version */ -#define __STM32WBxx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define __STM32WBxx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ |(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c index cd10e10227..026cdea0db 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c @@ -1016,27 +1016,25 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) #else /* Reset register IER */ - __HAL_ADC_DISABLE_IT(hadc, ( #if defined(ADC_SUPPORT_2_5_MSPS) - ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | - ADC_IT_EOCAL | ADC_IT_CCRDY | + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | + ADC_IT_EOCAL | ADC_IT_CCRDY)); #else - ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | - ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_JQOVF | + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | + ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_JQOVF)); #endif /* ADC_SUPPORT_2_5_MSPS */ - ADC_IT_EOS | ADC_IT_EOC | ADC_IT_OVR | + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_EOC | ADC_IT_OVR | ADC_IT_EOSMP | ADC_IT_RDY)); /* Reset register ISR */ - __HAL_ADC_CLEAR_FLAG(hadc, ( #if defined(ADC_SUPPORT_2_5_MSPS) - ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | - ADC_FLAG_EOCAL | ADC_FLAG_CCRDY | + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | + ADC_FLAG_EOCAL | ADC_FLAG_CCRDY)); #else - ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | - ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_JQOVF | + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | + ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_JQOVF)); #endif /* ADC_SUPPORT_2_5_MSPS */ - ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_OVR | + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_OVR | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); /* Reset register CR */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c index 3cd8e96110..20b66d3c44 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c index cbace79f81..7d75346870 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c @@ -2388,7 +2388,6 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, ui */ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) { - uint32_t tmpclksource = 0; uint32_t tmpIER; uint32_t tmpCFGR; uint32_t tmpCMP; @@ -2403,22 +2402,6 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) __set_PRIMASK(1) ; /*********** Save LPTIM Config ***********/ - /* Save LPTIM source clock */ - switch ((uint32_t)hlptim->Instance) - { - case LPTIM1_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); - break; -#if defined(LPTIM2) - case LPTIM2_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); - break; -#endif /* LPTIM2 */ - default: - break; - } - - /* Save LPTIM configuration registers */ tmpIER = hlptim->Instance->IER; tmpCFGR = hlptim->Instance->CFGR; tmpCMP = hlptim->Instance->CMP; @@ -2447,21 +2430,6 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /*********** Restore LPTIM Config ***********/ if ((tmpCMP != 0UL) || (tmpARR != 0UL)) { - /* Force LPTIM source kernel clock from APB */ - switch ((uint32_t)hlptim->Instance) - { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); - break; -#if defined(LPTIM2) - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1); - break; -#endif /* LPTIM2 */ - default: - break; - } - if (tmpCMP != 0UL) { /* Restore CMP register (LPTIM should be enabled first) */ @@ -2490,21 +2458,6 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); } - - /* Restore LPTIM source kernel clock */ - switch ((uint32_t)hlptim->Instance) - { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(tmpclksource); - break; -#if defined(LPTIM2) - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_CONFIG(tmpclksource); - break; -#endif /* LPTIM2 */ - default: - break; - } } /* Restore configuration registers (LPTIM should be disabled first) */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c index f247475876..4003cad00a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c @@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1404,7 +1404,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -1809,7 +1809,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -1930,7 +1929,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2006,7 +2005,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2038,11 +2037,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2092,6 +2091,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2103,10 +2108,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2137,7 +2144,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2165,6 +2172,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2177,10 +2190,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2210,7 +2225,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2219,7 +2234,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; @@ -2227,13 +2242,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c index 49457712e4..baadd33678 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c @@ -242,7 +242,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -279,7 +278,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } - /** * @brief Send LPM message to user layer callback. * @param hpcd PCD handle diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c index 71d2bc49dc..982b7fdd57 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c @@ -125,21 +125,43 @@ void HAL_PWR_DeInit(void) LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); /* Clear all flags */ +#if defined(PWR_CR3_E802A) && defined(PWR_CR5_SMPSEN) LL_PWR_WriteReg(SCR, - LL_PWR_SCR_CC2HF - | LL_PWR_SCR_CBLEAF - | LL_PWR_SCR_CCRPEF -#if defined(PWR_CR3_E802A) - | LL_PWR_SCR_C802AF - | LL_PWR_SCR_C802WUF -#endif /* PWR_CR3_E802A */ - | LL_PWR_SCR_CBLEWUF -#if defined(PWR_CR5_SMPSEN) - | LL_PWR_SCR_CBORHF - | LL_PWR_SCR_CSMPSFBF -#endif /* PWR_CR5_SMPSEN */ - | LL_PWR_SCR_CWUF - ); + LL_PWR_SCR_CC2HF + | LL_PWR_SCR_CBLEAF + | LL_PWR_SCR_CCRPEF + | LL_PWR_SCR_C802AF + | LL_PWR_SCR_C802WUF + | LL_PWR_SCR_CBLEWUF + | LL_PWR_SCR_CBORHF + | LL_PWR_SCR_CSMPSFBF + | LL_PWR_SCR_CWUF); +#elif defined(PWR_CR3_E802A) + LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CC2HF + | LL_PWR_SCR_CBLEAF + | LL_PWR_SCR_CCRPEF + | LL_PWR_SCR_C802AF + | LL_PWR_SCR_C802WUF + | LL_PWR_SCR_CBLEWUF + | LL_PWR_SCR_CWUF); +#elif defined(PWR_CR5_SMPSEN) + LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CC2HF + | LL_PWR_SCR_CBLEAF + | LL_PWR_SCR_CCRPEF + | LL_PWR_SCR_CBLEWUF + | LL_PWR_SCR_CBORHF + | LL_PWR_SCR_CSMPSFBF + | LL_PWR_SCR_CWUF); +#else + LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CC2HF + | LL_PWR_SCR_CBLEAF + | LL_PWR_SCR_CCRPEF + | LL_PWR_SCR_CBLEWUF + | LL_PWR_SCR_CWUF); +#endif LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_CCRPF diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c index fc71c19a3e..3696e0ab66 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c @@ -2631,6 +2631,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2658,6 +2661,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } @@ -2692,6 +2698,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2721,6 +2730,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c index efcc8af763..cab31ee3da 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -818,38 +820,35 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -922,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr ++; hspi->TxXferCount--; } @@ -941,13 +940,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -957,9 +956,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -984,19 +983,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1016,12 +1014,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1031,17 +1032,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1113,9 +1108,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1137,9 +1132,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1156,8 +1151,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1175,8 +1170,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1202,8 +1198,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1229,18 +1226,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1253,8 +1249,8 @@ error : * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1271,14 +1267,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1293,18 +1285,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1316,7 +1310,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1356,7 +1350,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1379,7 +1373,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1410,9 +1404,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1423,13 +1417,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -1454,13 +1448,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -1506,9 +1500,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1522,8 +1516,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -1548,8 +1543,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1565,30 +1561,32 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1599,9 +1597,8 @@ error : * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1609,14 +1606,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1625,7 +1620,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1673,8 +1668,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1687,13 +1681,15 @@ error : */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1704,12 +1700,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1781,8 +1771,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1794,11 +1783,11 @@ error : * @param Size amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1808,16 +1797,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1831,7 +1819,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1892,8 +1880,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1904,9 +1891,8 @@ error : * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1914,25 +1900,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1994,9 +1978,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2006,16 +1990,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2030,15 +2014,17 @@ error : */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -2055,12 +2041,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2138,9 +2118,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2150,16 +2130,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2172,12 +2152,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -2186,26 +2165,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -2214,7 +2192,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2305,9 +2283,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2326,9 +2304,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2337,16 +2315,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2439,7 +2418,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2472,7 +2452,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2727,9 +2708,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -3019,7 +3002,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3031,7 +3014,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3058,7 +3041,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3115,7 +3098,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3232,7 +3215,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3270,7 +3253,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3332,7 +3316,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3350,7 +3334,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3368,7 +3352,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3386,7 +3370,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3409,7 +3393,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3431,7 +3415,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3447,7 +3431,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3497,7 +3482,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3514,7 +3499,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3650,14 +3636,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in packing Bit mode */ if (hspi->TxXferCount >= 2U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3751,7 +3737,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3904,7 +3890,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3930,7 +3916,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -4032,7 +4018,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4387,7 +4373,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4430,7 +4417,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4459,7 +4447,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c index 97c320a227..971d8df592 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c @@ -3907,7 +3907,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c index b891d501b6..99eb0f14cf 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c @@ -562,46 +562,68 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { /* ========== Reset ADC registers ========== */ /* Reset register IER */ +#if !defined(ADC_SUPPORT_2_5_MSPS) CLEAR_BIT(ADCx->IER, (LL_ADC_IT_ADRDY | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR | LL_ADC_IT_EOSMP -#if !defined(ADC_SUPPORT_2_5_MSPS) | LL_ADC_IT_JEOC | LL_ADC_IT_JEOS | LL_ADC_IT_JQOVF -#endif /* !ADC_SUPPORT_2_5_MSPS */ | LL_ADC_IT_AWD1 | LL_ADC_IT_AWD2 | LL_ADC_IT_AWD3 + ) + ); +#endif /* !ADC_SUPPORT_2_5_MSPS */ #if defined(ADC_SUPPORT_2_5_MSPS) + CLEAR_BIT(ADCx->IER, + (LL_ADC_IT_ADRDY + | LL_ADC_IT_EOC + | LL_ADC_IT_EOS + | LL_ADC_IT_OVR + | LL_ADC_IT_EOSMP | LL_ADC_IT_CCRDY -#endif /* ADC_SUPPORT_2_5_MSPS */ + | LL_ADC_IT_AWD1 + | LL_ADC_IT_AWD2 + | LL_ADC_IT_AWD3 ) ); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Reset register ISR */ +#if !defined(ADC_SUPPORT_2_5_MSPS) SET_BIT(ADCx->ISR, (LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_EOSMP -#if !defined(ADC_SUPPORT_2_5_MSPS) | LL_ADC_FLAG_JEOC | LL_ADC_FLAG_JEOS | LL_ADC_FLAG_JQOVF -#endif /* !ADC_SUPPORT_2_5_MSPS */ | LL_ADC_FLAG_AWD1 | LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD3 + ) + ); +#endif /* !ADC_SUPPORT_2_5_MSPS */ #if defined(ADC_SUPPORT_2_5_MSPS) + SET_BIT(ADCx->ISR, + (LL_ADC_FLAG_ADRDY + | LL_ADC_FLAG_EOC + | LL_ADC_FLAG_EOS + | LL_ADC_FLAG_OVR + | LL_ADC_FLAG_EOSMP | LL_ADC_FLAG_CCRDY -#endif /* ADC_SUPPORT_2_5_MSPS */ + | LL_ADC_FLAG_AWD1 + | LL_ADC_FLAG_AWD2 + | LL_ADC_FLAG_AWD3 ) ); +#endif /* ADC_SUPPORT_2_5_MSPS */ #if defined(ADC_SUPPORT_2_5_MSPS) /* Reset register CR */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c index dbf02092dc..9d8d7115db 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c @@ -106,21 +106,43 @@ ErrorStatus LL_PWR_DeInit(void) LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); /* Clear all flags */ + #if defined(PWR_CR3_E802A) && defined(PWR_CR5_SMPSEN) +LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CC2HF + | LL_PWR_SCR_CBLEAF + | LL_PWR_SCR_CCRPEF + | LL_PWR_SCR_C802AF + | LL_PWR_SCR_C802WUF + | LL_PWR_SCR_CBLEWUF + | LL_PWR_SCR_CBORHF + | LL_PWR_SCR_CSMPSFBF + | LL_PWR_SCR_CWUF); +#elif defined(PWR_CR3_E802A) LL_PWR_WriteReg(SCR, - LL_PWR_SCR_CC2HF - | LL_PWR_SCR_CBLEAF - | LL_PWR_SCR_CCRPEF -#if defined(PWR_CR3_E802A) - | LL_PWR_SCR_C802AF - | LL_PWR_SCR_C802WUF -#endif /* PWR_CR3_E802A */ - | LL_PWR_SCR_CBLEWUF -#if defined(PWR_CR5_SMPSEN) - | LL_PWR_SCR_CBORHF - | LL_PWR_SCR_CSMPSFBF -#endif /* PWR_CR5_SMPSEN */ - | LL_PWR_SCR_CWUF - ); + LL_PWR_SCR_CC2HF + | LL_PWR_SCR_CBLEAF + | LL_PWR_SCR_CCRPEF + | LL_PWR_SCR_C802AF + | LL_PWR_SCR_C802WUF + | LL_PWR_SCR_CBLEWUF + | LL_PWR_SCR_CWUF); +#elif defined(PWR_CR5_SMPSEN) + LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CC2HF + | LL_PWR_SCR_CBLEAF + | LL_PWR_SCR_CCRPEF + | LL_PWR_SCR_CBLEWUF + | LL_PWR_SCR_CBORHF + | LL_PWR_SCR_CSMPSFBF + | LL_PWR_SCR_CWUF); +#else + LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CC2HF + | LL_PWR_SCR_CBLEAF + | LL_PWR_SCR_CCRPEF + | LL_PWR_SCR_CBLEWUF + | LL_PWR_SCR_CWUF); +#endif LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_CCRPF diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c index a275d6c739..a35c29fffa 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c @@ -129,7 +129,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -166,8 +166,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c index f3a23b9f39..27662c249a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c @@ -319,6 +319,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -423,7 +427,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -525,9 +529,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -559,19 +563,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -580,15 +590,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -599,18 +607,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -654,26 +652,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 0f8b0e5a07..cee30061e2 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -18,7 +18,7 @@ * STM32MP1: 1.6.0 * STM32U0: 1.2.0 * STM32U5: 1.6.0 - * STM32WB: 1.14.3 + * STM32WB: 1.14.4 * STM32WBA: 1.5.0 * STM32WL: 1.3.0 From d8a8b200008c91ace2a48bf456fe8107540fa18e Mon Sep 17 00:00:00 2001 From: "Vitor Moreno B. Sales" Date: Tue, 14 Jan 2025 10:42:22 -0300 Subject: [PATCH 067/141] Fix dead lock with pin above NUM_DIGITAL_PINS (#2629) Penalty for the check should be a single instruction for pin numbers below NUM_DIGITAL_PINS, 9 for pin numbers between PNUM_ANALOG_BASE and NUM_ANALOG_INTERNAL_FIRST. Tests done on a Black F407VE board Signed-off-by: Frederic Pillon Co-authored-by: Frederic Pillon --- cores/arduino/wiring_digital.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/cores/arduino/wiring_digital.c b/cores/arduino/wiring_digital.c index 5840435c1a..4141772835 100644 --- a/cores/arduino/wiring_digital.c +++ b/cores/arduino/wiring_digital.c @@ -78,17 +78,25 @@ void pinMode(uint32_t ulPin, uint32_t ulMode) void digitalWrite(uint32_t ulPin, uint32_t ulVal) { - digitalWriteFast(digitalPinToPinName(ulPin), ulVal); + PinName p = digitalPinToPinName(ulPin); + if (p != NC) { + digitalWriteFast(p, ulVal); + } } int digitalRead(uint32_t ulPin) { - return digitalReadFast(digitalPinToPinName(ulPin)); + PinName p = digitalPinToPinName(ulPin); + + return (p == NC) ? 0 : digitalReadFast(p); } void digitalToggle(uint32_t ulPin) { - digitalToggleFast(digitalPinToPinName(ulPin)); + PinName p = digitalPinToPinName(ulPin); + if (p != NC) { + digitalToggleFast(digitalPinToPinName(ulPin)); + } } #ifdef __cplusplus From b4f837908dcfee32fe966f005a470ab0a49fa430 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 14 Jan 2025 10:14:31 +0100 Subject: [PATCH 068/141] fix(stm32variant): wrong product line generated Fixes #2628. Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index 34936c8afd..ef65c6d380 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -1584,10 +1584,11 @@ def print_variant(generic_list, alt_syswkup_list): ) -def search_product_line(valueline): +def search_product_line(valueline: str, extra: str) -> str: product_line = "" + product_line_list = product_line_dict[mcu_family] if not valueline.startswith("STM32MP1"): - for pline in product_line_dict[mcu_family]: + for idx_pline, pline in enumerate(product_line_list): vline = valueline product_line = pline # Remove the 'x' character from pline and @@ -1600,6 +1601,10 @@ def search_product_line(valueline): else: break if pline >= vline: + if extra and len(product_line_list) > idx_pline + 1: + if product_line_list[idx_pline + 1] == (product_line + extra): + # Look for the next product line if contains the extra + product_line = product_line_list[idx_pline + 1] break else: # In case of CMSIS device does not exist @@ -1698,11 +1703,14 @@ def print_boards_entry(): } ) # Search product line for last flash size + # Keep the AQ if any + subp = pl_regex.search(subf.group(3)) product_line = search_product_line( "STM32" + subf.group(1) + subf.group(2).split("-")[-1] - + package_regex.sub(r"", subf.group(3)) + + package_regex.sub(r"", subf.group(3)), + subp.group(1) if subp and subp.group(1) is not None else "", ) else: valueline = mcu_refname @@ -1715,7 +1723,11 @@ def print_boards_entry(): "svd": search_svdfile(mcu_refname), } ) - product_line = search_product_line(package_regex.sub(r"", valueline)) + subp = pl_regex.search(valueline) + product_line = search_product_line( + package_regex.sub(r"", valueline), + subp.group(1) if subp and subp.group(1) is not None else "", + ) gen_entry = mcu_family.replace("STM32", "Gen") @@ -2685,6 +2697,7 @@ def manage_repo(): # Clean temporary dir deleteFolder(tmp_dir) +pl_regex = re.compile(r"([AQ])$") package_regex = re.compile(r"[\w][\w]([ANPQSXZ])?$") flash_group_regex = re.compile(r"(.*)\((.*)\)(.*)") From dfbd256eeb9506891b6343f2eeafeb5a64614bda Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 14 Jan 2025 14:58:51 +0100 Subject: [PATCH 069/141] variant: update wrong product lines Signed-off-by: Frederic Pillon --- boards.txt | 26 +++++++++---------- .../boards_entry.txt | 2 +- .../boards_entry.txt | 2 +- .../boards_entry.txt | 2 +- .../boards_entry.txt | 8 +++--- .../boards_entry.txt | 8 +++--- .../H7A3I(G-I)TxQ_H7B3IITxQ/boards_entry.txt | 6 ++--- .../H7A3L(G-I)HxQ_H7B3LIHxQ/boards_entry.txt | 6 ++--- .../H7A3QIYxQ_H7B3QIYxQ/boards_entry.txt | 4 +-- .../H7A3V(G-I)HxQ_H7B3VIHxQ/boards_entry.txt | 6 ++--- .../H7A3V(G-I)TxQ_H7B3VITxQ/boards_entry.txt | 6 ++--- .../H7A3Z(G-I)TxQ_H7B3ZITxQ/boards_entry.txt | 6 ++--- .../boards_entry.txt | 26 +++++++++---------- .../boards_entry.txt | 16 ++++++------ .../boards_entry.txt | 12 ++++----- .../boards_entry.txt | 6 ++--- .../boards_entry.txt | 16 ++++++------ .../boards_entry.txt | 6 ++--- 18 files changed, 82 insertions(+), 82 deletions(-) diff --git a/boards.txt b/boards.txt index 1b183ce43e..cd03bbedae 100644 --- a/boards.txt +++ b/boards.txt @@ -10935,7 +10935,7 @@ GenL1.menu.pnum.GENERIC_L100C6UXA=Generic L100C6UxA GenL1.menu.pnum.GENERIC_L100C6UXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L100C6UXA.upload.maximum_data_size=10240 GenL1.menu.pnum.GENERIC_L100C6UXA.build.board=GENERIC_L100C6UXA -GenL1.menu.pnum.GENERIC_L100C6UXA.build.product_line=STM32L100xB +GenL1.menu.pnum.GENERIC_L100C6UXA.build.product_line=STM32L100xBA GenL1.menu.pnum.GENERIC_L100C6UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L100C6UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L100.svd @@ -10971,7 +10971,7 @@ GenL1.menu.pnum.GENERIC_L151C6TXA=Generic L151C6TxA GenL1.menu.pnum.GENERIC_L151C6TXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L151C6TXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L151C6TXA.build.board=GENERIC_L151C6TXA -GenL1.menu.pnum.GENERIC_L151C6TXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151C6TXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151C6TXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151C6TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -10980,7 +10980,7 @@ GenL1.menu.pnum.GENERIC_L151C8TXA=Generic L151C8TxA GenL1.menu.pnum.GENERIC_L151C8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L151C8TXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151C8TXA.build.board=GENERIC_L151C8TXA -GenL1.menu.pnum.GENERIC_L151C8TXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151C8TXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151C8TXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151C8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -10989,7 +10989,7 @@ GenL1.menu.pnum.GENERIC_L151CBTXA=Generic L151CBTxA GenL1.menu.pnum.GENERIC_L151CBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L151CBTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151CBTXA.build.board=GENERIC_L151CBTXA -GenL1.menu.pnum.GENERIC_L151CBTXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151CBTXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151CBTXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151CBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -11025,7 +11025,7 @@ GenL1.menu.pnum.GENERIC_L151C6UXA=Generic L151C6UxA GenL1.menu.pnum.GENERIC_L151C6UXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L151C6UXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L151C6UXA.build.board=GENERIC_L151C6UXA -GenL1.menu.pnum.GENERIC_L151C6UXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151C6UXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151C6UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151C6UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -11034,7 +11034,7 @@ GenL1.menu.pnum.GENERIC_L151C8UXA=Generic L151C8UxA GenL1.menu.pnum.GENERIC_L151C8UXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L151C8UXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151C8UXA.build.board=GENERIC_L151C8UXA -GenL1.menu.pnum.GENERIC_L151C8UXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151C8UXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151C8UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151C8UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -11043,7 +11043,7 @@ GenL1.menu.pnum.GENERIC_L151CBUXA=Generic L151CBUxA GenL1.menu.pnum.GENERIC_L151CBUXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L151CBUXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151CBUXA.build.board=GENERIC_L151CBUXA -GenL1.menu.pnum.GENERIC_L151CBUXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151CBUXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151CBUXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151CBUXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -11088,7 +11088,7 @@ GenL1.menu.pnum.GENERIC_L152C6TXA=Generic L152C6TxA GenL1.menu.pnum.GENERIC_L152C6TXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L152C6TXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L152C6TXA.build.board=GENERIC_L152C6TXA -GenL1.menu.pnum.GENERIC_L152C6TXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152C6TXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152C6TXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152C6TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -11097,7 +11097,7 @@ GenL1.menu.pnum.GENERIC_L152C8TXA=Generic L152C8TxA GenL1.menu.pnum.GENERIC_L152C8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L152C8TXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152C8TXA.build.board=GENERIC_L152C8TXA -GenL1.menu.pnum.GENERIC_L152C8TXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152C8TXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152C8TXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152C8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -11106,7 +11106,7 @@ GenL1.menu.pnum.GENERIC_L152CBTXA=Generic L152CBTxA GenL1.menu.pnum.GENERIC_L152CBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L152CBTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152CBTXA.build.board=GENERIC_L152CBTXA -GenL1.menu.pnum.GENERIC_L152CBTXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152CBTXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152CBTXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152CBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -11142,7 +11142,7 @@ GenL1.menu.pnum.GENERIC_L152C6UXA=Generic L152C6UxA GenL1.menu.pnum.GENERIC_L152C6UXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L152C6UXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L152C6UXA.build.board=GENERIC_L152C6UXA -GenL1.menu.pnum.GENERIC_L152C6UXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152C6UXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152C6UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152C6UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -11151,7 +11151,7 @@ GenL1.menu.pnum.GENERIC_L152C8UXA=Generic L152C8UxA GenL1.menu.pnum.GENERIC_L152C8UXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L152C8UXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152C8UXA.build.board=GENERIC_L152C8UXA -GenL1.menu.pnum.GENERIC_L152C8UXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152C8UXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152C8UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152C8UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -11160,7 +11160,7 @@ GenL1.menu.pnum.GENERIC_L152CBUXA=Generic L152CBUxA GenL1.menu.pnum.GENERIC_L152CBUXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L152CBUXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152CBUXA.build.board=GENERIC_L152CBUXA -GenL1.menu.pnum.GENERIC_L152CBUXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152CBUXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152CBUXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152CBUXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd diff --git a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/boards_entry.txt b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/boards_entry.txt index d966e8d71c..9eada14b88 100644 --- a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/boards_entry.txt +++ b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/boards_entry.txt @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H730ABIXQ=Generic H730ABIxQ GenH7.menu.pnum.GENERIC_H730ABIXQ.upload.maximum_size=131072 GenH7.menu.pnum.GENERIC_H730ABIXQ.upload.maximum_data_size=577536 GenH7.menu.pnum.GENERIC_H730ABIXQ.build.board=GENERIC_H730ABIXQ -GenH7.menu.pnum.GENERIC_H730ABIXQ.build.product_line=STM32H730xx +GenH7.menu.pnum.GENERIC_H730ABIXQ.build.product_line=STM32H730xxQ GenH7.menu.pnum.GENERIC_H730ABIXQ.build.variant=STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI GenH7.menu.pnum.GENERIC_H730ABIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H730.svd diff --git a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/boards_entry.txt b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/boards_entry.txt index 915ec178f5..8c1a57b629 100644 --- a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/boards_entry.txt +++ b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/boards_entry.txt @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H730IBKXQ=Generic H730IBKxQ GenH7.menu.pnum.GENERIC_H730IBKXQ.upload.maximum_size=131072 GenH7.menu.pnum.GENERIC_H730IBKXQ.upload.maximum_data_size=577536 GenH7.menu.pnum.GENERIC_H730IBKXQ.build.board=GENERIC_H730IBKXQ -GenH7.menu.pnum.GENERIC_H730IBKXQ.build.product_line=STM32H730xx +GenH7.menu.pnum.GENERIC_H730IBKXQ.build.product_line=STM32H730xxQ GenH7.menu.pnum.GENERIC_H730IBKXQ.build.variant=STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK GenH7.menu.pnum.GENERIC_H730IBKXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H730.svd diff --git a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/boards_entry.txt b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/boards_entry.txt index 026f7af870..f20bd0efac 100644 --- a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/boards_entry.txt +++ b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/boards_entry.txt @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H730IBTXQ=Generic H730IBTxQ GenH7.menu.pnum.GENERIC_H730IBTXQ.upload.maximum_size=131072 GenH7.menu.pnum.GENERIC_H730IBTXQ.upload.maximum_data_size=577536 GenH7.menu.pnum.GENERIC_H730IBTXQ.build.board=GENERIC_H730IBTXQ -GenH7.menu.pnum.GENERIC_H730IBTXQ.build.product_line=STM32H730xx +GenH7.menu.pnum.GENERIC_H730IBTXQ.build.product_line=STM32H730xxQ GenH7.menu.pnum.GENERIC_H730IBTXQ.build.variant=STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT GenH7.menu.pnum.GENERIC_H730IBTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H730.svd diff --git a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/boards_entry.txt b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/boards_entry.txt index 293c28e63f..0674f7119a 100644 --- a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/boards_entry.txt +++ b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/boards_entry.txt @@ -8,7 +8,7 @@ GenH7.menu.pnum.GENERIC_H7A3AGIXQ=Generic H7A3AGIxQ GenH7.menu.pnum.GENERIC_H7A3AGIXQ.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H7A3AGIXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3AGIXQ.build.board=GENERIC_H7A3AGIXQ -GenH7.menu.pnum.GENERIC_H7A3AGIXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3AGIXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3AGIXQ.build.variant=STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ GenH7.menu.pnum.GENERIC_H7A3AGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -17,7 +17,7 @@ GenH7.menu.pnum.GENERIC_H7A3AIIXQ=Generic H7A3AIIxQ GenH7.menu.pnum.GENERIC_H7A3AIIXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7A3AIIXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3AIIXQ.build.board=GENERIC_H7A3AIIXQ -GenH7.menu.pnum.GENERIC_H7A3AIIXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3AIIXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3AIIXQ.build.variant=STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ GenH7.menu.pnum.GENERIC_H7A3AIIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H7B0ABIXQ=Generic H7B0ABIxQ GenH7.menu.pnum.GENERIC_H7B0ABIXQ.upload.maximum_size=131072 GenH7.menu.pnum.GENERIC_H7B0ABIXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B0ABIXQ.build.board=GENERIC_H7B0ABIXQ -GenH7.menu.pnum.GENERIC_H7B0ABIXQ.build.product_line=STM32H7B0xx +GenH7.menu.pnum.GENERIC_H7B0ABIXQ.build.product_line=STM32H7B0xxQ GenH7.menu.pnum.GENERIC_H7B0ABIXQ.build.variant=STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ GenH7.menu.pnum.GENERIC_H7B0ABIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B0.svd @@ -35,7 +35,7 @@ GenH7.menu.pnum.GENERIC_H7B3AIIXQ=Generic H7B3AIIxQ GenH7.menu.pnum.GENERIC_H7B3AIIXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7B3AIIXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B3AIIXQ.build.board=GENERIC_H7B3AIIXQ -GenH7.menu.pnum.GENERIC_H7B3AIIXQ.build.product_line=STM32H7B3xx +GenH7.menu.pnum.GENERIC_H7B3AIIXQ.build.product_line=STM32H7B3xxQ GenH7.menu.pnum.GENERIC_H7B3AIIXQ.build.variant=STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ GenH7.menu.pnum.GENERIC_H7B3AIIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd diff --git a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/boards_entry.txt b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/boards_entry.txt index 1176e026ca..882c696a76 100644 --- a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/boards_entry.txt +++ b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/boards_entry.txt @@ -8,7 +8,7 @@ GenH7.menu.pnum.GENERIC_H7A3IGKXQ=Generic H7A3IGKxQ GenH7.menu.pnum.GENERIC_H7A3IGKXQ.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H7A3IGKXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3IGKXQ.build.board=GENERIC_H7A3IGKXQ -GenH7.menu.pnum.GENERIC_H7A3IGKXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3IGKXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3IGKXQ.build.variant=STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ GenH7.menu.pnum.GENERIC_H7A3IGKXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -17,7 +17,7 @@ GenH7.menu.pnum.GENERIC_H7A3IIKXQ=Generic H7A3IIKxQ GenH7.menu.pnum.GENERIC_H7A3IIKXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7A3IIKXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3IIKXQ.build.board=GENERIC_H7A3IIKXQ -GenH7.menu.pnum.GENERIC_H7A3IIKXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3IIKXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3IIKXQ.build.variant=STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ GenH7.menu.pnum.GENERIC_H7A3IIKXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H7B0IBKXQ=Generic H7B0IBKxQ GenH7.menu.pnum.GENERIC_H7B0IBKXQ.upload.maximum_size=131072 GenH7.menu.pnum.GENERIC_H7B0IBKXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B0IBKXQ.build.board=GENERIC_H7B0IBKXQ -GenH7.menu.pnum.GENERIC_H7B0IBKXQ.build.product_line=STM32H7B0xx +GenH7.menu.pnum.GENERIC_H7B0IBKXQ.build.product_line=STM32H7B0xxQ GenH7.menu.pnum.GENERIC_H7B0IBKXQ.build.variant=STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ GenH7.menu.pnum.GENERIC_H7B0IBKXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B0.svd @@ -35,7 +35,7 @@ GenH7.menu.pnum.GENERIC_H7B3IIKXQ=Generic H7B3IIKxQ GenH7.menu.pnum.GENERIC_H7B3IIKXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7B3IIKXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B3IIKXQ.build.board=GENERIC_H7B3IIKXQ -GenH7.menu.pnum.GENERIC_H7B3IIKXQ.build.product_line=STM32H7B3xx +GenH7.menu.pnum.GENERIC_H7B3IIKXQ.build.product_line=STM32H7B3xxQ GenH7.menu.pnum.GENERIC_H7B3IIKXQ.build.variant=STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ GenH7.menu.pnum.GENERIC_H7B3IIKXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd diff --git a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/boards_entry.txt b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/boards_entry.txt index 7d7f2129f7..63c7d5302e 100644 --- a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/boards_entry.txt +++ b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/boards_entry.txt @@ -8,7 +8,7 @@ GenH7.menu.pnum.GENERIC_H7A3IGTXQ=Generic H7A3IGTxQ GenH7.menu.pnum.GENERIC_H7A3IGTXQ.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H7A3IGTXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3IGTXQ.build.board=GENERIC_H7A3IGTXQ -GenH7.menu.pnum.GENERIC_H7A3IGTXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3IGTXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3IGTXQ.build.variant=STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ GenH7.menu.pnum.GENERIC_H7A3IGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -17,7 +17,7 @@ GenH7.menu.pnum.GENERIC_H7A3IITXQ=Generic H7A3IITxQ GenH7.menu.pnum.GENERIC_H7A3IITXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7A3IITXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3IITXQ.build.board=GENERIC_H7A3IITXQ -GenH7.menu.pnum.GENERIC_H7A3IITXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3IITXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3IITXQ.build.variant=STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ GenH7.menu.pnum.GENERIC_H7A3IITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H7B3IITXQ=Generic H7B3IITxQ GenH7.menu.pnum.GENERIC_H7B3IITXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7B3IITXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B3IITXQ.build.board=GENERIC_H7B3IITXQ -GenH7.menu.pnum.GENERIC_H7B3IITXQ.build.product_line=STM32H7B3xx +GenH7.menu.pnum.GENERIC_H7B3IITXQ.build.product_line=STM32H7B3xxQ GenH7.menu.pnum.GENERIC_H7B3IITXQ.build.variant=STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ GenH7.menu.pnum.GENERIC_H7B3IITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd diff --git a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/boards_entry.txt b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/boards_entry.txt index d87f954bbf..90990f89ce 100644 --- a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/boards_entry.txt +++ b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/boards_entry.txt @@ -8,7 +8,7 @@ GenH7.menu.pnum.GENERIC_H7A3LGHXQ=Generic H7A3LGHxQ GenH7.menu.pnum.GENERIC_H7A3LGHXQ.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H7A3LGHXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3LGHXQ.build.board=GENERIC_H7A3LGHXQ -GenH7.menu.pnum.GENERIC_H7A3LGHXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3LGHXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3LGHXQ.build.variant=STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ GenH7.menu.pnum.GENERIC_H7A3LGHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -17,7 +17,7 @@ GenH7.menu.pnum.GENERIC_H7A3LIHXQ=Generic H7A3LIHxQ GenH7.menu.pnum.GENERIC_H7A3LIHXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7A3LIHXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3LIHXQ.build.board=GENERIC_H7A3LIHXQ -GenH7.menu.pnum.GENERIC_H7A3LIHXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3LIHXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3LIHXQ.build.variant=STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ GenH7.menu.pnum.GENERIC_H7A3LIHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H7B3LIHXQ=Generic H7B3LIHxQ GenH7.menu.pnum.GENERIC_H7B3LIHXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7B3LIHXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B3LIHXQ.build.board=GENERIC_H7B3LIHXQ -GenH7.menu.pnum.GENERIC_H7B3LIHXQ.build.product_line=STM32H7B3xx +GenH7.menu.pnum.GENERIC_H7B3LIHXQ.build.product_line=STM32H7B3xxQ GenH7.menu.pnum.GENERIC_H7B3LIHXQ.build.variant=STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ GenH7.menu.pnum.GENERIC_H7B3LIHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd diff --git a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/boards_entry.txt b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/boards_entry.txt index 8a0b7ef822..36ddba7371 100644 --- a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/boards_entry.txt +++ b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/boards_entry.txt @@ -8,7 +8,7 @@ GenH7.menu.pnum.GENERIC_H7A3QIYXQ=Generic H7A3QIYxQ GenH7.menu.pnum.GENERIC_H7A3QIYXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7A3QIYXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3QIYXQ.build.board=GENERIC_H7A3QIYXQ -GenH7.menu.pnum.GENERIC_H7A3QIYXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3QIYXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3QIYXQ.build.variant=STM32H7xx/H7A3QIYxQ_H7B3QIYxQ GenH7.menu.pnum.GENERIC_H7A3QIYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -17,7 +17,7 @@ GenH7.menu.pnum.GENERIC_H7B3QIYXQ=Generic H7B3QIYxQ GenH7.menu.pnum.GENERIC_H7B3QIYXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7B3QIYXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B3QIYXQ.build.board=GENERIC_H7B3QIYXQ -GenH7.menu.pnum.GENERIC_H7B3QIYXQ.build.product_line=STM32H7B3xx +GenH7.menu.pnum.GENERIC_H7B3QIYXQ.build.product_line=STM32H7B3xxQ GenH7.menu.pnum.GENERIC_H7B3QIYXQ.build.variant=STM32H7xx/H7A3QIYxQ_H7B3QIYxQ GenH7.menu.pnum.GENERIC_H7B3QIYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd diff --git a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/boards_entry.txt b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/boards_entry.txt index b689498a13..7a6c46630b 100644 --- a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/boards_entry.txt +++ b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/boards_entry.txt @@ -8,7 +8,7 @@ GenH7.menu.pnum.GENERIC_H7A3VGHXQ=Generic H7A3VGHxQ GenH7.menu.pnum.GENERIC_H7A3VGHXQ.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H7A3VGHXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3VGHXQ.build.board=GENERIC_H7A3VGHXQ -GenH7.menu.pnum.GENERIC_H7A3VGHXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3VGHXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3VGHXQ.build.variant=STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ GenH7.menu.pnum.GENERIC_H7A3VGHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -17,7 +17,7 @@ GenH7.menu.pnum.GENERIC_H7A3VIHXQ=Generic H7A3VIHxQ GenH7.menu.pnum.GENERIC_H7A3VIHXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7A3VIHXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3VIHXQ.build.board=GENERIC_H7A3VIHXQ -GenH7.menu.pnum.GENERIC_H7A3VIHXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3VIHXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3VIHXQ.build.variant=STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ GenH7.menu.pnum.GENERIC_H7A3VIHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H7B3VIHXQ=Generic H7B3VIHxQ GenH7.menu.pnum.GENERIC_H7B3VIHXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7B3VIHXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B3VIHXQ.build.board=GENERIC_H7B3VIHXQ -GenH7.menu.pnum.GENERIC_H7B3VIHXQ.build.product_line=STM32H7B3xx +GenH7.menu.pnum.GENERIC_H7B3VIHXQ.build.product_line=STM32H7B3xxQ GenH7.menu.pnum.GENERIC_H7B3VIHXQ.build.variant=STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ GenH7.menu.pnum.GENERIC_H7B3VIHXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd diff --git a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/boards_entry.txt b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/boards_entry.txt index ea78af4d26..a2467c8ce1 100644 --- a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/boards_entry.txt +++ b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/boards_entry.txt @@ -8,7 +8,7 @@ GenH7.menu.pnum.GENERIC_H7A3VGTXQ=Generic H7A3VGTxQ GenH7.menu.pnum.GENERIC_H7A3VGTXQ.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H7A3VGTXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3VGTXQ.build.board=GENERIC_H7A3VGTXQ -GenH7.menu.pnum.GENERIC_H7A3VGTXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3VGTXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3VGTXQ.build.variant=STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ GenH7.menu.pnum.GENERIC_H7A3VGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -17,7 +17,7 @@ GenH7.menu.pnum.GENERIC_H7A3VITXQ=Generic H7A3VITxQ GenH7.menu.pnum.GENERIC_H7A3VITXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7A3VITXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3VITXQ.build.board=GENERIC_H7A3VITXQ -GenH7.menu.pnum.GENERIC_H7A3VITXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3VITXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3VITXQ.build.variant=STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ GenH7.menu.pnum.GENERIC_H7A3VITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H7B3VITXQ=Generic H7B3VITxQ GenH7.menu.pnum.GENERIC_H7B3VITXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7B3VITXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B3VITXQ.build.board=GENERIC_H7B3VITXQ -GenH7.menu.pnum.GENERIC_H7B3VITXQ.build.product_line=STM32H7B3xx +GenH7.menu.pnum.GENERIC_H7B3VITXQ.build.product_line=STM32H7B3xxQ GenH7.menu.pnum.GENERIC_H7B3VITXQ.build.variant=STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ GenH7.menu.pnum.GENERIC_H7B3VITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/boards_entry.txt b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/boards_entry.txt index a21d08b98b..19b38d844a 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/boards_entry.txt +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/boards_entry.txt @@ -8,7 +8,7 @@ GenH7.menu.pnum.GENERIC_H7A3ZGTXQ=Generic H7A3ZGTxQ GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.upload.maximum_size=1048576 GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.board=GENERIC_H7A3ZGTXQ -GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -17,7 +17,7 @@ GenH7.menu.pnum.GENERIC_H7A3ZITXQ=Generic H7A3ZITxQ GenH7.menu.pnum.GENERIC_H7A3ZITXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7A3ZITXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.board=GENERIC_H7A3ZITXQ -GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.product_line=STM32H7A3xx +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.product_line=STM32H7A3xxQ GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ GenH7.menu.pnum.GENERIC_H7A3ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd @@ -26,7 +26,7 @@ GenH7.menu.pnum.GENERIC_H7B3ZITXQ=Generic H7B3ZITxQ GenH7.menu.pnum.GENERIC_H7B3ZITXQ.upload.maximum_size=2097152 GenH7.menu.pnum.GENERIC_H7B3ZITXQ.upload.maximum_data_size=1458176 GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.board=GENERIC_H7B3ZITXQ -GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.product_line=STM32H7B3xx +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.product_line=STM32H7B3xxQ GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ GenH7.menu.pnum.GENERIC_H7B3ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd diff --git a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/boards_entry.txt b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/boards_entry.txt index 007c24b004..8e63940790 100644 --- a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/boards_entry.txt +++ b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/boards_entry.txt @@ -17,7 +17,7 @@ GenL1.menu.pnum.GENERIC_L100C6UXA=Generic L100C6UxA GenL1.menu.pnum.GENERIC_L100C6UXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L100C6UXA.upload.maximum_data_size=10240 GenL1.menu.pnum.GENERIC_L100C6UXA.build.board=GENERIC_L100C6UXA -GenL1.menu.pnum.GENERIC_L100C6UXA.build.product_line=STM32L100xB +GenL1.menu.pnum.GENERIC_L100C6UXA.build.product_line=STM32L100xBA GenL1.menu.pnum.GENERIC_L100C6UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L100C6UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L100.svd @@ -53,7 +53,7 @@ GenL1.menu.pnum.GENERIC_L151C6TXA=Generic L151C6TxA GenL1.menu.pnum.GENERIC_L151C6TXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L151C6TXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L151C6TXA.build.board=GENERIC_L151C6TXA -GenL1.menu.pnum.GENERIC_L151C6TXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151C6TXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151C6TXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151C6TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -62,7 +62,7 @@ GenL1.menu.pnum.GENERIC_L151C8TXA=Generic L151C8TxA GenL1.menu.pnum.GENERIC_L151C8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L151C8TXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151C8TXA.build.board=GENERIC_L151C8TXA -GenL1.menu.pnum.GENERIC_L151C8TXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151C8TXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151C8TXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151C8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -71,7 +71,7 @@ GenL1.menu.pnum.GENERIC_L151CBTXA=Generic L151CBTxA GenL1.menu.pnum.GENERIC_L151CBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L151CBTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151CBTXA.build.board=GENERIC_L151CBTXA -GenL1.menu.pnum.GENERIC_L151CBTXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151CBTXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151CBTXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151CBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -107,7 +107,7 @@ GenL1.menu.pnum.GENERIC_L151C6UXA=Generic L151C6UxA GenL1.menu.pnum.GENERIC_L151C6UXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L151C6UXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L151C6UXA.build.board=GENERIC_L151C6UXA -GenL1.menu.pnum.GENERIC_L151C6UXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151C6UXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151C6UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151C6UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -116,7 +116,7 @@ GenL1.menu.pnum.GENERIC_L151C8UXA=Generic L151C8UxA GenL1.menu.pnum.GENERIC_L151C8UXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L151C8UXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151C8UXA.build.board=GENERIC_L151C8UXA -GenL1.menu.pnum.GENERIC_L151C8UXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151C8UXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151C8UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151C8UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -125,7 +125,7 @@ GenL1.menu.pnum.GENERIC_L151CBUXA=Generic L151CBUxA GenL1.menu.pnum.GENERIC_L151CBUXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L151CBUXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151CBUXA.build.board=GENERIC_L151CBUXA -GenL1.menu.pnum.GENERIC_L151CBUXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151CBUXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151CBUXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L151CBUXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -161,7 +161,7 @@ GenL1.menu.pnum.GENERIC_L152C6TXA=Generic L152C6TxA GenL1.menu.pnum.GENERIC_L152C6TXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L152C6TXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L152C6TXA.build.board=GENERIC_L152C6TXA -GenL1.menu.pnum.GENERIC_L152C6TXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152C6TXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152C6TXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152C6TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -170,7 +170,7 @@ GenL1.menu.pnum.GENERIC_L152C8TXA=Generic L152C8TxA GenL1.menu.pnum.GENERIC_L152C8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L152C8TXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152C8TXA.build.board=GENERIC_L152C8TXA -GenL1.menu.pnum.GENERIC_L152C8TXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152C8TXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152C8TXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152C8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -179,7 +179,7 @@ GenL1.menu.pnum.GENERIC_L152CBTXA=Generic L152CBTxA GenL1.menu.pnum.GENERIC_L152CBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L152CBTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152CBTXA.build.board=GENERIC_L152CBTXA -GenL1.menu.pnum.GENERIC_L152CBTXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152CBTXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152CBTXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152CBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -215,7 +215,7 @@ GenL1.menu.pnum.GENERIC_L152C6UXA=Generic L152C6UxA GenL1.menu.pnum.GENERIC_L152C6UXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L152C6UXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L152C6UXA.build.board=GENERIC_L152C6UXA -GenL1.menu.pnum.GENERIC_L152C6UXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152C6UXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152C6UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152C6UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -224,7 +224,7 @@ GenL1.menu.pnum.GENERIC_L152C8UXA=Generic L152C8UxA GenL1.menu.pnum.GENERIC_L152C8UXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L152C8UXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152C8UXA.build.board=GENERIC_L152C8UXA -GenL1.menu.pnum.GENERIC_L152C8UXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152C8UXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152C8UXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152C8UXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -233,7 +233,7 @@ GenL1.menu.pnum.GENERIC_L152CBUXA=Generic L152CBUxA GenL1.menu.pnum.GENERIC_L152CBUXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L152CBUXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152CBUXA.build.board=GENERIC_L152CBUXA -GenL1.menu.pnum.GENERIC_L152CBUXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152CBUXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152CBUXA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) GenL1.menu.pnum.GENERIC_L152CBUXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd diff --git a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/boards_entry.txt b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/boards_entry.txt index 60d457a4a9..7944e25d51 100644 --- a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/boards_entry.txt +++ b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/boards_entry.txt @@ -26,7 +26,7 @@ GenL1.menu.pnum.GENERIC_L100R8TXA=Generic L100R8TxA GenL1.menu.pnum.GENERIC_L100R8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L100R8TXA.upload.maximum_data_size=10240 GenL1.menu.pnum.GENERIC_L100R8TXA.build.board=GENERIC_L100R8TXA -GenL1.menu.pnum.GENERIC_L100R8TXA.build.product_line=STM32L100xB +GenL1.menu.pnum.GENERIC_L100R8TXA.build.product_line=STM32L100xBA GenL1.menu.pnum.GENERIC_L100R8TXA.build.variant=STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A) GenL1.menu.pnum.GENERIC_L100R8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L100.svd @@ -35,7 +35,7 @@ GenL1.menu.pnum.GENERIC_L100RBTXA=Generic L100RBTxA GenL1.menu.pnum.GENERIC_L100RBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L100RBTXA.upload.maximum_data_size=10240 GenL1.menu.pnum.GENERIC_L100RBTXA.build.board=GENERIC_L100RBTXA -GenL1.menu.pnum.GENERIC_L100RBTXA.build.product_line=STM32L100xB +GenL1.menu.pnum.GENERIC_L100RBTXA.build.product_line=STM32L100xBA GenL1.menu.pnum.GENERIC_L100RBTXA.build.variant=STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A) GenL1.menu.pnum.GENERIC_L100RBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L100.svd @@ -71,7 +71,7 @@ GenL1.menu.pnum.GENERIC_L151R6TXA=Generic L151R6TxA GenL1.menu.pnum.GENERIC_L151R6TXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L151R6TXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L151R6TXA.build.board=GENERIC_L151R6TXA -GenL1.menu.pnum.GENERIC_L151R6TXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151R6TXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151R6TXA.build.variant=STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A) GenL1.menu.pnum.GENERIC_L151R6TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -80,7 +80,7 @@ GenL1.menu.pnum.GENERIC_L151R8TXA=Generic L151R8TxA GenL1.menu.pnum.GENERIC_L151R8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L151R8TXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151R8TXA.build.board=GENERIC_L151R8TXA -GenL1.menu.pnum.GENERIC_L151R8TXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151R8TXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151R8TXA.build.variant=STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A) GenL1.menu.pnum.GENERIC_L151R8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -89,7 +89,7 @@ GenL1.menu.pnum.GENERIC_L151RBTXA=Generic L151RBTxA GenL1.menu.pnum.GENERIC_L151RBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L151RBTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151RBTXA.build.board=GENERIC_L151RBTXA -GenL1.menu.pnum.GENERIC_L151RBTXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151RBTXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151RBTXA.build.variant=STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A) GenL1.menu.pnum.GENERIC_L151RBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -125,7 +125,7 @@ GenL1.menu.pnum.GENERIC_L152R6TXA=Generic L152R6TxA GenL1.menu.pnum.GENERIC_L152R6TXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L152R6TXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L152R6TXA.build.board=GENERIC_L152R6TXA -GenL1.menu.pnum.GENERIC_L152R6TXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152R6TXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152R6TXA.build.variant=STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A) GenL1.menu.pnum.GENERIC_L152R6TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -134,7 +134,7 @@ GenL1.menu.pnum.GENERIC_L152R8TXA=Generic L152R8TxA GenL1.menu.pnum.GENERIC_L152R8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L152R8TXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152R8TXA.build.board=GENERIC_L152R8TXA -GenL1.menu.pnum.GENERIC_L152R8TXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152R8TXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152R8TXA.build.variant=STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A) GenL1.menu.pnum.GENERIC_L152R8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -143,7 +143,7 @@ GenL1.menu.pnum.GENERIC_L152RBTXA=Generic L152RBTxA GenL1.menu.pnum.GENERIC_L152RBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L152RBTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152RBTXA.build.board=GENERIC_L152RBTXA -GenL1.menu.pnum.GENERIC_L152RBTXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152RBTXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152RBTXA.build.variant=STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A) GenL1.menu.pnum.GENERIC_L152RBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd diff --git a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/boards_entry.txt b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/boards_entry.txt index 4eb18f5b81..6647d6ed1c 100644 --- a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/boards_entry.txt +++ b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/boards_entry.txt @@ -35,7 +35,7 @@ GenL1.menu.pnum.GENERIC_L151R6HXA=Generic L151R6HxA GenL1.menu.pnum.GENERIC_L151R6HXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L151R6HXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L151R6HXA.build.board=GENERIC_L151R6HXA -GenL1.menu.pnum.GENERIC_L151R6HXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151R6HXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151R6HXA.build.variant=STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A) GenL1.menu.pnum.GENERIC_L151R6HXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -44,7 +44,7 @@ GenL1.menu.pnum.GENERIC_L151R8HXA=Generic L151R8HxA GenL1.menu.pnum.GENERIC_L151R8HXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L151R8HXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151R8HXA.build.board=GENERIC_L151R8HXA -GenL1.menu.pnum.GENERIC_L151R8HXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151R8HXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151R8HXA.build.variant=STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A) GenL1.menu.pnum.GENERIC_L151R8HXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -53,7 +53,7 @@ GenL1.menu.pnum.GENERIC_L151RBHXA=Generic L151RBHxA GenL1.menu.pnum.GENERIC_L151RBHXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L151RBHXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151RBHXA.build.board=GENERIC_L151RBHXA -GenL1.menu.pnum.GENERIC_L151RBHXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151RBHXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151RBHXA.build.variant=STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A) GenL1.menu.pnum.GENERIC_L151RBHXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -89,7 +89,7 @@ GenL1.menu.pnum.GENERIC_L152R6HXA=Generic L152R6HxA GenL1.menu.pnum.GENERIC_L152R6HXA.upload.maximum_size=32768 GenL1.menu.pnum.GENERIC_L152R6HXA.upload.maximum_data_size=16384 GenL1.menu.pnum.GENERIC_L152R6HXA.build.board=GENERIC_L152R6HXA -GenL1.menu.pnum.GENERIC_L152R6HXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152R6HXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152R6HXA.build.variant=STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A) GenL1.menu.pnum.GENERIC_L152R6HXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -98,7 +98,7 @@ GenL1.menu.pnum.GENERIC_L152R8HXA=Generic L152R8HxA GenL1.menu.pnum.GENERIC_L152R8HXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L152R8HXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152R8HXA.build.board=GENERIC_L152R8HXA -GenL1.menu.pnum.GENERIC_L152R8HXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152R8HXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152R8HXA.build.variant=STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A) GenL1.menu.pnum.GENERIC_L152R8HXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -107,7 +107,7 @@ GenL1.menu.pnum.GENERIC_L152RBHXA=Generic L152RBHxA GenL1.menu.pnum.GENERIC_L152RBHXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L152RBHXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152RBHXA.build.board=GENERIC_L152RBHXA -GenL1.menu.pnum.GENERIC_L152RBHXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152RBHXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152RBHXA.build.variant=STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A) GenL1.menu.pnum.GENERIC_L152RBHXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd diff --git a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/boards_entry.txt b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/boards_entry.txt index 769fda1e49..4d8f137017 100644 --- a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/boards_entry.txt +++ b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/boards_entry.txt @@ -17,7 +17,7 @@ GenL1.menu.pnum.GENERIC_L151RCTXA=Generic L151RCTxA GenL1.menu.pnum.GENERIC_L151RCTXA.upload.maximum_size=262144 GenL1.menu.pnum.GENERIC_L151RCTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151RCTXA.build.board=GENERIC_L151RCTXA -GenL1.menu.pnum.GENERIC_L151RCTXA.build.product_line=STM32L151xC +GenL1.menu.pnum.GENERIC_L151RCTXA.build.product_line=STM32L151xCA GenL1.menu.pnum.GENERIC_L151RCTXA.build.variant=STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A) GenL1.menu.pnum.GENERIC_L151RCTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -53,7 +53,7 @@ GenL1.menu.pnum.GENERIC_L152RCTXA=Generic L152RCTxA GenL1.menu.pnum.GENERIC_L152RCTXA.upload.maximum_size=262144 GenL1.menu.pnum.GENERIC_L152RCTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152RCTXA.build.board=GENERIC_L152RCTXA -GenL1.menu.pnum.GENERIC_L152RCTXA.build.product_line=STM32L152xC +GenL1.menu.pnum.GENERIC_L152RCTXA.build.product_line=STM32L152xCA GenL1.menu.pnum.GENERIC_L152RCTXA.build.variant=STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A) GenL1.menu.pnum.GENERIC_L152RCTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -80,7 +80,7 @@ GenL1.menu.pnum.GENERIC_L162RCTXA=Generic L162RCTxA GenL1.menu.pnum.GENERIC_L162RCTXA.upload.maximum_size=262144 GenL1.menu.pnum.GENERIC_L162RCTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L162RCTXA.build.board=GENERIC_L162RCTXA -GenL1.menu.pnum.GENERIC_L162RCTXA.build.product_line=STM32L162xC +GenL1.menu.pnum.GENERIC_L162RCTXA.build.product_line=STM32L162xCA GenL1.menu.pnum.GENERIC_L162RCTXA.build.variant=STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A) GenL1.menu.pnum.GENERIC_L162RCTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L162.svd diff --git a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/boards_entry.txt b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/boards_entry.txt index 198745b477..65456d07d9 100644 --- a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/boards_entry.txt +++ b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/boards_entry.txt @@ -26,7 +26,7 @@ GenL1.menu.pnum.GENERIC_L151V8HXA=Generic L151V8HxA GenL1.menu.pnum.GENERIC_L151V8HXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L151V8HXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151V8HXA.build.board=GENERIC_L151V8HXA -GenL1.menu.pnum.GENERIC_L151V8HXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151V8HXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151V8HXA.build.variant=STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A) GenL1.menu.pnum.GENERIC_L151V8HXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -35,7 +35,7 @@ GenL1.menu.pnum.GENERIC_L151VBHXA=Generic L151VBHxA GenL1.menu.pnum.GENERIC_L151VBHXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L151VBHXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151VBHXA.build.board=GENERIC_L151VBHXA -GenL1.menu.pnum.GENERIC_L151VBHXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151VBHXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151VBHXA.build.variant=STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A) GenL1.menu.pnum.GENERIC_L151VBHXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -62,7 +62,7 @@ GenL1.menu.pnum.GENERIC_L151V8TXA=Generic L151V8TxA GenL1.menu.pnum.GENERIC_L151V8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L151V8TXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151V8TXA.build.board=GENERIC_L151V8TXA -GenL1.menu.pnum.GENERIC_L151V8TXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151V8TXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151V8TXA.build.variant=STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A) GenL1.menu.pnum.GENERIC_L151V8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -71,7 +71,7 @@ GenL1.menu.pnum.GENERIC_L151VBTXA=Generic L151VBTxA GenL1.menu.pnum.GENERIC_L151VBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L151VBTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151VBTXA.build.board=GENERIC_L151VBTXA -GenL1.menu.pnum.GENERIC_L151VBTXA.build.product_line=STM32L151xB +GenL1.menu.pnum.GENERIC_L151VBTXA.build.product_line=STM32L151xBA GenL1.menu.pnum.GENERIC_L151VBTXA.build.variant=STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A) GenL1.menu.pnum.GENERIC_L151VBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -98,7 +98,7 @@ GenL1.menu.pnum.GENERIC_L152V8HXA=Generic L152V8HxA GenL1.menu.pnum.GENERIC_L152V8HXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L152V8HXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152V8HXA.build.board=GENERIC_L152V8HXA -GenL1.menu.pnum.GENERIC_L152V8HXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152V8HXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152V8HXA.build.variant=STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A) GenL1.menu.pnum.GENERIC_L152V8HXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -107,7 +107,7 @@ GenL1.menu.pnum.GENERIC_L152VBHXA=Generic L152VBHxA GenL1.menu.pnum.GENERIC_L152VBHXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L152VBHXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152VBHXA.build.board=GENERIC_L152VBHXA -GenL1.menu.pnum.GENERIC_L152VBHXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152VBHXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152VBHXA.build.variant=STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A) GenL1.menu.pnum.GENERIC_L152VBHXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -134,7 +134,7 @@ GenL1.menu.pnum.GENERIC_L152V8TXA=Generic L152V8TxA GenL1.menu.pnum.GENERIC_L152V8TXA.upload.maximum_size=65536 GenL1.menu.pnum.GENERIC_L152V8TXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152V8TXA.build.board=GENERIC_L152V8TXA -GenL1.menu.pnum.GENERIC_L152V8TXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152V8TXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152V8TXA.build.variant=STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A) GenL1.menu.pnum.GENERIC_L152V8TXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -143,7 +143,7 @@ GenL1.menu.pnum.GENERIC_L152VBTXA=Generic L152VBTxA GenL1.menu.pnum.GENERIC_L152VBTXA.upload.maximum_size=131072 GenL1.menu.pnum.GENERIC_L152VBTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152VBTXA.build.board=GENERIC_L152VBTXA -GenL1.menu.pnum.GENERIC_L152VBTXA.build.product_line=STM32L152xB +GenL1.menu.pnum.GENERIC_L152VBTXA.build.product_line=STM32L152xBA GenL1.menu.pnum.GENERIC_L152VBTXA.build.variant=STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A) GenL1.menu.pnum.GENERIC_L152VBTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd diff --git a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/boards_entry.txt b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/boards_entry.txt index 621d46a2bb..823719adae 100644 --- a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/boards_entry.txt +++ b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/boards_entry.txt @@ -26,7 +26,7 @@ GenL1.menu.pnum.GENERIC_L151VCTXA=Generic L151VCTxA GenL1.menu.pnum.GENERIC_L151VCTXA.upload.maximum_size=262144 GenL1.menu.pnum.GENERIC_L151VCTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L151VCTXA.build.board=GENERIC_L151VCTXA -GenL1.menu.pnum.GENERIC_L151VCTXA.build.product_line=STM32L151xC +GenL1.menu.pnum.GENERIC_L151VCTXA.build.product_line=STM32L151xCA GenL1.menu.pnum.GENERIC_L151VCTXA.build.variant=STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A) GenL1.menu.pnum.GENERIC_L151VCTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd @@ -53,7 +53,7 @@ GenL1.menu.pnum.GENERIC_L152VCTXA=Generic L152VCTxA GenL1.menu.pnum.GENERIC_L152VCTXA.upload.maximum_size=262144 GenL1.menu.pnum.GENERIC_L152VCTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L152VCTXA.build.board=GENERIC_L152VCTXA -GenL1.menu.pnum.GENERIC_L152VCTXA.build.product_line=STM32L152xC +GenL1.menu.pnum.GENERIC_L152VCTXA.build.product_line=STM32L152xCA GenL1.menu.pnum.GENERIC_L152VCTXA.build.variant=STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A) GenL1.menu.pnum.GENERIC_L152VCTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd @@ -80,7 +80,7 @@ GenL1.menu.pnum.GENERIC_L162VCTXA=Generic L162VCTxA GenL1.menu.pnum.GENERIC_L162VCTXA.upload.maximum_size=262144 GenL1.menu.pnum.GENERIC_L162VCTXA.upload.maximum_data_size=32768 GenL1.menu.pnum.GENERIC_L162VCTXA.build.board=GENERIC_L162VCTXA -GenL1.menu.pnum.GENERIC_L162VCTXA.build.product_line=STM32L162xC +GenL1.menu.pnum.GENERIC_L162VCTXA.build.product_line=STM32L162xCA GenL1.menu.pnum.GENERIC_L162VCTXA.build.variant=STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A) GenL1.menu.pnum.GENERIC_L162VCTXA.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L162.svd From 5f34649441371c81950828717ec62acfc8e8e85e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 14 Jan 2025 17:07:40 +0100 Subject: [PATCH 070/141] feat(h7): add a message for the system power supply if it is not defined. Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/hw_config.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/libraries/SrcWrapper/src/stm32/hw_config.c b/libraries/SrcWrapper/src/stm32/hw_config.c index 8b7f7c61cc..efeee013de 100644 --- a/libraries/SrcWrapper/src/stm32/hw_config.c +++ b/libraries/SrcWrapper/src/stm32/hw_config.c @@ -21,6 +21,28 @@ extern "C" { #endif +#if defined(STM32H7xx) +#if !defined(USE_PWR_LDO_SUPPLY) && !defined(USE_PWR_DIRECT_SMPS_SUPPLY) &&\ +!defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) && !defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) &&\ +!defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && !defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) &&\ +!defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && !defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) &&\ +!defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) +#pragma message "\n\ +Configure the system power supply according to the\n\ +definition to be used at compilation preprocessing level.\n\ +The application shall set one of the following configuration option:\n\ + - USE_PWR_LDO_SUPPLY\n\ + - USE_PWR_DIRECT_SMPS_SUPPLY\n\ + - USE_PWR_EXTERNAL_SOURCE_SUPPLY\n\ + - USE_PWR_SMPS_1V8_SUPPLIES_LDO\n\ + - USE_PWR_SMPS_2V5_SUPPLIES_LDO\n\ + - USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO\n\ + - USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO\n\ + - USE_PWR_SMPS_1V8_SUPPLIES_EXT\n\ + - USE_PWR_SMPS_2V5_SUPPLIES_EXT\n" +#endif +#endif + #if defined(HAL_CRC_MODULE_ENABLED) CRC_HandleTypeDef hcrc = {.Instance = #if defined(CRC2_BASE) From 4759316ea20db8d728dc9e50bcb1d58b179e021b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 13 Jan 2025 11:32:36 +0100 Subject: [PATCH 071/141] variants(h7): add generic H7A3Z(G-I)TxQ and H7B3ZITxQ Signed-off-by: Frederic Pillon --- README.md | 2 + boards.txt | 27 ++ cmake/boards_db.cmake | 246 ++++++++++++++++++ .../H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c | 82 +++++- .../H7A3Z(G-I)TxQ_H7B3ZITxQ/ldscript.ld | 179 +++++++++++++ 5 files changed, 534 insertions(+), 2 deletions(-) create mode 100644 variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/ldscript.ld diff --git a/README.md b/README.md index 85af2dd6a6..fcd8fdbaf2 100644 --- a/README.md +++ b/README.md @@ -604,8 +604,10 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H757XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H7A3VGHX
                                                                                STM32H7A3VGTX | Generic Board | *2.8.0* | | | :green_heart: | STM32H7A3VIHX
                                                                                STM32H7A3VITX | Generic Board | *2.8.0* | | +| :yellow_heart: | STM32H7A3ZGTxQ
                                                                                STM32H7A3ZITxQ | Generic Board | **2.10.0** | | | :green_heart: | STM32H7B0VBTX | Generic Board | *2.8.0* | | | :green_heart: | STM32H7B3VIHX
                                                                                STM32H7B3VITX | Generic Board | *2.8.0* | | +| :yellow_heart: | STM32H7B3ZITxQ | Generic Board | **2.10.0** | | ### Generic STM32L0 boards diff --git a/boards.txt b/boards.txt index cd03bbedae..3c931e235d 100644 --- a/boards.txt +++ b/boards.txt @@ -9550,6 +9550,24 @@ GenH7.menu.pnum.GENERIC_H7A3VITX.build.product_line=STM32H7A3xx GenH7.menu.pnum.GENERIC_H7A3VITX.build.variant=STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T) GenH7.menu.pnum.GENERIC_H7A3VITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd +# Generic H7A3ZGTxQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ=Generic H7A3ZGTxQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.upload.maximum_data_size=1048576 +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.board=GENERIC_H7A3ZGTXQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.product_line=STM32H7A3xxQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd + +# Generic H7A3ZITxQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ=Generic H7A3ZITxQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.upload.maximum_data_size=1048576 +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.board=GENERIC_H7A3ZITXQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.product_line=STM32H7A3xxQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd + # Generic H7B0VBTx GenH7.menu.pnum.GENERIC_H7B0VBTX=Generic H7B0VBTx GenH7.menu.pnum.GENERIC_H7B0VBTX.upload.maximum_size=131072 @@ -9577,6 +9595,15 @@ GenH7.menu.pnum.GENERIC_H7B3VITX.build.product_line=STM32H7B3xx GenH7.menu.pnum.GENERIC_H7B3VITX.build.variant=STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T) GenH7.menu.pnum.GENERIC_H7B3VITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd +# Generic H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ=Generic H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.upload.maximum_data_size=1048576 +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.board=GENERIC_H7B3ZITXQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.product_line=STM32H7B3xxQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd + # Upload menu GenH7.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenH7.menu.upload_method.swdMethod.upload.protocol=swd diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 2c5a97e85e..4db190a96b 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -79836,6 +79836,170 @@ target_compile_options(GENERIC_H7A3VITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H7A3ZGTXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_H7A3ZGTXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ") +set(GENERIC_H7A3ZGTXQ_MAXSIZE 1048576) +set(GENERIC_H7A3ZGTXQ_MAXDATASIZE 1048576) +set(GENERIC_H7A3ZGTXQ_MCU cortex-m7) +set(GENERIC_H7A3ZGTXQ_FPCONF "-") +add_library(GENERIC_H7A3ZGTXQ INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H7A3xxQ " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7A3ZGTXQ_MCU} +) +target_compile_definitions(GENERIC_H7A3ZGTXQ INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H7A3ZGTXQ" + "BOARD_NAME=\"GENERIC_H7A3ZGTXQ\"" + "BOARD_ID=GENERIC_H7A3ZGTXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H7A3ZGTXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H7A3ZGTXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_H7A3ZGTXQ INTERFACE + "LINKER:--default-script=${GENERIC_H7A3ZGTXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=1048576" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7A3ZGTXQ_MCU} +) + +add_library(GENERIC_H7A3ZGTXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZGTXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H7A3ZGTXQ_serial_none INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H7A3ZGTXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H7A3ZGTXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H7A3ZGTXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H7A3ZGTXQ_usb_none INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZGTXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZGTXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H7A3ZGTXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H7A3ZITXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_H7A3ZITXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ") +set(GENERIC_H7A3ZITXQ_MAXSIZE 2097152) +set(GENERIC_H7A3ZITXQ_MAXDATASIZE 1048576) +set(GENERIC_H7A3ZITXQ_MCU cortex-m7) +set(GENERIC_H7A3ZITXQ_FPCONF "-") +add_library(GENERIC_H7A3ZITXQ INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H7A3xxQ " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7A3ZITXQ_MCU} +) +target_compile_definitions(GENERIC_H7A3ZITXQ INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H7A3ZITXQ" + "BOARD_NAME=\"GENERIC_H7A3ZITXQ\"" + "BOARD_ID=GENERIC_H7A3ZITXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H7A3ZITXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H7A3ZITXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_H7A3ZITXQ INTERFACE + "LINKER:--default-script=${GENERIC_H7A3ZITXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=1048576" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7A3ZITXQ_MCU} +) + +add_library(GENERIC_H7A3ZITXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZITXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H7A3ZITXQ_serial_none INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H7A3ZITXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H7A3ZITXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H7A3ZITXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H7A3ZITXQ_usb_none INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZITXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZITXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H7A3ZITXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H7B0VBTX # ----------------------------------------------------------------------------- @@ -80082,6 +80246,88 @@ target_compile_options(GENERIC_H7B3VITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H7B3ZITXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_H7B3ZITXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ") +set(GENERIC_H7B3ZITXQ_MAXSIZE 2097152) +set(GENERIC_H7B3ZITXQ_MAXDATASIZE 1048576) +set(GENERIC_H7B3ZITXQ_MCU cortex-m7) +set(GENERIC_H7B3ZITXQ_FPCONF "-") +add_library(GENERIC_H7B3ZITXQ INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H7B3xxQ " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7B3ZITXQ_MCU} +) +target_compile_definitions(GENERIC_H7B3ZITXQ INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H7B3ZITXQ" + "BOARD_NAME=\"GENERIC_H7B3ZITXQ\"" + "BOARD_ID=GENERIC_H7B3ZITXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H7B3ZITXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H7B3ZITXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_H7B3ZITXQ INTERFACE + "LINKER:--default-script=${GENERIC_H7B3ZITXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=1048576" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7B3ZITXQ_MCU} +) + +add_library(GENERIC_H7B3ZITXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H7B3ZITXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H7B3ZITXQ_serial_none INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H7B3ZITXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H7B3ZITXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H7B3ZITXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H7B3ZITXQ_usb_none INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H7B3ZITXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H7B3ZITXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H7B3ZITXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_L010C6TX # ----------------------------------------------------------------------------- diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c index 9fd6c852a1..668f3dddf0 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c @@ -21,8 +21,86 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /*AXI clock gating */ + RCC->CKGAENR = 0xFFFFFFFF; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = 64; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 35; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) { + Error_Handler(); + } + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL3.PLL3M = 4; + PeriphClkInitStruct.PLL3.PLL3N = 8; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 4; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3; + PeriphClkInitStruct.PLL2.PLL2M = 4; + PeriphClkInitStruct.PLL2.PLL2N = 10; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/ldscript.ld b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/ldscript.ld new file mode 100644 index 0000000000..c1f8244ffa --- /dev/null +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/ldscript.ld @@ -0,0 +1,179 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7 series +** 2048Kbytes FLASH and 1376Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +**************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET + DTCMRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + DTCMRAM2 (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = LD_MAX_DATA_SIZE + RAM_CD (xrw) : ORIGIN = 0x30000000, LENGTH = 128K + RAM_SRD (xrw) : ORIGIN = 0x38000000, LENGTH = 32K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From 296fa63e29930afc4733bc7d28722f1056af795f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 15 Jan 2025 08:54:17 +0100 Subject: [PATCH 072/141] variants(h7): add Nucleo-H7A3ZI-Q Fixes #2632. Signed-off-by: Frederic Pillon --- README.md | 1 + boards.txt | 16 ++ .../variant_NUCLEO_H7A3ZI_Q.cpp | 235 +++++++++++++++ .../variant_NUCLEO_H7A3ZI_Q.h | 269 ++++++++++++++++++ 4 files changed, 521 insertions(+) create mode 100644 variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.cpp create mode 100644 variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.h diff --git a/README.md b/README.md index fcd8fdbaf2..36dab505d7 100644 --- a/README.md +++ b/README.md @@ -113,6 +113,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H723ZG | [Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html) | *2.4.0* | | | :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 | | :green_heart: | STM32H753ZI | [Nucleo H753ZI](https://www.st.com/en/evaluation-tools/nucleo-h753zi.html) | *2.7.0* | | +| :yellow_heart: | STM32H7A3ZITxQ | [NNUCLEO-H7A3ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html) | **2.10.0** | | | :green_heart: | STM32L496ZG | [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) | *1.3.0* | | | :green_heart: | STM32L496ZG-P | [Nucleo L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) | *1.3.0* | | | :green_heart: | STM32L4R5ZI | [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) | *1.4.0* | | diff --git a/boards.txt b/boards.txt index 3c931e235d..0aee1594ac 100644 --- a/boards.txt +++ b/boards.txt @@ -273,6 +273,22 @@ Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.variant_h=variant_NUCLEO_H753ZI.h Nucleo_144.menu.pnum.NUCLEO_H753ZI.openocd.target=stm32h7x Nucleo_144.menu.pnum.NUCLEO_H753ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd +# NUCLEO_H7A3ZI_Q +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q=Nucleo H7A3ZI-Q +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.node=NOD_H7A3ZIQ +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.upload.maximum_size=2097152 +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.upload.maximum_data_size=1048576 +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.mcu=cortex-m7 +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.float-abi=-mfloat-abi=hard +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.board=NUCLEO_H7A3ZI_Q +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.series=STM32H7xx +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.product_line=STM32H7A3xxQ +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.variant_h=variant_NUCLEO_H7A3ZI_Q.h +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.openocd.target=stm32h7x +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd + # NUCLEO_L496ZG board Nucleo_144.menu.pnum.NUCLEO_L496ZG=Nucleo L496ZG Nucleo_144.menu.pnum.NUCLEO_L496ZG.node=NODE_L496ZG diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.cpp b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.cpp new file mode 100644 index 0000000000..91bc1e4ca8 --- /dev/null +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.cpp @@ -0,0 +1,235 @@ +/* + ******************************************************************************* + * Copyright (c) 2022, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_NUCLEO_H7A3ZI_Q) +#include "pins_arduino.h" + +// Pin number +const PinName digitalPin[] = { + PB_7, + PB_6, + PG_14, + PE_13, + PE_14, + PE_11, + PA_8, + PG_12, + PG_9, + PD_15, + PD_14, + PA_7, + PA_6, + PA_5, + PB_9, + PB_8, + PC_6, + PB_15, + PB_13, + PB_12, + PA_15, + PC_7, + PB_5, + PB_3, + PA_4, + PB_4, + PG_6, + PB_2, + PD_13, + PD_12, + PD_11, + PE_2, + PA_0, + PB_0, + PE_0, + PB_11, + PB_10, + PE_15, + PE_6, + PE_12, + PE_10, + PE_7, + PE_8, + PC_8, + PC_9, + PC_10, + PC_11, + PC_12, + PD_2, + PG_10, + PG_8, + PD_7, + PD_6, + PD_5, + PD_4, + PD_3, + PE_2, + PE_4, + PE_5, + PE_6, + PE_3, + PF_8, + PF_7, + PF_9, + PD_10, + PB_14, + PD_1, + PD_0, + PF_15, + PF_14, + PB_5, + PE_9, + PB_2, + PA_3, + PC_0, + PC_3_C, + PB_1, + PC_2_C, + PF_11, + PC_1, + PC_5, + PA_2, + PA_1, + PA_9, + PA_10, + PA_11, + PA_12, + PA_13, + PA_14, + PC_4, + PC_13, + PC_14, + PC_15, + PD_8, + PD_9, + PE_1, + PF_6, + PF_10, + PG_7, + PG_11, + PG_13, + PH_0, + PH_1 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 73, // A0 + 74, // A1 + 75, // A2 + 76, // A3 + 77, // A4 + 78, // A5 + 79, // A6 + 80, // A7 + 81, // A8 + 82, // A9 + 89, // A10 + 11, // A11 + 12, // A12 + 13, // A13 + 24, // A14 + 32, // A15 + 33, // A16 + 69 // A17 +}; + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /*AXI clock gating */ + RCC->CKGAENR = 0xFFFFFFFF; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 70; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL3.PLL3M = 1; + PeriphClkInitStruct.PLL3.PLL3N = 24; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 6; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } + +} + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_H7A3ZI_Q */ diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.h b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.h new file mode 100644 index 0000000000..e7cb370ae4 --- /dev/null +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.h @@ -0,0 +1,269 @@ +/* + ******************************************************************************* + * Copyright (c) 2022, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +// See UM2408, Figure 18. NUCLEO-H7A3ZI-Q extension connectors +// CN10 right Arduino Uno connector +#define PB7 0 +#define PB6 1 +#define PG14 2 +#define PE13 3 +#define PE14 4 +#define PE11 5 +#define PA8 6 +#define PG12 7 +// CN7 right Arduino Uno connector +#define PG9 8 +#define PD15 9 +#define PD14 10 +#define PA7 PIN_A11 +#define PA6 PIN_A12 +#define PA5 PIN_A13 +#define PB9 14 +#define PB8 15 +// CN7 left +#define PC6 16 +#define PB15 17 +#define PB13 18 +#define PB12 19 +#define PA15 20 +#define PC7 21 +#define PB5 22 +#define PB3 23 +#define PA4 PIN_A14 +#define PB4 25 +// CN10 Left +#define PG6 26 +#define PB2 27 +#define PD13 28 +#define PD12 29 +#define PD11 30 +#define PE2 31 +#define PA0 PIN_A15 +#define PB0 PIN_A16 +#define PE0 34 +// CN10 Right +#define PB11 35 +#define PB10 36 +#define PE15 37 +#define PE6 38 +#define PE12 39 +#define PE10 40 +#define PE7 41 +#define PE8 42 +// CN8 Left +#define PC8 43 +#define PC9 44 +#define PC10 45 +#define PC11 46 +#define PC12 47 +#define PD2 48 +#define PG10 49 +#define PG8 50 +// CN9 Left +#define PD7 51 +#define PD6 52 +#define PD5 53 +#define PD4 54 +#define PD3 55 +// 56 is PE2 (31) +#define PE4 57 +#define PE5 58 +// 59 is PE6 (38) +#define PE3 60 +#define PF8 61 +#define PF7 62 +#define PF9 63 +#define PD10 64 +// CN9 Right +#define PB14 65 +#define PD1 66 +#define PD0 67 +#define PF15 68 +#define PF14 PIN_A17 +// 70 is PB5 (22) +#define PE9 71 +// 72 is PB2 (27) +#define PA3 PIN_A0 +#define PC0 PIN_A1 +#define PC3_C PIN_A2 +#define PB1 PIN_A3 +#define PC2_C PIN_A4 +#define PF11 PIN_A5 +// CN7 left (analog part) +#define PC1 PIN_A6 +#define PC5 PIN_A7 +#define PA2 PIN_A8 +// ST morpho +#define PA1 PIN_A9 +#define PA9 83 +#define PA10 84 +#define PA11 85 +#define PA12 86 +#define PA13 87 +#define PA14 88 +#define PC4 PIN_A10 +#define PC13 90 +#define PC14 91 +#define PC15 92 +#define PD8 93 +#define PD9 94 +#define PE1 95 +#define PF6 96 +#define PF10 97 +#define PG7 98 +#define PG11 99 +#define PG13 100 +#define PH0 101 +#define PH1 102 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) + +#define NUM_DIGITAL_PINS 103 +#define NUM_DUALPAD_PINS 2 +#define NUM_ANALOG_INPUTS 18 + +// On-board LED pin number +#define LED_GREEN PB0 // LD1 +#define LED_YELLOW PE1 // LD2 +#define LED_RED PB14 // LD3 +#ifndef LED_BUILTIN + #define LED_BUILTIN LED_GREEN +#endif + + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 3 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PD9 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PD8 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// HSE default value is 25MHz in HAL +// By default HSE_BYPASS is based on HSI/2 from STLink +#ifndef HSE_BYPASS_NOT_USED + #define HSE_VALUE 8000000 +#endif + +#define USE_PWR_DIRECT_SMPS_SUPPLY + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #define SERIAL_PORT_MONITOR Serial + #define SERIAL_PORT_HARDWARE Serial +#endif From 76782015a99dd3fe0d7bea62b5628d02871523f4 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 10 Jan 2025 11:18:19 +0100 Subject: [PATCH 073/141] system(U5) update STM32U5xx HAL Drivers to v1.6.1 Included in STM32CubeU5 FW v1.7.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 84 +- .../STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h | 38 +- .../Inc/stm32u5xx_hal_comp.h | 10 +- .../Inc/stm32u5xx_hal_cordic.h | 21 +- .../Inc/stm32u5xx_hal_cortex.h | 70 +- .../Inc/stm32u5xx_hal_cryp.h | 28 +- .../Inc/stm32u5xx_hal_dac.h | 11 +- .../Inc/stm32u5xx_hal_dcmi.h | 2 +- .../Inc/stm32u5xx_hal_def.h | 4 +- .../Inc/stm32u5xx_hal_dma.h | 1 - .../Inc/stm32u5xx_hal_dsi.h | 6 +- .../Inc/stm32u5xx_hal_fdcan.h | 4 +- .../Inc/stm32u5xx_hal_fmac.h | 12 +- .../Inc/stm32u5xx_hal_gfxmmu.h | 14 +- .../Inc/stm32u5xx_hal_hash.h | 60 +- .../Inc/stm32u5xx_hal_hash_ex.h | 64 +- .../Inc/stm32u5xx_hal_lptim.h | 2 + .../Inc/stm32u5xx_hal_mmc.h | 4 +- .../Inc/stm32u5xx_hal_mmc_ex.h | 6 +- .../Inc/stm32u5xx_hal_pcd.h | 8 + .../Inc/stm32u5xx_hal_pcd_ex.h | 1 - .../Inc/stm32u5xx_hal_rng.h | 1 + .../Inc/stm32u5xx_hal_rng_ex.h | 38 +- .../Inc/stm32u5xx_hal_rtc.h | 7 + .../Inc/stm32u5xx_hal_sd.h | 4 +- .../Inc/stm32u5xx_hal_sd_ex.h | 4 +- .../Inc/stm32u5xx_hal_sdio.h | 24 +- .../Inc/stm32u5xx_hal_spi.h | 7 + .../Inc/stm32u5xx_hal_tim.h | 40 +- .../Inc/stm32u5xx_hal_uart.h | 6 +- .../Inc/stm32u5xx_hal_uart_ex.h | 2 - .../Inc/stm32u5xx_hal_usart.h | 5 +- .../Inc/stm32u5xx_hal_usart_ex.h | 2 +- .../Inc/stm32u5xx_hal_xspi.h | 136 ++- .../Inc/stm32u5xx_ll_adc.h | 107 +-- .../Inc/stm32u5xx_ll_cordic.h | 28 +- .../Inc/stm32u5xx_ll_cortex.h | 64 +- .../Inc/stm32u5xx_ll_fmac.h | 6 - .../Inc/stm32u5xx_ll_lptim.h | 21 +- .../Inc/stm32u5xx_ll_opamp.h | 14 +- .../Inc/stm32u5xx_ll_rng.h | 41 +- .../Inc/stm32u5xx_ll_sdmmc.h | 10 +- .../Inc/stm32u5xx_ll_system.h | 793 +++++++++++++++--- .../Inc/stm32u5xx_ll_tim.h | 18 +- .../Inc/stm32u5xx_ll_ucpd.h | 61 +- .../Inc/stm32u5xx_ll_usb.h | 2 +- .../STM32U5xx_HAL_Driver/Release_Notes.html | 203 ++++- .../STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c | 50 +- .../Src/stm32u5xx_hal_cordic.c | 2 +- .../Src/stm32u5xx_hal_cortex.c | 22 +- .../Src/stm32u5xx_hal_crc_ex.c | 2 - .../Src/stm32u5xx_hal_cryp.c | 144 +++- .../Src/stm32u5xx_hal_cryp_ex.c | 70 +- .../Src/stm32u5xx_hal_dac.c | 8 + .../Src/stm32u5xx_hal_dcmi.c | 10 +- .../Src/stm32u5xx_hal_dma_ex.c | 18 +- .../Src/stm32u5xx_hal_dsi.c | 8 +- .../Src/stm32u5xx_hal_fdcan.c | 4 +- .../Src/stm32u5xx_hal_fmac.c | 24 +- .../Src/stm32u5xx_hal_gfxmmu.c | 17 +- .../Src/stm32u5xx_hal_gtzc.c | 2 +- .../Src/stm32u5xx_hal_hash.c | 78 +- .../Src/stm32u5xx_hal_hash_ex.c | 64 +- .../Src/stm32u5xx_hal_hcd.c | 44 +- .../Src/stm32u5xx_hal_i2c.c | 67 +- .../Src/stm32u5xx_hal_iwdg.c | 3 +- .../Src/stm32u5xx_hal_lptim.c | 4 +- .../Src/stm32u5xx_hal_mmc.c | 7 +- .../Src/stm32u5xx_hal_mmc_ex.c | 6 +- .../Src/stm32u5xx_hal_ospi.c | 11 +- .../Src/stm32u5xx_hal_pcd.c | 44 +- .../Src/stm32u5xx_hal_pcd_ex.c | 2 - .../Src/stm32u5xx_hal_pka.c | 30 +- .../Src/stm32u5xx_hal_pwr.c | 10 +- .../Src/stm32u5xx_hal_pwr_ex.c | 16 +- .../Src/stm32u5xx_hal_rcc.c | 19 + .../Src/stm32u5xx_hal_rng.c | 16 +- .../Src/stm32u5xx_hal_rng_ex.c | 15 +- .../Src/stm32u5xx_hal_rtc.c | 54 +- .../Src/stm32u5xx_hal_sd.c | 4 +- .../Src/stm32u5xx_hal_sd_ex.c | 6 +- .../Src/stm32u5xx_hal_sdio.c | 73 +- .../Src/stm32u5xx_hal_smartcard.c | 56 ++ .../Src/stm32u5xx_hal_spi.c | 415 +++++++-- .../Src/stm32u5xx_hal_spi_ex.c | 1 - .../Src/stm32u5xx_hal_tim.c | 14 +- .../Src/stm32u5xx_hal_tim_ex.c | 52 +- .../Src/stm32u5xx_hal_uart.c | 34 +- .../Src/stm32u5xx_hal_uart_ex.c | 18 +- .../Src/stm32u5xx_hal_usart.c | 17 +- .../Src/stm32u5xx_hal_usart_ex.c | 2 +- .../Src/stm32u5xx_hal_xspi.c | 53 +- .../Src/stm32u5xx_ll_dma.c | 10 +- .../Src/stm32u5xx_ll_fmac.c | 2 - .../Src/stm32u5xx_ll_opamp.c | 2 +- .../Src/stm32u5xx_ll_rng.c | 2 +- .../Src/stm32u5xx_ll_sdmmc.c | 6 +- .../Src/stm32u5xx_ll_tim.c | 30 +- .../Src/stm32u5xx_ll_ucpd.c | 2 +- .../Src/stm32u5xx_ll_usb.c | 122 +-- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 101 files changed, 2730 insertions(+), 1158 deletions(-) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index d10f6f6f89..cf3942e283 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +817,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1817,7 +1847,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1999,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2731,6 +2761,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3659,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3910,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4204,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h index 08fef12a8b..a779890d07 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h @@ -143,10 +143,22 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ +/** + * @} + */ +#if defined(SYSCFG_CFGR1_ENDCAP) +/** @defgroup SYSCFG_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE + * @{ + */ +#define SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ /** * @} */ +#endif /* SYSCFG_CFGR1_ENDCAP */ /** @defgroup SYSCFG_Lock_items SYSCFG Lock items * @brief SYSCFG items to set lock on @@ -620,8 +632,14 @@ extern HAL_TickFreqTypeDef uwTickFreq; (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(SYSCFG_CFGR1_ENDCAP) +#define IS_SYSCFG_DECOUPLING_CAPACITANCE(__CAPA__) (((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_OFF) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_1_DIV_3) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_2_DIV_3) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_FULL)) +#endif /* SYSCFG_CFGR1_ENDCAP */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ ((__ATTRIBUTES__) == SYSCFG_NSEC)) @@ -642,11 +660,9 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) - - #endif /* __ARM_FEATURE_CMSE */ -#ifdef SYSCFG_OTGHSPHYCR_EN +#if defined SYSCFG_OTGHSPHYCR_EN #define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ @@ -750,8 +766,6 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); */ /* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); - void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); @@ -765,10 +779,14 @@ void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); #endif /* SYSCFG_OTGHSPHYCR_EN */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void); -void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void); +void HAL_SYSCFG_EnableIOAnalogBooster(void); +void HAL_SYSCFG_DisableIOAnalogBooster(void); +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void); +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void); +#if defined(SYSCFG_CFGR1_ENDCAP) +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance); +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void); +#endif /* SYSCFG_CFGR1_ENDCAP */ void HAL_SYSCFG_EnableSRAMCached(void); void HAL_SYSCFG_DisableSRAMCached(void); void HAL_SYSCFG_EnableVddCompensationCell(void); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h index 7220ae1737..423a1c1f19 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h @@ -753,11 +753,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Exported functions --------------------------------------------------------*/ -/** @addtogroup COMP_Exported_Functions COMP Exported Functions +/** @addtogroup COMP_Exported_Functions * @{ */ -/** @addtogroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions +/** @addtogroup COMP_Exported_Functions_Group1 * @{ */ @@ -778,7 +778,7 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM */ /* IO operation functions *****************************************************/ -/** @addtogroup COMP_Exported_Functions_Group2 Start-Stop operation functions +/** @addtogroup COMP_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); @@ -789,7 +789,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); */ /* Peripheral Control functions ************************************************/ -/** @addtogroup COMP_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup COMP_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); @@ -801,7 +801,7 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); */ /* Peripheral State functions **************************************************/ -/** @addtogroup COMP_Exported_Functions_Group4 Peripheral State functions +/** @addtogroup COMP_Exported_Functions_Group4 * @{ */ HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h index f489238642..315b3b4390 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h index 0e0e4fd4bd..7670159f27 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h @@ -123,10 +123,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE 0U -#define MPU_HARDFAULT_NMI 2U -#define MPU_PRIVILEGED_DEFAULT 4U -#define MPU_HFNMI_PRIVDEF 6U +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -134,8 +134,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE 1U -#define MPU_REGION_DISABLE 0U +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ /** * @} */ @@ -143,8 +143,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ /** * @} */ @@ -152,9 +152,9 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_NOT_SHAREABLE 0U -#define MPU_ACCESS_OUTER_SHAREABLE 2U -#define MPU_ACCESS_INNER_SHAREABLE 3U +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ /** * @} */ @@ -162,10 +162,10 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_PRIV_RW 0U -#define MPU_REGION_ALL_RW 1U -#define MPU_REGION_PRIV_RO 2U -#define MPU_REGION_ALL_RO 3U +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -203,22 +203,30 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ +#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h index a7c0a5589c..015418e3a3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h @@ -484,25 +484,25 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @arg @ref CRYP_FLAG_KEIF Key error flag * @arg @ref CRYP_FLAG_RWEIF Read/write Error flag - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (FlagStatus). */ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\ - ((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ - ((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ - ((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_WRERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \ + (CRYP_FLAG_WRERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RDERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \ - ((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \ - (((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))) + (CRYP_FLAG_RDERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \ + ((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET) /** @brief Clear the CRYP pending status flag. * @param __HANDLE__ specifies the CRYP handle. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h index cb23c4d9c3..bdd6bb9f74 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h @@ -291,10 +291,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h index 017e9108d3..24020a2f6c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h @@ -574,7 +574,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0 uint32_t YSize); HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask); +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h index 043f0df60a..5fac6913cf 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h @@ -174,7 +174,7 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM Compiler ------------ @@ -207,7 +207,7 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) /* ARM & GNUCompiler ---------------- */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h index 72153b44e9..a15d4fe8cf 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h @@ -561,7 +561,6 @@ typedef struct __DMA_HandleTypeDef */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dsi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dsi.h index 29a8e549ec..cbb6e35ffd 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dsi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dsi.h @@ -1246,7 +1246,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t *ParametersTable); + const uint8_t *ParametersTable); HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, @@ -1274,8 +1274,8 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane * @brief Peripheral State and Errors functions * @{ */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi); +HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h index 9a8741bbbf..0ddede43a2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h @@ -517,8 +517,8 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ -#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ -#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h index da7ed7596c..3641a3e164 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h @@ -243,10 +243,7 @@ typedef struct * @} */ - /* Exported constants --------------------------------------------------------*/ - - /** @defgroup FMAC_Exported_Constants FMAC Exported Constants * @{ */ @@ -357,7 +354,6 @@ typedef struct * @} */ - /* Exported variables --------------------------------------------------------*/ /** @defgroup FMAC_Exported_variables FMAC Exported variables * @{ @@ -499,7 +495,7 @@ typedef struct * @} */ -/* Private Macros-----------------------------------------------------------*/ +/* Private Macros-------------------------------------------------------------*/ /** @addtogroup FMAC_Private_Macros FMAC Private Macros * @{ */ @@ -578,9 +574,9 @@ typedef struct * @param __FUNCTION__ ID of the filter function. * @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid) */ -#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ - (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxmmu.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxmmu.h index b06c3dceae..0e7de3faf2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxmmu.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxmmu.h @@ -379,28 +379,28 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @{ */ /* Operation functions ********************************************************/ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address); -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber); -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine); #if defined(GFXMMU_CR_CE) HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam); HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_CachePrefetchTypeDef *CachePrefetch); + const GFXMMU_CachePrefetchTypeDef *CachePrefetch); #endif /* GFXMMU_CR_CE */ -HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers); +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers); #if defined(GFXMMU_CR_ACE) HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_AddressCacheTypeDef *AddressCache); + const GFXMMU_AddressCacheTypeDef *AddressCache); #endif /* GFXMMU_CR_ACE */ void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu); @@ -414,7 +414,7 @@ void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); * @{ */ /* State function *************************************************************/ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu); uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h index 2f02a3f675..72dc629173 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h @@ -117,13 +117,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -476,15 +476,15 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -497,15 +497,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -517,9 +517,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -531,9 +531,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -544,9 +544,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -558,8 +558,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -594,19 +594,19 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h index 3e26a61c46..adda0f89e4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h @@ -50,15 +50,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -69,15 +69,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -87,9 +87,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -99,9 +99,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -111,9 +111,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -124,8 +124,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -135,20 +135,20 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h index 0a6423dde0..06358af1a6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h @@ -220,6 +220,7 @@ typedef struct __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ __IO HAL_LPTIM_ChannelStateTypeDef ChannelState[2]; /*!< LPTIM channel operation state */ + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ @@ -616,6 +617,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value + * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. * @retval None * @note The ARR register can only be modified when the LPTIM instance is enabled. */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h index 892676b7a0..385cfc33b1 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h @@ -717,9 +717,9 @@ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_Parti * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h index 9aca5ee185..3289331d10 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h @@ -69,9 +69,11 @@ extern "C" { /** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions * @{ */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode, diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h index 62741b5ec5..a7958a58fc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h @@ -508,6 +508,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h index ab2bb878e0..60e75c07f6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h @@ -45,7 +45,6 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h index c6610c709f..d0847d18d3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h index a01303c1ba..807d02f26b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,11 +55,11 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNG_Ex_Auto_Reset */ + value of @ref RNGEx_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ uint32_t NoiseSource; /*!< RNG noise source control(Oscillator Enable signals) @@ -71,11 +71,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -114,7 +114,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct /** * @} */ -/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -138,7 +138,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -147,7 +147,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -156,7 +156,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -165,7 +165,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -204,7 +204,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -213,11 +213,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h index 69cb662c83..b81e33e4db 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h @@ -742,6 +742,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS)) +/** + * @brief Get RTC Binary mode. + * @param __HANDLE__ specifies the RTC handle. + * @retval The selected RTC Binary mode (RTC_BINARY_NONE, RTC_BINARY_ONLY, or RTC_BINARY_MIX). + */ +#define __HAL_RTC_GET_BINARY_MODE(__HANDLE__) (READ_REG(RTC->ICSR & RTC_ICSR_BIN)) + /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h index 952df68764..bae7bc2772 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h @@ -687,10 +687,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h index 18e89ad8e0..cc2de072fa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h @@ -69,9 +69,9 @@ extern "C" { /** @defgroup SDEx_Exported_Functions_Group1 Linked List functions * @{ */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h index 0368251abe..f51f6806b0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h @@ -6,7 +6,7 @@ ********************************************************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -154,12 +154,13 @@ typedef struct __SDIO_HandleTypeDef void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio); void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio); void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status); #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio); } SDIO_HandleTypeDef; @@ -186,14 +187,16 @@ typedef enum * @{ */ typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio); -#if (USE_SDIO_TRANSCEIVER != 0U) -typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); -#endif /* USE_SDIO_TRANSCEIVER */ /** * @} */ #endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ +#if (USE_SDIO_TRANSCEIVER != 0U) +typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio); typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func); /** * @} @@ -213,9 +216,7 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u #define HAL_SDIO_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ #define HAL_SDIO_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SDIO_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ -#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) #define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ /** * @} */ @@ -289,7 +290,7 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @} */ -/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Data block size enumeration +/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration * @{ */ #define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */ @@ -470,16 +471,19 @@ HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ pSDIO_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, pSDIO_TransceiverCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio); #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, - HAL_SDIO_IOFunction_CallbackTypeDef Callback); + HAL_SDIO_IOFunction_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h index bbc186528d..24fa33d53a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h @@ -1083,6 +1083,9 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + +#define IS_SPI_LIMITED_TRANSFER_SIZE(SIZE) (((SIZE) < 0x3FFU) && ((SIZE) != 0U)) + /** * @brief CRC Length for limited instance */ @@ -1092,6 +1095,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) +#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) + #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ @@ -1105,6 +1110,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) + +#define IS_SPI_TRANSFER_SIZE(SIZE) (((SIZE) < 0xFFFFU) && ((SIZE) != 0U)) /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h index e5919c183d..bbe19eb398 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h @@ -416,29 +416,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1964,9 +1963,11 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) : \ + ((__PERIOD__) > 0U )) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -2025,7 +2026,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h index 1460ba821b..240c76c5ae 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h @@ -292,7 +292,6 @@ typedef enum HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ @@ -1217,7 +1216,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1232,8 +1231,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h index fd29060dd7..062bc86ba6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h @@ -239,8 +239,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @{ */ -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h index 36b95bbe4f..d08fef2034 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h @@ -142,7 +142,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value @@ -708,8 +708,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h index 9a80671cb3..55deb3151d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h @@ -72,7 +72,7 @@ typedef struct * @{ */ #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h index 8014fe488d..0e3e1edf2f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h @@ -393,38 +393,38 @@ typedef struct /** @defgroup XSPI_MemorySize XSPI Memory Size * @{ */ -#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ -#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ -#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ -#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ -#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ -#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ -#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ -#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ -#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ -#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ -#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ -#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ -#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ -#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ -#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ -#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ -#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ -#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ -#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ -#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ -#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ -#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ -#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ -#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ -#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ -#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ -#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ -#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ -#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ -#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ -#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ -#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ +#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Bytes = 2^( 0+1)) */ +#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Bytes = 2^( 1+1)) */ +#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Bytes = 2^( 2+1)) */ +#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Bytes = 2^( 3+1)) */ +#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Bytes = 2^( 4+1)) */ +#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Bytes = 2^( 5+1)) */ +#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Bytes = 2^( 6+1)) */ +#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Bytes = 2^( 7+1)) */ +#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Bytes = 2^( 8+1)) */ +#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KBytes = 2^( 9+1)) */ +#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KBytes = 2^(10+1)) */ +#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KBytes = 2^(11+1)) */ +#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KBytes = 2^(12+1)) */ +#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */ +#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */ +#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */ +#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KBytes = 2^(16+1)) */ +#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KBytes = 2^(17+1)) */ +#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KBytes = 2^(18+1)) */ +#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MBytes = 2^(19+1)) */ +#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MBytes = 2^(20+1)) */ +#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MBytes = 2^(21+1)) */ +#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MBytes = 2^(22+1)) */ +#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */ +#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */ +#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */ +#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MBytes = 2^(26+1)) */ +#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MBytes = 2^(27+1)) */ +#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (512 MBytes = 2^(28+1)) */ +#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits ( 1 GBytes = 2^(29+1)) */ +#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits ( 2 GBytes = 2^(30+1)) */ +#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits ( 4 GBytes = 2^(31+1)) */ /** * @} */ @@ -480,38 +480,38 @@ typedef struct /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary * @{ */ -#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ -#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ -#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ -#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ -#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ -#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ -#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ -#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ -#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ -#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ -#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ -#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ -#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ -#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ -#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ -#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ -#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ -#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ -#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ -#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ -#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ -#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ -#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ -#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ -#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ -#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ -#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ -#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ -#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ -#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ -#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ -#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ +#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ +#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Bytes = 2^(1)) */ +#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Bytes = 2^(2)) */ +#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Bytes = 2^(3)) */ +#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Bytes = 2^(4)) */ +#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Bytes = 2^(5)) */ +#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Bytes = 2^(6)) */ +#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Bytes = 2^(7)) */ +#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Bytes = 2^(8)) */ +#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Bytes = 2^(9)) */ +#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KBytes = 2^(10)) */ +#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KBytes = 2^(11)) */ +#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KBytes = 2^(12)) */ +#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KBytes = 2^(13)) */ +#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KBytes = 2^(14)) */ +#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KBytes = 2^(15)) */ +#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KBytes = 2^(16)) */ +#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KBytes = 2^(17)) */ +#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KBytes = 2^(18)) */ +#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KBytes = 2^(19)) */ +#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MBytes = 2^(20)) */ +#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MBytes = 2^(21)) */ +#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MBytes = 2^(22)) */ +#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MBytes = 2^(23)) */ +#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MBytes = 2^(24)) */ +#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MBytes = 2^(25)) */ +#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MBytes = 2^(26)) */ +#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MBytes = 2^(27)) */ +#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MBytes = 2^(28)) */ +#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MBytes = 2^(29)) */ +#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GBytes = 2^(30)) */ +#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GBytes = 2^(31)) */ /** * @} */ @@ -781,7 +781,6 @@ typedef struct */ #if defined(OCTOSPIM) - /** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port * @{ */ @@ -971,11 +970,11 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_Hyper uint32_t Timeout); /* XSPI indirect mode functions */ -HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); -HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); /* XSPI status flag polling mode functions */ @@ -1191,7 +1190,6 @@ HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSC #define IS_XSPI_DLYB_BYPASS(DLYB) (((DLYB) == HAL_XSPI_DELAY_BLOCK_ON) || \ ((DLYB) == HAL_XSPI_DELAY_BLOCK_BYPASS)) - #define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h index a6970bfd12..9d72f9aed3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h @@ -3723,7 +3723,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32 { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); + /* Note: Value shift +1 for correspondence with channel definition using ADC_CHANNEL_ID_NUMBER_MASK */ + uint32_t ch_decimal = (READ_BIT(*preg, ADC_OFR1_OFFSET1_CH) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + 1UL)); + return (uint32_t)__LL_ADC_DECIMAL_NB_TO_CHANNEL(ch_decimal); } /** @@ -4779,42 +4781,8 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 (3) - * @arg @ref LL_ADC_CHANNEL_1 (3) - * @arg @ref LL_ADC_CHANNEL_2 (3) - * @arg @ref LL_ADC_CHANNEL_3 (3) - * @arg @ref LL_ADC_CHANNEL_4 (3) - * @arg @ref LL_ADC_CHANNEL_5 (3) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) - * - * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. - * (2) On STM32U5, parameter available only on ADC instance: ADC4. - * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). - * Other channels are slow channels (conversion rate: refer to reference manual). - * (1, 2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @retval Returned value corresponds to one of literals LL_ADC_CHANNEL_x with specific formatting, + * refer to note of this function. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { @@ -5968,42 +5936,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 (3) - * @arg @ref LL_ADC_CHANNEL_1 (3) - * @arg @ref LL_ADC_CHANNEL_2 (3) - * @arg @ref LL_ADC_CHANNEL_3 (3) - * @arg @ref LL_ADC_CHANNEL_4 (3) - * @arg @ref LL_ADC_CHANNEL_5 (3) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) - * - * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. - * (2) On STM32U5, parameter available only on ADC instance: ADC4. - * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). - * Other channels are slow channels (conversion rate: refer to reference manual). - * (1, 2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @retval Returned value corresponds to one of literals LL_ADC_CHANNEL_x with specific formatting, + * refer to note of this function. */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { @@ -8582,6 +8516,20 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } +/** + * @brief Get flag ADC internal voltage regulator (LDO) ready. + * @note On this STM32 series, this flag indicates LDO state in different way depending on ADC instances: + * - ADC4: latched as other flags, clear flag function available + * - ADC1, ADC2 (if available): current state (not latched as other flags, no clear flag function) + * @rmtoll ISR LDORDY LL_ADC_IsActiveFlag_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); +} + /** * @brief Clear flag ADC ready. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC @@ -8695,6 +8643,19 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); } +/** + * @brief Clear flag ADC internal voltage regulator (LDO) ready. + * @note On this STM32 series, this flag indicates LDO state in different way depending on ADC instances: + * - ADC4: latched as other flags, clear flag function available + * - ADC1, ADC2 (if available): current state (not latched as other flags, no clear flag function) + * @rmtoll ISR LDORDY LL_ADC_ClearFlag_LDORDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_LDORDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_LDORDY); +} /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h index 3920592b68..8dd4021760 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h index 78afbdd4f3..afae552ad3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h @@ -102,10 +102,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U -#define LL_MPU_CTRL_HARDFAULT_NMI 2U -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -113,22 +113,28 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes * @{ */ -#define LL_MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ +#define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} */ @@ -145,8 +151,8 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ /** * @} */ @@ -154,9 +160,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable * @{ */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ /** * @} */ @@ -164,10 +170,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes * @{ */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h index 970aeb9387..d8161456af 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h index da22b3e075..1fa88dfdaa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h @@ -94,10 +94,10 @@ static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = /** Legacy definitions for compatibility purpose @cond 0 */ -#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 /* for legacy purpose */ -#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 /* for legacy purpose */ -#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 /* for legacy purpose */ -#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 /* for legacy purpose */ +#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 +#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 +#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 +#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 /** @endcond */ @@ -541,12 +541,12 @@ typedef struct /** Legacy definitions for compatibility purpose @cond 0 */ -#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM /* for legacy purpose */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM /** @endcond */ @@ -1689,6 +1689,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL)); } + /** * @brief Clear the autoreload match flag (ARRMCF) * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h index b64ce2a80d..6acd292952 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h @@ -193,8 +193,8 @@ typedef struct /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting * @{ */ -#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ -#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINVERT_DAC (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */ /** * @} */ @@ -213,13 +213,15 @@ typedef struct * @{ */ #define LL_OPAMP_NONINVERTINGINPUT_IO0 LL_OPAMP_INPUT_NONINVERT_IO0 -#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINV_DAC1_CH1 +#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINVERT_DAC #define LL_OPAMP_INVERTINGINPUT_IO0 LL_OPAMP_INPUT_INVERT_IO0 #define LL_OPAMP_INVERTINGINPUT_IO1 LL_OPAMP_INPUT_INVERT_IO1 #define LL_OPAMP_INVERTINGINPUT_CONNECT_NO LL_OPAMP_INPUT_INVERT_CONNECT_NO -#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 LL_OPAMP_INPUT_NONINV_DAC1_CH1 +#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 LL_OPAMP_INPUT_NONINVERT_DAC + +#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 LL_OPAMP_INPUT_NONINVERT_DAC /** * @} */ @@ -554,7 +556,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @param InputNonInverting This parameter can be one of the following values: * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 - * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC * @retval None */ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting) @@ -568,7 +570,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @param OPAMPx OPAMP instance * @retval Returned value can be one of the following values: * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 - * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC */ __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h index 6a62949c2c..75a8fc455b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h @@ -674,6 +674,9 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { +#if defined(RNG_HTCR_NIST_VALUE) + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ +#endif /* defined(RNG_HTCR_NIST_VALUE) */ WRITE_REG(RNGx->HTCR, HTCFG); } @@ -691,11 +694,47 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) /** * @} */ +#if defined(RNG_NSCR_NIST_VALUE) + +/** @defgroup RNG_LL_EF_Noise_Test_Control Noise Test Control + * @{ + */ + +/** + * @brief Set RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_SetNoiseConfig + * @param RNGx RNG Instance + * @param NOISECFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetNoiseConfig(RNG_TypeDef *RNGx, uint32_t NOISECFG) +{ + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ + WRITE_REG(RNGx->NSCR, NOISECFG); +} + +/** + * @brief Get RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_GetNoiseConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Noise Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) +{ + + return (uint32_t)READ_REG(RNGx->NSCR); +} + +/** + * @} + */ + +#endif /* defined(RNG_NSCR_NIST_VALUE) */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h index f714f38b22..f8984ade48 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h @@ -357,12 +357,12 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ -#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_SWDATATIMEOUT */ #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) @@ -1208,12 +1208,12 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); /* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); @@ -1283,7 +1283,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** @addtogroup HAL_SDMMC_LL_Group6 * @{ */ -uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf); +uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf); uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode, SDMMC_DMALinkNodeTypeDef *pNode); uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h index 45b5f811d6..275a4da595 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h @@ -135,6 +135,19 @@ extern "C" { * @} */ +#if defined(SYSCFG_CFGR1_ENDCAP) +/** @defgroup SYSTEM_LL_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE + * @{ + */ +#define LL_SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_ENDCAP */ + /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK * @{ */ @@ -151,6 +164,77 @@ extern "C" { * @} */ +#if defined(SYSCFG_OTGHSPHYCR_CLKSEL) +/** @defgroup SYSTEM_LL_OTG_PHY_CLOCK_FREQUENCY SYSCFG OTG High-speed (HS) PHY reference clock frequency selection + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_CLK_16MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< Reference clock freqeuncy is 16 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 19.2 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_20MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 20 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_24MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 24 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_26MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | \ + SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 26 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_32MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | \ + SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 32 Mhz */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYCR_CLKSEL */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_OTG_PHYTUNER_DISCONNECT_THRESTHOLD SYSCFG OTG High-speed (HS) PHYTUNER disconnnect threshold + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_OTG_SQUELSH SYSCFG OTG High-speed (HS) PHY Squelch threshold adjustment + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** @defgroup SYSTEM_LL_OTG_TRANSMITTER_PREEMPHASIS_CURRENT SYSCFG OTG High-speed (HS) transmitter preemphasis current control + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | \ + SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** @defgroup SYSCFG_Lock_items SYSCFG Lock items + * @{ + */ +#define LL_SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ +#define LL_SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define LL_SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ +#define LL_SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ +#define LL_SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ +#define LL_SYSCFG_LOCK_ALL (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC | LL_SYSCFG_SAU | LL_SYSCFG_MPU_SEC | \ + LL_SYSCFG_VTOR_AIRCR_SEC) /*!< All */ +#else +#define LL_SYSCFG_LOCK_ALL (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes * @note Only available when system implements security (TZEN=1) * @{ @@ -267,10 +351,10 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE * @{ */ -#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ -#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 0 (VREF_OUT3) */ -#define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_2 /*!< Voltage reference scale 1 (VREF_OUT4) */ +#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define LL_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ /** * @} */ @@ -406,8 +490,75 @@ __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); } +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP LL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP LL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + +#if defined(SYSCFG_CFGR1_SRAMCACHED) +/** + * @brief Enable the cachability of internal SRAMs by DCACHE2. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_EnableSRAMsCachability + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableSRAMsCachability(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + +/** + * @brief Disable the cachability of internal SRAMs by DCACHE2. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_DisableSRAMsCachability + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableSRAMsCachability(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + /** - * @brief Enable Floating Point Unit Invalid operation Interrupt + * @brief Check if internal SRAMs cachability by DCACHE2 is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_IsEnabledSRAMsCachability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMsCachability(void) +{ + return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED) == SYSCFG_CFGR1_SRAMCACHED) ? 1UL : 0UL); +} +#endif /* SYSCFG_CFGR1_SRAMCACHED */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_FPU_IT_MANAGEMENT FPU interrupt management + * @{ + */ + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC * @retval None */ @@ -417,7 +568,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) } /** - * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @brief Enable Floating Point Unit Divide-by-zero Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC * @retval None */ @@ -427,7 +578,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) } /** - * @brief Enable Floating Point Unit Underflow Interrupt + * @brief Enable Floating Point Unit Underflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC * @retval None */ @@ -437,7 +588,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) } /** - * @brief Enable Floating Point Unit Overflow Interrupt + * @brief Enable Floating Point Unit Overflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC * @retval None */ @@ -447,7 +598,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) } /** - * @brief Enable Floating Point Unit Input denormal Interrupt + * @brief Enable Floating Point Unit Input denormal Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC * @retval None */ @@ -457,7 +608,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) } /** - * @brief Enable Floating Point Unit Inexact Interrupt + * @brief Enable Floating Point Unit Inexact Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC * @retval None */ @@ -467,7 +618,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) } /** - * @brief Disable Floating Point Unit Invalid operation Interrupt + * @brief Disable Floating Point Unit Invalid operation Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC * @retval None */ @@ -477,7 +628,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) } /** - * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @brief Disable Floating Point Unit Divide-by-zero Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC * @retval None */ @@ -487,7 +638,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) } /** - * @brief Disable Floating Point Unit Underflow Interrupt + * @brief Disable Floating Point Unit Underflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC * @retval None */ @@ -497,7 +648,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) } /** - * @brief Disable Floating Point Unit Overflow Interrupt + * @brief Disable Floating Point Unit Overflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC * @retval None */ @@ -507,7 +658,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) } /** - * @brief Disable Floating Point Unit Input denormal Interrupt + * @brief Disable Floating Point Unit Input denormal Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC * @retval None */ @@ -517,7 +668,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) } /** - * @brief Disable Floating Point Unit Inexact Interrupt + * @brief Disable Floating Point Unit Inexact Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC * @retval None */ @@ -587,7 +738,182 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) } /** - * @brief Set connections to TIM1/8/15/16/17 Break inputs + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_CPU_LOCK CPU secure/non-secure lock + * @{ + */ + +/** + * @brief Lock the secure or non-secure VTOR registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockVTOR + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockVTOR(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR); +#else + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check the lock state of secure or non-secure VTOR registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_IsLockedVTOR + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR) == SYSCFG_CSLCKR_LOCKSVTAIRCR) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure VTOR registers. + * @rmtoll CNSLCKR LOCKNSVTOR LL_SYSCFG_LockVTOR_NS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockVTOR_NS(void) +{ + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR); +} + +/** + * @brief Check the lock state of non-secure VTOR registers. + * @rmtoll CNSLCKR LOCKNSVTOR LL_SYSCFG_IsLockedVTOR_NS + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR_NS(void) +{ + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Lock the secure or non-secure MPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKNSMPU/LOCKSMPU LL_SYSCFG_LockMPU + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockMPU(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU); +#else + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check the lock state of secure or non-secure MPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKNSMPU/LOCKSMPU LL_SYSCFG_IsLockedMPU + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU) == SYSCFG_CSLCKR_LOCKSMPU) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure MPU registers. + * @rmtoll CNSLCKR LOCKNSMPU LL_SYSCFG_LockMPU_NS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockMPU_NS(void) +{ + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU); +} + +/** + * @brief Check the lock state of non-secure MPU registers. + * @rmtoll CNSLCKR LOCKNSMPU LL_SYSCFG_IsLockedMPU_NS + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU_NS(void) +{ + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL); +} + +/** + * @brief Lock the secure SAU registers. + * @rmtoll CSLCKR LOCKSAU LL_SYSCFG_LockSAU + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockSAU(void) +{ + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU); +} + +/** + * @brief Check the lock state of secure SAU registers. + * @rmtoll CSLCKR LOCKSAU LL_SYSCFG_IsLockedSAU + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedSAU(void) +{ + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU) == SYSCFG_CSLCKR_LOCKSAU) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Lock the secure or non-secure CPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockConfig + * @param Item Item(s) to set lock on. + * This parameter can be a combination of: + * @arg @ref LL_SYSCFG_MPU_NSEC + * @arg @ref LL_SYSCFG_VTOR_NSEC + * @arg @ref LL_SYSCFG_SAU + * @arg @ref LL_SYSCFG_MPU_SEC + * @arg @ref LL_SYSCFG_VTOR_AIRCR_SEC + * @arg @ref LL_SYSCFG_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockConfig(uint32_t Item) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + MODIFY_REG(SYSCFG->CSLCKR, (SYSCFG_CSLCKR_LOCKSVTAIRCR | SYSCFG_CSLCKR_LOCKSMPU | SYSCFG_CSLCKR_LOCKSAU), Item); +#else + MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure CPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockConfig_NS + * @param Item Item(s) to set lock on. + * This parameter can be a combination of: + * @arg @ref LL_SYSCFG_MPU_NSEC + * @arg @ref LL_SYSCFG_VTOR_NSEC + * @arg @ref LL_SYSCFG_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockConfig_NS(uint32_t Item) +{ + MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_TIMER_BREAK Timer break inputs + * @{ + */ + +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs. * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n @@ -605,7 +931,7 @@ __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) } /** - * @brief Get connections to TIM1/8/15/16/17 Break inputs + * @brief Get connections to TIM1/8/15/16/17 Break inputs. * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n @@ -622,63 +948,68 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); } +/** + * @} + */ /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management * @{ */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /** - * @brief Configure Secure mode - * @note Only available from secure state when system implements security (TZEN=1) - * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure - * @param Configuration This parameter shall be the full combination - * of the following values: - * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC - * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC - * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @brief Clear Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus * @retval None */ -__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) +__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) { - WRITE_REG(SYSCFG->SECCFGR, Configuration); + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); } -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @brief Get Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); +} /** - * @brief Get Secure mode configuration - * @note Only available when system implements security (TZEN=1) - * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure - * @retval Returned value is the combination of the following values: - * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC - * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC - * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus + * @retval None */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) +__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) { - return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); } /** - * @} + * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); +} /** * @} */ -/** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION +/** @defgroup SYSTEM_LL_EF_SYSCFG_COMPENSATION SYSCFG Compensation cell * @{ */ /** - * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -688,7 +1019,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -698,7 +1029,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -708,7 +1039,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -719,7 +1050,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void) #if defined(SYSCFG_CCVR_PCV3) /** - * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD + * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCVR PCV3 LL_SYSCFG_GetPMOSVddHSPICompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -729,7 +1060,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void) } /** - * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD + * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCVR NCV3 LL_SYSCFG_GetNMOSVddHSPICompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -740,7 +1071,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void) #endif /* SYSCFG_CCVR_PCV3 */ /** - * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS1 bit of the @@ -753,7 +1084,7 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) } /** - * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode * @retval Returned value is the PMOS compensation cell */ @@ -763,7 +1094,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) } /** - * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS2 bit of the @@ -775,9 +1106,8 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode) MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos); } - /** - * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode * @retval Returned value is the PMOS compensation */ @@ -788,7 +1118,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void) #if defined(SYSCFG_CCCR_PCC3) /** - * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD + * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC3 LL_SYSCFG_SetPMOSVddHSPICompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS3 bit of the @@ -801,7 +1131,7 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode) } /** - * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD + * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC3 LL_SYSCFG_GetPMOSVddHSPICompensationCode * @retval Returned value is the PMOS compensation */ @@ -812,7 +1142,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void) #endif /* SYSCFG_CCCR_PCC3 */ /** - * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS2 bit of the @@ -825,7 +1155,7 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode) } /** - * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode * @retval Returned value is the Vdd compensation cell code for NMOS transistors */ @@ -835,7 +1165,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void) } /** - * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS2 bit of the @@ -848,9 +1178,8 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode) MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos); } - /** - * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode * @retval Returned value is the NMOS compensation cell code */ @@ -861,7 +1190,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void) #if defined(SYSCFG_CCCR_NCC3) /** - * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD + * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC3 LL_SYSCFG_SetNMOSVddHSPICompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS3 bit of the @@ -875,7 +1204,7 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode) } /** - * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD + * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC3 LL_SYSCFG_GetNMOSVddHSPICompensationCode * @retval Returned value is the NMOS compensation cell code */ @@ -886,7 +1215,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void) #endif /* SYSCFG_CCCR_NCC3 */ /** - * @brief Enable the Compensation Cell of GPIO supplied by VDD + * @brief Enable the Compensation Cell of GPIO supplied by VDD. * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell * @note The vdd compensation cell can be used only when the device supply * voltage ranges from 1.71 to 3.6 V @@ -898,7 +1227,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void) } /** - * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2. * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell * @note The Vdd I/O compensation cell can be used only when the device supply * voltage ranges from 1.08 to 3.6 V @@ -911,7 +1240,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Enable the Compensation Cell of HSPI IO supplied by VDD + * @brief Enable the Compensation Cell of HSPI IO supplied by VDD. * @rmtoll CCCSR EN3 LL_SYSCFG_EnableVddHSPICompensationCell * @retval None */ @@ -922,7 +1251,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Disable the Compensation Cell of GPIO supplied by VDD + * @brief Disable the Compensation Cell of GPIO supplied by VDD. * @rmtoll CCCSR EN1 LL_SYSCFG_DisableVddCompensationCell * @note The Vdd compensation cell can be used only when the device supply * voltage ranges from 1.71 to 3.6 V @@ -934,7 +1263,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void) } /** - * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2. * @rmtoll CCCSR EN2 LL_SYSCFG_DisableVddIO2CompensationCell * @note The Vdd I/O compensation cell can be used only when the device supply * voltage ranges from 1.08 to 3.6 V @@ -947,7 +1276,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Disable the Compensation Cell of HSPI IO supplied by VDD + * @brief Disable the Compensation Cell of HSPI IO supplied by VDD. * @rmtoll CCCSR EN3 LL_SYSCFG_DisableVddHSPICompensationCell * @retval None */ @@ -958,7 +1287,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable + * @brief Check if the Compensation Cell of GPIO supplied by VDD is enabled. * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell * @retval State of bit (1 or 0). */ @@ -968,7 +1297,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void) } /** - * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable + * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enabled. * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell * @retval State of bit (1 or 0). */ @@ -979,7 +1308,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enable + * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enabled. * @rmtoll CCCSR EN3 LL_SYSCFG_IsEnabled_VddHSPICompensationCell * @retval State of bit (1 or 0). */ @@ -990,7 +1319,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD. * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR * @retval State of bit (1 or 0). */ @@ -1000,7 +1329,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) } /** - * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2 + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2. * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR * @retval State of bit (1 or 0). */ @@ -1011,7 +1340,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) #if defined(SYSCFG_CCCSR_RDY3) /** - * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD + * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD. * @rmtoll CCCSR RDY3 LL_SYSCFG_IsActiveFlag_VddHSPICMPCR * @retval State of bit (1 or 0). */ @@ -1022,7 +1351,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void) #endif /* SYSCFG_CCCSR_RDY3 */ /** - * @brief Set the compensation cell code selection of GPIO supplied by VDD + * @brief Set the compensation cell code selection of GPIO supplied by VDD. * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode * @param CompCode: Selects the code to be applied for the Vdd compensation cell * This parameter can be one of the following values: @@ -1036,7 +1365,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode) } /** - * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2 + * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2. * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode * @param CompCode: Selects the code to be applied for the VddIO compensation cell * This parameter can be one of the following values: @@ -1051,7 +1380,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode) #if defined(SYSCFG_CCCSR_CS3) /** - * @brief Set the compensation cell code selection of HSPI IO supplied by VDD + * @brief Set the compensation cell code selection of HSPI IO supplied by VDD. * @rmtoll CCCSR CS3 LL_SYSCFG_SetVddHSPICellCompensationCode * @param CompCode: Selects the code to be applied for the VddIO compensation cell * This parameter can be one of the following values: @@ -1066,7 +1395,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode) #endif /* SYSCFG_CCCSR_CS3 */ /** - * @brief Get the compensation cell code selection of GPIO supplied by VDD + * @brief Get the compensation cell code selection of GPIO supplied by VDD. * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1078,7 +1407,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) } /** - * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2 + * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2. * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1092,7 +1421,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void) #if defined(SYSCFG_CCCSR_CS3) /** - * @brief Get the compensation cell code selection of HSPI IO supplied by VDD + * @brief Get the compensation cell code selection of HSPI IO supplied by VDD. * @rmtoll CCCSR CS3 LL_SYSCFG_GetVddHSPICellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1104,6 +1433,247 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3)); } #endif /* SYSCFG_CCCSR_CS3 */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_OTGPHY OTG HS PHY configurations + * @{ + */ + +#if defined(SYSCFG_OTGHSPHYCR_EN) +/** + * @brief Enable the OTG high-speed PHY. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_EnableOTGPHY + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableOTGPHY(void) +{ + SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN); +} + +/** + * @brief Disable the OTG high-speed PHY. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_DisableOTGPHY + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableOTGPHY(void) +{ + CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN); +} + +/** + * @brief Check if the OTG high-speed PHY is enabled or disabled. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_IsEnabledOTGPHY + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHY(void) +{ + return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN) == SYSCFG_OTGHSPHYCR_EN) ? 1UL : 0UL); +} +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +#if defined(SYSCFG_OTGHSPHYCR_PDCTRL) +/** + * @brief Enable the OTG high-speed PHY common block power-down control. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_EnableOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableOTGPHYPowerDown(void) +{ + SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL); +} + +/** + * @brief Disable the OTG high-speed PHY common block power-down control. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_DisableOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableOTGPHYPowerDown(void) +{ + CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL); +} + +/** + * @brief Check if the OTG high-speed PHY common block power-down is enabled or disabled. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_IsEnabledOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHYPowerDown(void) +{ + return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL) == SYSCFG_OTGHSPHYCR_PDCTRL) ? 1UL : 0UL); +} +#endif /* SYSCFG_OTGHSPHYCR_PDCTRL */ + +#if defined(SYSCFG_OTGHSPHYCR_CLKSEL) +/** + * @brief Set the OTG high-speed PHY reference clock frequency selection. + * @rmtoll SYSCFG_OTGHSPHYCR CLKSEL LL_SYSCFG_SetOTGPHYReferenceClockFrequency + * @param ClockFrequency This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYReferenceClockFrequency(uint32_t ClockFrequency) +{ + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, ClockFrequency); +} + +/** + * @brief Get the OTG high-speed PHY reference clock frequency selection. + * @rmtoll SYSCFG_OTGHSPHYCR CLKSEL LL_SYSCFG_GetOTGPHYReferenceClockFrequency + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYReferenceClockFrequency(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL)); +} +#endif /* SYSCFG_OTGHSPHYCR_CLKSEL */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** + * @brief Set the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 COMPDISTUNE LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment + * @param DisconnectThreshold This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment(uint32_t DisconnectThreshold) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Get the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 COMPDISTUNE LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_SQRXTUNE) +/** + * @brief Set the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 SQRXTUNE LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment + * @param SquelchThreshold This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment(uint32_t SquelchThreshold) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Get the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 SQRXTUNE LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** + * @brief Set the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent + * @param PreemphasisCurrent This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +/** + * @brief Get the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure Secure mode. + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @param Configuration This parameter shall be the full combination + * of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) +{ + WRITE_REG(SYSCFG->SECCFGR, Configuration); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get Secure mode configuration. + * @note Only available when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); +} + +/** + * @} + */ + /** * @} */ @@ -1173,7 +1743,6 @@ __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } - /** * @brief Enable the Debug Clock Trace * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock @@ -1574,6 +2143,7 @@ __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) /** @defgroup SYSTEM_LL_EF_FLASH FLASH * @{ */ + /** * @brief Set FLASH Latency * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency @@ -1725,59 +2295,6 @@ __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) * @} */ - -/** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS ERASE MEMORIE STATUS - * @{ - */ - -/** - * @brief Clear Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); -} - -/** - * @brief Get Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); -} - - -/** - * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); -} - -/** - * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); -} -/** - * @} - */ - #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h index 4780f66494..ea33667602 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h @@ -682,10 +682,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); } @@ -4036,7 +4036,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u /** * @brief Select the external trigger (ETR) input source. - * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports ETR source selection. * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource * @param TIMx Timer instance diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h index 62b63d8264..46741ac84f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h @@ -869,7 +869,7 @@ __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Enable Rx hard resrt interrupt + * @brief Enable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1034,7 +1034,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Disable Rx hard resrt interrupt + * @brief Disable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1199,7 +1199,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPD } /** - * @brief Check if Rx hard resrt interrupt enabled + * @brief Check if Rx hard reset interrupt enabled * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Clear Rx hard resrt interrupt + * @brief Clear Rx hard reset interrupt * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1468,10 +1468,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) */ /** - * @brief Check if FRS interrupt + * @brief Check if FRS Event Flag is active * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { @@ -1482,7 +1482,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD * @brief Check if type c event on CC2 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { @@ -1493,7 +1493,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @brief Check if type c event on CC1 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { @@ -1501,10 +1501,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * } /** - * @brief Check if Rx message end interrupt + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { @@ -1512,10 +1523,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const } /** - * @brief Check if Rx overrun interrupt + * @brief Check if Rx overrun flag is active * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { @@ -1523,10 +1534,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard resrt interrupt + * @brief Check if Rx hard reset flag is active * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { @@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U } /** - * @brief Check if Rx orderset interrupt + * @brief Check if Rx orderset flag is active * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con } /** - * @brief Check if Rx non empty interrupt + * @brief Check if Rx non empty flag is active * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP } /** - * @brief Check if TX underrun interrupt + * @brief Check if TX underrun flag is active * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC } /** - * @brief Check if hard reset sent interrupt + * @brief Check if hard reset sent flag is active * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con } /** - * @brief Check if hard reset discard interrupt + * @brief Check if hard reset discard flag is active * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con } /** - * @brief Check if Tx message abort interrupt + * @brief Check if Tx message abort flag is active * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const } /** - * @brief Check if Tx message sent interrupt + * @brief Check if Tx message sent flag is active * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1611,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons } /** - * @brief Check if Tx message discarded interrupt + * @brief Check if Tx message discarded flag is active * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1622,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons } /** - * @brief Check if Tx data receive interrupt + * @brief Check if Tx data interrupt flag is active * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1812,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) /** * @brief Read data - * @rmtoll TXDR RXDATA LL_UCPD_ReadData + * @rmtoll RXDR RXDATA LL_UCPD_ReadData * @param UCPDx UCPD Instance * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF */ @@ -1855,7 +1866,7 @@ __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) */ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct); +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct); void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h index e644ab255a..ac1bb184ad 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h @@ -935,7 +935,7 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html index a4a9266bd7..22b823558e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html @@ -40,15 +40,164 @@

                                                                                Purpose

                                                                                Update History

                                                                                - +

                                                                                Main Changes

                                                                                  -
                                                                                • Maintenance Release V1.6.0 of STM32CubeU5 Firmware Package to deploy the new HAL SDIO driver.
                                                                                • General updates to fix known defects and implementation enhancements.

                                                                                HAL/LL Drivers updates

                                                                                  +
                                                                                • HAL/LL ADC driver +
                                                                                    +
                                                                                  • Add LL_ADC_IsActiveFlag_LDORDY() macro to get ADC internal voltage regulator ready flag.
                                                                                    • +
                                                                                  • Set return value of LL_ADC_GetOffsetChannel() to format LL_ADC_CHANNEL_X.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL CRYP driver +
                                                                                    +
                                                                                  • Update CRYP driver to use correctly the wrapped key in decryption mode.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL GFXMMU driver +
                                                                                    +
                                                                                  • Update HAL_GFXMMU_GetState() API to fix wrong interrupt management.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL GTZC driver +
                                                                                    +
                                                                                  • Update HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() API to use correct size in case of FMC_BANK1.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL IWDG driver +
                                                                                    +
                                                                                  • Calculate the maximum Timeout period HAL_IWDG_DEFAULT_TIMEOUT based on a Prescaler=128 at LSI frequency=32kHz.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL OPAMP driver +
                                                                                    +
                                                                                  • Rename the define of non-inverting OPAMP input connected to DAC output.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL OSPI driver +
                                                                                    +
                                                                                  • Fix issue related to second XSPI instance management inside XSPIM.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL PKA driver +
                                                                                    +
                                                                                  • Remove static global variables and add them to PKA handle to be compliant with HAL coding rules.
                                                                                    • +
                                                                                  • Use PKA RAM erase timeout in HAL_PKA_Init() and HAL_PKA_MspDeInit() APIs to avoid SAES decryption failure after PKA deinitialization.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL PWR driver +
                                                                                    +
                                                                                  • Add guidance to HAL_PWR_ConfigAttributes() API.
                                                                                    • +
                                                                                  • Enhance Wake-Up Interrupt Handling for STOP3 Mode.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL RCC driver +
                                                                                    +
                                                                                  • Add missing call to UNUSED() macro to avoid compilation warnings related to the unused arguments.
                                                                                    • +
                                                                                  • Add guidance to HAL_RCC_ConfigAttributes() API.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL TIM driver +
                                                                                    +
                                                                                  • Include Dithering mode in IS_TIM_PERIOD macro.
                                                                                    • +
                                                                                  • Fix update flag (UIF) clearing in TIM_Base_SetConfig.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL DMA driver +
                                                                                    +
                                                                                  • Update LL_DMA_CreateLinkNode() API to add missing assert checks.
                                                                                    • +
                                                                                  • Update HAL_DMAEx_List_BuildNode() API to remove duplicated assert checks.
                                                                                    • +
                                                                                  • Update DMA_List_BuildNode() API to clear CLLR register of the last node of a queue.
                                                                                    • +
                                                                                  • +
                                                                                • HAL FDCAN driver +
                                                                                    +
                                                                                  • Fix assert issue when Standard or Extended filter numbers are zero.
                                                                                    • +
                                                                                  • Fix the incorrect comments.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL RNG driver +
                                                                                    +
                                                                                  • Add LL_RNG_SetNoiseConfig() API to find the recommended value for NIST compliance.
                                                                                    • +
                                                                                  • Update HAL_RNG_GenerateRandomNumber() and HAL_RNGEx_RecoverSeedError() APIs to distinguish between RecoverSeedError and SeedError.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL RTC_BKP driver +
                                                                                    +
                                                                                  • Avoid entering initialization mode when calling HAL_RTC_Init() if the RTC is already configured in binary mode to prevent unwanted reset of the SSR register.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL SDMMC driver +
                                                                                    +
                                                                                  • Add missing eMMC RPMB APIs.
                                                                                    • +
                                                                                  • Add support of customized SDIO Card enumeration sequence.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL SPI driver +
                                                                                    +
                                                                                  • Add protection against wrong transfer size during transmission.
                                                                                    • +
                                                                                  • Update HAL_SPI_TransmitReceive_DMA() API to check coherence between data size and DMA TX configuration.
                                                                                    • +
                                                                                  • Fix CRC computation to feat with standard CRC16-CCITT (XMODEM).
                                                                                    • +
                                                                                  • +
                                                                                • HAL I2C driver +
                                                                                    +
                                                                                  • Remove tmp variable from I2C_TransferConfig() function.
                                                                                    • +
                                                                                  • Update HAL_I2C_IsDeviceReady() API to take into account the number of trials.
                                                                                    • +
                                                                                  • +
                                                                                • HAL SYSCFG driver +
                                                                                    +
                                                                                  • Rename APIs HAL_SYSCFG_EnableIOAnalogSwitchBooster(),HAL_SYSCFG_DisableIOAnalogSwitchBooster(), HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection() and HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection() to be aligned with MISRAC2012 rule 5.1
                                                                                    • +
                                                                                  • +
                                                                                • LL SYSTEM driver +
                                                                                    +
                                                                                  • Enhance LL System Source Code.
                                                                                    • +
                                                                                  • Fix LL_VREFBUF_VOLTAGE_SCALE3 value.
                                                                                    • +
                                                                                  • +
                                                                                • HAL UART driver +
                                                                                    +
                                                                                  • Ensure UART Rx buffer is not written beyond boundaries in case of RX FIFO reception in Interrupt mode.
                                                                                    • +
                                                                                  • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.
                                                                                    • +
                                                                                  • Ensure TC flag is cleared prior starting DMA transmit.
                                                                                    • +
                                                                                  • Remove reference to HAL_UARTEx_WakeupCallback and to HAL_UART_WAKEUP_CB_ID defines.
                                                                                    • +
                                                                                  • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring just after TC event.
                                                                                    • +
                                                                                  • Apply DMAT/DMAR specific management for HAL_UARTEx_ReceiveToIdle() and HAL_UARTEx_ReceiveToIdle_IT() APIs.
                                                                                    • +
                                                                                  • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode.
                                                                                    • +
                                                                                  • Correct wrong comment in HAL_UARTEx_DisableFifoMode() API.
                                                                                    • +
                                                                                  • +
                                                                                • HAL USART driver +
                                                                                    +
                                                                                  • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM.
                                                                                    • +
                                                                                  • Correct wrong comment in HAL_USARTEx_DisableFifoMode() API.
                                                                                    • +
                                                                                  • Improve the visibility of the SPI function support in HAL USART description and comments.
                                                                                    • +
                                                                                  • +
                                                                                • HAL SMARTCARD driver +
                                                                                    +
                                                                                  • Implement workaround to resolve HW bug.
                                                                                    • +
                                                                                  • +
                                                                                • HAL XSPI driver +
                                                                                    +
                                                                                  • Change XSPI_WaitFlagStateUntilTimeout() API handle state to HAL_XSPI_STATE_READY in case of Timeout to avoid blocking driver operation.
                                                                                    • +
                                                                                  • Correct comments for XSPI_MemorySize and XSPI_ChipSelectBoundary related definitions.
                                                                                    • +
                                                                                  • Update management of SSHIFT when DTR is activated for data transfer in XSPI_ConfigCmd() API.
                                                                                    • +
                                                                                  • Update state verification inside Abort APIs.
                                                                                    • +
                                                                                  • +
                                                                                • HAL/LL USB driver +
                                                                                    +
                                                                                  • hal_hcd.c/ll_usb.c: fix USB data toggle.
                                                                                    • +
                                                                                  • hal_pcd.c/ll_usb.c: fix added to support bulk transfer in double buffer mode.
                                                                                    • +
                                                                                  • hal_hcd.c: ensure to reactivate the usb channel in case of transfer error.
                                                                                    • +
                                                                                  • Fix the condition on EONUM flag of DOEPCTLx register in HAL_PCD_IRQHandler() to correctly check on the frame number parity.
                                                                                    • +
                                                                                  • +
                                                                                +

                                                                                Known Limitations

                                                                                +
                                                                                  +
                                                                                • N/A
                                                                                  • +
                                                                                +

                                                                                Backward compatibility

                                                                                +
                                                                                  +
                                                                                • N/A
                                                                                  • +
                                                                                +
                                                                                +
                                                                                +
                                                                                + +
                                                                                +

                                                                                Main Changes

                                                                                +
                                                                                  +
                                                                                • Maintenance Release V1.6.0 of STM32CubeU5 Firmware Package to deploy the new HAL SDIO driver.
                                                                                  • +
                                                                                • General updates to fix known defects and implementation enhancements.
                                                                                  • +
                                                                                +

                                                                                HAL/LL Drivers updates

                                                                                +
                                                                                • HAL GENERIC driver
                                                                                  • update stm32u5xx_hal_conf_template file to add the support for the new HAL SDIO driver.
                                                                                    • @@ -71,11 +220,11 @@

                                                                                    HAL/LL Drivers updates

                                                                                  • Support new HAL SDIO driver.
                                                                                -

                                                                                Known Limitations

                                                                                +

                                                                                Known Limitations

                                                                                • N/A
                                                                                -

                                                                                Backward compatibility

                                                                                +

                                                                                Backward compatibility

                                                                                • N/A
                                                                                @@ -84,7 +233,7 @@

                                                                                Backward compatibility

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • HAL and LL drivers Maintenance Release for STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U599xx/STM32U5A9xx, STM32U595xx/STM32U5A5xx, STM32U5F9xx/STM32U5G9xx and STM32U5F7xx/STM32U5G7xx devices
                                                                                • Add the HAL MMC replay protected memory block management feature
                                                                                  • @@ -265,11 +414,11 @@

                                                                                  LL Drivers updates

                                                                                • Rename LL_UTILS_PACKAGETYPE_WLCSP144_SMPS to LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS define
                                                                              -

                                                                              Known Limitations

                                                                              +

                                                                              Known Limitations

                                                                              • N/A
                                                                              -

                                                                              Backward compatibility

                                                                              +

                                                                              Backward compatibility

                                                                              • N/A
                                                                              @@ -278,7 +427,7 @@

                                                                              Backward compatibility

                                                                              -

                                                                              Main Changes

                                                                              +

                                                                              Main Changes

                                                                              • HAL and LL drivers Maintenance Release for STM32U5XX devices
                                                                              • Update ADC HAL and LL drivers to fix known defects and add implementation enhancements
                                                                                • @@ -302,11 +451,11 @@

                                                                                LL Drivers updates

                                                                              • Add new Helper macro for differential mode raw data to voltage conversion
                                                                            -

                                                                            Known Limitations

                                                                            +

                                                                            Known Limitations

                                                                            • N/A
                                                                            -

                                                                            Backward compatibility

                                                                            +

                                                                            Backward compatibility

                                                                            • N/A
                                                                            @@ -315,7 +464,7 @@

                                                                            Backward compatibility

                                                                            -

                                                                            Main Changes

                                                                            +

                                                                            Main Changes

                                                                            • HAL and LL drivers official Release for STM32U5F7xx/STM32U5G7xx, STM32U5F9xx/STM32U5G9xx, STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U595xx/STM32U5A5xx and STM32U599xx/STM32U5A9xx devices
                                                                            • Add 2 new HAL drivers : GFXTIM and JPEG highlighting the graphics aspect of STM32U5F7/STM32U5G7/STM32U5F9/STM32U5G9 devices
                                                                              • @@ -405,11 +554,11 @@

                                                                              LL Drivers updates

                                                                          Note: HAL/LL Backward compatibility ensured by legacy defines.

                                                                          -

                                                                          Known Limitations

                                                                          +

                                                                          Known Limitations

                                                                          • N/A
                                                                          -

                                                                          Backward compatibility

                                                                          +

                                                                          Backward compatibility

                                                                          • N/A
                                                                          @@ -418,7 +567,7 @@

                                                                          Backward compatibility

                                                                          -

                                                                          Main Changes

                                                                          +

                                                                          Main Changes

                                                                          • HAL and LL drivers Official Release for STM32U535xx / STM32U545xx, STM32U575xx / STM32U585xx, STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices.
                                                                          • Update STM32U545xx_User_Manual, STM32U585xx_User_Manual and STM32U5A9xx_User_Manual CHM User Manuals
                                                                            • @@ -618,11 +767,11 @@

                                                                            LL Drivers updates

                                                                        Note: HAL/LL Backward compatibility ensured by legacy defines.

                                                                        -

                                                                        Known Limitations

                                                                        +

                                                                        Known Limitations

                                                                        • N/A
                                                                        -

                                                                        Backward compatibility

                                                                        +

                                                                        Backward compatibility

                                                                        • N/A
                                                                        @@ -631,7 +780,7 @@

                                                                        Backward compatibility

                                                                        -

                                                                        Main Changes

                                                                        +

                                                                        Main Changes

                                                                        • HAL and LL drivers Maintenance Release for STM32U575xx / STM32U585xx devices and new support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
                                                                        • Add New LTDC, GFXMMU, DSI, GPU2D HAL drivers highlighting the graphics aspect of STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
                                                                          • @@ -858,11 +1007,11 @@

                                                                          LL Drivers updates

                                                                      Backward compatibility ensured by legacy defines

                                                                      -

                                                                      Known Limitations

                                                                      +

                                                                      Known Limitations

                                                                      • N/A
                                                                      -

                                                                      Backward compatibility

                                                                      +

                                                                      Backward compatibility

                                                                      • N/A
                                                                      @@ -871,7 +1020,7 @@

                                                                      Backward compatibility

                                                                      -

                                                                      Main Changes

                                                                      +

                                                                      Main Changes

                                                                      • Patch release V1.0.2 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
                                                                      @@ -887,11 +1036,11 @@

                                                                      LL Drivers updates

                                                                  • Backward compatibility ensured by legacy defines
                                                                  -

                                                                  Known Limitations

                                                                  +

                                                                  Known Limitations

                                                                  • N/A
                                                                  -

                                                                  Backward compatibility

                                                                  +

                                                                  Backward compatibility

                                                                  • N/A
                                                                  @@ -900,7 +1049,7 @@

                                                                  Backward compatibility

                                                                  -

                                                                  Main Changes

                                                                  +

                                                                  Main Changes

                                                                  • Patch release V1.0.1 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
                                                                  @@ -949,11 +1098,11 @@

                                                                  LL Drivers updates

                                                                • Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs
                                                              -

                                                              Known Limitations

                                                              +

                                                              Known Limitations

                                                              • N/A
                                                              -

                                                              Backward compatibility

                                                              +

                                                              Backward compatibility

                                                              • N/A
                                                              @@ -962,11 +1111,11 @@

                                                              Backward compatibility

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
                                                              -

                                                              Known Limitations

                                                              +

                                                              Known Limitations

                                                              • N/A
                                                              diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c index f1136de678..b587c12cca 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -52,11 +52,11 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.6.0 + * @brief STM32U5xx HAL Driver version number 1.6.1 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32U5xx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32U5xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ @@ -664,7 +664,7 @@ void HAL_SYSCFG_DisableVREFBUF(void) * * @retval None */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) +void HAL_SYSCFG_EnableIOAnalogBooster(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } @@ -674,7 +674,7 @@ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) * * @retval None */ -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) +void HAL_SYSCFG_DisableIOAnalogBooster(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } @@ -684,7 +684,7 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) * * @retval None */ -void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void) +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } @@ -694,11 +694,45 @@ void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void) * * @retval None */ -void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void) +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DECOUPLING_CAPACITANCE(Capacitance)); + + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + */ +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + #if defined(SYSCFG_CFGR1_SRAMCACHED) /** * @brief Enable the Cacheability of internal SRAMx by DCACHE2 @@ -756,6 +790,7 @@ void HAL_SYSCFG_EnableVddHSPICompensationCell(void) SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); } #endif /* SYSCFG_CCCSR_EN3 */ + /** * @brief Disable the Compensation Cell of GPIO supplied by VDD * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell @@ -865,8 +900,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - - /** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions * @brief SYSCFG attributes management functions. * @@ -957,7 +990,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri This parameter can be one of @ref SYSCFG_OTG_PHY_Enable * @retval None */ - void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) { /* Check the parameter */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c index d3b051c7e6..5eb8029c3d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c @@ -164,12 +164,12 @@ static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); + /** * @} */ /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions * @{ */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c index fc9ffb222d..4d317ce445 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c @@ -74,19 +74,23 @@ (++) Reload Value should not exceed 0xFFFFFF [..] - *** How to configure MPU (secure and non secure) using CORTEX HAL driver *** + *** How to configure MPU using CORTEX HAL driver *** =========================================================== [..] - This section provides functions allowing to Enable and configure the MPU secure and non-secure. + This section provides functions allowing to configure the Memory Protection Unit (MPU). + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. (#) Enable the MPU using HAL_MPU_Enable() function. - (#) Disable the MPU using HAL_MPU_Disable() function. - (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU. - (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU. - (#) Configure the MPU region using HAL_MPU_ConfigRegion() - and HAL_MPU_ConfigRegion_NS() to address the non secure MPU. - (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes() - and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context + and the same sequence as above applies to configure the non-secure MPU. @endverbatim ****************************************************************************** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c index 061ab92235..3d15366d20 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c index c873ad74f3..054ba9240e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c @@ -363,6 +363,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp); static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); @@ -635,6 +636,13 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); @@ -649,10 +657,23 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD { /* Disable AES to change key mode */ __HAL_CRYP_DISABLE(hcryp); + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set key mode selection (Normal, Wrapped or Shared key )*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ @@ -1206,7 +1227,11 @@ HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_Contex hcryp->Init.KeyMode = pcont->KeyMode; hcryp->Phase = pcont->Phase; hcryp->KeyIVConfig = pcont->KeyIVConfig; - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } /* Restore CRYP CR register content */ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); @@ -1379,11 +1404,25 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); } else { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode and normal key selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); } @@ -1474,10 +1513,22 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, { hcryp->Size = Size; } - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + if (IS_AES_ALL_INSTANCE(hcryp->Instance)) + { + /* Set Decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_DECRYPT | CRYP_KEYMODE_NORMAL); + } /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; @@ -1584,7 +1635,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1613,6 +1670,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1687,7 +1745,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1715,6 +1779,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1772,7 +1837,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1878,6 +1949,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1934,7 +2006,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1962,6 +2040,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -2005,26 +2084,30 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->IER; + uint32_t itflagsr = hcryp->Instance->SR; + uint32_t itflagisr = hcryp->Instance->ISR; + /* Check if Read or write error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET) + if ((itsource & CRYP_IT_RWEIE) != 0U) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET) + if ((itflagsr & CRYP_FLAG_WRERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET) + if ((itflagsr & CRYP_FLAG_RDERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } } /* Check if Key error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET) + if ((itsource & CRYP_IT_KEIE) != 0U) { - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET) + if ((itflagisr & CRYP_FLAG_KEIF) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF); @@ -2033,9 +2116,9 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) + if ((itflagisr & CRYP_FLAG_CCF) != 0U) { - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itsource & CRYP_IT_CCFIE) != 0U) { /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -3536,7 +3619,31 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Writes Key in Key registers. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3610,7 +3717,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -5761,7 +5867,7 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *In static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - uint32_t count = 0U; + uint32_t count; /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c index 86b58c4bce..6862b3b510 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c @@ -39,7 +39,7 @@ /** @addtogroup CRYPEx_Private_Defines * @{ */ - +#define CRYPEx_GENERAL_TIMEOUT 82U #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ @@ -66,6 +66,7 @@ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions * @{ @@ -125,6 +126,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c /* Check if initialization phase has already been performed */ if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -143,19 +151,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -459,7 +464,13 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Encryption operating mode(Mode 0)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -504,7 +515,13 @@ HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } status = CRYPEx_KeyDecrypt(hcryp, Timeout); } else @@ -724,6 +741,31 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T __HAL_UNLOCK(hcryp); return HAL_OK; } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ + +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c index cbfc1ac14f..f75b812b2a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c @@ -1263,6 +1263,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c index 30ce86bb76..828fbb74bd 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c @@ -86,7 +86,7 @@ and a pointer to the user callback function. Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: @@ -98,10 +98,10 @@ (+) MspDeInitCallback : callback for DCMI MspDeInit. By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak (overridden) functions: examples FrameEventCallback(), HAL_DCMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init + reset to the legacy weak (overridden) functions in the HAL_DCMI_Init and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -116,7 +116,7 @@ When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -1000,7 +1000,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) * the embedded synchronization delimiters unmasks. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask) +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask) { /* Process Locked */ __HAL_LOCK(hdcmi); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c index b8c6ac1ff6..d60eca23d8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c @@ -1091,10 +1091,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); } /* Check DMA channel security and privilege attributes parameters */ @@ -3901,9 +3897,21 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); } /********************************************************************************* CBR2 register value is updated */ - } + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + else + { + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + /* Update node information value ************************************************************************************/ /* Set node information */ pNode->NodeInfo = pNodeConfig->NodeType; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c index cfe40f630d..501784e610 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c @@ -1808,14 +1808,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t *ParametersTable) + const uint8_t *ParametersTable) { uint32_t uicounter; uint32_t nbBytes; uint32_t count; uint32_t tickstart; uint32_t fifoword; - uint8_t *pparams = ParametersTable; + const uint8_t *pparams = ParametersTable; /* Process locked */ __HAL_LOCK(hdsi); @@ -2861,7 +2861,7 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane * the configuration information for the DSI. * @retval HAL state */ -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi) { return hdsi->State; } @@ -2872,7 +2872,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) * the configuration information for the DSI. * @retval DSI Error Code */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi) { /* Get the error code */ return hdsi->ErrorCode; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c index b0dcc8edee..5ca5d8fee4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA if (sFilterConfig->IdType == FDCAN_STANDARD_ID) { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c index 5d437fa35d..0e65908df9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c @@ -204,7 +204,6 @@ not defined, the callback registration feature is not available and weak callbacks are used. - @endverbatim * */ @@ -229,7 +228,6 @@ /** @defgroup FMAC_Private_Constants FMAC Private Constants * @{ */ - #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) #define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U @@ -322,7 +320,6 @@ /* Private variables ---------------------------------------------------------*/ /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); @@ -348,7 +345,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /* Functions Definition ------------------------------------------------------*/ - /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ */ @@ -1203,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1222,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1239,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ @@ -2576,7 +2583,6 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) #else HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ - } /** @@ -2708,11 +2714,11 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ } + /** * @} */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c index c2b16597c9..82c12bf3e8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c @@ -538,7 +538,7 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @param Address Start address of LUT in flash. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address) @@ -593,7 +593,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber) { @@ -640,7 +640,7 @@ HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, * @param lutLine LUT line parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine) { HAL_StatusTypeDef status = HAL_OK; @@ -725,7 +725,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uin * @retval HAL status. * @note This function is only available on STM32U599/STM32U5A9 devices. */ -HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers) +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers) { HAL_StatusTypeDef status = HAL_OK; @@ -761,7 +761,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU * @note This function is only available on STM32U599/STM32U5A9 devices. */ HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_CachePrefetchTypeDef *CachePrefetch) + const GFXMMU_CachePrefetchTypeDef *CachePrefetch) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation)); @@ -814,7 +814,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, * @note This function is only available on STM32U5F9/STM32U5G9 devices. */ HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_AddressCacheTypeDef *AddressCache) + const GFXMMU_AddressCacheTypeDef *AddressCache) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_FUNCTIONAL_STATE(AddressCache->Activation)); @@ -910,7 +910,7 @@ __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) * @param hgfxmmu GFXMMU handle. * @retval GFXMMU state. */ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu) { /* Return GFXMMU handle state */ return hgfxmmu->State; @@ -924,6 +924,7 @@ HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) { uint32_t error_code; + uint32_t primask = __get_PRIMASK(); /* Enter in critical section */ __disable_irq(); @@ -933,7 +934,7 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; /* Exit from critical section */ - __enable_irq(); + __set_PRIMASK(primask); /* Return GFXMMU error code */ return error_code; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c index c8b17c129f..023a52131a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c @@ -612,7 +612,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddres break; #if defined (FMC_BANK1) case FMC_BANK1: - size = TZSC_MPCWM1_MEM_SIZE; + size = TZSC_MPCWM2_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) { register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c index 067f1133d5..8f81950c2d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c @@ -272,10 +272,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -764,7 +764,7 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -790,7 +790,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -805,7 +805,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -822,7 +822,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -848,7 +848,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -863,7 +863,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -911,7 +911,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -935,7 +935,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -965,7 +965,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -990,7 +990,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1004,7 +1004,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1077,7 +1077,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1107,7 +1107,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1164,7 +1164,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1183,7 +1183,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1225,7 +1225,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1243,7 +1243,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1297,7 +1297,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1832,7 +1832,7 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -1951,7 +1951,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -2502,10 +2502,10 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2537,7 +2537,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2553,7 +2553,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2561,7 +2561,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2639,9 +2639,9 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2673,7 +2673,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2684,7 +2684,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2742,7 +2742,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2864,7 +2864,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3030,7 +3030,7 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3235,7 +3235,7 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3313,7 +3313,7 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3424,7 +3424,7 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c index 8215c1549d..dcbae5f16a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c @@ -148,7 +148,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -174,7 +174,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -189,7 +189,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -206,7 +206,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -232,7 +232,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -247,7 +247,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -290,7 +290,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -328,7 +328,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -344,7 +344,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -382,7 +382,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -434,7 +434,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -464,7 +464,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -521,7 +521,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -540,7 +540,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -583,7 +583,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -601,7 +601,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -659,7 +659,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -683,7 +683,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -759,7 +759,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -780,7 +780,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -806,7 +806,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -829,7 +829,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -850,7 +850,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -898,7 +898,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -919,7 +919,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -945,7 +945,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -967,7 +967,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -988,7 +988,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -1014,7 +1014,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c index 009b208791..ad79d6e82e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c @@ -1710,6 +1710,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); @@ -2140,7 +2146,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, return HAL_ERROR; } - if (((epnum & 0xFU)== 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + if (((epnum & 0xFU) == 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) { hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; @@ -3832,8 +3838,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) { - hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; } else { @@ -3846,10 +3852,10 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + hhcd->hc[ch_num & 0xFU].toggle_in ^= 1U; } } - /* manage NACK Response */ + /* Manage NACK Response */ else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK) && (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE)) { @@ -3863,7 +3869,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); } } - /* manage STALL Response */ + /* Manage STALL Response */ else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) { (void)HAL_HCD_HC_Halt(hhcd, ch_num); @@ -3952,7 +3958,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Handle Isochronous channel */ if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) { - /* correct transaction */ + /* Correct transaction */ if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U) { /* Double buffer isochronous out */ @@ -3961,7 +3967,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); } #if (USE_USB_DOUBLE_BUFFER == 1U) - else /* double buffer isochronous out */ + else /* Double buffer isochronous out */ { /* Odd Transaction */ if ((ch_reg & USB_CH_DTOG_TX) != 0U) @@ -4010,14 +4016,20 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num & 0xFU].xfer_len = 0U; } + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + } + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { - /* manage multiple Xfer */ + /* Manage multiple Xfer */ hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; - /* start a new transfer */ + /* Start a new transfer */ (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); } else @@ -4026,12 +4038,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - - if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || - (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) - { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; - } } } /* Check NACK Response */ @@ -4046,7 +4052,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Get Channel register value */ WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); - /*clear NAK status*/ + /* Clear NAK status */ WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK; /* Update channel register Value */ @@ -4137,13 +4143,13 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) /* Host Port State */ hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - /* clear all allocated virtual channel */ + /* Clear all allocated virtual channel */ HAL_HCD_ClearPhyChannel(hhcd); /* Reset the PMA current pointer */ (void)HAL_HCD_PMAReset(hhcd); - /* reset Ep0 Pma allocation state */ + /* Reset Ep0 Pma allocation state */ hhcd->ep0_PmaAllocState = 0U; /* Disconnection Callback */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c index 31582a2dd2..3b1a2ee7f0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c @@ -3458,6 +3458,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3515,37 +3517,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -7624,15 +7653,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c index 6f6cac1fcc..b1c88eacc7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c @@ -137,7 +137,8 @@ The timeout value is multiplied by 1000 to be converted in milliseconds. LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / (LSI_VALUE / 128U)) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c index 184b4d0fca..821aaea8fa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c @@ -387,10 +387,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { if ((hlptim->Instance == LPTIM3) || (hlptim->Instance == LPTIM4)) { - /* Check LPTIM3 Input1 source */ + /* Check LPTIM Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); - /* Configure LPTIM3 Input1 source */ + /* Configure LPTIM Input1 source */ hlptim->Instance->CFGR2 = hlptim->Init.Input1Source; } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c index 634c867967..3ea9aaea58 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c @@ -2120,7 +2120,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); @@ -2271,7 +2271,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp * will contain the MMC card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); @@ -4302,7 +4302,6 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 * @brief Used to select the partition. * @param hmmc: Pointer to MMC handle * @param Partition: Partition type - * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) @@ -4683,7 +4682,7 @@ HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, /** * @brief Allows to get the value of write counter within the RPMB partition. * @param hmmc: Pointer to MMC handle - * @param Nonce: pointer to the value of nonce (16 bytes) + * @param pNonce: pointer to the value of nonce (16 bytes) * @param Timeout: Specify timeout value * @retval write counter value. */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c index 79589f4b74..77b66947a1 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c @@ -217,7 +217,8 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(MMC_DMALinkedListT * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -326,7 +327,8 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MM * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c index 1a4a2077a6..86b77be302 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c @@ -1148,7 +1148,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1241,7 +1242,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -2708,8 +2710,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || + ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c index 45621b97bb..bed0c62be8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c @@ -1055,7 +1055,6 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) __HAL_PCD_DISABLE(hpcd); (void)USB_DevDisconnect(hpcd->Instance); - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -1486,7 +1485,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -1951,7 +1950,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1966,7 +1965,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; #if defined (USB_OTG_FS) || defined (USB_OTG_HS) @@ -2642,7 +2641,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -2763,7 +2761,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2839,7 +2837,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2871,11 +2869,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2925,6 +2923,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2936,10 +2940,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2970,7 +2976,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2998,6 +3004,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -3010,10 +3022,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -3043,7 +3057,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -3052,13 +3066,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - #endif /* defined (USB_DRD_FS) */ /** @@ -3066,7 +3079,6 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c index a4a9f4ac5d..1e61af7f86 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c @@ -484,7 +484,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -519,7 +518,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } - #endif /* defined (USB_DRD_FS) */ /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c index 5618ef5b0b..b93ae117da 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c @@ -1121,11 +1121,18 @@ void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) */ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + } + else + { + return HAL_ERROR; + } } /** @@ -1136,11 +1143,18 @@ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTy */ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + } + else + { + return HAL_ERROR; + } } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c index a7a6fbda3e..29304a020b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c @@ -594,7 +594,6 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) * clear of pending events before. * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and * no clear of pending event before. - * @note In System STOP mode, all I/O pins keep the same state as in Run mode. * @retval None. */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) @@ -836,6 +835,13 @@ __weak void HAL_PWR_PVDCallback(void) * privileged access. * @note Privilege attribute for nsecure items can be managed by a secure * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). * @param Item : Specifies the item(s) to set attributes on. * This parameter can be a combination of @ref PWR_Items. * @param Attributes : Specifies the available attribute(s). @@ -933,6 +939,8 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; } #else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); /* Get Non-Secure privileges attribute */ attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; #endif /* __ARM_FEATURE_CMSE */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c index 0dc86b9ab2..15b487453a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c @@ -864,7 +864,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN1); } } @@ -877,7 +877,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN2); } } @@ -890,7 +890,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN3); } } @@ -903,7 +903,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN4); } } @@ -916,7 +916,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN5); } } @@ -929,7 +929,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN6); } } @@ -942,7 +942,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN7); } } @@ -955,7 +955,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN8); } } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c index 1b47d2327d..0d84eb060c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c @@ -1657,6 +1657,10 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio_initstruct; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); @@ -2062,6 +2066,14 @@ __weak void HAL_RCC_CSSCallback(void) /** * @brief Configure the RCC item attribute(s). * @note Available attributes are to secure items and set RCC as privileged. + * @note As the privileged attributes concern either all secure or all + * non-secure RCC resources accesses and not each RCC individual items + * access attribute, the application must ensure that the privilege + * access attribute configurations are coherent amongst the security + * level set on RCC individual items so not to overwrite a previous + * more restricted access rule (consider either all secure and/or all + * non-secure RCC resources accesses by privileged-only transactions or + * privileged and unprivileged transactions). * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref RCC_items * @param Attributes specifies the RCC secure/privilege attributes. @@ -2101,10 +2113,14 @@ void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) /* Non-secure Privilege attribute */ case RCC_NSEC_PRIV: SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); break; /* Non-secure Non-Privilege attribute */ case RCC_NSEC_NPRIV: CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); break; #endif /* __ARM_FEATURE_CMSE */ default: @@ -2154,6 +2170,9 @@ HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut #else /* Get Non-Secure privileges attribute */ attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + #endif /* __ARM_FEATURE_CMSE */ /* return value */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c index bfcbe13eee..eaa87eceab 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c @@ -197,8 +197,20 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#endif /* RNG_CR_NIST_VALUE */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* RNG_HTCR_NIST_VALUE */ +#if defined(RNG_NSCR_NIST_VALUE) + WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); +#endif /* RNG_NSCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -238,7 +250,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -641,6 +653,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c index adeb1b3bbb..1458006886 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -41,7 +41,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -53,11 +53,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -309,6 +309,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c index 96999b17f9..236e5ca5ee 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c @@ -362,39 +362,45 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Check if the calendar has been not initialized */ + /* Check whether the calendar needs to be initialized */ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) + /* Check that the RTC mode is not 'binary only' */ + if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY) { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); - /* Set RTC_CR register */ - SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); - - /* Configure the RTC PRER */ - WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Binary mode */ - MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); if (status == HAL_OK) { - MODIFY_REG(RTC->CR, \ - RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ - hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } } else { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c index 594045c1b8..af08837d2c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c @@ -2111,7 +2111,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); @@ -2327,7 +2327,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c index 0e44eb5a60..b18160c1ec 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c @@ -196,7 +196,8 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTyp * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, + const SDMMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -290,7 +291,8 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, + const SDMMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c index a2d420733b..83b3e70525 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -86,6 +86,9 @@ (#) Configure the SDIO Card speed mode by the API : HAL_SDIO_SetSpeedMode(). + (#) To custumize the SDIO Init card function for the enumeration card sequence, you can register a user callback + function by calling the HAL_SDIO_RegisterIdentifyCardCallback before the HAL_SDIO_Init() function. + *** SDIO Card Read operation *** ============================== [..] @@ -311,6 +314,7 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) { SDIO_InitTypeDef Init; uint32_t sdmmc_clk; + uint8_t data; /* Check the parameters */ assert_param(hsdio != NULL); @@ -375,12 +379,31 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); - if (SDIO_InitCard(hsdio) != HAL_OK) + if (hsdio->SDIO_IdentifyCard == NULL) + { + hsdio->SDIO_IdentifyCard = SDIO_InitCard; + } + /* SDIO enumeration sequence */ + if (hsdio->SDIO_IdentifyCard(hsdio) != HAL_OK) { hsdio->State = HAL_SDIO_STATE_RESET; return HAL_ERROR; } + /* Configure the SDMMC user parameters */ + Init.ClockEdge = hsdio->Init.ClockEdge; + Init.ClockPowerSave = hsdio->Init.ClockPowerSave; + Init.BusWide = hsdio->Init.BusWide; + Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; + Init.ClockDiv = hsdio->Init.ClockDiv; + (void)SDMMC_Init(hsdio->Instance, Init); + + data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + return HAL_ERROR; + } + hsdio->Context = SDIO_CONTEXT_NONE; hsdio->State = HAL_SDIO_STATE_READY; @@ -1937,6 +1960,7 @@ HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDI return status; } +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) /** @@ -1999,7 +2023,30 @@ HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsd } #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ +/** + * @brief Register a User SDIO Identification Callback + * @param hsdio: Pointer to SDIO handle + * @param pCallback: pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + hsdio->SDIO_IdentifyCard = pCallback; + + return HAL_OK; +} /** * @} */ @@ -2403,7 +2450,7 @@ HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) * @param Callback io IRQ handler. */ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, - HAL_SDIO_IOFunction_CallbackTypeDef Callback) + HAL_SDIO_IOFunction_CallbackTypeDef pCallback) { /* Check the parameters */ assert_param(hsdio != NULL); @@ -2415,7 +2462,7 @@ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, return HAL_ERROR; } - hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = Callback; + hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = pCallback; hsdio->IOFunctionMask |= (1U << (uint8_t)IOFunction); return HAL_OK; @@ -2444,7 +2491,6 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) uint16_t sdio_rca = 1U; uint32_t Resp4; uint32_t nbr_of_func; - SDMMC_InitTypeDef Init; /* Identify card operating voltage */ errorstate = SDMMC_CmdGoIdleState(hsdio->Instance); @@ -2514,21 +2560,6 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) return HAL_ERROR; } - /* Configure the SDMMC user parameters */ - Init.ClockEdge = hsdio->Init.ClockEdge; - Init.ClockPowerSave = hsdio->Init.ClockPowerSave; - Init.BusWide = hsdio->Init.BusWide; - Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; - Init.ClockDiv = hsdio->Init.ClockDiv; - (void)SDMMC_Init(hsdio->Instance, Init); - - uint8_t data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; - - if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) - { - return HAL_ERROR; - } - return HAL_OK; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c index dc0b588985..cb904b2194 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c @@ -828,6 +828,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, co /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -935,6 +943,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; @@ -1001,6 +1017,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->TxXferCount = Size; hsmartcard->TxISR = NULL; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -1094,6 +1118,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Configure Rx interrupt processing */ if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) { @@ -1395,8 +1427,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1420,8 +1454,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1492,8 +1528,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1558,8 +1596,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1657,9 +1697,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable DMA Tx at UART level */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1681,8 +1723,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1771,8 +1815,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1869,8 +1915,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -2052,8 +2100,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel */ if (hsmartcard->hdmarx != NULL) { @@ -2106,8 +2156,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel */ if (hsmartcard->hdmatx != NULL) { @@ -2744,10 +2796,12 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); hsmartcard->TxXferCount = 0U; +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } @@ -2767,10 +2821,12 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c index 58e66052ef..86f93668e9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c @@ -240,6 +240,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { uint32_t crc_length; uint32_t packet_length; +#if (USE_SPI_CRC != 0UL) + uint32_t crc_poly_msb_mask; +#endif /* USE_SPI_CRC */ /* Check the SPI handle allocation */ if (hspi == NULL) @@ -327,6 +330,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) crc_length = hspi->Init.CRCLength; } + /* Verify the correctness of polynom size */ + assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length)); + /* Verify that the CRC Length is higher than DataSize */ if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) { @@ -444,15 +450,21 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) { + /* Set SPI_CR1_CRC33_17 bit */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); } else { + /* Clear SPI_CR1_CRC33_17 bit */ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); - } - /* Write CRC polynomial in SPI Register */ - WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + /* Write CRC polynomial and set MSB bit at 1 in SPI Register */ + /* Set MSB is mandatory for a correct CRC computation */ + crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U)); + WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask); + } } #endif /* USE_SPI_CRC */ @@ -834,6 +846,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1050,6 +1072,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t temp_sr_reg; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ @@ -1057,6 +1082,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1115,13 +1150,32 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/EOT flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); hspi->pRxBuffPtr += sizeof(uint32_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1147,6 +1201,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1158,6 +1215,43 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1183,6 +1277,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1190,6 +1287,35 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr += sizeof(uint8_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1260,12 +1386,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t uint32_t tickstart; uint32_t fifo_length; + uint32_t temp_sr_reg; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1341,28 +1480,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check RXWNE/EOT flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL)) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount --; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1388,32 +1543,70 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1432,28 +1625,58 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1495,6 +1718,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if ((pData == NULL) || (Size == 0UL)) { return HAL_ERROR; @@ -1579,6 +1812,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1674,6 +1917,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1790,6 +2043,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1976,6 +2239,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } if (hspi->State != HAL_SPI_STATE_READY) { @@ -2166,6 +2438,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -2200,9 +2482,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) || \ + (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD)) && \ (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE) || \ + (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)))) { /* Restriction the DMA data received is not allowed in this mode */ /* Unlock the process */ @@ -2609,6 +2895,15 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized before any call to DMA Abort functions */ + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + } + if (hspi->hdmatx != NULL) { if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c index e46eb95022..e26b02892a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c @@ -57,7 +57,6 @@ data transfers. (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_ConfigureUnderrun() diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c index 97eadff426..48d7aa5653 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c @@ -7280,8 +7280,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -7294,16 +7292,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** @@ -7428,7 +7425,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c index afe917be16..186beac392 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c @@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1149,17 +1149,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1403,7 +1392,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2199,6 +2188,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2215,15 +2205,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -2231,20 +2213,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ @@ -2268,7 +2243,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2703,7 +2677,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } - case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -3177,7 +3150,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3191,7 +3164,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3206,7 +3179,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3221,7 +3194,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -3461,6 +3434,11 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } else { /* nothing to do */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c index e1a10962ca..0281da35c2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c @@ -721,7 +721,6 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -846,7 +845,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -1444,6 +1442,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ if (huart->hdmatx != NULL) { /* Set the UART DMA transfer complete callback */ @@ -1506,9 +1509,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } } +#if !defined(USART_DMAREQUESTS_SW_WA) /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -2577,6 +2582,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3919,7 +3946,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -4591,6 +4617,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4755,6 +4782,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c index 9118d79228..e276ee185f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; @@ -705,6 +705,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; @@ -824,6 +832,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c index 0d77c727ea..3793fb1b0a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -227,8 +227,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -240,7 +240,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -659,11 +659,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -3224,7 +3223,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c index 83112cccfe..c050547f02 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c index 3b52eeb352..f7dcc45345 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c @@ -1282,7 +1282,7 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusC * @note This function is used only in Indirect Write Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pD /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1444,7 +1444,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pDa * @note This function is used only in Indirect Write Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; @@ -1462,7 +1462,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const * of data and the fifo threshold should be aligned on word * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t data_size = hxspi->Instance->DLR + 1U; @@ -1644,7 +1644,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *cons if (status == HAL_OK) { hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -2542,12 +2542,10 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSP HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; uint32_t tickstart = HAL_GetTick(); - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Check if the DMA is enabled */ if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) @@ -2620,11 +2618,9 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Disable all interrupts */ HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); @@ -3586,7 +3582,7 @@ static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxsp { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hxspi->State = HAL_XSPI_STATE_ERROR; + hxspi->State = HAL_XSPI_STATE_READY; hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; return HAL_TIMEOUT; @@ -3662,6 +3658,14 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the CCR register with DQS and SIOO modes */ *ccr_reg = (pCmd->DQSMode | pCmd->SIOOMode); + /* Workaround for Erratasheet: Memory-mapped write error response when DQS output is disabled */ + if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + /* When doing memory-mapped writes, set the DQSE bit of the OCTOSPI_WCCR register, + even for memories that have no DQS pin. */ + SET_BIT((*ccr_reg), XSPI_CCR_DQSE); + } + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) { /* Configure the ABR register with alternate bytes value */ @@ -3684,6 +3688,25 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC } } + /* Configure SSHIFT register to handle SDR/DTR data transfer */ + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) + { + /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */ + CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) + { + /* Configure sample shifting */ + SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else + { + /* Do nothing */ + } + } + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) { if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c index 5b074bcdac..1ff6e2e7f2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c @@ -875,9 +875,8 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode)); assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); } - - /* Check node type */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE) + /* Check non 2D addressing settings */ + if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE) { assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength)); assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength)); @@ -1133,6 +1132,11 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2)); } } + else + { + /* Reset of the CLLR of the node being created */ + pNode->LinkRegisters[reg_counter] = 0U; + } return (uint32_t)SUCCESS; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c index efc43f5848..19e0f767ac 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c @@ -113,8 +113,6 @@ ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) return (status); } - - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c index 1b0a5d9547..183caeaf49 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c @@ -64,7 +64,7 @@ /* compatibility with other STM32 families. */ #define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__) \ ( ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0) \ - || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1) \ + || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC) \ ) /* Note: Comparator non-inverting inputs parameters are the same on all */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c index 468f19d98c..398fa82ccf 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c @@ -110,7 +110,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c index 2aea608e21..03636ed13f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c @@ -349,7 +349,7 @@ uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx) * the configuration information for the SDMMC command * @retval HAL status */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command) { uint32_t tmpreg = 0; @@ -417,7 +417,7 @@ uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -1849,7 +1849,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) * @param pNodeConf: Pointer to configuration parameters for new node to add. * @retval Error status */ -uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf) +uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf) { if ((pNode == NULL) || (pNodeConf == NULL)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c index 43623683e8..3fed68ca5d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c @@ -748,6 +748,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -760,8 +762,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); @@ -815,8 +815,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -844,8 +842,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -894,8 +894,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -923,8 +921,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -973,8 +973,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -1002,8 +1000,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1052,8 +1052,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1081,8 +1079,10 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); @@ -1357,7 +1357,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c index 66ed62f8cd..a7148bdac3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c @@ -112,7 +112,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) * the configuration information for the UCPD peripheral. * @retval An ErrorStatus enumeration value. (Return always SUCCESS) */ -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct) +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct) { /* Check the ucpd Instance UCPDx*/ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c index 4c841c9349..1ffe57c1f6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c @@ -794,17 +794,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } } if (dma == 1U) @@ -2604,6 +2604,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -2708,7 +2712,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -2810,9 +2814,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -2844,19 +2848,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -2865,15 +2875,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -2884,18 +2892,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -2939,26 +2937,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } @@ -3397,7 +3392,14 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, } /* Clear device address, Endpoint number and Low Speed Endpoint fields */ - wChRegVal &= ~(USB_CHEP_DEVADDR | USB_CHEP_ADDR | USB_CHEP_LSEP); + wChRegVal &= ~(USB_CHEP_DEVADDR | + USB_CHEP_ADDR | + USB_CHEP_LSEP | + USB_CHEP_NAK | + USB_CHEP_KIND | + USB_CHEP_ERRTX | + USB_CHEP_ERRRX | + (0xFU << 27)); /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | @@ -3446,6 +3448,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) if (hc->doublebuffer == 0U) { + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_RX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_RX_DTOG(USBx, phy_ch_num); + } + } + /* Set RX buffer count */ USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); } @@ -3503,6 +3517,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) { USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); } + + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_TX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_TX_DTOG(USBx, phy_ch_num); + } + } } #if (USE_USB_DOUBLE_BUFFER == 1U) else if (hc->ep_type == EP_TYPE_BULK) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index cee30061e2..6b5af8d613 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.6 * STM32MP1: 1.6.0 * STM32U0: 1.2.0 - * STM32U5: 1.6.0 + * STM32U5: 1.6.1 * STM32WB: 1.14.4 * STM32WBA: 1.5.0 * STM32WL: 1.3.0 From a2e6705c89c79ac90b59eada80091f81208dd0e2 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Jan 2025 11:16:52 +0100 Subject: [PATCH 074/141] system(U5): update STM32U5xx CMSIS Drivers to v1.4.1 Included in STM32CubeU5 FW v1.7.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32U5xx/Include/stm32u535xx.h | 9 +- .../Device/ST/STM32U5xx/Include/stm32u545xx.h | 9 +- .../Device/ST/STM32U5xx/Include/stm32u575xx.h | 356 +++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u585xx.h | 356 +++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u595xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u599xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5a5xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5a9xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5f7xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5f9xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5g7xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5g9xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5xx.h | 10 +- .../Device/ST/STM32U5xx/Release_Notes.html | 38 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 15 files changed, 2427 insertions(+), 1265 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h index 4c1c81abc7..a26269d33a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h @@ -216,7 +216,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -4796,6 +4796,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ /* */ @@ -16168,7 +16171,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20293,7 +20296,7 @@ typedef struct #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -4960,6 +4960,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ /* */ @@ -16720,7 +16723,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20889,7 +20892,7 @@ typedef struct #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5198,6 +5198,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) /******************************************************************************/ /* */ @@ -17682,7 +17686,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20856,9 +20860,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -20894,6 +20916,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -20965,11 +20990,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -20995,11 +21026,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -21040,9 +21074,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -21084,9 +21118,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -21118,6 +21152,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -21136,6 +21173,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -21177,21 +21217,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -21215,9 +21270,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -21251,6 +21306,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -21272,9 +21330,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -21328,12 +21386,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -21372,19 +21433,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -21597,51 +21684,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -21700,7 +21787,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -21709,7 +21795,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -21717,7 +21802,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -21763,9 +21847,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -21805,10 +21889,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -21820,7 +21904,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -21834,19 +21917,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -21950,6 +22030,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -21979,9 +22062,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -22014,9 +22097,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -22025,14 +22108,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -22064,15 +22147,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -22090,6 +22170,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22104,18 +22190,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -22125,22 +22229,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5411,6 +5411,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) /******************************************************************************/ /* */ @@ -18292,7 +18296,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -21518,9 +21522,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -21556,6 +21578,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -21627,11 +21652,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -21657,11 +21688,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -21702,9 +21736,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -21746,9 +21780,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -21780,6 +21814,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -21798,6 +21835,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -21839,21 +21879,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -21877,9 +21932,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -21913,6 +21968,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -21934,9 +21992,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -21990,12 +22048,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -22034,19 +22095,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -22259,51 +22346,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -22362,7 +22449,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -22371,7 +22457,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -22379,7 +22464,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -22425,9 +22509,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -22467,10 +22551,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22482,7 +22566,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -22496,19 +22579,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -22612,6 +22692,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -22641,9 +22724,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -22676,9 +22759,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -22687,14 +22770,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -22726,15 +22809,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -22752,6 +22832,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22766,18 +22852,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -22787,22 +22891,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5443,6 +5443,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -18792,7 +18796,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -22154,9 +22158,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -22192,6 +22214,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -22263,11 +22288,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -22293,11 +22324,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -22338,9 +22372,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -22382,9 +22416,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -22416,6 +22450,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -22434,6 +22471,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -22475,21 +22515,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -22513,9 +22568,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -22549,6 +22604,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -22570,9 +22628,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -22626,12 +22684,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -22670,19 +22731,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -22847,7 +22934,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -22875,13 +22962,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -22907,51 +22994,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -23010,7 +23097,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -23019,7 +23105,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -23027,7 +23112,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -23073,9 +23157,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -23115,10 +23199,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23130,7 +23214,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -23144,19 +23227,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -23260,6 +23340,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -23289,9 +23372,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -23324,9 +23407,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -23335,14 +23418,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -23374,15 +23457,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -23400,6 +23480,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23414,18 +23500,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -23435,22 +23539,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5731,6 +5731,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -22566,7 +22570,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -25988,9 +25992,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -26026,6 +26048,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -26097,11 +26122,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -26127,11 +26158,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -26172,9 +26206,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -26216,9 +26250,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -26250,6 +26284,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -26268,6 +26305,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -26309,21 +26349,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -26347,9 +26402,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -26383,6 +26438,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -26404,9 +26462,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -26460,12 +26518,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -26504,19 +26565,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -26681,7 +26768,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -26709,13 +26796,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -26741,51 +26828,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -26844,7 +26931,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -26853,7 +26939,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -26861,7 +26946,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -26907,9 +26991,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -26949,10 +27033,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -26964,7 +27048,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -26978,19 +27061,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -27094,6 +27174,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -27123,9 +27206,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -27158,9 +27241,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -27169,14 +27252,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -27208,15 +27291,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -27234,6 +27314,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27248,18 +27334,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -27269,22 +27373,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5656,6 +5656,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -19402,7 +19406,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -22816,9 +22820,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -22854,6 +22876,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -22925,11 +22950,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -22955,11 +22986,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -23000,9 +23034,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -23044,9 +23078,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -23078,6 +23112,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -23096,6 +23133,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -23137,21 +23177,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -23175,9 +23230,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -23211,6 +23266,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -23232,9 +23290,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -23288,12 +23346,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -23332,19 +23393,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -23509,7 +23596,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -23537,13 +23624,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -23569,51 +23656,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -23672,7 +23759,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -23681,7 +23767,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -23689,7 +23774,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -23735,9 +23819,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -23777,10 +23861,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23792,7 +23876,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -23806,19 +23889,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -23922,6 +24002,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -23951,9 +24034,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -23986,9 +24069,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -23997,14 +24080,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -24036,15 +24119,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -24062,6 +24142,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -24076,18 +24162,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -24097,22 +24201,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5944,6 +5944,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -23176,7 +23180,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -26650,9 +26654,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -26688,6 +26710,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -26759,11 +26784,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -26789,11 +26820,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -26834,9 +26868,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -26878,9 +26912,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -26912,6 +26946,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -26930,6 +26967,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -26971,21 +27011,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -27009,9 +27064,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -27045,6 +27100,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -27066,9 +27124,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -27122,12 +27180,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -27166,19 +27227,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -27343,7 +27430,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -27371,13 +27458,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -27403,51 +27490,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -27506,7 +27593,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -27515,7 +27601,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -27523,7 +27608,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -27569,9 +27653,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -27611,10 +27695,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27626,7 +27710,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -27640,19 +27723,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -27756,6 +27836,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -27785,9 +27868,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -27820,9 +27903,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -27831,14 +27914,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -27870,15 +27953,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -27896,6 +27976,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27910,18 +27996,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -27931,22 +28035,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5739,6 +5739,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -20385,7 +20389,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -23835,9 +23839,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -23873,6 +23895,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -23944,11 +23969,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -23974,11 +24005,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -24019,9 +24053,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -24063,9 +24097,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -24097,6 +24131,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -24115,6 +24152,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -24156,21 +24196,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -24194,9 +24249,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -24230,6 +24285,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -24251,9 +24309,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -24307,12 +24365,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -24351,19 +24412,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -24528,7 +24615,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -24556,13 +24643,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -24588,51 +24675,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -24691,7 +24778,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -24700,7 +24786,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -24708,7 +24793,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -24754,9 +24838,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -24796,10 +24880,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -24811,7 +24895,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -24825,19 +24908,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -24941,6 +25021,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -24970,9 +25053,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -25005,9 +25088,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -25016,14 +25099,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -25055,15 +25138,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -25081,6 +25161,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25095,18 +25181,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -25116,22 +25220,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5859,6 +5859,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -23526,7 +23530,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -26988,9 +26992,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -27026,6 +27048,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -27097,11 +27122,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -27127,11 +27158,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -27172,9 +27206,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -27216,9 +27250,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -27250,6 +27284,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -27268,6 +27305,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -27309,21 +27349,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -27347,9 +27402,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -27383,6 +27438,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -27404,9 +27462,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -27460,12 +27518,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -27504,19 +27565,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -27681,7 +27768,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -27709,13 +27796,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -27741,51 +27828,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -27844,7 +27931,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -27853,7 +27939,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -27861,7 +27946,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -27907,9 +27991,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -27949,10 +28033,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27964,7 +28048,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -27978,19 +28061,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -28094,6 +28174,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -28123,9 +28206,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -28158,9 +28241,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -28169,14 +28252,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -28208,15 +28291,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -28234,6 +28314,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28248,18 +28334,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -28269,22 +28373,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5952,6 +5952,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -20995,7 +20999,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -24497,9 +24501,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -24535,6 +24557,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -24606,11 +24631,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -24636,11 +24667,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -24681,9 +24715,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -24725,9 +24759,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -24759,6 +24793,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -24777,6 +24814,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -24818,21 +24858,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -24856,9 +24911,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -24892,6 +24947,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -24913,9 +24971,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -24969,12 +25027,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -25013,19 +25074,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -25190,7 +25277,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -25218,13 +25305,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -25250,51 +25337,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -25353,7 +25440,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -25362,7 +25448,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -25370,7 +25455,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -25416,9 +25500,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -25458,10 +25542,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25473,7 +25557,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -25487,19 +25570,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -25603,6 +25683,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -25632,9 +25715,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -25667,9 +25750,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -25678,14 +25761,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -25717,15 +25800,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -25743,6 +25823,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25757,18 +25843,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -25778,22 +25882,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -6072,6 +6072,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -24136,7 +24140,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -27650,9 +27654,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -27688,6 +27710,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -27759,11 +27784,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -27789,11 +27820,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -27834,9 +27868,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -27878,9 +27912,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -27912,6 +27946,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -27930,6 +27967,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -27971,21 +28011,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -28009,9 +28064,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -28045,6 +28100,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -28066,9 +28124,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -28122,12 +28180,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -28166,19 +28227,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -28343,7 +28430,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -28371,13 +28458,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -28403,51 +28490,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -28506,7 +28593,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -28515,7 +28601,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -28523,7 +28608,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -28569,9 +28653,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -28611,10 +28695,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28626,7 +28710,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -28640,19 +28723,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -28756,6 +28836,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -28785,9 +28868,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -28820,9 +28903,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -28831,14 +28914,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -28870,15 +28953,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -28896,6 +28976,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28910,18 +28996,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -28931,22 +29035,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!Release Notes for  STM32U5xx C

                                                              Update History

                                                              - +

                                                              Main Changes

                                                              +
                                                                +
                                                              • General updates to fix known defects and implementation enhancements.
                                                                • +
                                                              • Fix TAMP_CR3_ITAMP7NOER bit definition to be aligned with reference manual.
                                                                • +
                                                              • Add missing USB_OTG_GINTSTS_RSTDET bit definition.
                                                                • +
                                                              • Align USB OTG bit definition with reference manual.
                                                                • +
                                                              +

                                                              Backward Compatibility

                                                              +
                                                                +
                                                              • N/A
                                                                • +
                                                              +
                                                              +
                                                              +
                                                              + +
                                                              +

                                                              Main Changes

                                                              CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

                                                              • Add Bits definition for RNG_NSCR register for RNG noise source control
                                                                • @@ -45,7 +61,7 @@

                                                                Main Changes

                                                              • Fix wrong declaration of g_pfnVectors size in GCC startup_stm32u5XXxx.s files
                                                              • Update linker files to properly mark sections readonly for GCC12
                                                              -

                                                              Backward Compatibility

                                                              +

                                                              Backward Compatibility

                                                              • N/A
                                                              @@ -54,12 +70,12 @@

                                                              Backward Compatibility

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

                                                              • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h†file
                                                              -

                                                              Backward Compatibility

                                                              +

                                                              Backward Compatibility

                                                              • N/A
                                                              @@ -68,7 +84,7 @@

                                                              Backward Compatibility

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

                                                              • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices: @@ -78,7 +94,7 @@

                                                                Main Changes

                                                              • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
                                                            -

                                                            Backward Compatibility

                                                            +

                                                            Backward Compatibility

                                                            • N/A
                                                            @@ -87,7 +103,7 @@

                                                            Backward Compatibility

                                                            -

                                                            Main Changes

                                                            +

                                                            Main Changes

                                                            CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

                                                            • Support of stm32u535xx and stm32u545xx devices: @@ -140,7 +156,7 @@

                                                              Main Changes

                                                            • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
                                                          -

                                                          Backward Compatibility

                                                          +

                                                          Backward Compatibility

                                                          • N/A
                                                          @@ -149,7 +165,7 @@

                                                          Backward Compatibility

                                                          -

                                                          Main Changes

                                                          +

                                                          Main Changes

                                                          • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
                                                              @@ -179,7 +195,7 @@

                                                              Main Changes

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
                                                              • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
                                                                • @@ -191,7 +207,7 @@

                                                                Main Changes

                                                                -

                                                                Main Changes

                                                                +

                                                                Main Changes

                                                                • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
                                                                diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 0e3e0ae7c6..c2b839afcd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.6 * STM32MP1: 1.6.0 * STM32U0: 1.2.0 - * STM32U5: 1.4.0 + * STM32U5: 1.4.1 * STM32WB: 1.12.2 * STM32WBA: 1.5.0 * STM32WL: 1.2.0 From 82b932ab4a4b6295ef29b7548859c3cee63228cd Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 9 Dec 2024 11:47:47 +0100 Subject: [PATCH 075/141] fix(h5): review system clock configuration SPI clock selection have to be explicitly done and ensure frequency allows standard SPI freq based on the SPI baudrate prescaler. Also prevent to use HSE as it is not operational as oscillator. See Errata sheet. Fixes #2598 Signed-off-by: Frederic Pillon --- .../STM32H5xx/H503CB(T-U)/generic_clock.c | 34 +++++++---- variants/STM32H5xx/H503RBT/generic_clock.c | 12 +++- .../H503RBT/variant_NUCLEO_H503RB.cpp | 50 ++++++++++------ .../STM32H5xx/H562R(G-I)T/generic_clock.c | 46 ++++++++------ .../H562R(G-I)T/variant_WEACT_H562RG.cpp | 60 ++++++++++++------- .../H563IIKxQ_H573IIKxQ/generic_clock.c | 47 ++++++++++++--- .../variant_STM32H573I_DK.cpp | 39 +++++++++--- .../H563R(G-I)T_H573RIT/generic_clock.c | 33 ++++++---- .../H563Z(G-I)T_H573ZIT/generic_clock.c | 44 +++++++++----- .../variant_NUCLEO_H563ZI.cpp | 39 ++++++++---- 10 files changed, 282 insertions(+), 122 deletions(-) diff --git a/variants/STM32H5xx/H503CB(T-U)/generic_clock.c b/variants/STM32H5xx/H503CB(T-U)/generic_clock.c index 9bb79e4f8f..914aa62e0f 100644 --- a/variants/STM32H5xx/H503CB(T-U)/generic_clock.c +++ b/variants/STM32H5xx/H503CB(T-U)/generic_clock.c @@ -33,11 +33,8 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI - | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI + | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.CSIState = RCC_CSI_ON; @@ -47,7 +44,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; @@ -71,14 +68,31 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSI; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 + | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; + PeriphClkInitStruct.PLL2.PLL2M = 1; + PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 15; + PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 784645b735..2ac59ece4c 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -43,7 +43,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; @@ -64,9 +64,14 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /* Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_USB; + | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 + | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; PeriphClkInitStruct.PLL2.PLL2M = 1; PeriphClkInitStruct.PLL2.PLL2N = 125; @@ -80,6 +85,9 @@ WEAK void SystemClock_Config(void) PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index c4a3874d8a..1bdf66f48a 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -114,20 +114,27 @@ WEAK void SystemClock_Config(void) while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + /** Configure LSE Drive Capability + * Warning : Only applied when the LSE is disabled. + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE - | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE + | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 12; - RCC_OscInitStruct.PLL.PLLN = 250; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -148,23 +155,30 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /* Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - PeriphClkInitStruct.PLL2.PLL2M = 2; - PeriphClkInitStruct.PLL2.PLL2N = 31; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI1 + | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; + PeriphClkInitStruct.PLL2.PLL2M = 1; + PeriphClkInitStruct.PLL2.PLL2N = 125; PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 12; - PeriphClkInitStruct.PLL2.PLL2R = 3; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_3; + PeriphClkInitStruct.PLL2.PLL2Q = 15; + PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 2048; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H562R(G-I)T/generic_clock.c b/variants/STM32H5xx/H562R(G-I)T/generic_clock.c index 387eb2c67c..346843eb6d 100644 --- a/variants/STM32H5xx/H562R(G-I)T/generic_clock.c +++ b/variants/STM32H5xx/H562R(G-I)T/generic_clock.c @@ -33,14 +33,16 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI + | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 120; + RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; @@ -51,6 +53,7 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK @@ -66,36 +69,45 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC - | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SDMMC1 - | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB + | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 + | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI6; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; PeriphClkInitStruct.PLL2.PLL2M = 1; PeriphClkInitStruct.PLL2.PLL2N = 125; PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 2; - PeriphClkInitStruct.PLL2.PLL2R = 5; + PeriphClkInitStruct.PLL2.PLL2Q = 15; + PeriphClkInitStruct.PLL2.PLL2R = 10; PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVR; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; - PeriphClkInitStruct.PLL3.PLL3M = 1; - PeriphClkInitStruct.PLL3.PLL3N = 40; + PeriphClkInitStruct.PLL3.PLL3M = 2; + PeriphClkInitStruct.PLL3.PLL3N = 125; PeriphClkInitStruct.PLL3.PLL3P = 2; PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; - PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; - PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3Q; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL1Q; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp b/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp index 140bedd345..de8d46e0f5 100644 --- a/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp +++ b/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp @@ -112,23 +112,27 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSE ; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI + | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 62; + RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; - RCC_OscInitStruct.PLL.PLLFRACN = 4096; + RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK @@ -147,37 +151,49 @@ WEAK void SystemClock_Config(void) /** Configure the programming delay */ __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC - | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB + | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 + | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI6; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 32; + PeriphClkInitStruct.PLL2.PLL2N = 125; PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 8; - PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2Q = 15; + PeriphClkInitStruct.PLL2.PLL2R = 10; PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; - PeriphClkInitStruct.PLL3.PLL3M = 1; - PeriphClkInitStruct.PLL3.PLL3N = 48; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; + PeriphClkInitStruct.PLL3.PLL3M = 2; + PeriphClkInitStruct.PLL3.PLL3N = 125; PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 8; + PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; - PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL1Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } + + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); } #ifdef __cplusplus diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c index 708820d6df..341cde4070 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c @@ -33,11 +33,8 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI - | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI + | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.CSIState = RCC_CSI_ON; @@ -47,7 +44,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; @@ -71,17 +68,49 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 + | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 + | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 + | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; + PeriphClkInitStruct.PLL2.PLL2M = 1; + PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 15; + PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; + PeriphClkInitStruct.PLL3.PLL3M = 2; + PeriphClkInitStruct.PLL3.PLL3N = 125; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 5; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi5ClockSelection = RCC_SPI5CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp index 47585ba96a..0d4f520fb1 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp @@ -222,7 +222,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 5; RCC_OscInitStruct.PLL.PLLN = 100; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; @@ -245,25 +245,50 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } + + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SAI1 - | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_SDMMC1 - | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_CSI; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 + | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 + | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 + | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 + | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; PeriphClkInitStruct.PLL2.PLL2M = 1; PeriphClkInitStruct.PLL2.PLL2N = 32; PeriphClkInitStruct.PLL2.PLL2P = 1; - PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 4; PeriphClkInitStruct.PLL2.PLL2R = 2; PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVP; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; + PeriphClkInitStruct.PLL3.PLL3M = 2; + PeriphClkInitStruct.PLL3.PLL3N = 125; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 5; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL2P; PeriphClkInitStruct.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL2P; PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi5ClockSelection = RCC_SPI5CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c b/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c index cb3cdb6571..8a4327650f 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c @@ -34,8 +34,10 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI + | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -43,7 +45,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; @@ -67,33 +69,44 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 + | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_USB; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; PeriphClkInitStruct.PLL2.PLL2M = 1; PeriphClkInitStruct.PLL2.PLL2N = 125; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; - PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2R = 8; PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; - PeriphClkInitStruct.PLL3.PLL3M = 1; - PeriphClkInitStruct.PLL3.PLL3N = 48; + PeriphClkInitStruct.PLL3.PLL3M = 2; + PeriphClkInitStruct.PLL3.PLL3N = 125; PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 4; + PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; - PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; - PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c index 2d32b7fe70..f983f04d9c 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c @@ -34,8 +34,10 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI + | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -43,9 +45,9 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -67,33 +69,47 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI1 + | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 + | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 + | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_USB; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 2; - PeriphClkInitStruct.PLL2.PLL2N = 250; + PeriphClkInitStruct.PLL2.PLL2M = 1; + PeriphClkInitStruct.PLL2.PLL2N = 125; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; PeriphClkInitStruct.PLL3.PLL3M = 2; - PeriphClkInitStruct.PLL3.PLL3N = 240; + PeriphClkInitStruct.PLL3.PLL3N = 125; PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 10; + PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; - PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi5ClockSelection = RCC_SPI5CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp index b5b8a28c74..6446bceb5b 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp @@ -179,6 +179,12 @@ WEAK void SystemClock_Config(void) while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + /** Configure LSE Drive Capability + * Warning : Only applied when the LSE is disabled. + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ @@ -215,29 +221,28 @@ WEAK void SystemClock_Config(void) Error_Handler(); } - /** Initializes the peripherals clock + /** Configure the programming delay */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK3; - PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI1 + | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 + | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 + | RCC_PERIPHCLK_SPI6; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; PeriphClkInitStruct.PLL2.PLL2M = 2; PeriphClkInitStruct.PLL2.PLL2N = 125; - PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2P = 10; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVP | RCC_PLL2_DIVQ + | RCC_PLL2_DIVR; PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; PeriphClkInitStruct.PLL3.PLL3M = 2; PeriphClkInitStruct.PLL3.PLL3N = 96; @@ -248,6 +253,14 @@ WEAK void SystemClock_Config(void) PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL2P; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL2P; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL2P; + PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi5ClockSelection = RCC_SPI5CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { From bfdefe24f542b979956912af7f35fef8bb8da83a Mon Sep 17 00:00:00 2001 From: Sasha Olenyev Date: Tue, 5 Nov 2024 12:22:04 +0200 Subject: [PATCH 076/141] feat(uart): support UART Tx Rx pin swap function Resolves: #2538 --- libraries/SrcWrapper/src/stm32/uart.c | 55 +++++++++++++++++++++------ 1 file changed, 43 insertions(+), 12 deletions(-) diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index 219b42fc65..187335521d 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -121,16 +121,25 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par USART_TypeDef *uart_rx = pinmap_peripheral(obj->pin_rx, PinMap_UART_RX); USART_TypeDef *uart_rts = pinmap_peripheral(obj->pin_rts, PinMap_UART_RTS); USART_TypeDef *uart_cts = pinmap_peripheral(obj->pin_cts, PinMap_UART_CTS); + /* Check if pins are swapped */ +#if defined(UART_ADVFEATURE_SWAP_INIT) + USART_TypeDef *uart_tx_swap = pinmap_peripheral(obj->pin_tx, PinMap_UART_RX); + USART_TypeDef *uart_rx_swap = pinmap_peripheral(obj->pin_rx, PinMap_UART_TX); +#else + /* Pin swap not supported */ + USART_TypeDef *uart_tx_swap = NP; + USART_TypeDef *uart_rx_swap = NP; +#endif /* Pin Tx must not be NP */ - if (uart_tx == NP) { + if ((uart_tx == NP) && (uart_tx_swap == NP)) { if (obj != &serial_debug) { core_debug("ERROR: [U(S)ART] Tx pin has no peripheral!\n"); } return; } /* Pin Rx must not be NP if not half-duplex */ - if ((obj->pin_rx != NC) && (uart_rx == NP)) { + if ((obj->pin_rx != NC) && (uart_rx == NP) && (uart_rx_swap == NP)) { if (obj != &serial_debug) { core_debug("ERROR: [U(S)ART] Rx pin has no peripheral!\n"); } @@ -156,6 +165,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par * and assign it to the object */ obj->uart = pinmap_merge_peripheral(uart_tx, uart_rx); + if (obj->uart == NP) { + /* Regular pins not matched, check if they can be swapped */ + obj->uart = pinmap_merge_peripheral(uart_tx_swap, uart_rx_swap); + } /* We also merge RTS/CTS and assert all pins belong to the same instance */ obj->uart = pinmap_merge_peripheral(obj->uart, uart_rts); obj->uart = pinmap_merge_peripheral(obj->uart, uart_cts); @@ -328,10 +341,26 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par #endif /* Configure UART GPIO pins */ - pinmap_pinout(obj->pin_tx, PinMap_UART_TX); - if (uart_rx != NP) { - pinmap_pinout(obj->pin_rx, PinMap_UART_RX); +#if defined(UART_ADVFEATURE_SWAP_INIT) + uint32_t pin_swap = UART_ADVFEATURE_SWAP_DISABLE; +#endif + if (uart_tx != NP) { + /* Regular GPIO */ + pinmap_pinout(obj->pin_tx, PinMap_UART_TX); + if (uart_rx != NP) { + pinmap_pinout(obj->pin_rx, PinMap_UART_RX); + } + } +#if defined(UART_ADVFEATURE_SWAP_INIT) + else if (uart_tx_swap != NP) { + /* Swapped GPIO */ + pinmap_pinout(obj->pin_tx, PinMap_UART_RX); + if (uart_rx_swap != NP) { + pinmap_pinout(obj->pin_rx, PinMap_UART_TX); + } + pin_swap = UART_ADVFEATURE_SWAP_ENABLE; } +#endif /* Configure flow control */ uint32_t flow_control = UART_HWCONTROL_NONE; @@ -354,8 +383,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par huart->Init.Mode = UART_MODE_TX_RX; huart->Init.HwFlowCtl = flow_control; huart->Init.OverSampling = UART_OVERSAMPLING_16; -#if !defined(STM32F1xx) && !defined(STM32F2xx) && !defined(STM32F4xx)\ - && !defined(STM32L1xx) +#if defined(UART_ADVFEATURE_SWAP_INIT) + huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_SWAP_INIT; + huart->AdvancedInit.Swap = pin_swap; +#elif defined(UART_ADVFEATURE_NO_INIT) huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; #endif #ifdef UART_ONE_BIT_SAMPLE_DISABLE @@ -391,7 +422,7 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par HAL_UARTEx_DisableStopMode(huart); } /* Trying default LPUART clock source */ - if (uart_rx == NP) { + if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { return; } @@ -416,7 +447,7 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_LSE); } #endif - if (uart_rx == NP) { + if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { return; } @@ -438,7 +469,7 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_HSI); } #endif - if (uart_rx == NP) { + if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { return; } @@ -465,7 +496,7 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_PCLK1); } #endif - if (uart_rx == NP) { + if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { return; } @@ -490,7 +521,7 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par } #endif - if (uart_rx == NP) { + if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) != HAL_OK) { return; } From e5fed33f7766aa9c5f02c98dcf63915fe902b3ca Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 22 Jan 2025 16:57:48 +0100 Subject: [PATCH 077/141] chore: update cmake Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 108 +++++++++++++++--- .../H7A3Z(G-I)TxQ_H7B3ZITxQ/CMakeLists.txt | 1 + 2 files changed, 96 insertions(+), 13 deletions(-) diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 4db190a96b..40181d8660 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -89928,7 +89928,7 @@ set(GENERIC_L100C6UXA_MCU cortex-m3) set(GENERIC_L100C6UXA_FPCONF "-") add_library(GENERIC_L100C6UXA INTERFACE) target_compile_options(GENERIC_L100C6UXA INTERFACE - "SHELL:-DSTM32L100xB " + "SHELL:-DSTM32L100xBA " "SHELL:" "SHELL:" "SHELL: " @@ -90068,7 +90068,7 @@ set(GENERIC_L151C6TXA_MCU cortex-m3) set(GENERIC_L151C6TXA_FPCONF "-") add_library(GENERIC_L151C6TXA INTERFACE) target_compile_options(GENERIC_L151C6TXA INTERFACE - "SHELL:-DSTM32L151xB " + "SHELL:-DSTM32L151xBA " "SHELL:" "SHELL:" "SHELL: " @@ -90208,7 +90208,7 @@ set(GENERIC_L151C6UXA_MCU cortex-m3) set(GENERIC_L151C6UXA_FPCONF "-") add_library(GENERIC_L151C6UXA INTERFACE) target_compile_options(GENERIC_L151C6UXA INTERFACE - "SHELL:-DSTM32L151xB " + "SHELL:-DSTM32L151xBA " "SHELL:" "SHELL:" "SHELL: " @@ -90348,7 +90348,7 @@ set(GENERIC_L151C8TXA_MCU cortex-m3) set(GENERIC_L151C8TXA_FPCONF "-") add_library(GENERIC_L151C8TXA INTERFACE) target_compile_options(GENERIC_L151C8TXA INTERFACE - "SHELL:-DSTM32L151xB " + "SHELL:-DSTM32L151xBA " "SHELL:" "SHELL:" "SHELL: " @@ -90488,7 +90488,7 @@ set(GENERIC_L151C8UXA_MCU cortex-m3) set(GENERIC_L151C8UXA_FPCONF "-") add_library(GENERIC_L151C8UXA INTERFACE) target_compile_options(GENERIC_L151C8UXA INTERFACE - "SHELL:-DSTM32L151xB " + "SHELL:-DSTM32L151xBA " "SHELL:" "SHELL:" "SHELL: " @@ -90628,7 +90628,7 @@ set(GENERIC_L151CBTXA_MCU cortex-m3) set(GENERIC_L151CBTXA_FPCONF "-") add_library(GENERIC_L151CBTXA INTERFACE) target_compile_options(GENERIC_L151CBTXA INTERFACE - "SHELL:-DSTM32L151xB " + "SHELL:-DSTM32L151xBA " "SHELL:" "SHELL:" "SHELL: " @@ -90768,7 +90768,7 @@ set(GENERIC_L151CBUXA_MCU cortex-m3) set(GENERIC_L151CBUXA_FPCONF "-") add_library(GENERIC_L151CBUXA INTERFACE) target_compile_options(GENERIC_L151CBUXA INTERFACE - "SHELL:-DSTM32L151xB " + "SHELL:-DSTM32L151xBA " "SHELL:" "SHELL:" "SHELL: " @@ -91048,7 +91048,7 @@ set(GENERIC_L152C6TXA_MCU cortex-m3) set(GENERIC_L152C6TXA_FPCONF "-") add_library(GENERIC_L152C6TXA INTERFACE) target_compile_options(GENERIC_L152C6TXA INTERFACE - "SHELL:-DSTM32L152xB " + "SHELL:-DSTM32L152xBA " "SHELL:" "SHELL:" "SHELL: " @@ -91188,7 +91188,7 @@ set(GENERIC_L152C6UXA_MCU cortex-m3) set(GENERIC_L152C6UXA_FPCONF "-") add_library(GENERIC_L152C6UXA INTERFACE) target_compile_options(GENERIC_L152C6UXA INTERFACE - "SHELL:-DSTM32L152xB " + "SHELL:-DSTM32L152xBA " "SHELL:" "SHELL:" "SHELL: " @@ -91328,7 +91328,7 @@ set(GENERIC_L152C8TXA_MCU cortex-m3) set(GENERIC_L152C8TXA_FPCONF "-") add_library(GENERIC_L152C8TXA INTERFACE) target_compile_options(GENERIC_L152C8TXA INTERFACE - "SHELL:-DSTM32L152xB " + "SHELL:-DSTM32L152xBA " "SHELL:" "SHELL:" "SHELL: " @@ -91468,7 +91468,7 @@ set(GENERIC_L152C8UXA_MCU cortex-m3) set(GENERIC_L152C8UXA_FPCONF "-") add_library(GENERIC_L152C8UXA INTERFACE) target_compile_options(GENERIC_L152C8UXA INTERFACE - "SHELL:-DSTM32L152xB " + "SHELL:-DSTM32L152xBA " "SHELL:" "SHELL:" "SHELL: " @@ -91608,7 +91608,7 @@ set(GENERIC_L152CBTXA_MCU cortex-m3) set(GENERIC_L152CBTXA_FPCONF "-") add_library(GENERIC_L152CBTXA INTERFACE) target_compile_options(GENERIC_L152CBTXA INTERFACE - "SHELL:-DSTM32L152xB " + "SHELL:-DSTM32L152xBA " "SHELL:" "SHELL:" "SHELL: " @@ -91748,7 +91748,7 @@ set(GENERIC_L152CBUXA_MCU cortex-m3) set(GENERIC_L152CBUXA_FPCONF "-") add_library(GENERIC_L152CBUXA INTERFACE) target_compile_options(GENERIC_L152CBUXA INTERFACE - "SHELL:-DSTM32L152xB " + "SHELL:-DSTM32L152xBA " "SHELL:" "SHELL:" "SHELL: " @@ -106350,6 +106350,88 @@ target_compile_options(NUCLEO_H753ZI_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_H7A3ZI_Q +# ----------------------------------------------------------------------------- + +set(NUCLEO_H7A3ZI_Q_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ") +set(NUCLEO_H7A3ZI_Q_MAXSIZE 2097152) +set(NUCLEO_H7A3ZI_Q_MAXDATASIZE 1048576) +set(NUCLEO_H7A3ZI_Q_MCU cortex-m7) +set(NUCLEO_H7A3ZI_Q_FPCONF "fpv4-sp-d16-hard") +add_library(NUCLEO_H7A3ZI_Q INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q INTERFACE + "SHELL:-DSTM32H7A3xxQ " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_H7A3ZI_Q_MCU} +) +target_compile_definitions(NUCLEO_H7A3ZI_Q INTERFACE + "STM32H7xx" + "ARDUINO_NUCLEO_H7A3ZI_Q" + "BOARD_NAME=\"NUCLEO_H7A3ZI_Q\"" + "BOARD_ID=NUCLEO_H7A3ZI_Q" + "VARIANT_H=\"variant_NUCLEO_H7A3ZI_Q.h\"" +) +target_include_directories(NUCLEO_H7A3ZI_Q INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${NUCLEO_H7A3ZI_Q_VARIANT_PATH} +) + +target_link_options(NUCLEO_H7A3ZI_Q INTERFACE + "LINKER:--default-script=${NUCLEO_H7A3ZI_Q_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=1048576" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_H7A3ZI_Q_MCU} +) + +add_library(NUCLEO_H7A3ZI_Q_serial_disabled INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_H7A3ZI_Q_serial_generic INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_H7A3ZI_Q_serial_none INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_H7A3ZI_Q_usb_CDC INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_H7A3ZI_Q_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_H7A3ZI_Q_usb_HID INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_H7A3ZI_Q_usb_none INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_H7A3ZI_Q_xusb_FS INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_H7A3ZI_Q_xusb_HS INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_H7A3ZI_Q_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_H7A3ZI_Q_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_L010RB # ----------------------------------------------------------------------------- diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/CMakeLists.txt b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/CMakeLists.txt index 2a4d55b6b1..f91ab0ed5d 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/CMakeLists.txt +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_NUCLEO_H7A3ZI_Q.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) From eebd0e37a7de432719074edb331f894a9d9b1241 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 22 Jan 2025 16:52:54 +0100 Subject: [PATCH 078/141] fix(uart): add missing USART11 and UART12 support STM32H5 have those instances. Fixes #2640. Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/uart.c | 65 ++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index 187335521d..e762e007ab 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -68,6 +68,12 @@ typedef enum { #if defined(UART10_BASE) || defined(USART10_BASE) UART10_INDEX, #endif +#if defined(USART11_BASE) + UART11_INDEX, +#endif +#if defined(UART12_BASE) + UART12_INDEX, +#endif #if defined(LPUART1_BASE) LPUART1_INDEX, #endif @@ -339,7 +345,24 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par obj->irq = USART10_IRQn; } #endif - +#if defined(USART11_BASE) + else if (obj->uart == USART11) { + __HAL_RCC_USART11_FORCE_RESET(); + __HAL_RCC_USART11_RELEASE_RESET(); + __HAL_RCC_USART11_CLK_ENABLE(); + obj->index = UART11_INDEX; + obj->irq = USART11_IRQn; + } +#endif +#if defined(UART12_BASE) + else if (obj->uart == UART12) { + __HAL_RCC_UART12_FORCE_RESET(); + __HAL_RCC_UART12_RELEASE_RESET(); + __HAL_RCC_UART12_CLK_ENABLE(); + obj->index = UART12_INDEX; + obj->irq = UART12_IRQn; + } +#endif /* Configure UART GPIO pins */ #if defined(UART_ADVFEATURE_SWAP_INIT) uint32_t pin_swap = UART_ADVFEATURE_SWAP_DISABLE; @@ -660,6 +683,20 @@ void uart_deinit(serial_t *obj) __HAL_RCC_USART10_RELEASE_RESET(); __HAL_RCC_USART10_CLK_DISABLE(); break; +#endif +#if defined(USART11_BASE) + case UART11_INDEX: + __HAL_RCC_USART11_FORCE_RESET(); + __HAL_RCC_USART11_RELEASE_RESET(); + __HAL_RCC_USART11_CLK_DISABLE(); + break; +#endif +#if defined(UART12_BASE) + case UART12_INDEX: + __HAL_RCC_UART12_FORCE_RESET(); + __HAL_RCC_UART12_RELEASE_RESET(); + __HAL_RCC_UART12_CLK_DISABLE(); + break; #endif } @@ -1280,6 +1317,32 @@ void USART10_IRQHandler(void) } #endif +/** + * @brief USART 11 IRQ handler + * @param None + * @retval None + */ +#if defined(USART11_BASE) +void USART11_IRQHandler(void) +{ + HAL_NVIC_ClearPendingIRQ(USART11_IRQn); + HAL_UART_IRQHandler(uart_handlers[UART11_INDEX]); +} +#endif + +/** + * @brief UART 12 IRQ handler + * @param None + * @retval None + */ +#if defined(UART12_BASE) +void UART12_IRQHandler(void) +{ + HAL_NVIC_ClearPendingIRQ(UART12_IRQn); + HAL_UART_IRQHandler(uart_handlers[UART12_INDEX]); +} +#endif + /** * @brief HAL UART Call Back * @param UART handler From fbd3538a281af8608a55a4a24a3abc48859c311d Mon Sep 17 00:00:00 2001 From: Moddingear Date: Sat, 1 Feb 2025 19:58:32 +0100 Subject: [PATCH 079/141] Update HSE valkue on variant_B_G431B_ESC1.h HSE was set to 24MHz instead of 8MHz Signed-off-by: Moddingear --- variants/STM32G4xx/G431C(6-8-B)U_G441CBU/variant_B_G431B_ESC1.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/variant_B_G431B_ESC1.h b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/variant_B_G431B_ESC1.h index 04073db29f..a00af9d73b 100644 --- a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/variant_B_G431B_ESC1.h +++ b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/variant_B_G431B_ESC1.h @@ -214,7 +214,7 @@ #endif /* HAL configuration */ -#define HSE_VALUE (24000000UL) +#define HSE_VALUE (8000000UL) /* Extra HAL modules */ #if !defined(HAL_DAC_MODULE_DISABLED) From ee9c0dd5148985348361163f7da1dd79f8fe05bd Mon Sep 17 00:00:00 2001 From: jackb60 <40903548+jackb60@users.noreply.github.com> Date: Tue, 4 Feb 2025 03:12:17 -0500 Subject: [PATCH 080/141] variant(f4): add generic F042K(4-6)Ux (#2648) Signed-off-by: jackb60 <40903548+jackb60@users.noreply.github.com> --- README.md | 1 + boards.txt | 18 ++ .../STM32F0xx/F042K(4-6)U/generic_clock.c | 38 +++- variants/STM32F0xx/F042K(4-6)U/ldscript.ld | 187 ++++++++++++++++++ 4 files changed, 242 insertions(+), 2 deletions(-) create mode 100644 variants/STM32F0xx/F042K(4-6)U/ldscript.ld diff --git a/README.md b/README.md index 36dab505d7..a0cfffd4a3 100644 --- a/README.md +++ b/README.md @@ -242,6 +242,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F042F4
                                                                STM32F042F6 | Generic Board | *2.4.0* | | | :green_heart: | STM32F042G4
                                                                STM32F042G6 | Generic Board | *2.4.0* | | | :green_heart: | STM32F042K4T
                                                                STM32F042K6T | Generic Board | **2.0.1** | | +| :yellow_heart: | STM32F042K4U
                                                                STM32F042K6U | Generic Board | **2.10.0** | | | :green_heart: | STM32F042T6 | Generic Board | *2.4.0* | | | :green_heart: | STM32F048G6 | Generic Board | *2.4.0* | | | :green_heart: | STM32F048T6 | Generic Board | *2.4.0* | | diff --git a/boards.txt b/boards.txt index 0aee1594ac..a635b5b2e7 100644 --- a/boards.txt +++ b/boards.txt @@ -2073,6 +2073,15 @@ GenF0.menu.pnum.GENERIC_F042K4TX.build.product_line=STM32F042x6 GenF0.menu.pnum.GENERIC_F042K4TX.build.variant=STM32F0xx/F042K(4-6)T GenF0.menu.pnum.GENERIC_F042K4TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd +# Generic F042K4Ux +GenF0.menu.pnum.GENERIC_F042K4UX=Generic F042K4Ux +GenF0.menu.pnum.GENERIC_F042K4UX.upload.maximum_size=16384 +GenF0.menu.pnum.GENERIC_F042K4UX.upload.maximum_data_size=6144 +GenF0.menu.pnum.GENERIC_F042K4UX.build.board=GENERIC_F042K4UX +GenF0.menu.pnum.GENERIC_F042K4UX.build.product_line=STM32F042x6 +GenF0.menu.pnum.GENERIC_F042K4UX.build.variant=STM32F0xx/F042K(4-6)U +GenF0.menu.pnum.GENERIC_F042K4UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd + # Generic F042K6Tx GenF0.menu.pnum.GENERIC_F042K6TX=Generic F042K6Tx GenF0.menu.pnum.GENERIC_F042K6TX.upload.maximum_size=32768 @@ -2082,6 +2091,15 @@ GenF0.menu.pnum.GENERIC_F042K6TX.build.product_line=STM32F042x6 GenF0.menu.pnum.GENERIC_F042K6TX.build.variant=STM32F0xx/F042K(4-6)T GenF0.menu.pnum.GENERIC_F042K6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd +# Generic F042K6Ux +GenF0.menu.pnum.GENERIC_F042K6UX=Generic F042K6Ux +GenF0.menu.pnum.GENERIC_F042K6UX.upload.maximum_size=32768 +GenF0.menu.pnum.GENERIC_F042K6UX.upload.maximum_data_size=6144 +GenF0.menu.pnum.GENERIC_F042K6UX.build.board=GENERIC_F042K6UX +GenF0.menu.pnum.GENERIC_F042K6UX.build.product_line=STM32F042x6 +GenF0.menu.pnum.GENERIC_F042K6UX.build.variant=STM32F0xx/F042K(4-6)U +GenF0.menu.pnum.GENERIC_F042K6UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd + # Generic F042T6Yx GenF0.menu.pnum.GENERIC_F042T6YX=Generic F042T6Yx GenF0.menu.pnum.GENERIC_F042T6YX.upload.maximum_size=32768 diff --git a/variants/STM32F0xx/F042K(4-6)U/generic_clock.c b/variants/STM32F0xx/F042K(4-6)U/generic_clock.c index 691a010770..021aaf16da 100644 --- a/variants/STM32F0xx/F042K(4-6)U/generic_clock.c +++ b/variants/STM32F0xx/F042K(4-6)U/generic_clock.c @@ -20,8 +20,42 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI48; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_USART1 + | RCC_PERIPHCLK_I2C1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32F0xx/F042K(4-6)U/ldscript.ld b/variants/STM32F0xx/F042K(4-6)U/ldscript.ld new file mode 100644 index 0000000000..37f8a5fd91 --- /dev/null +++ b/variants/STM32F0xx/F042K(4-6)U/ldscript.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32F042K6Ux Device from STM32F0 series +** 32KBytes FLASH +** 6KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From eb243d5fa35322b8b939125dabacbf42897c175c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 3 Feb 2025 16:53:50 +0100 Subject: [PATCH 081/141] chore(uart): set LSE as source only if LSE is ready Fixes #2642. Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/uart.c | 31 +++++++++++++++------------ 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index e762e007ab..04ccb2c820 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -15,6 +15,7 @@ #include "uart.h" #include "Arduino.h" #include "PinAF_STM32F1.h" +#include "stm32yyxx_ll_rcc.h" #ifdef __cplusplus extern "C" { @@ -457,28 +458,30 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if (baudrate <= 9600) { /* Enable the clock if not already set by user */ enableClock(LSE_CLOCK); - if (obj->uart == LPUART1) { - __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_LSE); - } + if (LL_RCC_LSE_IsReady()) { + if (obj->uart == LPUART1) { + __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_LSE); + } #if defined(LPUART2_BASE) - if (obj->uart == LPUART2) { - __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_LSE); - } + if (obj->uart == LPUART2) { + __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_LSE); + } #endif #if defined(LPUART3_BASE) - if (obj->uart == LPUART3) { - __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_LSE); - } + if (obj->uart == LPUART3) { + __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_LSE); + } #endif - if ((uart_rx == NP) && (uart_rx_swap == NP)) { - if (HAL_HalfDuplex_Init(huart) == HAL_OK) { + if ((uart_rx == NP) && (uart_rx_swap == NP)) { + if (HAL_HalfDuplex_Init(huart) == HAL_OK) { + return; + } + } else if (HAL_UART_Init(huart) == HAL_OK) { return; } - } else if (HAL_UART_Init(huart) == HAL_OK) { - return; } } - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) { + if (LL_RCC_HSI_IsReady()) { if (obj->uart == LPUART1) { __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_HSI); } From c5dfeaedb2ba877fee47a86f66998e74f8103589 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 3 Feb 2025 15:09:34 +0100 Subject: [PATCH 082/141] system(WL) update STM32WLxx HAL Drivers to v1.3.1 Included in STM32CubeWL FW v1.3.1 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 2 +- .../Inc/stm32wlxx_hal_cortex.h | 2 + .../Inc/stm32wlxx_hal_i2c.h | 15 +- .../Inc/stm32wlxx_hal_smbus.h | 4 +- .../Inc/stm32wlxx_ll_i2c.h | 125 ++-- .../Inc/stm32wlxx_ll_utils.h | 2 +- .../{License.md => LICENSE.md} | 0 .../STM32WLxx_HAL_Driver/Release_Notes.html | 628 ++++++++++++----- .../STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c | 5 +- .../Src/stm32wlxx_hal_adc.c | 26 +- .../Src/stm32wlxx_hal_cortex.c | 81 ++- .../Src/stm32wlxx_hal_cryp.c | 62 +- .../Src/stm32wlxx_hal_dac_ex.c | 19 +- .../Src/stm32wlxx_hal_i2c.c | 653 +++++++++++++----- .../Src/stm32wlxx_hal_smbus.c | 37 +- .../Src/stm32wlxx_hal_spi.c | 135 ++-- .../Src/stm32wlxx_hal_subghz.c | 15 +- .../Src/stm32wlxx_hal_tim.c | 86 ++- .../Src/stm32wlxx_hal_uart.c | 79 +-- .../Src/stm32wlxx_hal_uart_ex.c | 12 +- .../Src/stm32wlxx_ll_adc.c | 25 +- .../Src/stm32wlxx_ll_gpio.c | 2 - .../Src/stm32wlxx_ll_tim.c | 1 - .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 24 files changed, 1395 insertions(+), 623 deletions(-) rename system/Drivers/STM32WLxx_HAL_Driver/{License.md => LICENSE.md} (100%) diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 7a4550c7f6..c3fa678347 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -1291,7 +1291,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) || defined(STM32MP2) +#if defined(STM32U5) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h index 2a0ef1b38f..0402add0e3 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h @@ -308,6 +308,8 @@ void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1U) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h index 5037fbf7ee..9cf8b1a1f7 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h @@ -203,10 +203,13 @@ typedef struct __I2C_HandleTypeDef HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ +#endif /*HAL_DMA_MODULE_ENABLED*/ + HAL_LockTypeDef Lock; /*!< I2C locking object */ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ @@ -661,6 +664,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); +#if defined(HAL_DMA_MODULE_ENABLED) /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); @@ -681,6 +685,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @} */ @@ -709,9 +714,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); * @{ */ /* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); /** * @} @@ -804,8 +809,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ - (~I2C_CR2_RD_WRN))) + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h index 8bb3014242..423f747b6c 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h @@ -751,8 +751,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /* Peripheral State and Errors functions **************************************************/ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_i2c.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_i2c.h index ffb04293ea..f9adda22f3 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_i2c.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_i2c.h @@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); } @@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); } @@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); } @@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); } @@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); } @@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) { uint32_t data_reg_addr; @@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } @@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); } @@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); } @@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); } @@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT */ -__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); } @@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); } @@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); } @@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); } @@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); } @@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); } @@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); } @@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); } @@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) * @arg @ref LL_I2C_MODE_SMBUS_DEVICE * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP */ -__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); } @@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); } @@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); } @@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); } @@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); } @@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); } @@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ (ClockTimeout)) ? 1UL : 0UL); @@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); } @@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); } @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); } @@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); } @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); } @@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); } @@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); } @@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); } @@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); } @@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); } @@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); } @@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); } @@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); } @@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); } @@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); } @@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); } @@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); } @@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); } @@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); } @@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); } @@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); } @@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); } @@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); } @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); } @@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); } @@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans * @arg @ref LL_I2C_REQUEST_WRITE * @arg @ref LL_I2C_REQUEST_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); } @@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); } @@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** @@ -2150,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr * @arg @ref LL_I2C_DIRECTION_WRITE * @arg @ref LL_I2C_DIRECTION_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); } @@ -2161,7 +2168,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); } @@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); } @@ -2204,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); } @@ -2215,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) { return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); } diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h index 61803a4d44..cea51bf1c2 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h @@ -178,7 +178,7 @@ typedef struct */ #define LL_UTILS_PACKAGETYPE_UFBGA73 0x00000000U /*!< UFBGA73 package type */ #define LL_UTILS_PACKAGETYPE_WLCSP59 0x00000002U /*!< WLSCSP59 package type */ -#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQPFN48 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQPFN48 package type */ /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/License.md b/system/Drivers/STM32WLxx_HAL_Driver/LICENSE.md similarity index 100% rename from system/Drivers/STM32WLxx_HAL_Driver/License.md rename to system/Drivers/STM32WLxx_HAL_Driver/LICENSE.md diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WLxx_HAL_Driver/Release_Notes.html index d0cf1216e7..749fa01818 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WLxx_HAL_Driver/Release_Notes.html @@ -5,16 +5,24 @@ Release Notes for STM32WLxx HAL Drivers Package - - @@ -24,45 +32,238 @@

                                                                Release Notes for

                                                                STM32WLxx HAL Drivers

                                                                Copyright © 2020 STMicroelectronics

                                                                - +

                                                                Purpose

                                                                -

                                                                The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

                                                                -

                                                                The Portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

                                                                -

                                                                The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provide basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not Fully Portable across the STM32 families; the availability of some functions depend on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

                                                                -
                                                                  -
                                                                • New set of inline function for direct and atomic register access
                                                                  • -
                                                                • One-shot operations that can be used by the HAL drivers or from application level.
                                                                  • -
                                                                • Fully Independent from HAL and can be used in standalone usage (without HAL drivers)
                                                                  • +

                                                                  The STM32Cube HAL and LL, an STM32 abstraction layer embedded +software, ensure maximized portability across STM32 portfolio.

                                                                  +

                                                                  The Portable APIs layer provides a generic, multi instanced and +simple set of APIs to interact with the upper layer (application, +libraries and stacks). It is composed of native and extended APIs set. +It is directly built around a generic architecture and allows the +build-upon layers, like the middleware layer, to implement its functions +without knowing in-depth the used STM32 device. This improves the +library code reusability and guarantees an easy portability on other +devices and STM32 families.

                                                                  +

                                                                  The Low Layer (LL) drivers are part of the STM32Cube firmware HAL +that provide basic set of optimized and one shot services. The Low layer +drivers, contrary to the HAL ones are not Fully Portable across the +STM32 families; the availability of some functions depend on the +physical availability of the relative features on the product. The Low +Layer (LL) drivers are designed to offer the following features:

                                                                  +
                                                                    +
                                                                  • New set of inline function for direct and atomic register +access
                                                                    • +
                                                                  • One-shot operations that can be used by the HAL drivers or from +application level.
                                                                    • +
                                                                  • Fully Independent from HAL and can be used in standalone usage +(without HAL drivers)
                                                                  • Full features coverage of the all the supported peripherals.
                                                                -
                                                                -

                                                                Update History

                                                                +
                                                                +

                                                                Update History

                                                                - + +

                                                                Main Changes

                                                                  -
                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                  • -
                                                                • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (DAC, IRDA, LPTIM, SMARTCARD, TIM, UART, USART)
                                                                  • -
                                                                • Enhance code quality (MISRA-C rules 8.13, 11.9) for some drivers: ADC, COMP, DMA, IRDA, LPTIM, SMARTCARD, TIM, UART, USART
                                                                  • +
                                                                • Patch release of HAL and Low Layer drivers to +include latest corrections
                                                                  • +
                                                                • Update the following IPs Drivers: ADC, CORTEX, CRYP, DAC, GENERIC, +GPIO, I2C, SMBUS, SPIU, SUBGHZ, TIM, UART, UTILS

                                                                Contents

                                                                HAL Drivers updates

                                                                • HAL ADC driver
                                                                    +
                                                                  • Fix MISRA-C 2012 Rule 15.7 issue
                                                                    • +
                                                                  • Improve de-init sequence by reset clock configuration on last step +(otherwise, under specific clock source selection, some parameters can +be not reset)
                                                                    • +
                                                                  • Add CFGR1_CHSELRMOD bit to be reset by LL_ADC_DeInit() function
                                                                    • +
                                                                  • +
                                                                • HAL CORTEX driver +
                                                                    +
                                                                  • Update HAL_MPU_ConfigRegion() to allow the configuration of the MPU +registers independently of the value of Enable/Disable field and add new +APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion()
                                                                    • +
                                                                  • +
                                                                • HAL CRYP driver +
                                                                    +
                                                                  • Update AES GCM in interrupt mode to avoid Computation Completed IRQ +fires before the DINR pointer increment
                                                                    • +
                                                                  • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ +fires before the DINR pointer increment
                                                                    • +
                                                                  • +
                                                                • HAL DAC driver +
                                                                    +
                                                                  • Fix HAL DAC calibration procedure (function +HAL_DACEx_SelfCalibrate() ) to manage case of calibration factor equal +to range maximum value (previously, in this case calibration factor was +reset, leading to voltage accuracy not optimal)
                                                                    • +
                                                                  • Update DAC buffer calibration according to Reference Manual
                                                                    • +
                                                                  • +
                                                                • HAL Generic driver +
                                                                    +
                                                                  • Update of HAL_GetTickFreq() brief
                                                                    • +
                                                                  • +
                                                                • HAL I2C driver +
                                                                    +
                                                                  • Remove HAL DMA dependency thanks to the HAL_DMA_MODULE_ENABLED +define
                                                                    • +
                                                                  • Solve Slave No stretch not functional by using HAL Slave +interface
                                                                    • +
                                                                  • Update I2C_WaitOnFlagUntilTimeout() API to handle error case
                                                                    • +
                                                                  • Update HAL_I2C_Slave_Transmit() to check if the received NACK is the +good one
                                                                    • +
                                                                  • Update HAL_I2C_Init() API to clear ADD10 bit in 7 bit addressing +mode
                                                                    • +
                                                                  • Update I2C_GENERATE_START() macro to generate stop automatically in +10 bit addressing mode
                                                                    • +
                                                                  • Remove the unusable code in function HAL_I2C_IsDeviceReady
                                                                    • +
                                                                  • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const +qualifiers
                                                                    • +
                                                                  • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF +independently from I2C_FLAG_RXNE
                                                                    • +
                                                                  • Update HAL I2C driver to prefetch data before starting the +transmission: implementation of errata sheet workaround I2C2-190208 : +Transmission stalled after first byte
                                                                    • +
                                                                  • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to +prevent the call of HAL_I2C_ListenCpltCallback twice
                                                                    • +
                                                                  • Update HAL_I2C_Mem_Write_IT API to initialize XferSize at 0
                                                                    • +
                                                                  • Enhance HAL I2C to be thread safe
                                                                    • +
                                                                  • +
                                                                • HAL SMBUS driver +
                                                                    +
                                                                  • Update SMBUS_ITErrorHandler to flush TXDR just in case of error
                                                                    • +
                                                                  • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const +qualifiers
                                                                    • +
                                                                  • Update HAL SMBUS driver to prefetch data before starting the +transmission: implementation of errata sheet workaround I2C2-190208 : +Transmission stalled after first byte
                                                                    • +
                                                                  • +
                                                                • HAL SPI driver +
                                                                    +
                                                                  • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of +one byte transaction
                                                                    • +
                                                                  • Update IT API to enable interrupts after process unlock
                                                                    • +
                                                                  • Fix driver to don’t update state in case of error +(HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT)
                                                                    • +
                                                                  • +
                                                                • HAL SUBGHZ driver +
                                                                    +
                                                                  • Change macro from ‘CM0PLUS’ to ‘CORE_CM0PLUS’ as in preprocessor +directives
                                                                    • +
                                                                  • +
                                                                • HAL TIM driver +
                                                                    +
                                                                  • Update interrupt flag is cleared when the update event is generated +by software
                                                                    • +
                                                                  • Remove multiple volatile reads or writes in interrupt handler for +better performance
                                                                    • +
                                                                  • +
                                                                • HAL UART driver +
                                                                    +
                                                                  • Avoid RTOF flag to be cleared by a transmit process in polling +mode
                                                                    • +
                                                                  • Fix incorrect gState check in +HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to +allow user Rx Event Callback registration when a transmit is +ongoing
                                                                    • +
                                                                  • Update initialisation sequence for TXINV, RXINV and TXRXSWAP +settings
                                                                    • +
                                                                  • +
                                                                • HAL UTILS driver +
                                                                    +
                                                                  • Fix UFQFPN48 package definition
                                                                    +
                                                                    • +
                                                                  • +
                                                                +

                                                                LL Drivers updates

                                                                +
                                                                  +
                                                                • LL GPIO driver +
                                                                    +
                                                                  • Remove a redundant call to LL_GPIO_SetPinMode() within the +LL_GPIO_Init() API
                                                                    • +
                                                                  • +
                                                                • LL I2C driver +
                                                                    +
                                                                  • Update LL_I2C_HandleTranfer function to prevent undefined behavior +of volatile usage before updating the CR2 register
                                                                    • +
                                                                  • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const +qualifiers
                                                                    +
                                                                    • +
                                                                  • +
                                                                +

                                                                Known Limitations

                                                                +

                                                                None

                                                                +

                                                                Development Toolchains and +Compilers

                                                                +
                                                                  +
                                                                • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + Patch +EWARM
                                                                  • +
                                                                • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + +Keil +DFP V1.1.1 Pack
                                                                  • +
                                                                • STM32CubeIDE 1.11.0 (GNU Tools for STM32 10.3-2021.10)
                                                                  • +
                                                                +

                                                                Supported Devices and boards

                                                                +

                                                                Supported Devices:

                                                                +
                                                                  +
                                                                • STM32WL55xx
                                                                  • +
                                                                • STM32WL54xx
                                                                  • +
                                                                • STM32WLE5xx
                                                                  • +
                                                                • STM32WLE4xx
                                                                  • +
                                                                • STM32WL5Mxx
                                                                  • +
                                                                +

                                                                Backward Compatibility

                                                                +

                                                                Not applicable

                                                                +

                                                                Dependencies

                                                                +

                                                                None

                                                                +


                                                                +

                                                                +
                                                                +
                                                                +
                                                                + + +
                                                                +

                                                                Main Changes

                                                                +
                                                                  +
                                                                • Maintenance release of HAL and Low Layer drivers to +include latest corrections
                                                                  • +
                                                                • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & +HAL_xxxx_UnregisterCallback for IPs (DAC, IRDA, LPTIM, SMARTCARD, TIM, +UART, USART)
                                                                  • +
                                                                • Enhance code quality (MISRA-C rules 8.13, 11.9) for some drivers: +ADC, COMP, DMA, IRDA, LPTIM, SMARTCARD, TIM, UART, USART
                                                                  • +
                                                                +

                                                                Contents

                                                                +

                                                                HAL Drivers updates

                                                                +
                                                                  +
                                                                • HAL ADC driver +
                                                                  • Disable AutoPowerOff when performing calibration
                                                                    • -
                                                                  • Rename ADC_TRx registers to AWDxTR to be in accordance with the Reference Manual
                                                                    • +
                                                                  • Rename ADC_TRx registers to AWDxTR to be in accordance with the +Reference Manual
                                                                • HAL CORTEX driver
                                                                    -
                                                                  • Remove #define LL_MPU_TEX_LEVEL4 (no Level 2 cache for STM32 SoC with Armv7-M cortex)
                                                                    • +
                                                                  • Remove #define LL_MPU_TEX_LEVEL4 (no Level 2 cache for STM32 SoC +with Armv7-M cortex)
                                                                • HAL CRC driver
                                                                    -
                                                                  • Add filter in HAL_CRCEx_Polynomial_Set() function to exclude even polynomials
                                                                    • +
                                                                  • Add filter in HAL_CRCEx_Polynomial_Set() function to exclude even +polynomials
                                                                • HAL CRYP driver
                                                                    @@ -75,72 +276,90 @@

                                                                    HAL Drivers updates

                                                                • HAL EXTI driver
                                                                    -
                                                                  • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine()
                                                                    • +
                                                                  • Fix computation of pExtiConfig->GPIOSel in +HAL_EXTI_GetConfigLine()
                                                                • HAL Generic driver
                                                                    -
                                                                  • Add HAL_RADIO APIs to handle Radio services (only for STM32WL5M)
                                                                    • +
                                                                  • Add HAL_RADIO APIs to handle Radio services (only for +STM32WL5M)
                                                                • HAL I2C driver
                                                                  • Fix Timeout issue using HAL MEM interface through FreeRTOS
                                                                  • Fix I2C_IsErrorOccurred returning error if timeout is detected
                                                                    • -
                                                                  • Fix ADDRF flag cleared too early when the restart is received but the direction has changed
                                                                    • +
                                                                  • Fix ADDRF flag cleared too early when the restart is received but +the direction has changed
                                                                • HAL IRDA driver
                                                                    -
                                                                  • Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig()
                                                                    • +
                                                                  • Fix wrong cast when computing the USARTDIV value in +IRDA_SetConfig()
                                                                • HAL LPTIM driver
                                                                  • Enhance LPTIM state management
                                                                    • -
                                                                  • Fix IS_LPTIM_AUTORELOAD & IS_LPTIM_PERIOD macros to check that AutoReload value must be strictly greater than 0
                                                                    • +
                                                                  • Fix IS_LPTIM_AUTORELOAD & IS_LPTIM_PERIOD macros to check that +AutoReload value must be strictly greater than 0
                                                                • HAL RCC driver
                                                                    -
                                                                  • Optimize HAL_RCC_OscConfig function when checking if oscillator is ready
                                                                    • +
                                                                  • Optimize HAL_RCC_OscConfig function when checking if oscillator is +ready
                                                                  • Optimize HAL_RCC_GetOscConfig function
                                                                    • -
                                                                  • Remove GPIO configuration in HAL_RCCEx_EnableLSCO & HAL_RCCEx_DisableLSCO functions
                                                                    • +
                                                                  • Remove GPIO configuration in HAL_RCCEx_EnableLSCO & +HAL_RCCEx_DisableLSCO functions
                                                                • HAL RTC driver
                                                                    -
                                                                  • Improve HAL_RTC_Init function to avoid initialization if already done
                                                                    • +
                                                                  • Improve HAL_RTC_Init function to avoid initialization if already +done
                                                                • HAL SMARTCARD driver
                                                                    -
                                                                  • Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig() function
                                                                    • +
                                                                  • Fix wrong cast when computing the USARTDIV value in +SMARTCARD_SetConfig() function
                                                                • HAL SUBGHZ driver
                                                                  • Clear the interrupt CR register just after having read it
                                                                    • -
                                                                  • Support new feature LoraFHSS (Lora Frequency Hopping Spread Spectrum)
                                                                    • -
                                                                  • Add new state HAL_SUBGHZ_STATE_RESET_RF_READY to avoid to reinitialize RF on existing from Standby mode
                                                                    • +
                                                                  • Support new feature LoraFHSS (Lora Frequency Hopping Spread +Spectrum)
                                                                    • +
                                                                  • Add new state HAL_SUBGHZ_STATE_RESET_RF_READY to avoid to +reinitialize RF on existing from Standby mode
                                                                • HAL TIM driver
                                                                  • Improve driver robustness against wrong period values
                                                                  • Improve driver robustness against wrong DMA related parameters
                                                                    • -
                                                                  • Add new __HAL_TIM_SELECT_CCDMAREQUEST() macro to select CCx DMA source
                                                                    • +
                                                                  • Add new __HAL_TIM_SELECT_CCDMAREQUEST() macro to select CCx DMA +source
                                                                • HAL UART driver
                                                                    -
                                                                  • Fix wrong cast when computing the USARTDIV value in UART_SetConfig() function
                                                                    • -
                                                                  • Add HAL_UARTEx_GetRxEventType function to retrieve the type of event that has led the RxEventCallback execution
                                                                    • -
                                                                  • Remove HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs to fix a concurrent access issue
                                                                    • -
                                                                  • Disable the Receiver Timeout Interrupt when data reception is completed
                                                                    • +
                                                                  • Fix wrong cast when computing the USARTDIV value in UART_SetConfig() +function
                                                                    • +
                                                                  • Add HAL_UARTEx_GetRxEventType function to retrieve the type of event +that has led the RxEventCallback execution
                                                                    • +
                                                                  • Remove HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs to fix a +concurrent access issue
                                                                    • +
                                                                  • Disable the Receiver Timeout Interrupt when data reception is +completed


                                                                -

                                                                LL Drivers updates

                                                                +

                                                                LL Drivers updates

                                                                • LL LPTIM driver
                                                                    -
                                                                  • Enhance code quality by renaming all functions LL_LPTIM_ClearFLAG_Xxxxx with LL_LPTIM_ClearFlag_Xxxxx
                                                                    • +
                                                                  • Enhance code quality by renaming all functions +LL_LPTIM_ClearFLAG_Xxxxx with LL_LPTIM_ClearFlag_Xxxxx
                                                                • LL System driver
                                                                    -
                                                                  • Fix LL_SYSCFG_GetEXTISource function which returned wrong result on M4 core
                                                                    • +
                                                                  • Fix LL_SYSCFG_GetEXTISource function which returned wrong result on +M4 core
                                                                • LL USART driver
                                                                    @@ -148,20 +367,28 @@

                                                                    LL Drivers updates

                                                                • LL Utils driver
                                                                    -
                                                                  • Fix a wrong parameter of __LL_RCC_CALC_MSI_FREQ given erroneous PLL frequency
                                                                    • +
                                                                  • Fix a wrong parameter of __LL_RCC_CALC_MSI_FREQ given erroneous PLL +frequency


                                                                -

                                                                Known Limitations

                                                                +

                                                                Known Limitations

                                                                None

                                                                -

                                                                Development Toolchains and Compilers

                                                                -
                                                                  -
                                                                • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + Patch EWARM
                                                                  • -
                                                                • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + Keil DFP V1.1.1 Pack
                                                                  • +

                                                                  Development Toolchains +and Compilers

                                                                  +
                                                                    +
                                                                  • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + Patch +EWARM
                                                                    • +
                                                                  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + +Keil +DFP V1.1.1 Pack
                                                                  • STM32CubeIDE 1.11.0 (GNU Tools for STM32 10.3-2021.10)
                                                                  -

                                                                  Supported Devices and boards

                                                                  +

                                                                  Supported Devices and +boards

                                                                  Supported Devices:

                                                                  • STM32WL55xx
                                                                    • @@ -170,60 +397,74 @@

                                                                    Supported Devices and boards

                                                                  • STM32WLE4xx
                                                                  • STM32WL5Mxx
                                                                  -

                                                                  Backward Compatibility

                                                                  +

                                                                  Backward Compatibility

                                                                  Not applicable

                                                                  -

                                                                  Dependencies

                                                                  +

                                                                  Dependencies

                                                                  None


                                                                - + +
                                                                -

                                                                Main Changes

                                                                +

                                                                Main Changes

                                                                  -
                                                                • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                  • -
                                                                • All source files: update disclaimer to add reference to the new license agreement
                                                                  • +
                                                                • Maintenance release of HAL and Low Layer drivers to +include latest corrections
                                                                  • +
                                                                • All source files: update disclaimer to add reference to the new +license agreement
                                                                • Correct English spelling errors and typos
                                                                -

                                                                Contents

                                                                -

                                                                HAL Drivers updates

                                                                +

                                                                Contents

                                                                +

                                                                HAL Drivers updates

                                                                • HAL ADC driver
                                                                  • Enhance ADC calibration to reduce noise effect
                                                                    • -
                                                                  • Fix write access to registers ADC_CFGR1 and ADC_CFGR2 in HAL_ADC_Init() and HAL_ADC_AnalogWDGConfig() functions
                                                                    • +
                                                                  • Fix write access to registers ADC_CFGR1 and ADC_CFGR2 in +HAL_ADC_Init() and HAL_ADC_AnalogWDGConfig() functions
                                                                • HAL GPIO driver
                                                                    -
                                                                  • Reorder EXTI config in HAL_GPIO_Init/HAL_GPIO_DeInit to avoid unexpected level detection
                                                                    • -
                                                                  • Add new HAL_GPIO_WriteMultipleStatePin() API for multiple pin access in same cycle
                                                                    • +
                                                                  • Reorder EXTI config in HAL_GPIO_Init/HAL_GPIO_DeInit to avoid +unexpected level detection
                                                                    • +
                                                                  • Add new HAL_GPIO_WriteMultipleStatePin() API for multiple pin access +in same cycle
                                                                • HAL I2C driver
                                                                  • Fix written reserved bit 28 in I2C_CR2 register
                                                                  • Improve I2C_WaitOnFlagUntilTimeout() description to match code
                                                                  • Update to handle errors in polling mode
                                                                    • -
                                                                  • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs
                                                                    • -
                                                                  • Fix some communication issue due to low system frequency execution (HSI)
                                                                    • +
                                                                  • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and +correctly manage when error occurs
                                                                    • +
                                                                  • Fix some communication issue due to low system frequency execution +(HSI)
                                                                • HAL IRDA driver
                                                                    -
                                                                  • Improve header description of IRDA_WaitOnFlagUntilTimeout() function
                                                                    • -
                                                                  • Add a check on the IRDA parity before enabling the parity error interrupt
                                                                    • +
                                                                  • Improve header description of IRDA_WaitOnFlagUntilTimeout() +function
                                                                    • +
                                                                  • Add a check on the IRDA parity before enabling the parity error +interrupt
                                                                • HAL LPTIM driver
                                                                    -
                                                                  • Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
                                                                    • +
                                                                  • Add check on PRIMASK register to prevent from enabling unwanted +global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
                                                                • HAL RCC driver
                                                                    -
                                                                  • Enhance RCC_MCOx in order to support both MCO number and AF mapping
                                                                    • +
                                                                  • Enhance RCC_MCOx in order to support both MCO number and AF +mapping
                                                                • HAL SMARTCARD driver
                                                                    -
                                                                  • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function
                                                                    • +
                                                                  • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() +function
                                                                • HAL SMBUS driver
                                                                    @@ -232,27 +473,34 @@

                                                                    HAL Drivers updates

                                                                  • HAL_SMBUSEx_EnableWakeUp()
                                                                  • HAL_SMBUSEx_DisableWakeUp()
                                                                  • -
                                                                • Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master
                                                                  • +
                                                                • Update to fix issue of mismatched data received by master in case of +data size to be transmitted by the slave is greater than the data size +to be received by the master
                                                                • Add flush on TX register
                                                              • HAL TIM driver
                                                                  -
                                                                • Fix incorrect behavior of the timer if input signal changes before the end of timer configuration
                                                                  • +
                                                                • Fix incorrect behavior of the timer if input signal changes before +the end of timer configuration
                                                              • HAL UART driver
                                                                  -
                                                                • Improve header description of UART_WaitOnFlagUntilTimeout() function
                                                                  • -
                                                                • Add a check on the UART parity before enabling the parity error interruption
                                                                  • +
                                                                • Improve header description of UART_WaitOnFlagUntilTimeout() +function
                                                                  • +
                                                                • Add a check on the UART parity before enabling the parity error +interruption
                                                              • HAL USART driver
                                                                  -
                                                                • Improve header description of USART_WaitOnFlagUntilTimeout() function
                                                                  • -
                                                                • Add a check on the USART parity before enabling the parity error interruption
                                                                  • +
                                                                • Improve header description of USART_WaitOnFlagUntilTimeout() +function
                                                                  • +
                                                                • Add a check on the USART parity before enabling the parity error +interruption


                                                              -

                                                              LL Drivers updates

                                                              +

                                                              LL Drivers updates

                                                              • LL ADC driver
                                                                  @@ -264,7 +512,8 @@

                                                                  LL Drivers updates

                                                              • LL CRC driver
                                                                  -
                                                                • Rectified @brief of LL_CRC_GetOutputDataReverseMode() API
                                                                  • +
                                                                • Rectified @brief of +LL_CRC_GetOutputDataReverseMode() API
                                                              • LL LPUART driver
                                                                  @@ -272,8 +521,11 @@

                                                                  LL Drivers updates

                                                              • LL RCC driver
                                                                  -
                                                                • Add missing API: LL_RCC_PLL_IsEnabledDomain_ADC, LL_RCC_PLL_IsEnabledDomain_RNG, LL_RCC_PLL_IsEnabledDomain_I2S, LL_RCC_PLL_IsEnabledDomain_SYS
                                                                  • -
                                                                • Add check of PLL enable bit when a peripheral using PPL P or PLL Q
                                                                  • +
                                                                • Add missing API: LL_RCC_PLL_IsEnabledDomain_ADC, +LL_RCC_PLL_IsEnabledDomain_RNG, LL_RCC_PLL_IsEnabledDomain_I2S, +LL_RCC_PLL_IsEnabledDomain_SYS
                                                                  • +
                                                                • Add check of PLL enable bit when a peripheral using PPL P or PLL +Q
                                                              • LL RNG driver
                                                                  @@ -281,19 +533,24 @@

                                                                  LL Drivers updates

                                                              • Utils driver
                                                                  -
                                                                • Fix LL_PLL_ConfigSystemClock_HSE to take into account the setting of RCC_CR_HSEPRE when computing pllrfreq
                                                                  +
                                                                • Fix LL_PLL_ConfigSystemClock_HSE to take into account the setting of +RCC_CR_HSEPRE when computing pllrfreq
                                                              -

                                                              Known Limitations

                                                              +

                                                              Known Limitations

                                                              None

                                                              -

                                                              Development Toolchains and Compilers

                                                              +

                                                              Development Toolchains +and Compilers

                                                              • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
                                                                • -
                                                              • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
                                                                • -
                                                              • STM32CubeIDE 1.9.0 (native GNU ARM 10.3-2021-10 or optional GNU ARM 9-2020-q2-update)
                                                                • +
                                                              • RealView Microcontroller Development Kit (MDK-ARM) toolchain +V5.31
                                                                • +
                                                              • STM32CubeIDE 1.9.0 (native GNU ARM 10.3-2021-10 or optional GNU ARM +9-2020-q2-update)
                                                              -

                                                              Supported Devices and boards

                                                              +

                                                              Supported Devices and +boards

                                                              Supported Devices:

                                                              • STM32WL55xx
                                                                • @@ -301,20 +558,23 @@

                                                                Supported Devices and boards

                                                              • STM32WLE5xx
                                                              • STM32WLE4xx
                                                              -

                                                              Backward Compatibility

                                                              +

                                                              Backward Compatibility

                                                              Not applicable

                                                              -

                                                              Dependencies

                                                              +

                                                              Dependencies

                                                              None


                                                              - + +
                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                                -
                                                              • Maintenance release of HAL and Low Layer drivers to include latest corrections
                                                                • +
                                                              • Maintenance release of HAL and Low Layer drivers to +include latest corrections
                                                              • Update of HAL SMBUS driver to introduce fast mode and fast mode plus
                                                                • Add extension files stm32wlxx_hal_smbus_ex.h/.c for new APIs: @@ -324,37 +584,48 @@

                                                                  Main Changes

                                                            -

                                                            Contents

                                                            -

                                                            HAL Drivers updates

                                                            +

                                                            Contents

                                                            +

                                                            HAL Drivers updates

                                                            • HAL ADC driver
                                                                -
                                                              • Update CFGR2 oversampling bitfields conditionally to oversampling enable
                                                                • -
                                                              • Update timeout mechanism to avoid false timeout detection in case of preemption
                                                                • -
                                                              • Update wait_loop_index computation so delay in us is always multiplicated by at least value “1â€
                                                                • +
                                                              • Update CFGR2 oversampling bitfields conditionally to oversampling +enable
                                                                • +
                                                              • Update timeout mechanism to avoid false timeout detection in case of +preemption
                                                                • +
                                                              • Update wait_loop_index computation so delay in us is always +multiplicated by at least value “1â€
                                                            • HAL COMP driver
                                                                -
                                                              • Update wait_loop_index computation so delay in us is always multiplicated by at least value “1â€
                                                                • +
                                                              • Update wait_loop_index computation so delay in us is always +multiplicated by at least value “1â€
                                                            • HAL CORTEX driver
                                                                -
                                                              • Disable the smallest MPU region sizes (32B, 64B, 128B) in the M0+ context
                                                                • +
                                                              • Disable the smallest MPU region sizes (32B, 64B, 128B) in the M0+ +context
                                                            • HAL CRYP driver
                                                                -
                                                              • Update HAL_CRYP_SetConfig() and HAL_CRYP_GetConfig() APIs to set/get the continent of KeyIVConfigSkip correctly
                                                                • -
                                                              • Resolve interrupt mode related GCM decryption issue causing wrong computation of decryption size
                                                                • -
                                                              • Update HAL_CRYP_InCpltCallback() API to fix an incorrect condition call at resumption time
                                                                • -
                                                              • Update CRYP_AESCCM_Process_IT() to fix incorrect CCM header length management when data are fed to the peripheral under interrupt
                                                                • +
                                                              • Update HAL_CRYP_SetConfig() and HAL_CRYP_GetConfig() APIs to set/get +the continent of KeyIVConfigSkip correctly
                                                                • +
                                                              • Resolve interrupt mode related GCM decryption issue causing wrong +computation of decryption size
                                                                • +
                                                              • Update HAL_CRYP_InCpltCallback() API to fix an incorrect condition +call at resumption time
                                                                • +
                                                              • Update CRYP_AESCCM_Process_IT() to fix incorrect CCM header length +management when data are fed to the peripheral under interrupt
                                                            • HAL EXTI driver
                                                                -
                                                              • Update HAL_EXTI_GetConfigLine() to set default configuration value of Trigger and GPIOSel before checking each corresponding register
                                                                • +
                                                              • Update HAL_EXTI_GetConfigLine() to set default configuration value +of Trigger and GPIOSel before checking each corresponding register
                                                            • HAL GPIO driver
                                                                -
                                                              • Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected
                                                                • +
                                                              • Update HAL_GPIO_Init() API to avoid the configuration of PUPDR +register when Analog mode is selected
                                                            • HAL HSEM driver
                                                                @@ -362,7 +633,8 @@

                                                                HAL Drivers updates

                                                            • HAL I2C driver
                                                                -
                                                              • Updated I2C_IsAcknowledgeFailed() to avoid keeping I2C in busy state if NACK is received after transmitting register address
                                                                • +
                                                              • Updated I2C_IsAcknowledgeFailed() to avoid keeping I2C in busy state +if NACK is received after transmitting register address
                                                            • HAL IRDA driver
                                                                @@ -370,38 +642,50 @@

                                                                HAL Drivers updates

                                                            • HAL IWDG driver
                                                                -
                                                              • Updated HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout vulnerability issue
                                                                • +
                                                              • Updated HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout +vulnerability issue
                                                            • HAL LPTIM driver
                                                                -
                                                              • Update HAL_LPTIM_Init() API implementation to configure digital filter for external clock when LPTIM is clocked by an internal clock source
                                                                • +
                                                              • Update HAL_LPTIM_Init() API implementation to configure digital +filter for external clock when LPTIM is clocked by an internal clock +source
                                                            • HAL PWR driver
                                                                -
                                                              • Correct HAL_PWREx_DisableInternalWakeUpLine() to update CM0+ register
                                                                • +
                                                              • Correct HAL_PWREx_DisableInternalWakeUpLine() to update CM0+ +register
                                                            • HAL RCC driver
                                                              • Update definition of IS_RCC_OSCILLATORTYPE() macro
                                                                • -
                                                              • Update IS_RCC_PERIPHCLOCK() macro definition depending on targeted derivative
                                                                • -
                                                              • Add new API HAL_RCC_GetResetSource() to get all reset sources and clear flags for next reset
                                                                • +
                                                              • Update IS_RCC_PERIPHCLOCK() macro definition depending on targeted +derivative
                                                                • +
                                                              • Add new API HAL_RCC_GetResetSource() to get all reset sources and +clear flags for next reset
                                                            • HAL RNG driver
                                                                -
                                                              • Update timeout mechanism to avoid false timeout detection in case of preemption
                                                                • +
                                                              • Update timeout mechanism to avoid false timeout detection in case of +preemption
                                                            • HAL RTC driver
                                                                -
                                                              • Update HAL_RTC_DeactivateAlarm() to fix issue where Alarm Autoclear remained activated after deactivating alarm
                                                                • -
                                                              • Update HAL_RTCEx_SetTimeStamp_IT() to avoid the call of TimeStamp callback during the setting of the TimeStamp
                                                                • -
                                                              • Update assertions in HAL_RTC_SetAlarm() and HAL_RTC_SetAlarm_IT() to allow user to unset some Alarm parameters when AlarmMask is set
                                                                • +
                                                              • Update HAL_RTC_DeactivateAlarm() to fix issue where Alarm Autoclear +remained activated after deactivating alarm
                                                                • +
                                                              • Update HAL_RTCEx_SetTimeStamp_IT() to avoid the call of TimeStamp +callback during the setting of the TimeStamp
                                                                • +
                                                              • Update assertions in HAL_RTC_SetAlarm() and HAL_RTC_SetAlarm_IT() to +allow user to unset some Alarm parameters when AlarmMask is set
                                                              • Update HAL_RTC_DeactivateAlarm() to clear Alarm Flag
                                                              • Update HAL_RTCEx_DeactivateTimeStamp() to clear TimeStamp flag
                                                                • -
                                                              • Update HAL_RTCEx_DeactivateInternalTimeStamp() to clear Internal TimeStamp flag +
                                                              • Update HAL_RTCEx_DeactivateInternalTimeStamp() to clear Internal +TimeStamp flag
                                                                • The flag is cleared only if TSOVF & TSE are set to 0
                                                                • -
                                                              • Update HAL_RTCEx_DeactivateWakeUpTimer() to clear WakeUpTimer flag
                                                                • +
                                                              • Update HAL_RTCEx_DeactivateWakeUpTimer() to clear WakeUpTimer +flag
                                                              • Update HAL_RTCEx_DeactivateSSRU() to clear SSR Underflow flag
                                                              • Update HAL_RTC_WaitForSynchro() to fix issue to clear RSF flag
                                                              • @@ -413,42 +697,56 @@

                                                              HAL Drivers updates

                                                              • Add support for Fast Mode Plus to be SMBUS Rev3 compliant:
                                                                  -
                                                                • Add HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+
                                                                  • +
                                                                • Add HAL_SMBUSEx_EnableFastModePlus() and +HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+
                                                            • HAL SPI driver
                                                                -
                                                              • Update in SPI_WaitFifoStateUntilTimeout() to fix code optimization issue
                                                                • +
                                                              • Update in SPI_WaitFifoStateUntilTimeout() to fix code optimization +issue
                                                              • Update to fix MISRA-C 2012 Rule-13.2 issue
                                                            • HAL SUBGHZ driver
                                                                -
                                                              • Update HAL_Delay() by a polling loop to avoid blocking situation in case of Systick is mapped on Tick
                                                                • -
                                                              • Update HAL_SUBGHZ_DeInit() to check RF Busy bit and deassert the reset signal on RF side
                                                                • +
                                                              • Update HAL_Delay() by a polling loop to avoid blocking situation in +case of Systick is mapped on Tick
                                                                • +
                                                              • Update HAL_SUBGHZ_DeInit() to check RF Busy bit and deassert the +reset signal on RF side
                                                            • HAL TIM driver
                                                                -
                                                              • Update HAL_TIMEx_OnePulseN_Start and HAL_TIMEx_OnePulseN_Stop (pooling and IT mode) to take into consideration all OutputChannel parameters
                                                                • +
                                                              • Update HAL_TIMEx_OnePulseN_Start and HAL_TIMEx_OnePulseN_Stop +(pooling and IT mode) to take into consideration all OutputChannel +parameters
                                                              • Correct CodeSpell typos in HAL TIM drivers
                                                                • -
                                                              • Update timeout mechanism to avoid false timeout detection in case of preemption
                                                                • -
                                                              • Update input capture measurement in DMA mode to avoid zero return values at high frequencies
                                                                • +
                                                              • Update timeout mechanism to avoid false timeout detection in case of +preemption
                                                                • +
                                                              • Update input capture measurement in DMA mode to avoid zero return +values at high frequencies
                                                            • HAL UART driver
                                                                -
                                                              • Remove an invalid FIFO mode configuration from UART_SetConfig() as it is not is not member of UART_InitTypeDef Structure
                                                                • -
                                                              • Update HAL_UART_IRQHandler() API to handle receiver timeout interrupt +
                                                              • Remove an invalid FIFO mode configuration from UART_SetConfig() as +it is not is not member of UART_InitTypeDef Structure
                                                                • +
                                                              • Update HAL_UART_IRQHandler() API to handle receiver timeout +interrupt
                                                                  -
                                                                • Update UART receive processes (IT and DMA) to handle the UART receive’s timeout interrupt
                                                                  • +
                                                                • Update UART receive processes (IT and DMA) to handle the UART +receive’s timeout interrupt
                                                              • Update arrays definition to be declared as static const
                                                                • -
                                                              • Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA()
                                                                • -
                                                              • Update UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback
                                                                • -
                                                              • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)
                                                                • +
                                                              • Fix erroneous UART’s handle state in case of error returned after +DMA reception start within UART_Start_Receive_DMA()
                                                                • +
                                                              • Update UART ReceptionType management in case of ReceptionToIdle API +are called from RxEvent callback
                                                                • +
                                                              • Handling of UART concurrent register access in case of race +condition between Tx and Rx transfers (HAL UART and LL LPUART)


                                                            -

                                                            LL Drivers updates

                                                            +

                                                            LL Drivers updates

                                                            • LL RCC driver
                                                                @@ -456,40 +754,51 @@

                                                                LL Drivers updates

                                                            • LL RTC driver
                                                                -
                                                              • Fix wrong reference of RTC instance in LL_RTC_TIME_Init() and LL_RTC_DATE_Init() functions
                                                                • +
                                                              • Fix wrong reference of RTC instance in LL_RTC_TIME_Init() and +LL_RTC_DATE_Init() functions
                                                            • LL SPI driver
                                                              • Updated to set the FRXTH bit for 8bit data in LL_SPI_Init() API
                                                                • -
                                                              • Update LL_SPI_TransmitData8() to avoid casting the result to 8 bits
                                                                • +
                                                              • Update LL_SPI_TransmitData8() to avoid casting the result to 8 +bits
                                                            • LL TIM driver
                                                                -
                                                              • Updated LL_TIM_GetCounterMode() API to return the correct counter mode
                                                                • -
                                                              • Update reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode
                                                                • +
                                                              • Updated LL_TIM_GetCounterMode() API to return the correct counter +mode
                                                                • +
                                                              • Update reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse +Mode
                                                            • LL LPUART driver
                                                                -
                                                              • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)
                                                                • +
                                                              • Handling of UART concurrent register access in case of race +condition between Tx and Rx transfers (HAL UART and LL LPUART)
                                                            • LL USART driver
                                                                -
                                                              • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)
                                                                • -
                                                              • LL_USART_ClockInit now supports clock phase and clock polarity configuration for SPI_Slave mode
                                                                • -
                                                              • Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro
                                                                • +
                                                              • Handling of UART concurrent register access in case of race +condition between Tx and Rx transfers (HAL UART and LL LPUART)
                                                                • +
                                                              • LL_USART_ClockInit now supports clock phase and clock polarity +configuration for SPI_Slave mode
                                                                • +
                                                              • Remove useless check on maximum BRR value by removing +IS_LL_USART_BRR_MAX() macro


                                                            -

                                                            Known Limitations

                                                            +

                                                            Known Limitations

                                                            None

                                                            -

                                                            Development Toolchains and Compilers

                                                            +

                                                            Development Toolchains +and Compilers

                                                            • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
                                                              • -
                                                            • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
                                                              • +
                                                            • RealView Microcontroller Development Kit (MDK-ARM) toolchain +V5.31
                                                            • STM32CubeIDE 1.7.0
                                                            -

                                                            Supported Devices and boards

                                                            +

                                                            Supported Devices and +boards

                                                            Supported Devices:

                                                            • STM32WL55xx
                                                              • @@ -497,30 +806,35 @@

                                                              Supported Devices and boards

                                                            • STM32WLE5xx
                                                            • STM32WLE4xx
                                                            -

                                                            Backward Compatibility

                                                            +

                                                            Backward Compatibility

                                                            Not applicable

                                                            -

                                                            Dependencies

                                                            +

                                                            Dependencies

                                                            None


                                                          - + +
                                                          -

                                                          Main Changes

                                                          +

                                                          Main Changes

                                                          First Official Release

                                                          -

                                                          Contents

                                                          +

                                                          Contents

                                                          First official release of LL / HAL Drivers for STM32WLxx series.

                                                          -

                                                          Known Limitations

                                                          +

                                                          Known Limitations

                                                          None

                                                          -

                                                          Development Toolchains and Compilers

                                                          +

                                                          Development Toolchains +and Compilers

                                                          • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
                                                            • -
                                                          • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.28
                                                            • +
                                                          • RealView Microcontroller Development Kit (MDK-ARM) toolchain +V5.28
                                                          • STM32CubeIDE 1.5.0
                                                          -

                                                          Supported Devices and boards

                                                          +

                                                          Supported Devices and +boards

                                                          Supported Devices:

                                                          • STM32WL55xx
                                                            • @@ -528,21 +842,25 @@

                                                            Supported Devices and boards

                                                          • STM32WLE5xx
                                                          • STM32WLE4xx
                                                          -

                                                          Backward Compatibility

                                                          +

                                                          Backward Compatibility

                                                          Not applicable

                                                          -

                                                          Dependencies

                                                          +

                                                          Dependencies

                                                          None


                                                          -
                                                        +